LLVM 20.0.0git
RISCVDeadRegisterDefinitions.cpp
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1//===- RISCVDeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===---------------------------------------------------------------------===//
8//
9// This pass rewrites Rd to x0 for instrs whose return values are unused.
10//
11//===---------------------------------------------------------------------===//
12
13#include "RISCV.h"
14#include "RISCVInstrInfo.h"
15#include "RISCVSubtarget.h"
16#include "llvm/ADT/Statistic.h"
22
23using namespace llvm;
24#define DEBUG_TYPE "riscv-dead-defs"
25#define RISCV_DEAD_REG_DEF_NAME "RISC-V Dead register definitions"
26
27STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");
28
29namespace {
30class RISCVDeadRegisterDefinitions : public MachineFunctionPass {
31public:
32 static char ID;
33
34 RISCVDeadRegisterDefinitions() : MachineFunctionPass(ID) {}
35 bool runOnMachineFunction(MachineFunction &MF) override;
36 void getAnalysisUsage(AnalysisUsage &AU) const override {
37 AU.setPreservesCFG();
45 }
46
47 StringRef getPassName() const override { return RISCV_DEAD_REG_DEF_NAME; }
48};
49} // end anonymous namespace
50
51char RISCVDeadRegisterDefinitions::ID = 0;
52INITIALIZE_PASS(RISCVDeadRegisterDefinitions, DEBUG_TYPE,
53 RISCV_DEAD_REG_DEF_NAME, false, false)
54
56 return new RISCVDeadRegisterDefinitions();
57}
58
59bool RISCVDeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
60 if (skipFunction(MF.getFunction()))
61 return false;
62
65 LiveIntervals &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
66 LLVM_DEBUG(dbgs() << "***** RISCVDeadRegisterDefinitions *****\n");
67
68 bool MadeChange = false;
69 for (MachineBasicBlock &MBB : MF) {
70 for (MachineInstr &MI : MBB) {
71 // We only handle non-computational instructions since some NOP encodings
72 // are reserved for HINT instructions.
73 const MCInstrDesc &Desc = MI.getDesc();
74 if (!Desc.mayLoad() && !Desc.mayStore() &&
75 !Desc.hasUnmodeledSideEffects() &&
76 MI.getOpcode() != RISCV::PseudoVSETVLI &&
77 MI.getOpcode() != RISCV::PseudoVSETIVLI)
78 continue;
79 // For PseudoVSETVLIX0, Rd = X0 has special meaning.
80 if (MI.getOpcode() == RISCV::PseudoVSETVLIX0)
81 continue;
82 for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) {
83 MachineOperand &MO = MI.getOperand(I);
84 if (!MO.isReg() || !MO.isDef() || MO.isEarlyClobber())
85 continue;
86 // Be careful not to change the register if it's a tied operand.
87 if (MI.isRegTiedToUseOperand(I)) {
88 LLVM_DEBUG(dbgs() << " Ignoring, def is tied operand.\n");
89 continue;
90 }
91 Register Reg = MO.getReg();
92 if (!Reg.isVirtual() || !MO.isDead())
93 continue;
94 LLVM_DEBUG(dbgs() << " Dead def operand #" << I << " in:\n ";
95 MI.print(dbgs()));
96 const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF);
97 if (!(RC && RC->contains(RISCV::X0))) {
98 LLVM_DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");
99 continue;
100 }
101 assert(LIS.hasInterval(Reg));
102 LIS.removeInterval(Reg);
103 MO.setReg(RISCV::X0);
104 LLVM_DEBUG(dbgs() << " Replacing with zero register. New:\n ";
105 MI.print(dbgs()));
106 ++NumDeadDefsReplaced;
107 MadeChange = true;
108 }
109 }
110 }
111
112 return MadeChange;
113}
MachineBasicBlock & MBB
#define LLVM_DEBUG(X)
Definition: Debug.h:101
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
#define RISCV_DEAD_REG_DEF_NAME
#define DEBUG_TYPE
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Definition: Statistic.h:166
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:256
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:310
bool hasInterval(Register Reg) const
void removeInterval(Register Reg)
Interval removal.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setReg(Register Reg)
Change the register this operand corresponds to.
bool isEarlyClobber() const
Register getReg() const
getReg - Returns the register number.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:130
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
FunctionPass * createRISCVDeadRegisterDefinitionsPass()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
Description of the encoding of one expression Op.