42#define DEBUG_TYPE "machine-scheduler"
50 case RISCV::VMNAND_MM:
51 case RISCV::VMANDN_MM:
56 case RISCV::VMXNOR_MM:
64 case RISCV::VMADC_VVM:
65 case RISCV::VMADC_VXM:
66 case RISCV::VMADC_VIM:
69 case RISCV::VMSBC_VVM:
70 case RISCV::VMSBC_VXM:
80 case RISCV::VMSLTU_VV:
81 case RISCV::VMSLTU_VX:
85 case RISCV::VMSLEU_VV:
86 case RISCV::VMSLEU_VX:
87 case RISCV::VMSLEU_VI:
88 case RISCV::VMSGTU_VX:
89 case RISCV::VMSGTU_VI:
100 case RISCV::VMFLE_VF:
101 case RISCV::VMFGT_VF:
102 case RISCV::VMFGE_VF:
116 SUnit *NearestUseV0SU =
nullptr;
119 if (
MI->findRegisterUseOperand(RISCV::V0,
TRI))
120 NearestUseV0SU = &SU;
132std::unique_ptr<ScheduleDAGMutation>
134 return std::make_unique<RISCVVectorMaskDAGMutation>(
TRI);
unsigned const TargetRegisterInfo * TRI
Representation of each machine instruction.
RISCVVectorMaskDAGMutation(const TargetRegisterInfo *TRI)
void apply(ScheduleDAGInstrs *DAG) override
@ Artificial
Arbitrary strong DAG edge (no real dependence).
Scheduling unit. This is a node in the scheduling DAG.
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
A ScheduleDAG for scheduling lists of MachineInstr.
bool addEdge(SUnit *SuccSU, const SDep &PredDep)
Add a DAG edge to the given SU with the given predecessor dependence data.
Mutate the DAG as a postpass after normal DAG building.
std::vector< SUnit > SUnits
The scheduling units.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static VLMUL getLMul(uint64_t TSFlags)
unsigned getRVVMCOpcode(unsigned RVVPseudoOpcode)
This is an optimization pass for GlobalISel generic memory operations.
static bool isVectorMaskProducer(const MachineInstr *MI)
std::unique_ptr< ScheduleDAGMutation > createRISCVVectorMaskDAGMutation(const TargetRegisterInfo *TRI)