54 const auto Arch = TT.getArch();
61 return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-"
62 "v256:256-v512:512-v1024:1024-n8:16:32:64-G1";
63 if (TT.getVendor() == Triple::VendorType::AMD &&
64 TT.getOS() == Triple::OSType::AMDHSA)
65 return "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-"
66 "v512:512-v1024:1024-n32:64-S32-G1-P4-A0";
67 return "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-"
68 "v512:512-v1024:1024-n8:16:32:64-G1";
83 std::optional<Reloc::Model> RM,
84 std::optional<CodeModel::Model> CM,
90 Subtarget(TT, CPU.str(), FS.str(), *this) {
99#define GET_PASS_REGISTRY "SPIRVPassRegistry.def"
111 return getTM<SPIRVTargetMachine>();
113 void addMachineSSAOptimization()
override;
114 void addIRPasses()
override;
115 void addISelPrepare()
override;
117 bool addIRTranslator()
override;
118 void addPreLegalizeMachineIR()
override;
119 bool addLegalizeMachineIR()
override;
120 bool addRegBankSelect()
override;
121 bool addGlobalInstructionSelect()
override;
123 FunctionPass *createTargetRegisterAllocator(
bool)
override;
124 void addFastRegAlloc()
override {}
125 void addOptimizedRegAlloc()
override {}
127 void addPostRegAlloc()
override;
128 void addPreEmitPass()
override;
137FunctionPass *SPIRVPassConfig::createTargetRegisterAllocator(
bool) {
142void SPIRVPassConfig::addMachineSSAOptimization() {
147void SPIRVPassConfig::addPostRegAlloc() {
173 return new SPIRVPassConfig(*
this, PM);
176void SPIRVPassConfig::addIRPasses() {
179 if (TM.getSubtargetImpl()->isVulkanEnv()) {
209void SPIRVPassConfig::addISelPrepare() {
214bool SPIRVPassConfig::addIRTranslator() {
219void SPIRVPassConfig::addPreLegalizeMachineIR() {
224bool SPIRVPassConfig::addLegalizeMachineIR() {
231bool SPIRVPassConfig::addRegBankSelect() {
237 "spv-emit-nonsemantic-debug-info",
238 cl::desc(
"Emit SPIR-V NonSemantic.Shader.DebugInfo.100 instructions"),
241void SPIRVPassConfig::addPreEmitPass() {
254 MachineFunctionProperties::Property::RegBankSelected);
260bool SPIRVPassConfig::addGlobalInstructionSelect() {
261 addPass(
new SPIRVInstructionSelect());
#define LLVM_EXTERNAL_VISIBILITY
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
This file declares the IRTranslator pass.
static std::string computeDataLayout()
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSPIRVTarget()
static cl::opt< bool > SPVEnableNonSemanticDI("spv-emit-nonsemantic-debug-info", cl::desc("Emit SPIR-V NonSemantic.Shader.DebugInfo.100 instructions"), cl::Optional, cl::init(false))
Target-Independent Code Generator Pass Configuration Options pass.
implements a set of functionality in the TargetMachine class for targets that make use of the indepen...
FunctionPass class - This class is used to implement most global optimizations.
This pass is responsible for selecting generic machine instructions to target-specific instructions.
MachineFunctionProperties getRequiredProperties() const override
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & reset(Property P)
This class provides access to building LLVM's passes.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
void registerPassBuilderCallbacks(PassBuilder &PB) override
Allow the target to modify the pass pipeline.
SPIRVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
~SPIRVTargetObjectFile() override
StringRef - Represent a constant reference to a string, i.e.
void setFastISel(bool Enable)
void setRequiresStructuredCFG(bool Value)
void setGlobalISel(bool Enable)
void setO0WantsFastISel(bool Enable)
Target-Independent Code Generator Pass Configuration Options.
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Interfaces for registering analysis passes, producing common pass manager configurations,...
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
FunctionPass * createSPIRVStructurizerPass()
FunctionPass * createPromoteMemoryToRegisterPass()
MachineFunctionPass * createSPIRVEmitNonSemanticDIPass(SPIRVTargetMachine *TM)
Target & getTheSPIRV32Target()
ModulePass * createSPIRVEmitIntrinsicsPass(SPIRVTargetMachine *TM)
FunctionPass * createRegToMemWrapperPass()
FunctionPass * createSPIRVPreLegalizerPass()
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
char & RemoveLoadsIntoFakeUsesID
RemoveLoadsIntoFakeUses pass.
FunctionPass * createSPIRVStripConvergenceIntrinsicsPass()
char & LiveDebugValuesID
LiveDebugValues pass.
void initializeSPIRVModuleAnalysisPass(PassRegistry &)
static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)
FunctionPass * createSPIRVPostLegalizerPass()
CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
char & MachineLateInstrsCleanupID
MachineLateInstrsCleanup - This pass removes redundant identical instructions after register allocati...
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
char & FuncletLayoutID
This pass lays out funclets contiguously.
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
CodeGenOptLevel
Code generation optimization level.
Target & getTheSPIRV64Target()
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Target & getTheSPIRVLogicalTarget()
FunctionPass * createSPIRVRegularizerPass()
void initializeSPIRVStructurizerPass(PassRegistry &)
FunctionPass * createSPIRVMergeRegionExitTargetsPass()
void initializeSPIRVConvergenceRegionAnalysisWrapperPassPass(PassRegistry &)
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
char & BranchFolderPassID
BranchFolding - This pass performs machine code CFG based optimizations to delete branches to branche...
ModulePass * createSPIRVPrepareFunctionsPass(const SPIRVTargetMachine &TM)
Pass * createLoopSimplifyPass()
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
Implement std::hash so that hash_code can be used in STL containers.
RegisterTargetMachine - Helper template for registering a target machine implementation,...