#include "SPIRVUtils.h"
#include "MCTargetDesc/SPIRVBaseInfo.h"
#include "SPIRV.h"
#include "SPIRVGlobalRegistry.h"
#include "SPIRVInstrInfo.h"
#include "SPIRVSubtarget.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Demangle/Demangle.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/IntrinsicsSPIRV.h"
#include <queue>
#include <vector>

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.

Functions
static uint32_t	llvm::convertCharsToWord (const StringRef &Str, unsigned i)
static size_t	llvm::getPaddedLen (const StringRef &Str)
void	llvm::addStringImm (const StringRef &Str, MCInst &Inst)
void	llvm::addStringImm (const StringRef &Str, MachineInstrBuilder &MIB)
void	llvm::addStringImm (const StringRef &Str, IRBuilder<> &B, std::vector< Value * > &Args)
std::string	llvm::getStringImm (const MachineInstr &MI, unsigned StartIndex)
std::string	llvm::getStringValueFromReg (Register Reg, MachineRegisterInfo &MRI)
void	llvm::addNumImm (const APInt &Imm, MachineInstrBuilder &MIB)
void	llvm::buildOpName (Register Target, const StringRef &Name, MachineIRBuilder &MIRBuilder)
void	llvm::buildOpName (Register Target, const StringRef &Name, MachineInstr &I, const SPIRVInstrInfo &TII)
static void	llvm::finishBuildOpDecorate (MachineInstrBuilder &MIB, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
void	llvm::buildOpDecorate (Register Reg, MachineIRBuilder &MIRBuilder, SPIRV::Decoration::Decoration Dec, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
void	llvm::buildOpDecorate (Register Reg, MachineInstr &I, const SPIRVInstrInfo &TII, SPIRV::Decoration::Decoration Dec, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
void	llvm::buildOpMemberDecorate (Register Reg, MachineIRBuilder &MIRBuilder, SPIRV::Decoration::Decoration Dec, uint32_t Member, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
void	llvm::buildOpMemberDecorate (Register Reg, MachineInstr &I, const SPIRVInstrInfo &TII, SPIRV::Decoration::Decoration Dec, uint32_t Member, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
void	llvm::buildOpSpirvDecorations (Register Reg, MachineIRBuilder &MIRBuilder, const MDNode *GVarMD, const SPIRVSubtarget &ST)
MachineBasicBlock::iterator	llvm::getOpVariableMBBIt (MachineInstr &I)
MachineBasicBlock::iterator	llvm::getInsertPtValidEnd (MachineBasicBlock *MBB)
SPIRV::StorageClass::StorageClass	llvm::addressSpaceToStorageClass (unsigned AddrSpace, const SPIRVSubtarget &STI)
SPIRV::MemorySemantics::MemorySemantics	llvm::getMemSemanticsForStorageClass (SPIRV::StorageClass::StorageClass SC)
SPIRV::MemorySemantics::MemorySemantics	llvm::getMemSemantics (AtomicOrdering Ord)
SPIRV::Scope::Scope	llvm::getMemScope (LLVMContext &Ctx, SyncScope::ID Id)
MachineInstr *	llvm::getDefInstrMaybeConstant (Register &ConstReg, const MachineRegisterInfo *MRI)
uint64_t	llvm::getIConstVal (Register ConstReg, const MachineRegisterInfo *MRI)
bool	llvm::isSpvIntrinsic (const MachineInstr &MI, Intrinsic::ID IntrinsicID)
Type *	llvm::getMDOperandAsType (const MDNode *N, unsigned I)
static bool	llvm::isPipeOrAddressSpaceCastBI (const StringRef MangledName)
static bool	llvm::isEnqueueKernelBI (const StringRef MangledName)
static bool	llvm::isKernelQueryBI (const StringRef MangledName)
static bool	llvm::isNonMangledOCLBuiltin (StringRef Name)
std::string	llvm::getOclOrSpirvBuiltinDemangledName (StringRef Name)
bool	llvm::hasBuiltinTypePrefix (StringRef Name)
bool	llvm::isSpecialOpaqueType (const Type *Ty)
bool	llvm::isEntryPoint (const Function &F)
Type *	llvm::parseBasicTypeName (StringRef &TypeName, LLVMContext &Ctx)
bool	llvm::sortBlocks (Function &F)
MachineInstr *	llvm::getVRegDef (MachineRegisterInfo &MRI, Register Reg)
bool	llvm::getVacantFunctionName (Module &M, std::string &Name)
void	llvm::setRegClassType (Register Reg, SPIRVType SpvType, SPIRVGlobalRegistry GR, MachineRegisterInfo *MRI, const MachineFunction &MF, bool Force)
void	llvm::setRegClassType (Register Reg, const Type Ty, SPIRVGlobalRegistry GR, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AccessQual, bool EmitIR, bool Force)
Register	llvm::createVirtualRegister (SPIRVType SpvType, SPIRVGlobalRegistry GR, MachineRegisterInfo *MRI, const MachineFunction &MF)
Register	llvm::createVirtualRegister (SPIRVType SpvType, SPIRVGlobalRegistry GR, MachineIRBuilder &MIRBuilder)
Register	llvm::createVirtualRegister (const Type Ty, SPIRVGlobalRegistry GR, MachineIRBuilder &MIRBuilder, SPIRV::AccessQualifier::AccessQualifier AccessQual, bool EmitIR)
CallInst *	llvm::buildIntrWithMD (Intrinsic::ID IntrID, ArrayRef< Type * > Types, Value Arg, Value Arg2, ArrayRef< Constant * > Imms, IRBuilder<> &B)
bool	llvm::isNestedPointer (const Type *Ty)
bool	llvm::isSpvIntrinsic (const Value *Arg)
SmallVector< MachineInstr *, 4 >	llvm::createContinuedInstructions (MachineIRBuilder &MIRBuilder, unsigned Opcode, unsigned MinWC, unsigned ContinuedOpcode, ArrayRef< Register > Args, Register ReturnRegister, Register TypeID)
SmallVector< unsigned, 1 >	llvm::getSpirvLoopControlOperandsFromLoopMetadata (Loop *L)
const std::set< unsigned > &	llvm::getTypeFoldingSupportedOpcodes ()
bool	llvm::isTypeFoldingSupported (unsigned Opcode)
MachineInstr *	llvm::passCopy (MachineInstr Def, const MachineRegisterInfo MRI)
MachineInstr *	llvm::getDef (const MachineOperand &MO, const MachineRegisterInfo *MRI)
MachineInstr *	llvm::getImm (const MachineOperand &MO, const MachineRegisterInfo *MRI)
int64_t	llvm::foldImm (const MachineOperand &MO, const MachineRegisterInfo *MRI)
unsigned	llvm::getArrayComponentCount (const MachineRegisterInfo MRI, const MachineInstr ResType)
MachineBasicBlock::iterator	llvm::getFirstValidInstructionInsertPoint (MachineBasicBlock &BB)

Namespaces

Functions