LLVM 24.0.0git
llvm::CandidateHeuristics Class Reference

CandidateHeuristics contains state and implementations to facilitate making per instruction scheduling decisions; it contains methods used in tryCandidate to decide which instruction to schedule next. More...

#include "Target/AMDGPU/AMDGPUCoExecSchedStrategy.h"

Classes

struct  StallCosts

Public Member Functions

 CandidateHeuristics ()=default
void initialize (ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel, const TargetRegisterInfo *TRI)
void updateForScheduling (SUnit *SU)
 Update the state to reflect that SU is going to be scheduled.
HardwareUnitInfo * getHWUIFromFlavor (AMDGPU::InstructionFlavor Flavor)
 Given a Flavor , find the corresponding HardwareUnit.
void sortHWUIResources ()
 Sort the HardwarUnitInfo vector.
unsigned getStructuralStallCycles (SchedBoundary &Zone, SUnit *SU)
bool tryEffectiveStall (GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, SchedBoundary &Zone)
bool tryMemoryPipeline (GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, SchedBoundary &Zone)
 Prioritize instructions involved the memory pipeline.
bool tryCriticalResource (GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, SchedBoundary *Zone) const
 Check for critical resource consumption.
bool tryCriticalResourceDependency (GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, SchedBoundary *Zone) const
 Check for dependencies of instructions that use prioritized HardwareUnits.
void dumpRegionSummary ()

Protected Member Functions

void collectRegionSummary ()
 Walk over the region and collect characteristics for the various heuristics.
unsigned getMaxBlockingCycles (const MCSchedClassDesc *SC, const MachineInstr *MI)
unsigned getHWUICyclesForSU (SUnit *SU)
 Compute the blocking cycles for the appropriate HardwareUnit given an SU.
unsigned getHWUICyclesForMI (MachineInstr *MI)
 Compute the blocking cycles for the appropriate HardwareUnit given an MI.
unsigned getCarriedLatency (SUnit *SU)
 Estimate the block carried latency from loads for a given SU.
StallCosts getStallCosts (SUnit *SU, SchedBoundary &Zone)

Protected Attributes

ScheduleDAGMI * DAG
const SIInstrInfo * SII
const SIRegisterInfo * SRI
const TargetSchedModel * SchedModel
SmallVector< HardwareUnitInfo, 8 > HWUInfo
DenseMap< MachineInstr *, unsigned > CarriedLatencies

Detailed Description

CandidateHeuristics contains state and implementations to facilitate making per instruction scheduling decisions; it contains methods used in tryCandidate to decide which instruction to schedule next.

Definition at line 214 of file AMDGPUCoExecSchedStrategy.h.

Constructor & Destructor Documentation

◆ CandidateHeuristics()

llvm::CandidateHeuristics::CandidateHeuristics ( )
default

References DAG, SchedModel, and TRI.

Member Function Documentation

◆ collectRegionSummary()

void CandidateHeuristics::collectRegionSummary ( )
protected

Walk over the region and collect characteristics for the various heuristics.

Definition at line 717 of file AMDGPUCoExecSchedStrategy.cpp.

References CarriedLatencies, llvm::AMDGPU::classifyFlavor(), DAG, dumpRegionSummary(), getCarriedLatency(), getHWUICyclesForSU(), HWUInfo, LLVM_DEBUG, MI, SchedModel, and SII.

Referenced by initialize().

◆ dumpRegionSummary()

void CandidateHeuristics::dumpRegionSummary ( )

◆ getCarriedLatency()

unsigned CandidateHeuristics::getCarriedLatency ( SUnit * SU)
protected

Estimate the block carried latency from loads for a given SU.

This is essentially global scheduling info that our local scheduling infrastructure lacks the necessary infrastructure to accurately measure. Thus, this method just attempts to find a reasonable upper bound for carried load latency to avoid long stalls.

Definition at line 638 of file AMDGPUCoExecSchedStrategy.cpp.

References assert(), BlockCarriedLatency, llvm::AMDGPU::classifyFlavor(), DAG, llvm::AMDGPU::DS, llvm::AMDGPU::Fence, getHWUICyclesForMI(), llvm::SUnit::getInstr(), I, llvm::SlotIndex::isEarlierInstr(), llvm::Latency, MBB, MI, and SII.

Referenced by collectRegionSummary().

◆ getHWUICyclesForMI()

unsigned CandidateHeuristics::getHWUICyclesForMI ( MachineInstr * MI)
protected

Compute the blocking cycles for the appropriate HardwareUnit given an MI.

Definition at line 597 of file AMDGPUCoExecSchedStrategy.cpp.

References assert(), getMaxBlockingCycles(), MI, and SchedModel.

Referenced by getCarriedLatency().

◆ getHWUICyclesForSU()

unsigned CandidateHeuristics::getHWUICyclesForSU ( SUnit * SU)
protected

Compute the blocking cycles for the appropriate HardwareUnit given an SU.

Definition at line 589 of file AMDGPUCoExecSchedStrategy.cpp.

References assert(), DAG, llvm::SUnit::getInstr(), getMaxBlockingCycles(), MI, SchedModel, and SII.

Referenced by collectRegionSummary(), getStallCosts(), and updateForScheduling().

◆ getHWUIFromFlavor()

HardwareUnitInfo * CandidateHeuristics::getHWUIFromFlavor ( AMDGPU::InstructionFlavor Flavor)

Given a Flavor , find the corresponding HardwareUnit.

Returns
the mapped HardwareUnit.

Definition at line 563 of file AMDGPUCoExecSchedStrategy.cpp.

References HWUInfo.

Referenced by getStallCosts(), and updateForScheduling().

◆ getMaxBlockingCycles()

unsigned CandidateHeuristics::getMaxBlockingCycles ( const MCSchedClassDesc * SC,
const MachineInstr * MI )
protected
Returns
the maximum blocking cycles according to the SchedModel for a given MCSchedClassDesc SC.

Definition at line 572 of file AMDGPUCoExecSchedStrategy.cpp.

References MI, SchedModel, and SII.

Referenced by getHWUICyclesForMI(), and getHWUICyclesForSU().

◆ getStallCosts()

◆ getStructuralStallCycles()

◆ initialize()

◆ sortHWUIResources()

void CandidateHeuristics::sortHWUIResources ( )

Sort the HardwarUnitInfo vector.

After sorting, the HWUI that are highest priority are first. Priority is determined by maximizing coexecution and keeping the critical HardwareUnit busy.

Definition at line 754 of file AMDGPUCoExecSchedStrategy.cpp.

References A(), B(), HWUInfo, and llvm::sort().

◆ tryCriticalResource()

bool CandidateHeuristics::tryCriticalResource ( GenericSchedulerBase::SchedCandidate & TryCand,
GenericSchedulerBase::SchedCandidate & Cand,
SchedBoundary * Zone ) const

Check for critical resource consumption.

Prefer the candidate that uses the most prioritized HardwareUnit. If both candidates use the same HarwareUnit, prefer the candidate with higher priority on that HardwareUnit.

Definition at line 1022 of file AMDGPUCoExecSchedStrategy.cpp.

References llvm::HardwareUnitInfo::contains(), llvm::AMDGPU::DS, llvm::HardwareUnitInfo::getHigherPriority(), llvm::HardwareUnitInfo::getType(), HWUInfo, I, llvm::GenericSchedulerBase::SchedCandidate::Reason, llvm::GenericSchedulerBase::RegCritical, llvm::GenericSchedulerBase::SchedCandidate::SU, and tryCriticalResourceDependency().

◆ tryCriticalResourceDependency()

bool CandidateHeuristics::tryCriticalResourceDependency ( GenericSchedulerBase::SchedCandidate & TryCand,
GenericSchedulerBase::SchedCandidate & Cand,
SchedBoundary * Zone ) const

Check for dependencies of instructions that use prioritized HardwareUnits.

Prefer the candidate that is a dependency of an instruction that uses the most prioritized HardwareUnit. If both candidates enable the same HardwareUnit, prefer the candidate that enables the higher priority instruction on that HardwareUnit.

Definition at line 935 of file AMDGPUCoExecSchedStrategy.cpp.

References llvm::AMDGPU::classifyFlavor(), DAG, llvm::AMDGPU::DS, llvm::Enabled, llvm::SUnit::getHeight(), llvm::SUnit::getInstr(), llvm::HardwareUnitInfo::getNextTargetSU(), llvm::HardwareUnitInfo::getType(), HWUInfo, I, llvm::GenericSchedulerBase::SchedCandidate::Reason, llvm::GenericSchedulerBase::RegCritical, SII, llvm::GenericSchedulerBase::SchedCandidate::SU, and llvm::AMDGPU::WMMA.

Referenced by tryCriticalResource().

◆ tryEffectiveStall()

◆ tryMemoryPipeline()

bool CandidateHeuristics::tryMemoryPipeline ( GenericSchedulerBase::SchedCandidate & TryCand,
GenericSchedulerBase::SchedCandidate & Cand,
SchedBoundary & Zone )

Prioritize instructions involved the memory pipeline.

Currently we don't have any modelling of pipelined loads, so we control the layout of the pipeline per iteration by giving the user some control over the stalls (e.g. between s_barrier_signal and s_barrier_wait) and scheduling the pipeline instructions as soon as they are ready.

TODO – add better modelling and heuristics for pipelining based scheduling.

Definition at line 899 of file AMDGPUCoExecSchedStrategy.cpp.

References llvm::AMDGPU::classifyFlavor(), llvm::AMDGPU::DMA, llvm::CandidateHeuristics::StallCosts::Effective, llvm::AMDGPU::Fence, llvm::SUnit::getInstr(), getStallCosts(), llvm::GenericSchedulerBase::SchedCandidate::Reason, llvm::GenericSchedulerBase::RegCritical, SII, and llvm::GenericSchedulerBase::SchedCandidate::SU.

◆ updateForScheduling()

void CandidateHeuristics::updateForScheduling ( SUnit * SU)

Update the state to reflect that SU is going to be scheduled.

Definition at line 602 of file AMDGPUCoExecSchedStrategy.cpp.

References assert(), llvm::AMDGPU::classifyFlavor(), getHWUICyclesForSU(), getHWUIFromFlavor(), llvm::SUnit::getInstr(), llvm::HardwareUnitInfo::markScheduled(), and SII.

Member Data Documentation

◆ CarriedLatencies

DenseMap<MachineInstr *, unsigned> llvm::CandidateHeuristics::CarriedLatencies
protected

Definition at line 231 of file AMDGPUCoExecSchedStrategy.h.

Referenced by collectRegionSummary(), and getStallCosts().

◆ DAG

◆ HWUInfo

◆ SchedModel

◆ SII

◆ SRI

const SIRegisterInfo* llvm::CandidateHeuristics::SRI
protected

Definition at line 228 of file AMDGPUCoExecSchedStrategy.h.

Referenced by initialize().


The documentation for this class was generated from the following files: