23 for (
auto &
op :
I.operands()) {
24 if (!
op.isReg() || !
op.isDef())
26 if (isDivergent(
op.getReg()))
35 bool insertedDivergent =
false;
36 const auto &
MRI =
F.getRegInfo();
37 const auto &
TRI = *
MRI.getTargetRegisterInfo();
39 if (!
op.isReg() || !
op.isDef())
41 if (!
op.getReg().isVirtual())
44 if (!AllDefsDivergent) {
45 auto *RC =
MRI.getRegClassOrNull(
op.getReg());
46 if (RC && !
TRI.isDivergentRegClass(RC))
49 insertedDivergent |= markDivergent(
op.getReg());
51 return insertedDivergent;
56 const auto &
InstrInfo = *
F.getSubtarget().getInstrInfo();
61 if (
uniformity == InstructionUniformity::AlwaysUniform) {
62 addUniformOverride(
instr);
66 if (
uniformity == InstructionUniformity::NeverUniform) {
67 markDefsDivergent(
instr,
false);
76 const auto &RegInfo =
F.getRegInfo();
77 for (
MachineInstr &UserInstr : RegInfo.use_instructions(Reg)) {
78 if (markDivergent(UserInstr))
79 Worklist.push_back(&UserInstr);
86 assert(!isAlwaysUniform(Instr));
90 if (
op.isReg() &&
op.isDef() &&
op.getReg().isVirtual())
91 pushUsers(
op.getReg());
99 for (
auto &Op :
I.operands()) {
100 if (!
Op.isReg() || !
Op.readsReg())
102 auto Reg =
Op.getReg();
106 if (
Reg.isPhysical())
109 auto *
Def =
F.getRegInfo().getVRegDef(Reg);
122 auto Reg = U.getReg();
123 if (isDivergent(Reg))
126 const auto &RegInfo =
F.getRegInfo();
127 auto *Def = RegInfo.getOneDef(Reg);
131 auto *DefInstr = Def->getParent();
132 auto *UseInstr = U.getParent();
133 return isTemporalDivergent(*UseInstr->getParent(), *DefInstr);
146 assert(
F.getRegInfo().isSSA() &&
"Expected to be run on SSA form!");
159 MachineUniformityAnalysisPass();
175 MachineUniformityInfoPrinterPass();
183char MachineUniformityAnalysisPass::ID = 0;
185MachineUniformityAnalysisPass::MachineUniformityAnalysisPass()
191 "Machine Uniformity Info Analysis",
true,
true)
197void MachineUniformityAnalysisPass::getAnalysisUsage(
AnalysisUsage &AU)
const {
198 AU.setPreservesAll();
204bool MachineUniformityAnalysisPass::runOnMachineFunction(
MachineFunction &MF) {
205 auto &DomTree = getAnalysis<MachineDominatorTree>().getBase();
206 auto &CI = getAnalysis<MachineCycleInfoWrapperPass>().getCycleInfo();
213 OS <<
"MachineUniformityInfo for function: " << UI.getFunction().getName()
218char MachineUniformityInfoPrinterPass::ID = 0;
220MachineUniformityInfoPrinterPass::MachineUniformityInfoPrinterPass()
227 "print-machine-uniformity",
228 "Print Machine Uniformity Info Analysis",
true,
true)
234void MachineUniformityInfoPrinterPass::getAnalysisUsage(
236 AU.setPreservesAll();
237 AU.addRequired<MachineUniformityAnalysisPass>();
241bool MachineUniformityInfoPrinterPass::runOnMachineFunction(
243 auto &UI = getAnalysis<MachineUniformityAnalysisPass>();
unsigned const MachineRegisterInfo * MRI
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
This file declares a specialization of the GenericSSAContext<X> template class for Machine IR.
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unify loop Fixup each natural loop to have a single exit block
Represent the analysis usage information of a pass.
Core dominator tree base class.
A possibly irreducible generalization of a Loop.
bool contains(const BlockT *Block) const
Return whether Block is contained in the cycle.
Legacy analysis pass which computes a MachineCycleInfo.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Representation of each machine instruction.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
iterator_range< mop_iterator > operands()
MachineOperand class - Representation of each machine instruction operand.
A Module instance is used to store all the information related to an LLVM module.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Wrapper class representing virtual and physical registers.
This class implements an extremely fast bulk output stream that can only output to a stream.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
MachineUniformityInfo computeMachineUniformityInfo(MachineFunction &F, const MachineCycleInfo &cycleInfo, const MachineDomTree &domTree)
Compute uniformity information for a Machine IR function.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
void initializeMachineUniformityAnalysisPassPass(PassRegistry &)
GenericUniformityInfo< MachineSSAContext > MachineUniformityInfo
void initializeMachineUniformityInfoPrinterPassPass(PassRegistry &)