LLVM  9.0.0svn
AVRAsmParser.cpp
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1 //===---- AVRAsmParser.cpp - Parse AVR assembly to MCInst instructions ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "AVR.h"
10 #include "AVRRegisterInfo.h"
12 #include "MCTargetDesc/AVRMCExpr.h"
14 
15 #include "llvm/ADT/APInt.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstBuilder.h"
24 #include "llvm/MC/MCStreamer.h"
26 #include "llvm/MC/MCSymbol.h"
27 #include "llvm/MC/MCValue.h"
28 #include "llvm/Support/Debug.h"
31 
32 #include <sstream>
33 
34 #define DEBUG_TYPE "avr-asm-parser"
35 
36 using namespace llvm;
37 
38 namespace {
39 /// Parses AVR assembly from a stream.
40 class AVRAsmParser : public MCTargetAsmParser {
41  const MCSubtargetInfo &STI;
42  MCAsmParser &Parser;
43  const MCRegisterInfo *MRI;
44  const std::string GENERATE_STUBS = "gs";
45 
46 #define GET_ASSEMBLER_HEADER
47 #include "AVRGenAsmMatcher.inc"
48 
49  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
50  OperandVector &Operands, MCStreamer &Out,
51  uint64_t &ErrorInfo,
52  bool MatchingInlineAsm) override;
53 
54  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
55 
56  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
57  SMLoc NameLoc, OperandVector &Operands) override;
58 
59  bool ParseDirective(AsmToken DirectiveID) override;
60 
61  OperandMatchResultTy parseMemriOperand(OperandVector &Operands);
62 
63  bool parseOperand(OperandVector &Operands);
64  int parseRegisterName(unsigned (*matchFn)(StringRef));
65  int parseRegisterName();
66  int parseRegister();
67  bool tryParseRegisterOperand(OperandVector &Operands);
68  bool tryParseExpression(OperandVector &Operands);
69  bool tryParseRelocExpression(OperandVector &Operands);
70  void eatComma();
71 
72  unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
73  unsigned Kind) override;
74 
75  unsigned toDREG(unsigned Reg, unsigned From = AVR::sub_lo) {
76  MCRegisterClass const *Class = &AVRMCRegisterClasses[AVR::DREGSRegClassID];
77  return MRI->getMatchingSuperReg(Reg, From, Class);
78  }
79 
80  bool emit(MCInst &Instruction, SMLoc const &Loc, MCStreamer &Out) const;
81  bool invalidOperand(SMLoc const &Loc, OperandVector const &Operands,
82  uint64_t const &ErrorInfo);
83  bool missingFeature(SMLoc const &Loc, uint64_t const &ErrorInfo);
84 
85  bool parseLiteralValues(unsigned SizeInBytes, SMLoc L);
86 
87 public:
88  AVRAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
89  const MCInstrInfo &MII, const MCTargetOptions &Options)
90  : MCTargetAsmParser(Options, STI, MII), STI(STI), Parser(Parser) {
92  MRI = getContext().getRegisterInfo();
93 
94  setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
95  }
96 
97  MCAsmParser &getParser() const { return Parser; }
98  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
99 };
100 
101 /// An parsed AVR assembly operand.
102 class AVROperand : public MCParsedAsmOperand {
103  typedef MCParsedAsmOperand Base;
104  enum KindTy { k_Immediate, k_Register, k_Token, k_Memri } Kind;
105 
106 public:
107  AVROperand(StringRef Tok, SMLoc const &S)
108  : Base(), Kind(k_Token), Tok(Tok), Start(S), End(S) {}
109  AVROperand(unsigned Reg, SMLoc const &S, SMLoc const &E)
110  : Base(), Kind(k_Register), RegImm({Reg, nullptr}), Start(S), End(E) {}
111  AVROperand(MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
112  : Base(), Kind(k_Immediate), RegImm({0, Imm}), Start(S), End(E) {}
113  AVROperand(unsigned Reg, MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
114  : Base(), Kind(k_Memri), RegImm({Reg, Imm}), Start(S), End(E) {}
115 
116  struct RegisterImmediate {
117  unsigned Reg;
118  MCExpr const *Imm;
119  };
120  union {
121  StringRef Tok;
122  RegisterImmediate RegImm;
123  };
124 
125  SMLoc Start, End;
126 
127 public:
128  void addRegOperands(MCInst &Inst, unsigned N) const {
129  assert(Kind == k_Register && "Unexpected operand kind");
130  assert(N == 1 && "Invalid number of operands!");
131 
133  }
134 
135  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
136  // Add as immediate when possible
137  if (!Expr)
139  else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
140  Inst.addOperand(MCOperand::createImm(CE->getValue()));
141  else
142  Inst.addOperand(MCOperand::createExpr(Expr));
143  }
144 
145  void addImmOperands(MCInst &Inst, unsigned N) const {
146  assert(Kind == k_Immediate && "Unexpected operand kind");
147  assert(N == 1 && "Invalid number of operands!");
148 
149  const MCExpr *Expr = getImm();
150  addExpr(Inst, Expr);
151  }
152 
153  /// Adds the contained reg+imm operand to an instruction.
154  void addMemriOperands(MCInst &Inst, unsigned N) const {
155  assert(Kind == k_Memri && "Unexpected operand kind");
156  assert(N == 2 && "Invalid number of operands");
157 
159  addExpr(Inst, getImm());
160  }
161 
162  void addImmCom8Operands(MCInst &Inst, unsigned N) const {
163  assert(N == 1 && "Invalid number of operands!");
164  // The operand is actually a imm8, but we have its bitwise
165  // negation in the assembly source, so twiddle it here.
166  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
167  Inst.addOperand(MCOperand::createImm(~(uint8_t)CE->getValue()));
168  }
169 
170  bool isImmCom8() const {
171  if (!isImm()) return false;
172  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
173  if (!CE) return false;
174  int64_t Value = CE->getValue();
175  return isUInt<8>(Value);
176  }
177 
178  bool isReg() const { return Kind == k_Register; }
179  bool isImm() const { return Kind == k_Immediate; }
180  bool isToken() const { return Kind == k_Token; }
181  bool isMem() const { return Kind == k_Memri; }
182  bool isMemri() const { return Kind == k_Memri; }
183 
184  StringRef getToken() const {
185  assert(Kind == k_Token && "Invalid access!");
186  return Tok;
187  }
188 
189  unsigned getReg() const {
190  assert((Kind == k_Register || Kind == k_Memri) && "Invalid access!");
191 
192  return RegImm.Reg;
193  }
194 
195  const MCExpr *getImm() const {
196  assert((Kind == k_Immediate || Kind == k_Memri) && "Invalid access!");
197  return RegImm.Imm;
198  }
199 
200  static std::unique_ptr<AVROperand> CreateToken(StringRef Str, SMLoc S) {
201  return make_unique<AVROperand>(Str, S);
202  }
203 
204  static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S,
205  SMLoc E) {
206  return make_unique<AVROperand>(RegNum, S, E);
207  }
208 
209  static std::unique_ptr<AVROperand> CreateImm(const MCExpr *Val, SMLoc S,
210  SMLoc E) {
211  return make_unique<AVROperand>(Val, S, E);
212  }
213 
214  static std::unique_ptr<AVROperand>
215  CreateMemri(unsigned RegNum, const MCExpr *Val, SMLoc S, SMLoc E) {
216  return make_unique<AVROperand>(RegNum, Val, S, E);
217  }
218 
219  void makeToken(StringRef Token) {
220  Kind = k_Token;
221  Tok = Token;
222  }
223 
224  void makeReg(unsigned RegNo) {
225  Kind = k_Register;
226  RegImm = {RegNo, nullptr};
227  }
228 
229  void makeImm(MCExpr const *Ex) {
230  Kind = k_Immediate;
231  RegImm = {0, Ex};
232  }
233 
234  void makeMemri(unsigned RegNo, MCExpr const *Imm) {
235  Kind = k_Memri;
236  RegImm = {RegNo, Imm};
237  }
238 
239  SMLoc getStartLoc() const { return Start; }
240  SMLoc getEndLoc() const { return End; }
241 
242  virtual void print(raw_ostream &O) const {
243  switch (Kind) {
244  case k_Token:
245  O << "Token: \"" << getToken() << "\"";
246  break;
247  case k_Register:
248  O << "Register: " << getReg();
249  break;
250  case k_Immediate:
251  O << "Immediate: \"" << *getImm() << "\"";
252  break;
253  case k_Memri: {
254  // only manually print the size for non-negative values,
255  // as the sign is inserted automatically.
256  O << "Memri: \"" << getReg() << '+' << *getImm() << "\"";
257  break;
258  }
259  }
260  O << "\n";
261  }
262 };
263 
264 } // end anonymous namespace.
265 
266 // Auto-generated Match Functions
267 
268 /// Maps from the set of all register names to a register number.
269 /// \note Generated by TableGen.
270 static unsigned MatchRegisterName(StringRef Name);
271 
272 /// Maps from the set of all alternative registernames to a register number.
273 /// \note Generated by TableGen.
274 static unsigned MatchRegisterAltName(StringRef Name);
275 
276 bool AVRAsmParser::invalidOperand(SMLoc const &Loc,
277  OperandVector const &Operands,
278  uint64_t const &ErrorInfo) {
279  SMLoc ErrorLoc = Loc;
280  char const *Diag = 0;
281 
282  if (ErrorInfo != ~0U) {
283  if (ErrorInfo >= Operands.size()) {
284  Diag = "too few operands for instruction.";
285  } else {
286  AVROperand const &Op = (AVROperand const &)*Operands[ErrorInfo];
287 
288  // TODO: See if we can do a better error than just "invalid ...".
289  if (Op.getStartLoc() != SMLoc()) {
290  ErrorLoc = Op.getStartLoc();
291  }
292  }
293  }
294 
295  if (!Diag) {
296  Diag = "invalid operand for instruction";
297  }
298 
299  return Error(ErrorLoc, Diag);
300 }
301 
302 bool AVRAsmParser::missingFeature(llvm::SMLoc const &Loc,
303  uint64_t const &ErrorInfo) {
304  return Error(Loc, "instruction requires a CPU feature not currently enabled");
305 }
306 
307 bool AVRAsmParser::emit(MCInst &Inst, SMLoc const &Loc, MCStreamer &Out) const {
308  Inst.setLoc(Loc);
309  Out.EmitInstruction(Inst, STI);
310 
311  return false;
312 }
313 
314 bool AVRAsmParser::MatchAndEmitInstruction(SMLoc Loc, unsigned &Opcode,
315  OperandVector &Operands,
316  MCStreamer &Out, uint64_t &ErrorInfo,
317  bool MatchingInlineAsm) {
318  MCInst Inst;
319  unsigned MatchResult =
320  MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
321 
322  switch (MatchResult) {
323  case Match_Success: return emit(Inst, Loc, Out);
324  case Match_MissingFeature: return missingFeature(Loc, ErrorInfo);
325  case Match_InvalidOperand: return invalidOperand(Loc, Operands, ErrorInfo);
326  case Match_MnemonicFail: return Error(Loc, "invalid instruction");
327  default: return true;
328  }
329 }
330 
331 /// Parses a register name using a given matching function.
332 /// Checks for lowercase or uppercase if necessary.
333 int AVRAsmParser::parseRegisterName(unsigned (*matchFn)(StringRef)) {
334  StringRef Name = Parser.getTok().getString();
335 
336  int RegNum = matchFn(Name);
337 
338  // GCC supports case insensitive register names. Some of the AVR registers
339  // are all lower case, some are all upper case but non are mixed. We prefer
340  // to use the original names in the register definitions. That is why we
341  // have to test both upper and lower case here.
342  if (RegNum == AVR::NoRegister) {
343  RegNum = matchFn(Name.lower());
344  }
345  if (RegNum == AVR::NoRegister) {
346  RegNum = matchFn(Name.upper());
347  }
348 
349  return RegNum;
350 }
351 
352 int AVRAsmParser::parseRegisterName() {
353  int RegNum = parseRegisterName(&MatchRegisterName);
354 
355  if (RegNum == AVR::NoRegister)
356  RegNum = parseRegisterName(&MatchRegisterAltName);
357 
358  return RegNum;
359 }
360 
361 int AVRAsmParser::parseRegister() {
362  int RegNum = AVR::NoRegister;
363 
364  if (Parser.getTok().is(AsmToken::Identifier)) {
365  // Check for register pair syntax
366  if (Parser.getLexer().peekTok().is(AsmToken::Colon)) {
367  Parser.Lex();
368  Parser.Lex(); // Eat high (odd) register and colon
369 
370  if (Parser.getTok().is(AsmToken::Identifier)) {
371  // Convert lower (even) register to DREG
372  RegNum = toDREG(parseRegisterName());
373  }
374  } else {
375  RegNum = parseRegisterName();
376  }
377  }
378  return RegNum;
379 }
380 
381 bool AVRAsmParser::tryParseRegisterOperand(OperandVector &Operands) {
382  int RegNo = parseRegister();
383 
384  if (RegNo == AVR::NoRegister)
385  return true;
386 
387  AsmToken const &T = Parser.getTok();
388  Operands.push_back(AVROperand::CreateReg(RegNo, T.getLoc(), T.getEndLoc()));
389  Parser.Lex(); // Eat register token.
390 
391  return false;
392 }
393 
394 bool AVRAsmParser::tryParseExpression(OperandVector &Operands) {
395  SMLoc S = Parser.getTok().getLoc();
396 
397  if (!tryParseRelocExpression(Operands))
398  return false;
399 
400  if ((Parser.getTok().getKind() == AsmToken::Plus ||
401  Parser.getTok().getKind() == AsmToken::Minus) &&
402  Parser.getLexer().peekTok().getKind() == AsmToken::Identifier) {
403  // Don't handle this case - it should be split into two
404  // separate tokens.
405  return true;
406  }
407 
408  // Parse (potentially inner) expression
409  MCExpr const *Expression;
410  if (getParser().parseExpression(Expression))
411  return true;
412 
413  SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
414  Operands.push_back(AVROperand::CreateImm(Expression, S, E));
415  return false;
416 }
417 
418 bool AVRAsmParser::tryParseRelocExpression(OperandVector &Operands) {
419  bool isNegated = false;
421 
422  SMLoc S = Parser.getTok().getLoc();
423 
424  // Check for sign
425  AsmToken tokens[2];
426  size_t ReadCount = Parser.getLexer().peekTokens(tokens);
427 
428  if (ReadCount == 2) {
429  if ((tokens[0].getKind() == AsmToken::Identifier &&
430  tokens[1].getKind() == AsmToken::LParen) ||
431  (tokens[0].getKind() == AsmToken::LParen &&
432  tokens[1].getKind() == AsmToken::Minus)) {
433 
434  AsmToken::TokenKind CurTok = Parser.getLexer().getKind();
435  if (CurTok == AsmToken::Minus ||
436  tokens[1].getKind() == AsmToken::Minus) {
437  isNegated = true;
438  } else {
439  assert(CurTok == AsmToken::Plus);
440  isNegated = false;
441  }
442 
443  // Eat the sign
444  if (CurTok == AsmToken::Minus || CurTok == AsmToken::Plus)
445  Parser.Lex();
446  }
447  }
448 
449  // Check if we have a target specific modifier (lo8, hi8, &c)
450  if (Parser.getTok().getKind() != AsmToken::Identifier ||
451  Parser.getLexer().peekTok().getKind() != AsmToken::LParen) {
452  // Not a reloc expr
453  return true;
454  }
455  StringRef ModifierName = Parser.getTok().getString();
456  ModifierKind = AVRMCExpr::getKindByName(ModifierName.str().c_str());
457 
458  if (ModifierKind != AVRMCExpr::VK_AVR_None) {
459  Parser.Lex();
460  Parser.Lex(); // Eat modifier name and parenthesis
461  if (Parser.getTok().getString() == GENERATE_STUBS &&
462  Parser.getTok().getKind() == AsmToken::Identifier) {
463  std::string GSModName = ModifierName.str() + "_" + GENERATE_STUBS;
464  ModifierKind = AVRMCExpr::getKindByName(GSModName.c_str());
465  if (ModifierKind != AVRMCExpr::VK_AVR_None)
466  Parser.Lex(); // Eat gs modifier name
467  }
468  } else {
469  return Error(Parser.getTok().getLoc(), "unknown modifier");
470  }
471 
472  if (tokens[1].getKind() == AsmToken::Minus ||
473  tokens[1].getKind() == AsmToken::Plus) {
474  Parser.Lex();
475  assert(Parser.getTok().getKind() == AsmToken::LParen);
476  Parser.Lex(); // Eat the sign and parenthesis
477  }
478 
479  MCExpr const *InnerExpression;
480  if (getParser().parseExpression(InnerExpression))
481  return true;
482 
483  if (tokens[1].getKind() == AsmToken::Minus ||
484  tokens[1].getKind() == AsmToken::Plus) {
485  assert(Parser.getTok().getKind() == AsmToken::RParen);
486  Parser.Lex(); // Eat closing parenthesis
487  }
488 
489  // If we have a modifier wrap the inner expression
490  assert(Parser.getTok().getKind() == AsmToken::RParen);
491  Parser.Lex(); // Eat closing parenthesis
492 
493  MCExpr const *Expression = AVRMCExpr::create(ModifierKind, InnerExpression,
494  isNegated, getContext());
495 
496  SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
497  Operands.push_back(AVROperand::CreateImm(Expression, S, E));
498 
499  return false;
500 }
501 
502 bool AVRAsmParser::parseOperand(OperandVector &Operands) {
503  LLVM_DEBUG(dbgs() << "parseOperand\n");
504 
505  switch (getLexer().getKind()) {
506  default:
507  return Error(Parser.getTok().getLoc(), "unexpected token in operand");
508 
510  // Try to parse a register, if it fails,
511  // fall through to the next case.
512  if (!tryParseRegisterOperand(Operands)) {
513  return false;
514  }
516  case AsmToken::LParen:
517  case AsmToken::Integer:
518  case AsmToken::Dot:
519  return tryParseExpression(Operands);
520  case AsmToken::Plus:
521  case AsmToken::Minus: {
522  // If the sign preceeds a number, parse the number,
523  // otherwise treat the sign a an independent token.
524  switch (getLexer().peekTok().getKind()) {
525  case AsmToken::Integer:
526  case AsmToken::BigNum:
528  case AsmToken::Real:
529  if (!tryParseExpression(Operands))
530  return false;
531  break;
532  default:
533  break;
534  }
535  // Treat the token as an independent token.
536  Operands.push_back(AVROperand::CreateToken(Parser.getTok().getString(),
537  Parser.getTok().getLoc()));
538  Parser.Lex(); // Eat the token.
539  return false;
540  }
541  }
542 
543  // Could not parse operand
544  return true;
545 }
546 
548 AVRAsmParser::parseMemriOperand(OperandVector &Operands) {
549  LLVM_DEBUG(dbgs() << "parseMemriOperand()\n");
550 
551  SMLoc E, S;
552  MCExpr const *Expression;
553  int RegNo;
554 
555  // Parse register.
556  {
557  RegNo = parseRegister();
558 
559  if (RegNo == AVR::NoRegister)
560  return MatchOperand_ParseFail;
561 
562  S = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
563  Parser.Lex(); // Eat register token.
564  }
565 
566  // Parse immediate;
567  {
568  if (getParser().parseExpression(Expression))
569  return MatchOperand_ParseFail;
570 
571  E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
572  }
573 
574  Operands.push_back(AVROperand::CreateMemri(RegNo, Expression, S, E));
575 
576  return MatchOperand_Success;
577 }
578 
579 bool AVRAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
580  SMLoc &EndLoc) {
581  StartLoc = Parser.getTok().getLoc();
582  RegNo = parseRegister();
583  EndLoc = Parser.getTok().getLoc();
584 
585  return (RegNo == AVR::NoRegister);
586 }
587 
588 void AVRAsmParser::eatComma() {
589  if (getLexer().is(AsmToken::Comma)) {
590  Parser.Lex();
591  } else {
592  // GCC allows commas to be omitted.
593  }
594 }
595 
596 bool AVRAsmParser::ParseInstruction(ParseInstructionInfo &Info,
597  StringRef Mnemonic, SMLoc NameLoc,
598  OperandVector &Operands) {
599  Operands.push_back(AVROperand::CreateToken(Mnemonic, NameLoc));
600 
601  bool first = true;
602  while (getLexer().isNot(AsmToken::EndOfStatement)) {
603  if (!first) eatComma();
604 
605  first = false;
606 
607  auto MatchResult = MatchOperandParserImpl(Operands, Mnemonic);
608 
609  if (MatchResult == MatchOperand_Success) {
610  continue;
611  }
612 
613  if (MatchResult == MatchOperand_ParseFail) {
614  SMLoc Loc = getLexer().getLoc();
615  Parser.eatToEndOfStatement();
616 
617  return Error(Loc, "failed to parse register and immediate pair");
618  }
619 
620  if (parseOperand(Operands)) {
621  SMLoc Loc = getLexer().getLoc();
622  Parser.eatToEndOfStatement();
623  return Error(Loc, "unexpected token in argument list");
624  }
625  }
626  Parser.Lex(); // Consume the EndOfStatement
627  return false;
628 }
629 
630 bool AVRAsmParser::ParseDirective(llvm::AsmToken DirectiveID) {
631  StringRef IDVal = DirectiveID.getIdentifier();
632  if (IDVal.lower() == ".long") {
633  parseLiteralValues(SIZE_LONG, DirectiveID.getLoc());
634  } else if (IDVal.lower() == ".word" || IDVal.lower() == ".short") {
635  parseLiteralValues(SIZE_WORD, DirectiveID.getLoc());
636  } else if (IDVal.lower() == ".byte") {
637  parseLiteralValues(1, DirectiveID.getLoc());
638  }
639  return true;
640 }
641 
642 bool AVRAsmParser::parseLiteralValues(unsigned SizeInBytes, SMLoc L) {
643  MCAsmParser &Parser = getParser();
644  AVRMCELFStreamer &AVRStreamer =
645  static_cast<AVRMCELFStreamer &>(Parser.getStreamer());
646  AsmToken Tokens[2];
647  size_t ReadCount = Parser.getLexer().peekTokens(Tokens);
648  if (ReadCount == 2 && Parser.getTok().getKind() == AsmToken::Identifier &&
649  Tokens[0].getKind() == AsmToken::Minus &&
650  Tokens[1].getKind() == AsmToken::Identifier) {
651  MCSymbol *Symbol = getContext().getOrCreateSymbol(".text");
652  AVRStreamer.EmitValueForModiferKind(Symbol, SizeInBytes, L,
654  return false;
655  }
656 
657  if (Parser.getTok().getKind() == AsmToken::Identifier &&
658  Parser.getLexer().peekTok().getKind() == AsmToken::LParen) {
659  StringRef ModifierName = Parser.getTok().getString();
660  AVRMCExpr::VariantKind ModifierKind =
661  AVRMCExpr::getKindByName(ModifierName.str().c_str());
662  if (ModifierKind != AVRMCExpr::VK_AVR_None) {
663  Parser.Lex();
664  Parser.Lex(); // Eat the modifier and parenthesis
665  } else {
666  return Error(Parser.getTok().getLoc(), "unknown modifier");
667  }
668  MCSymbol *Symbol =
669  getContext().getOrCreateSymbol(Parser.getTok().getString());
670  AVRStreamer.EmitValueForModiferKind(Symbol, SizeInBytes, L, ModifierKind);
671  return false;
672  }
673 
674  auto parseOne = [&]() -> bool {
675  const MCExpr *Value;
676  if (Parser.parseExpression(Value))
677  return true;
678  Parser.getStreamer().EmitValue(Value, SizeInBytes, L);
679  return false;
680  };
681  return (parseMany(parseOne));
682 }
683 
684 extern "C" void LLVMInitializeAVRAsmParser() {
686 }
687 
688 #define GET_REGISTER_MATCHER
689 #define GET_MATCHER_IMPLEMENTATION
690 #include "AVRGenAsmMatcher.inc"
691 
692 // Uses enums defined in AVRGenAsmMatcher.inc
693 unsigned AVRAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
694  unsigned ExpectedKind) {
695  AVROperand &Op = static_cast<AVROperand &>(AsmOp);
696  MatchClassKind Expected = static_cast<MatchClassKind>(ExpectedKind);
697 
698  // If need be, GCC converts bare numbers to register names
699  // It's ugly, but GCC supports it.
700  if (Op.isImm()) {
701  if (MCConstantExpr const *Const = dyn_cast<MCConstantExpr>(Op.getImm())) {
702  int64_t RegNum = Const->getValue();
703  std::ostringstream RegName;
704  RegName << "r" << RegNum;
705  RegNum = MatchRegisterName(RegName.str().c_str());
706  if (RegNum != AVR::NoRegister) {
707  Op.makeReg(RegNum);
708  if (validateOperandClass(Op, Expected) == Match_Success) {
709  return Match_Success;
710  }
711  }
712  // Let the other quirks try their magic.
713  }
714  }
715 
716  if (Op.isReg()) {
717  // If the instruction uses a register pair but we got a single, lower
718  // register we perform a "class cast".
719  if (isSubclass(Expected, MCK_DREGS)) {
720  unsigned correspondingDREG = toDREG(Op.getReg());
721 
722  if (correspondingDREG != AVR::NoRegister) {
723  Op.makeReg(correspondingDREG);
724  return validateOperandClass(Op, Expected);
725  }
726  }
727  }
728  return Match_InvalidOperand;
729 }
static bool isReg(const MCInst &MI, unsigned OpNo)
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
Definition: MCAsmMacro.h:110
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:218
This class represents lattice values for constants.
Definition: AllocatorList.h:23
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
Generic assembler parser interface, for use by target specific assembly parsers.
Definition: MCAsmParser.h:109
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
virtual void Initialize(MCAsmParser &Parser)
Initialize the extension for parsing using the given Parser.
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:136
MCTargetAsmParser - Generic interface to target specific assembly parsers.
void push_back(const T &Elt)
Definition: SmallVector.h:211
unsigned Reg
const int SIZE_WORD
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
const int SIZE_LONG
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Definition: MCAsmParser.cpp:33
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:960
Target & getTheAVRTarget()
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string...
Definition: MCAsmMacro.h:99
VariantKind
Specifies the type of an expression.
Definition: AVRMCExpr.h:22
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:115
const FeatureBitset & getFeatureBits() const
Generic assembler lexer interface, for use by target specific assembly lexers.
Definition: MCAsmLexer.h:39
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Target independent representation for an assembler token.
Definition: MCAsmMacro.h:21
Tagged union holding either a T or a Error.
Definition: CachePruning.h:22
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:122
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand...
This file implements a class to represent arbitrary precision integral constant values and operations...
virtual bool parseExpression(const MCExpr *&Res, SMLoc &EndLoc)=0
Parse an arbitrary expression.
std::pair< StringRef, StringRef > getToken(StringRef Source, StringRef Delimiters=" \\\)
getToken - This function extracts one token from source, ignoring any leading characters that appear ...
RegisterMCAsmParser - Helper template for registering a target specific assembly parser, for use in the target machine initialization function.
SMLoc getLoc() const
Definition: MCAsmLexer.cpp:27
MCRegisterClass - Base class of TargetRegisterClass.
LLVM_NODISCARD std::string upper() const
Convert the given ASCII string to uppercase.
Definition: StringRef.cpp:115
void EmitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:159
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
virtual void eatToEndOfStatement()=0
Skip to the end of the current statement, for error recovery.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const char * getPointer() const
Definition: SMLoc.h:34
int64_t getValue() const
Definition: MCExpr.h:151
Streaming machine code generation interface.
Definition: MCStreamer.h:188
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:342
unsigned const MachineRegisterInfo * MRI
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
SMLoc getEndLoc() const
Definition: MCAsmLexer.cpp:31
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
virtual MCAsmLexer & getLexer()=0
void LLVMInitializeAVRAsmParser()
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
const AsmToken peekTok(bool ShouldSkipSpace=true)
Look ahead at the next token to be lexed.
Definition: MCAsmLexer.h:105
size_t size() const
Definition: SmallVector.h:52
void setLoc(SMLoc loc)
Definition: MCInst.h:176
static unsigned MatchRegisterAltName(StringRef Name)
Maps from the set of all alternative registernames to a register number.
unsigned first
AsmToken::TokenKind getKind() const
Get the kind of current token.
Definition: MCAsmLexer.h:132
BlockVerifier::State From
virtual MCStreamer & getStreamer()=0
Return the output streamer for the assembler.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
bool is(TokenKind K) const
Definition: MCAsmMacro.h:82
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Base class for user error types.
Definition: Error.h:344
static unsigned MatchRegisterName(StringRef Name)
Maps from the set of all register names to a register number.
static SMLoc getFromPointer(const char *Ptr)
Definition: SMLoc.h:36
#define N
Generic base class for all target subtargets.
static const AVRMCExpr * create(VariantKind Kind, const MCExpr *Expr, bool isNegated, MCContext &Ctx)
Creates an AVR machine code expression.
Definition: AVRMCExpr.cpp:38
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
static VariantKind getKindByName(StringRef Name)
Definition: AVRMCExpr.cpp:202
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:107
void EmitValueForModiferKind(const MCSymbol *Sym, unsigned SizeInBytes, SMLoc Loc=SMLoc(), AVRMCExpr::VariantKind ModifierKind=AVRMCExpr::VK_AVR_None)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:72
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
virtual size_t peekTokens(MutableArrayRef< AsmToken > Buf, bool ShouldSkipSpace=true)=0
Look ahead an arbitrary number of tokens.
Represents a location in source code.
Definition: SMLoc.h:23
#define LLVM_DEBUG(X)
Definition: Debug.h:122
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:122
TokenKind getKind() const
Definition: MCAsmMacro.h:81