LLVM  6.0.0svn
AVRAsmParser.cpp
Go to the documentation of this file.
1 //===---- AVRAsmParser.cpp - Parse AVR assembly to MCInst instructions ----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "AVR.h"
11 #include "AVRRegisterInfo.h"
12 #include "MCTargetDesc/AVRMCExpr.h"
14 
15 #include "llvm/ADT/APInt.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstBuilder.h"
24 #include "llvm/MC/MCStreamer.h"
26 #include "llvm/MC/MCSymbol.h"
27 #include "llvm/MC/MCValue.h"
28 #include "llvm/Support/Debug.h"
31 
32 #include <sstream>
33 
34 #define DEBUG_TYPE "avr-asm-parser"
35 
36 namespace llvm {
37 
38 /// Parses AVR assembly from a stream.
40  const MCSubtargetInfo &STI;
41  MCAsmParser &Parser;
42  const MCRegisterInfo *MRI;
43 
44 #define GET_ASSEMBLER_HEADER
45 #include "AVRGenAsmMatcher.inc"
46 
47  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
48  OperandVector &Operands, MCStreamer &Out,
49  uint64_t &ErrorInfo,
50  bool MatchingInlineAsm) override;
51 
52  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
53 
54  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
55  SMLoc NameLoc, OperandVector &Operands) override;
56 
57  bool ParseDirective(AsmToken directiveID) override;
58 
59  OperandMatchResultTy parseMemriOperand(OperandVector &Operands);
60 
61  bool parseOperand(OperandVector &Operands);
62  int parseRegisterName(unsigned (*matchFn)(StringRef));
63  int parseRegisterName();
64  int parseRegister();
65  bool tryParseRegisterOperand(OperandVector &Operands);
66  bool tryParseExpression(OperandVector &Operands);
67  bool tryParseRelocExpression(OperandVector &Operands);
68  void eatComma();
69 
70  unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
71  unsigned Kind) override;
72 
73  unsigned toDREG(unsigned Reg, unsigned From = AVR::sub_lo) {
74  MCRegisterClass const *Class = &AVRMCRegisterClasses[AVR::DREGSRegClassID];
75  return MRI->getMatchingSuperReg(Reg, From, Class);
76  }
77 
78  bool emit(MCInst &Instruction, SMLoc const &Loc, MCStreamer &Out) const;
79  bool invalidOperand(SMLoc const &Loc, OperandVector const &Operands,
80  uint64_t const &ErrorInfo);
81  bool missingFeature(SMLoc const &Loc, uint64_t const &ErrorInfo);
82 
83 public:
85  const MCInstrInfo &MII, const MCTargetOptions &Options)
86  : MCTargetAsmParser(Options, STI, MII), STI(STI), Parser(Parser) {
88  MRI = getContext().getRegisterInfo();
89 
90  setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
91  }
92 
93  MCAsmParser &getParser() const { return Parser; }
94  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
95 };
96 
97 /// An parsed AVR assembly operand.
99  typedef MCParsedAsmOperand Base;
100  enum KindTy { k_Immediate, k_Register, k_Token, k_Memri } Kind;
101 
102 public:
103  AVROperand(StringRef Tok, SMLoc const &S)
104  : Base(), Kind(k_Token), Tok(Tok), Start(S), End(S) {}
105  AVROperand(unsigned Reg, SMLoc const &S, SMLoc const &E)
106  : Base(), Kind(k_Register), RegImm({Reg, nullptr}), Start(S), End(E) {}
107  AVROperand(MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
108  : Base(), Kind(k_Immediate), RegImm({0, Imm}), Start(S), End(E) {}
109  AVROperand(unsigned Reg, MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
110  : Base(), Kind(k_Memri), RegImm({Reg, Imm}), Start(S), End(E) {}
111 
113  unsigned Reg;
114  MCExpr const *Imm;
115  };
116  union {
119  };
120 
122 
123 public:
124  void addRegOperands(MCInst &Inst, unsigned N) const {
125  assert(Kind == k_Register && "Unexpected operand kind");
126  assert(N == 1 && "Invalid number of operands!");
127 
129  }
130 
131  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
132  // Add as immediate when possible
133  if (!Expr)
135  else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
136  Inst.addOperand(MCOperand::createImm(CE->getValue()));
137  else
138  Inst.addOperand(MCOperand::createExpr(Expr));
139  }
140 
141  void addImmOperands(MCInst &Inst, unsigned N) const {
142  assert(Kind == k_Immediate && "Unexpected operand kind");
143  assert(N == 1 && "Invalid number of operands!");
144 
145  const MCExpr *Expr = getImm();
146  addExpr(Inst, Expr);
147  }
148 
149  /// Adds the contained reg+imm operand to an instruction.
150  void addMemriOperands(MCInst &Inst, unsigned N) const {
151  assert(Kind == k_Memri && "Unexpected operand kind");
152  assert(N == 2 && "Invalid number of operands");
153 
155  addExpr(Inst, getImm());
156  }
157 
158  bool isReg() const { return Kind == k_Register; }
159  bool isImm() const { return Kind == k_Immediate; }
160  bool isToken() const { return Kind == k_Token; }
161  bool isMem() const { return Kind == k_Memri; }
162  bool isMemri() const { return Kind == k_Memri; }
163 
164  StringRef getToken() const {
165  assert(Kind == k_Token && "Invalid access!");
166  return Tok;
167  }
168 
169  unsigned getReg() const {
170  assert((Kind == k_Register || Kind == k_Memri) && "Invalid access!");
171 
172  return RegImm.Reg;
173  }
174 
175  const MCExpr *getImm() const {
176  assert((Kind == k_Immediate || Kind == k_Memri) && "Invalid access!");
177  return RegImm.Imm;
178  }
179 
180  static std::unique_ptr<AVROperand> CreateToken(StringRef Str, SMLoc S) {
181  return make_unique<AVROperand>(Str, S);
182  }
183 
184  static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S,
185  SMLoc E) {
186  return make_unique<AVROperand>(RegNum, S, E);
187  }
188 
189  static std::unique_ptr<AVROperand> CreateImm(const MCExpr *Val, SMLoc S,
190  SMLoc E) {
191  return make_unique<AVROperand>(Val, S, E);
192  }
193 
194  static std::unique_ptr<AVROperand>
195  CreateMemri(unsigned RegNum, const MCExpr *Val, SMLoc S, SMLoc E) {
196  return make_unique<AVROperand>(RegNum, Val, S, E);
197  }
198 
199  void makeToken(StringRef Token) {
200  Kind = k_Token;
201  Tok = Token;
202  }
203 
204  void makeReg(unsigned RegNo) {
205  Kind = k_Register;
206  RegImm = {RegNo, nullptr};
207  }
208 
209  void makeImm(MCExpr const *Ex) {
210  Kind = k_Immediate;
211  RegImm = {0, Ex};
212  }
213 
214  void makeMemri(unsigned RegNo, MCExpr const *Imm) {
215  Kind = k_Memri;
216  RegImm = {RegNo, Imm};
217  }
218 
219  SMLoc getStartLoc() const { return Start; }
220  SMLoc getEndLoc() const { return End; }
221 
222  virtual void print(raw_ostream &O) const {
223  switch (Kind) {
224  case k_Token:
225  O << "Token: \"" << getToken() << "\"";
226  break;
227  case k_Register:
228  O << "Register: " << getReg();
229  break;
230  case k_Immediate:
231  O << "Immediate: \"" << *getImm() << "\"";
232  break;
233  case k_Memri: {
234  // only manually print the size for non-negative values,
235  // as the sign is inserted automatically.
236  O << "Memri: \"" << getReg() << '+' << *getImm() << "\"";
237  break;
238  }
239  }
240  O << "\n";
241  }
242 };
243 
244 // Auto-generated Match Functions
245 
246 /// Maps from the set of all register names to a register number.
247 /// \note Generated by TableGen.
248 static unsigned MatchRegisterName(StringRef Name);
249 
250 /// Maps from the set of all alternative registernames to a register number.
251 /// \note Generated by TableGen.
252 static unsigned MatchRegisterAltName(StringRef Name);
253 
254 bool AVRAsmParser::invalidOperand(SMLoc const &Loc,
255  OperandVector const &Operands,
256  uint64_t const &ErrorInfo) {
257  SMLoc ErrorLoc = Loc;
258  char const *Diag = 0;
259 
260  if (ErrorInfo != ~0U) {
261  if (ErrorInfo >= Operands.size()) {
262  Diag = "too few operands for instruction.";
263  } else {
264  AVROperand const &Op = (AVROperand const &)*Operands[ErrorInfo];
265 
266  // TODO: See if we can do a better error than just "invalid ...".
267  if (Op.getStartLoc() != SMLoc()) {
268  ErrorLoc = Op.getStartLoc();
269  }
270  }
271  }
272 
273  if (!Diag) {
274  Diag = "invalid operand for instruction";
275  }
276 
277  return Error(ErrorLoc, Diag);
278 }
279 
280 bool AVRAsmParser::missingFeature(llvm::SMLoc const &Loc,
281  uint64_t const &ErrorInfo) {
282  return Error(Loc, "instruction requires a CPU feature not currently enabled");
283 }
284 
285 bool AVRAsmParser::emit(MCInst &Inst, SMLoc const &Loc, MCStreamer &Out) const {
286  Inst.setLoc(Loc);
287  Out.EmitInstruction(Inst, STI);
288 
289  return false;
290 }
291 
292 bool AVRAsmParser::MatchAndEmitInstruction(SMLoc Loc, unsigned &Opcode,
293  OperandVector &Operands,
294  MCStreamer &Out, uint64_t &ErrorInfo,
295  bool MatchingInlineAsm) {
296  MCInst Inst;
297  unsigned MatchResult =
298  MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
299 
300  switch (MatchResult) {
301  case Match_Success: return emit(Inst, Loc, Out);
302  case Match_MissingFeature: return missingFeature(Loc, ErrorInfo);
303  case Match_InvalidOperand: return invalidOperand(Loc, Operands, ErrorInfo);
304  case Match_MnemonicFail: return Error(Loc, "invalid instruction");
305  default: return true;
306  }
307 }
308 
309 /// Parses a register name using a given matching function.
310 /// Checks for lowercase or uppercase if necessary.
311 int AVRAsmParser::parseRegisterName(unsigned (*matchFn)(StringRef)) {
312  StringRef Name = Parser.getTok().getString();
313 
314  int RegNum = matchFn(Name);
315 
316  // GCC supports case insensitive register names. Some of the AVR registers
317  // are all lower case, some are all upper case but non are mixed. We prefer
318  // to use the original names in the register definitions. That is why we
319  // have to test both upper and lower case here.
320  if (RegNum == AVR::NoRegister) {
321  RegNum = matchFn(Name.lower());
322  }
323  if (RegNum == AVR::NoRegister) {
324  RegNum = matchFn(Name.upper());
325  }
326 
327  return RegNum;
328 }
329 
330 int AVRAsmParser::parseRegisterName() {
331  int RegNum = parseRegisterName(&MatchRegisterName);
332 
333  if (RegNum == AVR::NoRegister)
334  RegNum = parseRegisterName(&MatchRegisterAltName);
335 
336  return RegNum;
337 }
338 
339 int AVRAsmParser::parseRegister() {
340  int RegNum = AVR::NoRegister;
341 
342  if (Parser.getTok().is(AsmToken::Identifier)) {
343  // Check for register pair syntax
344  if (Parser.getLexer().peekTok().is(AsmToken::Colon)) {
345  Parser.Lex();
346  Parser.Lex(); // Eat high (odd) register and colon
347 
348  if (Parser.getTok().is(AsmToken::Identifier)) {
349  // Convert lower (even) register to DREG
350  RegNum = toDREG(parseRegisterName());
351  }
352  } else {
353  RegNum = parseRegisterName();
354  }
355  }
356  return RegNum;
357 }
358 
359 bool AVRAsmParser::tryParseRegisterOperand(OperandVector &Operands) {
360  int RegNo = parseRegister();
361 
362  if (RegNo == AVR::NoRegister)
363  return true;
364 
365  AsmToken const &T = Parser.getTok();
366  Operands.push_back(AVROperand::CreateReg(RegNo, T.getLoc(), T.getEndLoc()));
367  Parser.Lex(); // Eat register token.
368 
369  return false;
370 }
371 
372 bool AVRAsmParser::tryParseExpression(OperandVector &Operands) {
373  SMLoc S = Parser.getTok().getLoc();
374 
375  if (!tryParseRelocExpression(Operands))
376  return false;
377 
378  if ((Parser.getTok().getKind() == AsmToken::Plus ||
379  Parser.getTok().getKind() == AsmToken::Minus) &&
380  Parser.getLexer().peekTok().getKind() == AsmToken::Identifier) {
381  // Don't handle this case - it should be split into two
382  // separate tokens.
383  return true;
384  }
385 
386  // Parse (potentially inner) expression
387  MCExpr const *Expression;
388  if (getParser().parseExpression(Expression))
389  return true;
390 
391  SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
392  Operands.push_back(AVROperand::CreateImm(Expression, S, E));
393  return false;
394 }
395 
396 bool AVRAsmParser::tryParseRelocExpression(OperandVector &Operands) {
397  bool isNegated = false;
399 
400  SMLoc S = Parser.getTok().getLoc();
401 
402  // Check for sign
403  AsmToken tokens[2];
404  size_t ReadCount = Parser.getLexer().peekTokens(tokens);
405 
406  if (ReadCount == 2) {
407  if (tokens[0].getKind() == AsmToken::Identifier &&
408  tokens[1].getKind() == AsmToken::LParen) {
409 
410  AsmToken::TokenKind CurTok = Parser.getLexer().getKind();
411  if (CurTok == AsmToken::Minus) {
412  isNegated = true;
413  } else {
414  assert(CurTok == AsmToken::Plus);
415  isNegated = false;
416  }
417 
418  // Eat the sign
419  Parser.Lex();
420  }
421  }
422 
423  // Check if we have a target specific modifier (lo8, hi8, &c)
424  if (Parser.getTok().getKind() != AsmToken::Identifier ||
425  Parser.getLexer().peekTok().getKind() != AsmToken::LParen) {
426  // Not a reloc expr
427  return true;
428  }
429  StringRef ModifierName = Parser.getTok().getString();
430  ModifierKind = AVRMCExpr::getKindByName(ModifierName.str().c_str());
431 
432  if (ModifierKind != AVRMCExpr::VK_AVR_None) {
433  Parser.Lex();
434  Parser.Lex(); // Eat modifier name and parenthesis
435  } else {
436  return Error(Parser.getTok().getLoc(), "unknown modifier");
437  }
438 
439  MCExpr const *InnerExpression;
440  if (getParser().parseExpression(InnerExpression))
441  return true;
442 
443  // If we have a modifier wrap the inner expression
444  assert(Parser.getTok().getKind() == AsmToken::RParen);
445  Parser.Lex(); // Eat closing parenthesis
446 
447  MCExpr const *Expression = AVRMCExpr::create(ModifierKind, InnerExpression,
448  isNegated, getContext());
449 
450  SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
451  Operands.push_back(AVROperand::CreateImm(Expression, S, E));
452 
453  return false;
454 }
455 
456 bool AVRAsmParser::parseOperand(OperandVector &Operands) {
457  DEBUG(dbgs() << "parseOperand\n");
458 
459  switch (getLexer().getKind()) {
460  default:
461  return Error(Parser.getTok().getLoc(), "unexpected token in operand");
462 
464  // Try to parse a register, if it fails,
465  // fall through to the next case.
466  if (!tryParseRegisterOperand(Operands)) {
467  return false;
468  }
470  case AsmToken::LParen:
471  case AsmToken::Integer:
472  case AsmToken::Dot:
473  return tryParseExpression(Operands);
474  case AsmToken::Plus:
475  case AsmToken::Minus: {
476  // If the sign preceeds a number, parse the number,
477  // otherwise treat the sign a an independent token.
478  switch (getLexer().peekTok().getKind()) {
479  case AsmToken::Integer:
480  case AsmToken::BigNum:
482  case AsmToken::Real:
483  if (!tryParseExpression(Operands))
484  return false;
485  default:
486  break;
487  }
488  // Treat the token as an independent token.
490  Parser.getTok().getLoc()));
491  Parser.Lex(); // Eat the token.
492  return false;
493  }
494  }
495 
496  // Could not parse operand
497  return true;
498 }
499 
501 AVRAsmParser::parseMemriOperand(OperandVector &Operands) {
502  DEBUG(dbgs() << "parseMemriOperand()\n");
503 
504  SMLoc E, S;
505  MCExpr const *Expression;
506  int RegNo;
507 
508  // Parse register.
509  {
510  RegNo = parseRegister();
511 
512  if (RegNo == AVR::NoRegister)
513  return MatchOperand_ParseFail;
514 
515  S = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
516  Parser.Lex(); // Eat register token.
517  }
518 
519  // Parse immediate;
520  {
521  if (getParser().parseExpression(Expression))
522  return MatchOperand_ParseFail;
523 
524  E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
525  }
526 
527  Operands.push_back(AVROperand::CreateMemri(RegNo, Expression, S, E));
528 
529  return MatchOperand_Success;
530 }
531 
532 bool AVRAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
533  SMLoc &EndLoc) {
534  StartLoc = Parser.getTok().getLoc();
535  RegNo = parseRegister();
536  EndLoc = Parser.getTok().getLoc();
537 
538  return (RegNo == AVR::NoRegister);
539 }
540 
541 void AVRAsmParser::eatComma() {
542  if (getLexer().is(AsmToken::Comma)) {
543  Parser.Lex();
544  } else {
545  // GCC allows commas to be omitted.
546  }
547 }
548 
549 bool AVRAsmParser::ParseInstruction(ParseInstructionInfo &Info,
550  StringRef Mnemonic, SMLoc NameLoc,
551  OperandVector &Operands) {
552  Operands.push_back(AVROperand::CreateToken(Mnemonic, NameLoc));
553 
554  bool first = true;
555  while (getLexer().isNot(AsmToken::EndOfStatement)) {
556  if (!first) eatComma();
557 
558  first = false;
559 
560  auto MatchResult = MatchOperandParserImpl(Operands, Mnemonic);
561 
562  if (MatchResult == MatchOperand_Success) {
563  continue;
564  }
565 
566  if (MatchResult == MatchOperand_ParseFail) {
567  SMLoc Loc = getLexer().getLoc();
568  Parser.eatToEndOfStatement();
569 
570  return Error(Loc, "failed to parse register and immediate pair");
571  }
572 
573  if (parseOperand(Operands)) {
574  SMLoc Loc = getLexer().getLoc();
575  Parser.eatToEndOfStatement();
576  return Error(Loc, "unexpected token in argument list");
577  }
578  }
579  Parser.Lex(); // Consume the EndOfStatement
580  return false;
581 }
582 
583 bool AVRAsmParser::ParseDirective(llvm::AsmToken DirectiveID) { return true; }
584 
585 extern "C" void LLVMInitializeAVRAsmParser() {
587 }
588 
589 #define GET_REGISTER_MATCHER
590 #define GET_MATCHER_IMPLEMENTATION
591 #include "AVRGenAsmMatcher.inc"
592 
593 // Uses enums defined in AVRGenAsmMatcher.inc
594 unsigned AVRAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
595  unsigned ExpectedKind) {
596  AVROperand &Op = static_cast<AVROperand &>(AsmOp);
597  MatchClassKind Expected = static_cast<MatchClassKind>(ExpectedKind);
598 
599  // If need be, GCC converts bare numbers to register names
600  // It's ugly, but GCC supports it.
601  if (Op.isImm()) {
602  if (MCConstantExpr const *Const = dyn_cast<MCConstantExpr>(Op.getImm())) {
603  int64_t RegNum = Const->getValue();
604  std::ostringstream RegName;
605  RegName << "r" << RegNum;
606  RegNum = MatchRegisterName(RegName.str().c_str());
607  if (RegNum != AVR::NoRegister) {
608  Op.makeReg(RegNum);
609  if (validateOperandClass(Op, Expected) == Match_Success) {
610  return Match_Success;
611  }
612  }
613  // Let the other quirks try their magic.
614  }
615  }
616 
617  if (Op.isReg()) {
618  // If the instruction uses a register pair but we got a single, lower
619  // register we perform a "class cast".
620  if (isSubclass(Expected, MCK_DREGS)) {
621  unsigned correspondingDREG = toDREG(Op.getReg());
622 
623  if (correspondingDREG != AVR::NoRegister) {
624  Op.makeReg(correspondingDREG);
625  return validateOperandClass(Op, Expected);
626  }
627  }
628  }
629  return Match_InvalidOperand;
630 }
631 
632 } // end of namespace llvm
void push_back(const T &Elt)
Definition: SmallVector.h:212
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
Definition: MCAsmLexer.h:116
An parsed AVR assembly operand.
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:228
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
void makeReg(unsigned RegNo)
AVROperand(unsigned Reg, MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
LLVM_ATTRIBUTE_ALWAYS_INLINE size_type size() const
Definition: SmallVector.h:136
Generic assembler parser interface, for use by target specific assembly parsers.
Definition: MCAsmParser.h:110
virtual void Initialize(MCAsmParser &Parser)
Initialize the extension for parsing using the given Parser.
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:137
MCTargetAsmParser - Generic interface to target specific assembly parsers.
bool isToken() const
isToken - Is this a token operand?
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
bool isImm() const
isImm - Is this an immediate operand?
AVROperand(unsigned Reg, SMLoc const &S, SMLoc const &E)
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Definition: MCAsmParser.cpp:33
void makeImm(MCExpr const *Ex)
bool isMem() const
isMem - Is this a memory operand?
virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, bool PrintSchedInfo=false)
Emit the given Instruction into the current section.
Definition: MCStreamer.cpp:863
Parses AVR assembly from a stream.
bool Error(SMLoc L, const Twine &Msg, SMRange Range=SMRange())
Target & getTheAVRTarget()
SMLoc getLoc() const
Get the current source location.
Definition: MCAsmLexer.cpp:22
VariantKind
Specifies the type of an expression.
Definition: AVRMCExpr.h:23
const MCExpr * getImm() const
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:116
const FeatureBitset & getFeatureBits() const
getFeatureBits - Return the feature bits.
Generic assembler lexer interface, for use by target specific assembly lexers.
Definition: MCAsmLexer.h:149
static unsigned MatchRegisterAltName(StringRef Name)
Maps from the set of all alternative registernames to a register number.
RegisterImmediate RegImm
static std::unique_ptr< AVROperand > CreateReg(unsigned RegNum, SMLoc S, SMLoc E)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:36
Reg
All possible values of the reg field in the ModR/M byte.
Target independent representation for an assembler token.
Definition: MCAsmLexer.h:27
SMLoc getStartLoc() const
getStartLoc - Get the location of the first token of this operand.
void addRegOperands(MCInst &Inst, unsigned N) const
virtual void print(raw_ostream &O) const
print - Print a debug representation of the operand to the given stream.
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand...
This file implements a class to represent arbitrary precision integral constant values and operations...
virtual bool parseExpression(const MCExpr *&Res, SMLoc &EndLoc)=0
Parse an arbitrary expression.
std::pair< StringRef, StringRef > getToken(StringRef Source, StringRef Delimiters=" \\\)
getToken - This function extracts one token from source, ignoring any leading characters that appear ...
RegisterMCAsmParser - Helper template for registering a target specific assembly parser, for use in the target machine initialization function.
AVROperand(MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
SMLoc getLoc() const
Definition: MCAsmLexer.cpp:26
LLVM_NODISCARD std::string upper() const
Convert the given ASCII string to uppercase.
Definition: StringRef.cpp:131
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:159
virtual void eatToEndOfStatement()=0
Skip to the end of the current statement, for error recovery.
void makeMemri(unsigned RegNo, MCExpr const *Imm)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
const char * getPointer() const
Definition: SMLoc.h:35
Streaming machine code generation interface.
Definition: MCStreamer.h:169
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
SMLoc getEndLoc() const
Definition: MCAsmLexer.cpp:30
bool isMemri() const
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static std::unique_ptr< AVROperand > CreateImm(const MCExpr *Val, SMLoc S, SMLoc E)
static std::unique_ptr< AVROperand > CreateMemri(unsigned RegNum, const MCExpr *Val, SMLoc S, SMLoc E)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
virtual MCAsmLexer & getLexer()=0
void addMemriOperands(MCInst &Inst, unsigned N) const
Adds the contained reg+imm operand to an instruction.
static const unsigned End
const AsmToken peekTok(bool ShouldSkipSpace=true)
Look ahead at the next token to be lexed.
Definition: MCAsmLexer.h:223
void addImmOperands(MCInst &Inst, unsigned N) const
SmallVectorImpl< std::unique_ptr< MCParsedAsmOperand > > OperandVector
void setLoc(SMLoc loc)
Definition: MCInst.h:177
AVROperand(StringRef Tok, SMLoc const &S)
unsigned first
AsmToken::TokenKind getKind() const
Get the kind of current token.
Definition: MCAsmLexer.h:250
bool isReg() const
isReg - Is this a register operand?
const MCInstrInfo & MII
void makeToken(StringRef Token)
SMLoc getEndLoc() const
getEndLoc - Get the location of the last token of this operand.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
bool is(TokenKind K) const
Definition: MCAsmLexer.h:88
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
static std::unique_ptr< AVROperand > CreateToken(StringRef Str, SMLoc S)
Base class for user error types.
Definition: Error.h:331
static SMLoc getFromPointer(const char *Ptr)
Definition: SMLoc.h:37
StringRef getToken() const
void setAvailableFeatures(uint64_t Value)
void addExpr(MCInst &Inst, const MCExpr *Expr) const
unsigned getReg() const
#define N
MCSubtargetInfo - Generic base class for all target subtargets.
static const AVRMCExpr * create(VariantKind Kind, const MCExpr *Expr, bool isNegated, MCContext &Ctx)
Creates an AVR machine code expression.
Definition: AVRMCExpr.cpp:36
MCAsmParser & getParser() const
static VariantKind getKindByName(StringRef Name)
Definition: AVRMCExpr.cpp:177
const unsigned Kind
MCAsmLexer & getLexer() const
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:123
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:285
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:235
static unsigned MatchRegisterName(StringRef Name)
Maps from the set of all register names to a register number.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:44
#define DEBUG(X)
Definition: Debug.h:118
void addOperand(const MCOperand &Op)
Definition: MCInst.h:184
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
AVRAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser, const MCInstrInfo &MII, const MCTargetOptions &Options)
virtual size_t peekTokens(MutableArrayRef< AsmToken > Buf, bool ShouldSkipSpace=true)=0
Look ahead an arbitrary number of tokens.
Represents a location in source code.
Definition: SMLoc.h:24
void LLVMInitializeAVRAsmParser()
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:123
TokenKind getKind() const
Definition: MCAsmLexer.h:87