LLVM  7.0.0svn
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1 //===-- HexagonISelDAGToDAG.h -----------------------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 // Hexagon specific code to select Hexagon machine instructions for
10 // SelectionDAG operations.
11 //===----------------------------------------------------------------------===//
16 #include "HexagonSubtarget.h"
17 #include "HexagonTargetMachine.h"
18 #include "llvm/ADT/StringRef.h"
21 #include "llvm/Support/CodeGen.h"
23 #include <vector>
25 namespace llvm {
26 class MachineFunction;
27 class HexagonInstrInfo;
28 class HexagonRegisterInfo;
29 class HexagonTargetLowering;
32  const HexagonSubtarget *HST;
33  const HexagonInstrInfo *HII;
34  const HexagonRegisterInfo *HRI;
35 public:
38  : SelectionDAGISel(tm, OptLevel), HST(nullptr), HII(nullptr),
39  HRI(nullptr) {}
42  // Reset the subtarget each time through.
43  HST = &MF.getSubtarget<HexagonSubtarget>();
44  HII = HST->getInstrInfo();
45  HRI = HST->getRegisterInfo();
47  return true;
48  }
50  bool ComplexPatternFuncMutatesDAG() const override {
51  return true;
52  }
53  void PreprocessISelDAG() override;
54  void EmitFunctionEntryCode() override;
56  void Select(SDNode *N) override;
58  // Complex Pattern Selectors.
59  inline bool SelectAddrGA(SDValue &N, SDValue &R);
60  inline bool SelectAddrGP(SDValue &N, SDValue &R);
61  inline bool SelectAnyImm(SDValue &N, SDValue &R);
62  inline bool SelectAnyInt(SDValue &N, SDValue &R);
63  bool SelectAnyImmediate(SDValue &N, SDValue &R, uint32_t LogAlign);
64  bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP,
65  uint32_t LogAlign);
66  bool SelectAddrFI(SDValue &N, SDValue &R);
67  bool DetectUseSxtw(SDValue &N, SDValue &R);
69  inline bool SelectAnyImm0(SDValue &N, SDValue &R);
70  inline bool SelectAnyImm1(SDValue &N, SDValue &R);
71  inline bool SelectAnyImm2(SDValue &N, SDValue &R);
72  inline bool SelectAnyImm3(SDValue &N, SDValue &R);
74  StringRef getPassName() const override {
75  return "Hexagon DAG->DAG Pattern Instruction Selection";
76  }
78  // Generate a machine instruction node corresponding to the circ/brev
79  // load intrinsic.
81  // Given the circ/brev load intrinsic and the already generated machine
82  // instruction, generate the appropriate store (that is a part of the
83  // intrinsic's functionality).
86  void SelectFrameIndex(SDNode *N);
87  /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
88  /// inline asm expressions.
90  unsigned ConstraintID,
91  std::vector<SDValue> &OutOps) override;
93  bool SelectBrevLdIntrinsic(SDNode *IntN);
94  bool SelectNewCircIntrinsic(SDNode *IntN);
95  void SelectLoad(SDNode *N);
96  void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl);
97  void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl);
98  void SelectStore(SDNode *N);
99  void SelectSHL(SDNode *N);
100  void SelectZeroExtend(SDNode *N);
101  void SelectIntrinsicWChain(SDNode *N);
103  void SelectConstant(SDNode *N);
104  void SelectConstantFP(SDNode *N);
105  void SelectV65Gather(SDNode *N);
106  void SelectV65GatherPred(SDNode *N);
107  void SelectHVXDualOutput(SDNode *N);
108  void SelectAddSubCarry(SDNode *N);
109  void SelectVAlign(SDNode *N);
110  void SelectVAlignAddr(SDNode *N);
111  void SelectTypecast(SDNode *N);
112  void SelectP2D(SDNode *N);
113  void SelectD2P(SDNode *N);
114  void SelectQ2V(SDNode *N);
115  void SelectV2Q(SDNode *N);
117  // Include the declarations autogenerated from the selection patterns.
118  #define GET_DAGISEL_DECL
119  #include "HexagonGenDAGISel.inc"
121 private:
122  // This is really only to get access to ReplaceNode (which is a protected
123  // member). Any other members used by HvxSelector can be moved around to
124  // make them accessible).
125  friend struct HvxSelector;
127  SDValue selectUndef(const SDLoc &dl, MVT ResTy) {
128  SDNode *U = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy);
129  return SDValue(U, 0);
130  }
132  void SelectHvxShuffle(SDNode *N);
133  void SelectHvxRor(SDNode *N);
134  void SelectHvxVAlign(SDNode *N);
136  bool keepsLowBits(const SDValue &Val, unsigned NumBits, SDValue &Src);
137  bool isAlignedMemNode(const MemSDNode *N) const;
138  bool isSmallStackStore(const StoreSDNode *N) const;
139  bool isPositiveHalfWord(const SDNode *N) const;
140  bool hasOneUse(const SDNode *N) const;
142  // DAG preprocessing functions.
143  void ppSimplifyOrSelect0(std::vector<SDNode*> &&Nodes);
144  void ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes);
145  void ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes);
146  void ppHoistZextI1(std::vector<SDNode*> &&Nodes);
148  SmallDenseMap<SDNode *,int> RootWeights;
149  SmallDenseMap<SDNode *,int> RootHeights;
150  SmallDenseMap<const Value *,int> GAUsesInFunction;
151  int getWeight(SDNode *N);
152  int getHeight(SDNode *N);
153  SDValue getMultiplierForSHL(SDNode *N);
154  SDValue factorOutPowerOf2(SDValue V, unsigned Power);
155  unsigned getUsesInFunction(const Value *V);
156  SDValue balanceSubTree(SDNode *N, bool Factorize = false);
157  void rebalanceAddressTrees();
158 }; // end HexagonDAGToDAGISel
159 }
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool DetectUseSxtw(SDValue &N, SDValue &R)
bool SelectAddrFI(SDValue &N, SDValue &R)
MachineFunction * MF
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s), MachineInstr opcode, and operands.
const HexagonRegisterInfo * getRegisterInfo() const override
void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl)
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool SelectNewCircIntrinsic(SDNode *IntN)
Generate a machine instruction node for the new circlar buffer intrinsics.
bool SelectBrevLdIntrinsic(SDNode *IntN)
SDNode * StoreInstrForLoadIntrinsic(MachineSDNode *LoadN, SDNode *IntN)
This class is used to represent ISD::STORE nodes.
CodeGenOpt::Level OptLevel
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool SelectAnyImm0(SDValue &N, SDValue &R)
bool SelectAnyInt(SDValue &N, SDValue &R)
bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps) override
SelectInlineAsmMemoryOperand - Implement addressing mode selection for inline asm expressions...
StringRef getPassName() const override
getPassName - Return a nice clean name for a pass.
void SelectZeroExtend(SDNode *N)
bool SelectAnyImm2(SDValue &N, SDValue &R)
void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl)
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool SelectAddrGA(SDValue &N, SDValue &R)
bool ComplexPatternFuncMutatesDAG() const override
Return true if complex patterns for this target can mutate the DAG.
bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP, uint32_t LogAlign)
An SDNode that represents everything that will be needed to construct a MachineInstr.
This is an abstract virtual class for memory operations.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
HexagonDAGToDAGISel(HexagonTargetMachine &tm, CodeGenOpt::Level OptLevel)
Represents one node in the SelectionDAG.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
bool SelectAnyImmediate(SDValue &N, SDValue &R, uint32_t LogAlign)
bool SelectAnyImm3(SDValue &N, SDValue &R)
bool SelectAnyImm1(SDValue &N, SDValue &R)
bool SelectAddrGP(SDValue &N, SDValue &R)
#define N
bool tryLoadOfLoadIntrinsic(LoadSDNode *N)
bool SelectAnyImm(SDValue &N, SDValue &R)
void PreprocessISelDAG() override
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
LLVM Value Representation.
Definition: Value.h:73
const HexagonInstrInfo * getInstrInfo() const override
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
MachineSDNode * LoadInstrForLoadIntrinsic(SDNode *IntN)
void Select(SDNode *N) override
Main hook for targets to transform nodes into machine nodes.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
This class is used to represent ISD::LOAD nodes.