LLVM  7.0.0svn
HexagonVectorPrint.cpp
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1 //===- HexagonVectorPrint.cpp - Generate vector printing instructions -----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This pass adds the capability to generate pseudo vector/predicate register
11 // printing instructions. These pseudo instructions should be used with the
12 // simulator, NEVER on hardware.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "HexagonInstrInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "llvm/ADT/StringRef.h"
26 #include "llvm/IR/DebugLoc.h"
27 #include "llvm/IR/InlineAsm.h"
28 #include "llvm/Pass.h"
30 #include "llvm/Support/Debug.h"
33 #include <string>
34 #include <vector>
35 
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "hexagon-vector-print"
39 
40 static cl::opt<bool> TraceHexVectorStoresOnly("trace-hex-vector-stores-only",
42  cl::desc("Enables tracing of vector stores"));
43 
44 namespace llvm {
45 
48 
49 } // end namespace llvm
50 
51 namespace {
52 
53 class HexagonVectorPrint : public MachineFunctionPass {
54  const HexagonSubtarget *QST = nullptr;
55  const HexagonInstrInfo *QII = nullptr;
56  const HexagonRegisterInfo *QRI = nullptr;
57 
58 public:
59  static char ID;
60 
61  HexagonVectorPrint() : MachineFunctionPass(ID) {
63  }
64 
65  StringRef getPassName() const override { return "Hexagon VectorPrint pass"; }
66 
67  bool runOnMachineFunction(MachineFunction &Fn) override;
68 };
69 
70 } // end anonymous namespace
71 
72 char HexagonVectorPrint::ID = 0;
73 
74 static bool isVecReg(unsigned Reg) {
75  return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31)
76  || (Reg >= Hexagon::W0 && Reg <= Hexagon::W15)
77  || (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3);
78 }
79 
80 static std::string getStringReg(unsigned R) {
81  if (R >= Hexagon::V0 && R <= Hexagon::V31) {
82  static const char* S[] = { "20", "21", "22", "23", "24", "25", "26", "27",
83  "28", "29", "2a", "2b", "2c", "2d", "2e", "2f",
84  "30", "31", "32", "33", "34", "35", "36", "37",
85  "38", "39", "3a", "3b", "3c", "3d", "3e", "3f"};
86  return S[R-Hexagon::V0];
87  }
88  if (R >= Hexagon::Q0 && R <= Hexagon::Q3) {
89  static const char* S[] = { "00", "01", "02", "03"};
90  return S[R-Hexagon::Q0];
91 
92  }
93  llvm_unreachable("valid vreg");
94 }
95 
96 static void addAsmInstr(MachineBasicBlock *MBB, unsigned Reg,
98  const DebugLoc &DL, const HexagonInstrInfo *QII,
99  MachineFunction &Fn) {
100  std::string VDescStr = ".long 0x1dffe0" + getStringReg(Reg);
101  const char *cstr = Fn.createExternalSymbolName(VDescStr);
102  unsigned ExtraInfo = InlineAsm::Extra_HasSideEffects;
103  BuildMI(*MBB, I, DL, QII->get(TargetOpcode::INLINEASM))
104  .addExternalSymbol(cstr)
105  .addImm(ExtraInfo);
106 }
107 
108 static bool getInstrVecReg(const MachineInstr &MI, unsigned &Reg) {
109  if (MI.getNumOperands() < 1) return false;
110  // Vec load or compute.
111  if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef()) {
112  Reg = MI.getOperand(0).getReg();
113  if (isVecReg(Reg))
114  return !TraceHexVectorStoresOnly;
115  }
116  // Vec store.
117  if (MI.mayStore() && MI.getNumOperands() >= 3 && MI.getOperand(2).isReg()) {
118  Reg = MI.getOperand(2).getReg();
119  if (isVecReg(Reg))
120  return true;
121  }
122  // Vec store post increment.
123  if (MI.mayStore() && MI.getNumOperands() >= 4 && MI.getOperand(3).isReg()) {
124  Reg = MI.getOperand(3).getReg();
125  if (isVecReg(Reg))
126  return true;
127  }
128  return false;
129 }
130 
131 bool HexagonVectorPrint::runOnMachineFunction(MachineFunction &Fn) {
132  bool Changed = false;
133  QST = &Fn.getSubtarget<HexagonSubtarget>();
134  QRI = QST->getRegisterInfo();
135  QII = QST->getInstrInfo();
136  std::vector<MachineInstr *> VecPrintList;
137  for (auto &MBB : Fn)
138  for (auto &MI : MBB) {
139  if (MI.isBundle()) {
140  MachineBasicBlock::instr_iterator MII = MI.getIterator();
141  for (++MII; MII != MBB.instr_end() && MII->isInsideBundle(); ++MII) {
142  if (MII->getNumOperands() < 1)
143  continue;
144  unsigned Reg = 0;
145  if (getInstrVecReg(*MII, Reg)) {
146  VecPrintList.push_back((&*MII));
147  LLVM_DEBUG(dbgs() << "Found vector reg inside bundle \n";
148  MII->dump());
149  }
150  }
151  } else {
152  unsigned Reg = 0;
153  if (getInstrVecReg(MI, Reg)) {
154  VecPrintList.push_back(&MI);
155  LLVM_DEBUG(dbgs() << "Found vector reg \n"; MI.dump());
156  }
157  }
158  }
159 
160  Changed = !VecPrintList.empty();
161  if (!Changed)
162  return Changed;
163 
164  for (auto *I : VecPrintList) {
165  DebugLoc DL = I->getDebugLoc();
166  MachineBasicBlock *MBB = I->getParent();
167  LLVM_DEBUG(dbgs() << "Evaluating V MI\n"; I->dump());
168  unsigned Reg = 0;
169  if (!getInstrVecReg(*I, Reg))
170  llvm_unreachable("Need a vector reg");
171  MachineBasicBlock::instr_iterator MII = I->getIterator();
172  if (I->isInsideBundle()) {
173  LLVM_DEBUG(dbgs() << "add to end of bundle\n"; I->dump());
174  while (MBB->instr_end() != MII && MII->isInsideBundle())
175  MII++;
176  } else {
177  LLVM_DEBUG(dbgs() << "add after instruction\n"; I->dump());
178  MII++;
179  }
180  if (MBB->instr_end() == MII)
181  continue;
182 
183  if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) {
184  LLVM_DEBUG(dbgs() << "adding dump for V" << Reg - Hexagon::V0 << '\n');
185  addAsmInstr(MBB, Reg, MII, DL, QII, Fn);
186  } else if (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) {
187  LLVM_DEBUG(dbgs() << "adding dump for W" << Reg - Hexagon::W0 << '\n');
188  addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1,
189  MII, DL, QII, Fn);
190  addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2,
191  MII, DL, QII, Fn);
192  } else if (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3) {
193  LLVM_DEBUG(dbgs() << "adding dump for Q" << Reg - Hexagon::Q0 << '\n');
194  addAsmInstr(MBB, Reg, MII, DL, QII, Fn);
195  } else
196  llvm_unreachable("Bad Vector reg");
197  }
198  return Changed;
199 }
200 
201 //===----------------------------------------------------------------------===//
202 // Public Constructor Functions
203 //===----------------------------------------------------------------------===//
204 INITIALIZE_PASS(HexagonVectorPrint, "hexagon-vector-print",
205  "Hexagon VectorPrint pass", false, false)
206 
208  return new HexagonVectorPrint();
209 }
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
instr_iterator instr_end()
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
FunctionPass * createHexagonVectorPrint()
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
A debug info location.
Definition: DebugLoc.h:34
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
unsigned getNumOperands() const
Access to explicit operands of the instruction.
Definition: MachineInstr.h:314
const HexagonRegisterInfo * getRegisterInfo() const override
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:628
void dump() const
Definition: Pass.cpp:130
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:672
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
static bool getInstrVecReg(const MachineInstr &MI, unsigned &Reg)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
static bool isVecReg(unsigned Reg)
const char * createExternalSymbolName(StringRef Name)
Allocate a string and populate it with the given external symbol name.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Iterator for intrusive lists based on ilist_node.
static void addAsmInstr(MachineBasicBlock *MBB, unsigned Reg, MachineBasicBlock::instr_iterator I, const DebugLoc &DL, const HexagonInstrInfo *QII, MachineFunction &Fn)
static cl::opt< bool > TraceHexVectorStoresOnly("trace-hex-vector-stores-only", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enables tracing of vector stores"))
void initializeHexagonVectorPrintPass(PassRegistry &)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:133
Representation of each machine instruction.
Definition: MachineInstr.h:60
INITIALIZE_PASS(HexagonVectorPrint, "hexagon-vector-print", "Hexagon VectorPrint pass", false, false) FunctionPass *llvm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
#define I(x, y, z)
Definition: MD5.cpp:58
bool isReg() const
isReg - Tests if this is a MO_Register operand.
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39
#define LLVM_DEBUG(X)
Definition: Debug.h:119
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:316
static std::string getStringReg(unsigned R)