LLVM  9.0.0svn
X86ATTInstPrinter.cpp
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1 //===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file includes code for rendering MCInst instances as AT&T-style
10 // assembly.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86ATTInstPrinter.h"
16 #include "X86InstComments.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/Support/Casting.h"
23 #include "llvm/Support/Format.h"
25 #include <cassert>
26 #include <cinttypes>
27 #include <cstdint>
28 
29 using namespace llvm;
30 
31 #define DEBUG_TYPE "asm-printer"
32 
33 // Include the auto-generated portion of the assembly writer.
34 #define PRINT_ALIAS_INSTR
35 #include "X86GenAsmWriter.inc"
36 
37 void X86ATTInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
38  OS << markup("<reg:") << '%' << getRegisterName(RegNo) << markup(">");
39 }
40 
42  StringRef Annot, const MCSubtargetInfo &STI) {
43  // If verbose assembly is enabled, we can print some informative comments.
44  if (CommentStream)
45  HasCustomInstComment = EmitAnyX86InstComments(MI, *CommentStream, MII);
46 
47  printInstFlags(MI, OS);
48 
49  // Output CALLpcrel32 as "callq" in 64-bit mode.
50  // In Intel annotation it's always emitted as "call".
51  //
52  // TODO: Probably this hack should be redesigned via InstAlias in
53  // InstrInfo.td as soon as Requires clause is supported properly
54  // for InstAlias.
55  if (MI->getOpcode() == X86::CALLpcrel32 &&
56  (STI.getFeatureBits()[X86::Mode64Bit])) {
57  OS << "\tcallq\t";
58  printPCRelImm(MI, 0, OS);
59  }
60  // data16 and data32 both have the same encoding of 0x66. While data32 is
61  // valid only in 16 bit systems, data16 is valid in the rest.
62  // There seems to be some lack of support of the Requires clause that causes
63  // 0x66 to be interpreted as "data16" by the asm printer.
64  // Thus we add an adjustment here in order to print the "right" instruction.
65  else if (MI->getOpcode() == X86::DATA16_PREFIX &&
66  STI.getFeatureBits()[X86::Mode16Bit]) {
67  OS << "\tdata32";
68  }
69  // Try to print any aliases first.
70  else if (!printAliasInstr(MI, OS))
71  printInstruction(MI, OS);
72 
73  // Next always print the annotation.
74  printAnnotation(OS, Annot);
75 }
76 
77 void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
78  raw_ostream &O) {
79  const MCOperand &Op = MI->getOperand(OpNo);
80  if (Op.isReg()) {
81  printRegName(O, Op.getReg());
82  } else if (Op.isImm()) {
83  // Print immediates as signed values.
84  int64_t Imm = Op.getImm();
85  O << markup("<imm:") << '$' << formatImm(Imm) << markup(">");
86 
87  // TODO: This should be in a helper function in the base class, so it can
88  // be used by other printers.
89 
90  // If there are no instruction-specific comments, add a comment clarifying
91  // the hex value of the immediate operand when it isn't in the range
92  // [-256,255].
93  if (CommentStream && !HasCustomInstComment && (Imm > 255 || Imm < -256)) {
94  // Don't print unnecessary hex sign bits.
95  if (Imm == (int16_t)(Imm))
96  *CommentStream << format("imm = 0x%" PRIX16 "\n", (uint16_t)Imm);
97  else if (Imm == (int32_t)(Imm))
98  *CommentStream << format("imm = 0x%" PRIX32 "\n", (uint32_t)Imm);
99  else
100  *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Imm);
101  }
102  } else {
103  assert(Op.isExpr() && "unknown operand kind in printOperand");
104  O << markup("<imm:") << '$';
105  Op.getExpr()->print(O, &MAI);
106  O << markup(">");
107  }
108 }
109 
111  raw_ostream &O) {
112  const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg);
113  const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg);
114  const MCOperand &DispSpec = MI->getOperand(Op + X86::AddrDisp);
115 
116  O << markup("<mem:");
117 
118  // If this has a segment register, print it.
120 
121  if (DispSpec.isImm()) {
122  int64_t DispVal = DispSpec.getImm();
123  if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
124  O << formatImm(DispVal);
125  } else {
126  assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
127  DispSpec.getExpr()->print(O, &MAI);
128  }
129 
130  if (IndexReg.getReg() || BaseReg.getReg()) {
131  O << '(';
132  if (BaseReg.getReg())
133  printOperand(MI, Op + X86::AddrBaseReg, O);
134 
135  if (IndexReg.getReg()) {
136  O << ',';
137  printOperand(MI, Op + X86::AddrIndexReg, O);
138  unsigned ScaleVal = MI->getOperand(Op + X86::AddrScaleAmt).getImm();
139  if (ScaleVal != 1) {
140  O << ',' << markup("<imm:") << ScaleVal // never printed in hex.
141  << markup(">");
142  }
143  }
144  O << ')';
145  }
146 
147  O << markup(">");
148 }
149 
151  raw_ostream &O) {
152  O << markup("<mem:");
153 
154  // If this has a segment register, print it.
155  printOptionalSegReg(MI, Op + 1, O);
156 
157  O << "(";
158  printOperand(MI, Op, O);
159  O << ")";
160 
161  O << markup(">");
162 }
163 
165  raw_ostream &O) {
166  O << markup("<mem:");
167 
168  O << "%es:(";
169  printOperand(MI, Op, O);
170  O << ")";
171 
172  O << markup(">");
173 }
174 
176  raw_ostream &O) {
177  const MCOperand &DispSpec = MI->getOperand(Op);
178 
179  O << markup("<mem:");
180 
181  // If this has a segment register, print it.
182  printOptionalSegReg(MI, Op + 1, O);
183 
184  if (DispSpec.isImm()) {
185  O << formatImm(DispSpec.getImm());
186  } else {
187  assert(DispSpec.isExpr() && "non-immediate displacement?");
188  DispSpec.getExpr()->print(O, &MAI);
189  }
190 
191  O << markup(">");
192 }
193 
195  raw_ostream &O) {
196  if (MI->getOperand(Op).isExpr())
197  return printOperand(MI, Op, O);
198 
199  O << markup("<imm:") << '$' << formatImm(MI->getOperand(Op).getImm() & 0xff)
200  << markup(">");
201 }
202 
204  raw_ostream &OS) {
205  const MCOperand &Op = MI->getOperand(OpNo);
206  unsigned Reg = Op.getReg();
207  // Override the default printing to print st(0) instead st.
208  if (Reg == X86::ST0)
209  OS << markup("<reg:") << "%st(0)" << markup(">");
210  else
211  printRegName(OS, Reg);
212 }
void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
bool isImm() const
Definition: MCInst.h:58
static const char * getRegisterName(unsigned RegNo)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned Reg
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:123
bool isReg() const
Definition: MCInst.h:57
const FeatureBitset & getFeatureBits() const
void printSTiRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS)
void printInstruction(const MCInst *MI, raw_ostream &OS)
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
bool EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, const MCInstrInfo &MCII)
EmitAnyX86InstComments - This function decodes x86 instructions and prints newline terminated strings...
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
Definition: MCInstPrinter.h:95
const MCExpr * getExpr() const
Definition: MCInst.h:95
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
void printOptionalSegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O)
void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &OS)
void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O)
printPCRelImm - This is used to print an immediate value that ends up being encoded as a pc-relative ...
int64_t getImm() const
Definition: MCInst.h:75
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:38
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:41
StringRef markup(StringRef s) const
Utility functions to make adding mark ups simpler.
bool isExpr() const
Definition: MCInst.h:60
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS) override
void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS)
void printInstFlags(const MCInst *MI, raw_ostream &O)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &OS)
raw_ostream * CommentStream
A stream that comments can be emitted to if desired.
Definition: MCInstPrinter.h:44
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:45
void printSrcIdx(const MCInst *MI, unsigned Op, raw_ostream &O)
Generic base class for all target subtargets.
const MCInstrInfo & MII
Definition: MCInstPrinter.h:46
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
bool printAliasInstr(const MCInst *MI, raw_ostream &OS)
IRTranslator LLVM IR MI
void printDstIdx(const MCInst *MI, unsigned Op, raw_ostream &O)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
unsigned getOpcode() const
Definition: MCInst.h:171
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34