62void AMDGPUAsmBackend::relaxInstruction(
MCInst &Inst,
68 Inst = std::move(Res);
71bool AMDGPUAsmBackend::fixupNeedsRelaxation(
const MCFixup &
Fixup,
76 return (((int64_t(
Value)/4)-1) == 0x3f);
79bool AMDGPUAsmBackend::mayNeedRelaxation(
const MCInst &Inst,
81 if (!STI.
hasFeature(AMDGPU::FeatureOffset3fBug))
114 int64_t SignedValue =
static_cast<int64_t
>(
Value);
116 switch (
Fixup.getTargetKind()) {
118 int64_t BrImm = (SignedValue - 4) / 4;
120 if (Ctx && !isInt<16>(BrImm))
156 assert(
Offset + NumBytes <= Data.size() &&
"Invalid fixup offset!");
160 for (
unsigned i = 0; i != NumBytes; ++i)
161 Data[
Offset + i] |=
static_cast<uint8_t
>((
Value >> (i * 8)) & 0xff);
164std::optional<MCFixupKind>
169#include
"llvm/BinaryFormat/ELFRelocs/AMDGPU.def"
192bool AMDGPUAsmBackend::shouldForceRelocation(
const MCAssembler &,
199unsigned AMDGPUAsmBackend::getMinimumNopSize()
const {
215 const uint32_t Encoded_S_NOP_0 = 0xbf800000;
218 support::endian::write<uint32_t>(
OS, Encoded_S_NOP_0, Endian);
229class ELFAMDGPUAsmBackend :
public AMDGPUAsmBackend {
231 bool HasRelocationAddend;
236 : AMDGPUAsmBackend(
T), Is64Bit(
TT.getArch() ==
Triple::amdgcn),
237 HasRelocationAddend(
TT.getOS() ==
Triple::AMDHSA) {
238 switch (
TT.getOS()) {
253 std::unique_ptr<MCObjectTargetWriter>
254 createObjectTargetWriter()
const override {
unsigned const MachineRegisterInfo * MRI
#define ELF_RELOC(Name, Value)
static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, MCContext *Ctx)
static unsigned getFixupKindNumBytes(unsigned Kind)
Provides AMDGPU specific target descriptions.
Analysis containing CSE Info
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Generic interface to target specific assembler backends.
virtual unsigned getMinimumNopSize() const
Returns the minimum size of a nop in bytes on this target.
virtual bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const =0
Write an (optimal) nop sequence of Count bytes to the given output.
virtual void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const
Relax the instruction in the given fragment to the next wider instruction.
virtual bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const
Check whether the given instruction may need relaxation.
virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value) const
Simple predicate for targets where !Resolved implies requiring relaxation.
virtual bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, const MCSubtargetInfo *STI)
Hook to check if a relocation is needed for some target specific reason.
virtual unsigned getNumFixupKinds() const =0
Get the number of target specific fixup kinds.
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
virtual std::optional< MCFixupKind > getFixupKind(StringRef Name) const
Map a relocation name used in .reloc to a fixup kind.
virtual void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const =0
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
Context object for machine code objects.
void reportError(SMLoc L, const Twine &Msg)
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Instances of this class represent a single low-level machine instruction.
unsigned getOpcode() const
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
const MCOperand & getOperand(unsigned i) const
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
This represents an "assembler immediate".
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
StringRef - Represent a constant reference to a string, i.e.
A switch()-like statement whose cases are string literals.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
raw_ostream & write_zeros(unsigned NumZeros)
write_zeros - Insert 'NumZeros' nulls.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ fixup_si_sopp_br
16-bit PC relative fixup for SOPP branch instructions.
LLVM_READONLY int getSOPPWithRelaxation(uint16_t Opcode)
This is an optimization pass for GlobalISel generic memory operations.
MCAsmBackend * createAMDGPUAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter > createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, bool HasRelocationAddend)
MCFixupKind
Extensible enumeration to represent the type of a fixup.
@ FK_PCRel_4
A four-byte pc relative fixup.
@ FK_SecRel_2
A two-byte section relative fixup.
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
@ FK_Data_8
A eight-byte fixup.
@ FK_Data_1
A one-byte fixup.
@ FK_Data_4
A four-byte fixup.
@ FK_SecRel_8
A eight-byte section relative fixup.
@ FK_SecRel_4
A four-byte section relative fixup.
@ FK_SecRel_1
A one-byte section relative fixup.
@ FK_Data_2
A two-byte fixup.
Target independent information on a fixup kind.
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...