LLVM 20.0.0git
AMDGPUAsmBackend.cpp
Go to the documentation of this file.
1//===-- AMDGPUAsmBackend.cpp - AMDGPU Assembler Backend -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
16#include "llvm/MC/MCAssembler.h"
17#include "llvm/MC/MCContext.h"
24
25using namespace llvm;
26using namespace llvm::AMDGPU;
27
28namespace {
29
30class AMDGPUAsmBackend : public MCAsmBackend {
31public:
32 AMDGPUAsmBackend(const Target &T) : MCAsmBackend(llvm::endianness::little) {}
33
34 unsigned getNumFixupKinds() const override { return AMDGPU::NumTargetFixupKinds; };
35
36 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
38 uint64_t Value, bool IsResolved,
39 const MCSubtargetInfo *STI) const override;
41 uint64_t Value) const override;
42
43 void relaxInstruction(MCInst &Inst,
44 const MCSubtargetInfo &STI) const override;
45
46 bool mayNeedRelaxation(const MCInst &Inst,
47 const MCSubtargetInfo &STI) const override;
48
49 unsigned getMinimumNopSize() const override;
51 const MCSubtargetInfo *STI) const override;
52
53 std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;
54 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
55 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
56 const MCValue &Target,
57 const MCSubtargetInfo *STI) override;
58};
59
60} //End anonymous namespace
61
62void AMDGPUAsmBackend::relaxInstruction(MCInst &Inst,
63 const MCSubtargetInfo &STI) const {
64 MCInst Res;
65 unsigned RelaxedOpcode = AMDGPU::getSOPPWithRelaxation(Inst.getOpcode());
66 Res.setOpcode(RelaxedOpcode);
67 Res.addOperand(Inst.getOperand(0));
68 Inst = std::move(Res);
69}
70
71bool AMDGPUAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
72 uint64_t Value) const {
73 // if the branch target has an offset of x3f this needs to be relaxed to
74 // add a s_nop 0 immediately after branch to effectively increment offset
75 // for hardware workaround in gfx1010
76 return (((int64_t(Value)/4)-1) == 0x3f);
77}
78
79bool AMDGPUAsmBackend::mayNeedRelaxation(const MCInst &Inst,
80 const MCSubtargetInfo &STI) const {
81 if (!STI.hasFeature(AMDGPU::FeatureOffset3fBug))
82 return false;
83
85 return true;
86
87 return false;
88}
89
90static unsigned getFixupKindNumBytes(unsigned Kind) {
91 switch (Kind) {
93 return 2;
94 case FK_SecRel_1:
95 case FK_Data_1:
96 return 1;
97 case FK_SecRel_2:
98 case FK_Data_2:
99 return 2;
100 case FK_SecRel_4:
101 case FK_Data_4:
102 case FK_PCRel_4:
103 return 4;
104 case FK_SecRel_8:
105 case FK_Data_8:
106 return 8;
107 default:
108 llvm_unreachable("Unknown fixup kind!");
109 }
110}
111
113 MCContext *Ctx) {
114 int64_t SignedValue = static_cast<int64_t>(Value);
115
116 switch (Fixup.getTargetKind()) {
118 int64_t BrImm = (SignedValue - 4) / 4;
119
120 if (Ctx && !isInt<16>(BrImm))
121 Ctx->reportError(Fixup.getLoc(), "branch size exceeds simm16");
122
123 return BrImm;
124 }
125 case FK_Data_1:
126 case FK_Data_2:
127 case FK_Data_4:
128 case FK_Data_8:
129 case FK_PCRel_4:
130 case FK_SecRel_4:
131 return Value;
132 default:
133 llvm_unreachable("unhandled fixup kind");
134 }
135}
136
137void AMDGPUAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
138 const MCValue &Target,
140 bool IsResolved,
141 const MCSubtargetInfo *STI) const {
142 if (Fixup.getKind() >= FirstLiteralRelocationKind)
143 return;
144
145 Value = adjustFixupValue(Fixup, Value, &Asm.getContext());
146 if (!Value)
147 return; // Doesn't change encoding.
148
149 MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
150
151 // Shift the value into position.
152 Value <<= Info.TargetOffset;
153
154 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
155 uint32_t Offset = Fixup.getOffset();
156 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
157
158 // For each byte of the fragment that the fixup touches, mask in the bits from
159 // the fixup value.
160 for (unsigned i = 0; i != NumBytes; ++i)
161 Data[Offset + i] |= static_cast<uint8_t>((Value >> (i * 8)) & 0xff);
162}
163
164std::optional<MCFixupKind>
165AMDGPUAsmBackend::getFixupKind(StringRef Name) const {
167#define ELF_RELOC(Name, Value) \
169#include "llvm/BinaryFormat/ELFRelocs/AMDGPU.def"
170#undef ELF_RELOC
171 .Default(std::nullopt);
172}
173
174const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo(
175 MCFixupKind Kind) const {
176 const static MCFixupKindInfo Infos[AMDGPU::NumTargetFixupKinds] = {
177 // name offset bits flags
178 { "fixup_si_sopp_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
179 };
180
181 if (Kind >= FirstLiteralRelocationKind)
183
184 if (Kind < FirstTargetFixupKind)
186
187 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
188 "Invalid kind!");
189 return Infos[Kind - FirstTargetFixupKind];
190}
191
192bool AMDGPUAsmBackend::shouldForceRelocation(const MCAssembler &,
193 const MCFixup &Fixup,
194 const MCValue &,
195 const MCSubtargetInfo *STI) {
196 return Fixup.getKind() >= FirstLiteralRelocationKind;
197}
198
199unsigned AMDGPUAsmBackend::getMinimumNopSize() const {
200 return 4;
201}
202
203bool AMDGPUAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
204 const MCSubtargetInfo *STI) const {
205 // If the count is not 4-byte aligned, we must be writing data into the text
206 // section (otherwise we have unaligned instructions, and thus have far
207 // bigger problems), so just write zeros instead.
208 OS.write_zeros(Count % 4);
209
210 // We are properly aligned, so write NOPs as requested.
211 Count /= 4;
212
213 // FIXME: R600 support.
214 // s_nop 0
215 const uint32_t Encoded_S_NOP_0 = 0xbf800000;
216
217 for (uint64_t I = 0; I != Count; ++I)
218 support::endian::write<uint32_t>(OS, Encoded_S_NOP_0, Endian);
219
220 return true;
221}
222
223//===----------------------------------------------------------------------===//
224// ELFAMDGPUAsmBackend class
225//===----------------------------------------------------------------------===//
226
227namespace {
228
229class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
230 bool Is64Bit;
231 bool HasRelocationAddend;
232 uint8_t OSABI = ELF::ELFOSABI_NONE;
233
234public:
235 ELFAMDGPUAsmBackend(const Target &T, const Triple &TT)
236 : AMDGPUAsmBackend(T), Is64Bit(TT.getArch() == Triple::amdgcn),
237 HasRelocationAddend(TT.getOS() == Triple::AMDHSA) {
238 switch (TT.getOS()) {
239 case Triple::AMDHSA:
241 break;
242 case Triple::AMDPAL:
244 break;
245 case Triple::Mesa3D:
247 break;
248 default:
249 break;
250 }
251 }
252
253 std::unique_ptr<MCObjectTargetWriter>
254 createObjectTargetWriter() const override {
255 return createAMDGPUELFObjectWriter(Is64Bit, OSABI, HasRelocationAddend);
256 }
257};
258
259} // end anonymous namespace
260
262 const MCSubtargetInfo &STI,
263 const MCRegisterInfo &MRI,
264 const MCTargetOptions &Options) {
265 return new ELFAMDGPUAsmBackend(T, STI.getTargetTriple());
266}
unsigned const MachineRegisterInfo * MRI
#define ELF_RELOC(Name, Value)
static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, MCContext *Ctx)
static unsigned getFixupKindNumBytes(unsigned Kind)
Provides AMDGPU specific target descriptions.
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
@ Default
Definition: DwarfDebug.cpp:87
std::string Name
static LVOptions Options
Definition: LVOptions.cpp:25
#define I(x, y, z)
Definition: MD5.cpp:58
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:42
virtual unsigned getMinimumNopSize() const
Returns the minimum size of a nop in bytes on this target.
Definition: MCAsmBackend.h:207
virtual bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const =0
Write an (optimal) nop sequence of Count bytes to the given output.
virtual void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const
Relax the instruction in the given fragment to the next wider instruction.
Definition: MCAsmBackend.h:179
virtual bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const
Check whether the given instruction may need relaxation.
Definition: MCAsmBackend.h:155
virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value) const
Simple predicate for targets where !Resolved implies requiring relaxation.
Definition: MCAsmBackend.h:169
virtual bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, const MCSubtargetInfo *STI)
Hook to check if a relocation is needed for some target specific reason.
Definition: MCAsmBackend.h:96
virtual unsigned getNumFixupKinds() const =0
Get the number of target specific fixup kinds.
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
virtual std::optional< MCFixupKind > getFixupKind(StringRef Name) const
Map a relocation name used in .reloc to a fixup kind.
virtual void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const =0
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
Context object for machine code objects.
Definition: MCContext.h:83
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:1068
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getOpcode() const
Definition: MCInst.h:198
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
void setOpcode(unsigned Op)
Definition: MCInst.h:197
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
This represents an "assembler immediate".
Definition: MCValue.h:36
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
raw_ostream & write_zeros(unsigned NumZeros)
write_zeros - Insert 'NumZeros' nulls.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ fixup_si_sopp_br
16-bit PC relative fixup for SOPP branch instructions.
LLVM_READONLY int getSOPPWithRelaxation(uint16_t Opcode)
@ ELFOSABI_AMDGPU_HSA
Definition: ELF.h:362
@ ELFOSABI_AMDGPU_MESA3D
Definition: ELF.h:364
@ ELFOSABI_NONE
Definition: ELF.h:342
@ ELFOSABI_AMDGPU_PAL
Definition: ELF.h:363
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
MCAsmBackend * createAMDGPUAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter > createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, bool HasRelocationAddend)
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
@ FirstTargetFixupKind
Definition: MCFixup.h:45
@ FK_PCRel_4
A four-byte pc relative fixup.
Definition: MCFixup.h:30
@ FK_SecRel_2
A two-byte section relative fixup.
Definition: MCFixup.h:41
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
Definition: MCFixup.h:50
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
@ FK_SecRel_8
A eight-byte section relative fixup.
Definition: MCFixup.h:43
@ FK_NONE
A no-op fixup.
Definition: MCFixup.h:22
@ FK_SecRel_4
A four-byte section relative fixup.
Definition: MCFixup.h:42
@ FK_SecRel_1
A one-byte section relative fixup.
Definition: MCFixup.h:40
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
endianness
Definition: bit.h:70
Target independent information on a fixup kind.
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...