LLVM 22.0.0git
BPFISelLowering.h
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1//===-- BPFISelLowering.h - BPF DAG Lowering Interface ----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that BPF uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_BPF_BPFISELLOWERING_H
15#define LLVM_LIB_TARGET_BPF_BPFISELLOWERING_H
16
17#include "BPF.h"
20
21namespace llvm {
22class BPFSubtarget;
23namespace BPFISD {
24enum NodeType : unsigned {
31 MEMCPY
32};
33}
34
36public:
37 explicit BPFTargetLowering(const TargetMachine &TM, const BPFSubtarget &STI);
38
39 // Provide custom lowering hooks for some operations.
40 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
41
42 // This method returns the name of a target specific DAG node.
43 const char *getTargetNodeName(unsigned Opcode) const override;
44
45 // This method decides whether folding a constant offset
46 // with the given GlobalAddress is legal.
47 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
48
50 getConstraintType(StringRef Constraint) const override;
51
52 std::pair<unsigned, const TargetRegisterClass *>
54 StringRef Constraint, MVT VT) const override;
55
58 MachineBasicBlock *BB) const override;
59
60 bool getHasAlu32() const { return HasAlu32; }
61 bool getHasJmp32() const { return HasJmp32; }
62 bool getHasJmpExt() const { return HasJmpExt; }
63
65 EVT VT) const override;
66
67 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
68
69private:
70 // Control Instruction Selection Features
71 bool HasAlu32;
72 bool HasJmp32;
73 bool HasJmpExt;
74 bool HasMovsx;
75
76 SDValue LowerSDIVSREM(SDValue Op, SelectionDAG &DAG) const;
77 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
78 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
79 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
80 SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) const;
81 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
82 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
83 SDValue LowerTRAP(SDValue Op, SelectionDAG &DAG) const;
84
85 template <class NodeTy>
86 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
87
88 // Lower the result values of a call, copying them out of physregs into vregs
89 SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
90 CallingConv::ID CallConv, bool IsVarArg,
92 const SDLoc &DL, SelectionDAG &DAG,
93 SmallVectorImpl<SDValue> &InVals) const;
94
95 // Maximum number of arguments to a call
96 static const size_t MaxArgs;
97
98 // Lower a call into CALLSEQ_START - BPFISD:CALL - CALLSEQ_END chain
100 SmallVectorImpl<SDValue> &InVals) const override;
101
102 // Lower incoming arguments, copy physregs into vregs
103 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
104 bool IsVarArg,
106 const SDLoc &DL, SelectionDAG &DAG,
107 SmallVectorImpl<SDValue> &InVals) const override;
108
109 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
111 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
112 SelectionDAG &DAG) const override;
113
114 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
115 SelectionDAG &DAG) const override;
116
117 EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op,
118 const AttributeList &FuncAttributes) const override {
119 return Op.size() >= 8 ? MVT::i64 : MVT::i32;
120 }
121
122 bool isIntDivCheap(EVT VT, AttributeList Attr) const override {
123 return false;
124 }
125
126 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
127 Type *Ty) const override {
128 return true;
129 }
130
131 // Prevent reducing load width during SelectionDag phase.
132 // Otherwise, we may transform the following
133 // ctx = ctx + reloc_offset
134 // ... (*(u32 *)ctx) & 0x8000...
135 // to
136 // ctx = ctx + reloc_offset
137 // ... (*(u8 *)(ctx + 1)) & 0x80 ...
138 // which will be rejected by the verifier.
139 bool
140 shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT,
141 std::optional<unsigned> ByteOffset) const override {
142 return false;
143 }
144
145 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
146 Type *Ty, unsigned AS,
147 Instruction *I = nullptr) const override;
148
149 // isTruncateFree - Return true if it's free to truncate a value of
150 // type Ty1 to type Ty2. e.g. On BPF at alu32 mode, it's free to truncate
151 // a i64 value in register R1 to i32 by referencing its sub-register W1.
152 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
153 bool isTruncateFree(EVT VT1, EVT VT2) const override;
154
155 // For 32bit ALU result zext to 64bit is free.
156 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
157 bool isZExtFree(EVT VT1, EVT VT2) const override;
158 bool isZExtFree(SDValue Val, EVT VT2) const override;
159
160 unsigned EmitSubregExt(MachineInstr &MI, MachineBasicBlock *BB, unsigned Reg,
161 bool isSigned) const;
162
163 MachineBasicBlock * EmitInstrWithCustomInserterMemcpy(MachineInstr &MI,
164 MachineBasicBlock *BB)
165 const;
166
167};
168}
169
170#endif
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
static bool isSigned(unsigned int Opcode)
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
Register Reg
Register const TargetRegisterInfo * TRI
This file describes how to lower LLVM code to machine code.
BPFTargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:63
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
Machine Value Type.
Representation of each machine instruction.
Definition: MachineInstr.h:72
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:229
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:574
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:55
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:83
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1574
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1671
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
#define N
Extended Value Type.
Definition: ValueTypes.h:35
This structure contains all information that is necessary for lowering calls.