ARMISelLowering.cpp File Reference

#include "ARMISelLowering.h"
#include "ARMBaseInstrInfo.h"
#include "ARMBaseRegisterInfo.h"
#include "ARMCallingConv.h"
#include "ARMConstantPoolValue.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMPerfectShuffle.h"
#include "ARMRegisterInfo.h"
#include "ARMSelectionDAGInfo.h"
#include "ARMSubtarget.h"
#include "ARMTargetTransformInfo.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "MCTargetDesc/ARMBaseInfo.h"
#include "Utils/ARMBaseInfo.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Twine.h"
#include "llvm/Analysis/VectorUtils.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/ComplexDeinterleavingPass.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RuntimeLibcallUtil.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/CodeGenTypes/MachineValueType.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constant.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalAlias.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/GlobalVariable.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Instruction.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IntrinsicsARM.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/User.h"
#include "llvm/IR/Value.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/MC/MCSchedule.h"
#include "llvm/Support/AtomicOrdering.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/TargetParser/Triple.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <iterator>
#include <limits>
#include <optional>
#include <tuple>
#include <utility>
#include <vector>

Go to the source code of this file.

Classes
struct	BaseUpdateTarget
	Load/store instruction that can be merged with a base address update. More...
struct	BaseUpdateUser

Macros
#define	DEBUG_TYPE   "arm-isel"

Typedefs
using	RCPair = std::pair<unsigned, const TargetRegisterClass *>

Enumerations
enum	ShuffleOpCodes {   OP_COPY = 0 , OP_VREV , OP_VDUP0 , OP_VDUP1 ,   OP_VDUP2 , OP_VDUP3 , OP_VEXT1 , OP_VEXT2 ,   OP_VEXT3 , OP_VUZPL , OP_VUZPR , OP_VZIPL ,   OP_VZIPR , OP_VTRNL , OP_VTRNR }
enum	HABaseType {   HA_UNKNOWN = 0 , HA_FLOAT , HA_DOUBLE , HA_VECT64 ,   HA_VECT128 }

Functions
	STATISTIC (NumTailCalls, "Number of tail calls")
	STATISTIC (NumOptimizedImms, "Number of times immediates were optimized")
	STATISTIC (NumMovwMovt, "Number of GAs materialized with movw + movt")
	STATISTIC (NumLoopByVals, "Number of loops generated for byval arguments")
	STATISTIC (NumConstpoolPromoted, "Number of constants with their storage promoted into constant pools")
static SDValue	handleCMSEValue (const SDValue &Value, const ISD::InputArg &Arg, SelectionDAG &DAG, const SDLoc &DL)
static bool	isSRL16 (const SDValue &Op)
static bool	isSRA16 (const SDValue &Op)
static bool	isSHL16 (const SDValue &Op)
static bool	isS16 (const SDValue &Op, SelectionDAG &DAG)
static ARMCC::CondCodes	IntCCToARMCC (ISD::CondCode CC)
	IntCCToARMCC - Convert a DAG integer condition code to an ARM CC.
static void	FPCCToARMCC (ISD::CondCode CC, ARMCC::CondCodes &CondCode, ARMCC::CondCodes &CondCode2)
	FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
static bool	canGuaranteeTCO (CallingConv::ID CC, bool GuaranteeTailCalls)
static SDValue	LowerInterruptReturn (SmallVectorImpl< SDValue > &RetOps, const SDLoc &DL, SelectionDAG &DAG)
static SDValue	LowerWRITE_REGISTER (SDValue Op, SelectionDAG &DAG)
static bool	allUsersAreInFunction (const Value *V, const Function *F)
	Return true if all users of V are within function F, looking through ConstantExprs.
static SDValue	promoteToConstantPool (const ARMTargetLowering *TLI, const GlobalValue *GV, SelectionDAG &DAG, EVT PtrVT, const SDLoc &dl)
static SDValue	LowerATOMIC_FENCE (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	LowerPREFETCH (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	LowerVASTART (SDValue Op, SelectionDAG &DAG)
static bool	isFloatingPointZero (SDValue Op)
	isFloatingPointZero - Return true if this is +0.0.
static bool	isSafeSignedCMN (SDValue Op, SelectionDAG &DAG)
static bool	isCMN (SDValue Op, ISD::CondCode CC, SelectionDAG &DAG)
static unsigned	getCmpOperandFoldingProfit (SDValue Op, const ARMSubtarget &ST)
	Returns how profitable it is to fold a comparison's operand's shift and/or extension operations into the comparison instruction's second operand (so_reg_imm / so_reg_reg for ARM, t2_so_reg for Thumb-2).
static SDValue	getShiftedLowMaskZeroTest (SDValue Value, SelectionDAG &DAG, const SDLoc &DL)
static SDValue	valueToCarryFlag (SDValue Value, SelectionDAG &DAG, bool Invert)
static SDValue	carryFlagToValue (SDValue Flags, EVT VT, SelectionDAG &DAG, bool Invert)
static SDValue	overflowFlagToValue (SDValue Flags, EVT VT, SelectionDAG &DAG)
static SDValue	LowerADDSUBSAT (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static void	checkVSELConstraints (ISD::CondCode CC, ARMCC::CondCodes &CondCode, bool &swpCmpOps, bool &swpVselOps)
static bool	isGTorGE (ISD::CondCode CC)
static bool	isLTorLE (ISD::CondCode CC)
static bool	isLowerSaturate (const SDValue LHS, const SDValue RHS, const SDValue TrueVal, const SDValue FalseVal, const ISD::CondCode CC, const SDValue K)
static SDValue	LowerSaturatingConditional (SDValue Op, SelectionDAG &DAG)
static bool	isLowerSaturatingConditional (const SDValue &Op, SDValue &V, SDValue &SatK)
static SDValue	matchCSET (unsigned &Opcode, bool &InvertCond, SDValue TrueVal, SDValue FalseVal, const ARMSubtarget *Subtarget)
static bool	canChangeToInt (SDValue Op, bool &SeenZero, const ARMSubtarget *Subtarget)
	canChangeToInt - Given the fp compare operand, return true if it is suitable to morph to an integer compare sequence.
static SDValue	bitcastf32Toi32 (SDValue Op, SelectionDAG &DAG)
static void	expandf64Toi32 (SDValue Op, SelectionDAG &DAG, SDValue &RetVal1, SDValue &RetVal2)
static SDValue	getInvertedARMCondCode (SDValue ARMcc, SelectionDAG &DAG)
static SDValue	LowerVectorFP_TO_INT (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerFP_TO_INT_SAT (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	LowerVectorINT_TO_FP (SDValue Op, SelectionDAG &DAG)
static void	ExpandREAD_REGISTER (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
static SDValue	CombineVMOVDRRCandidateWithVecOp (const SDNode *BC, SelectionDAG &DAG)
	BC is a bitcast that is about to be turned into a VMOVDRR.
static SDValue	getZeroVector (EVT VT, SelectionDAG &DAG, const SDLoc &dl)
	getZeroVector - Returns a vector of specified type with all zero elements.
static SDValue	LowerCTTZ (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerCTPOP (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
static bool	getVShiftImm (SDValue Op, unsigned ElementBits, int64_t &Cnt)
	Getvshiftimm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value.
static bool	isVShiftLImm (SDValue Op, EVT VT, bool isLong, int64_t &Cnt)
	isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation.
static bool	isVShiftRImm (SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, int64_t &Cnt)
	isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation.
static SDValue	LowerShift (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	Expand64BitShift (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerVSETCC (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerSETCCCARRY (SDValue Op, SelectionDAG &DAG)
static SDValue	isVMOVModifiedImm (uint64_t SplatBits, uint64_t SplatUndef, unsigned SplatBitSize, SelectionDAG &DAG, const SDLoc &dl, EVT &VT, EVT VectorVT, VMOVModImmType type)
	isVMOVModifiedImm - Check if the specified splat value corresponds to a valid vector constant for a NEON or MVE instruction with a "modified immediate" operand (e.g., VMOV).
static bool	isSingletonVEXTMask (ArrayRef< int > M, EVT VT, unsigned &Imm)
static bool	isVEXTMask (ArrayRef< int > M, EVT VT, bool &ReverseVEXT, unsigned &Imm)
static bool	isVTBLMask (ArrayRef< int > M, EVT VT)
static unsigned	isNEONTwoResultShuffleMask (ArrayRef< int > ShuffleMask, EVT VT, unsigned &WhichResult, bool &isV_UNDEF)
	Check if ShuffleMask is a NEON two-result shuffle (VZIP, VUZP, VTRN), and return the corresponding ARMISD opcode if it is, or 0 if it isn't.
static bool	isReverseMask (ArrayRef< int > M, EVT VT)
static bool	isTruncMask (ArrayRef< int > M, EVT VT, bool Top, bool SingleSource)
static bool	isVMOVNMask (ArrayRef< int > M, EVT VT, bool Top, bool SingleSource)
static bool	isVMOVNTruncMask (ArrayRef< int > M, EVT ToVT, bool rev)
static SDValue	LowerBuildVectorOfFPTrunc (SDValue BV, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerBuildVectorOfFPExt (SDValue BV, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	IsSingleInstrConstant (SDValue N, SelectionDAG &DAG, const ARMSubtarget *ST, const SDLoc &dl)
static SDValue	LowerBUILD_VECTOR_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerBUILD_VECTORToVIDUP (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static bool	IsQRMVEInstruction (const SDNode *N, const SDNode *Op)
static bool	isLegalMVEShuffleOp (unsigned PFEntry)
static SDValue	GeneratePerfectShuffle (unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl)
	GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle.
static SDValue	LowerVECTOR_SHUFFLEv8i8 (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG)
static SDValue	LowerReverse_VECTOR_SHUFFLE (SDValue Op, SelectionDAG &DAG)
static EVT	getVectorTyFromPredicateVector (EVT VT)
static SDValue	PromoteMVEPredVector (SDLoc dl, SDValue Pred, EVT VT, SelectionDAG &DAG)
static SDValue	LowerVECTOR_SHUFFLE_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerVECTOR_SHUFFLEUsingMovs (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG)
static SDValue	LowerVECTOR_SHUFFLEUsingOneOff (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG)
static SDValue	LowerVECTOR_SHUFFLE (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerINSERT_VECTOR_ELT_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerEXTRACT_VECTOR_ELT_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerEXTRACT_VECTOR_ELT (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerCONCAT_VECTORS_i1 (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerCONCAT_VECTORS (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerEXTRACT_SUBVECTOR (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerTruncatei1 (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerTruncate (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	LowerVectorExtend (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static bool	isExtendedBUILD_VECTOR (SDNode *N, SelectionDAG &DAG, bool isSigned)
	isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each element has been zero/sign-extended, depending on the isSigned parameter, from an integer type half its size.
static bool	isSignExtended (SDNode *N, SelectionDAG &DAG)
	isSignExtended - Check if a node is a vector value that is sign-extended or a constant BUILD_VECTOR with sign-extended elements.
static bool	isZeroExtended (SDNode *N, SelectionDAG &DAG)
	isZeroExtended - Check if a node is a vector value that is zero-extended (or any-extended) or a constant BUILD_VECTOR with zero-extended elements.
static EVT	getExtensionTo64Bits (const EVT &OrigVT)
static SDValue	AddRequiredExtensionForVMULL (SDValue N, SelectionDAG &DAG, const EVT &OrigTy, const EVT &ExtTy, unsigned ExtOpcode)
	AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total value size to 64 bits.
static SDValue	SkipLoadExtensionForVMULL (LoadSDNode *LD, SelectionDAG &DAG)
	SkipLoadExtensionForVMULL - return a load of the original vector size that does not do any sign/zero extension.
static SDValue	SkipExtensionForVMULL (SDNode *N, SelectionDAG &DAG)
	SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND, ANY_EXTEND, extending load, or BUILD_VECTOR with extended elements, return the unextended value.
static bool	isAddSubSExt (SDNode *N, SelectionDAG &DAG)
static bool	isAddSubZExt (SDNode *N, SelectionDAG &DAG)
static SDValue	LowerMUL (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerSDIV_v4i8 (SDValue X, SDValue Y, const SDLoc &dl, SelectionDAG &DAG)
static SDValue	LowerSDIV_v4i16 (SDValue N0, SDValue N1, const SDLoc &dl, SelectionDAG &DAG)
static SDValue	LowerSDIV (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerUDIV (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerADDSUBO_CARRY (SDValue Op, SelectionDAG &DAG, unsigned Opcode, bool IsSigned)
static SDValue	WinDBZCheckDenominator (SelectionDAG &DAG, SDNode *N, SDValue InChain)
static SDValue	LowerPredicateLoad (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerPredicateStore (SDValue Op, SelectionDAG &DAG)
static bool	isZeroVector (SDValue N)
static SDValue	LowerMLOAD (SDValue Op, SelectionDAG &DAG)
static SDValue	LowerVecReduce (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerVecReduceF (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerVecReduceMinMax (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	LowerAtomicLoadStore (SDValue Op, SelectionDAG &DAG)
static void	ReplaceREADCYCLECOUNTER (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	createGPRPairNode2xi32 (SelectionDAG &DAG, SDValue V0, SDValue V1)
static SDValue	createGPRPairNodei64 (SelectionDAG &DAG, SDValue V)
static void	ReplaceCMP_SWAP_64Results (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
static void	ReplaceLongIntrinsic (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
static MachineBasicBlock *	OtherSucc (MachineBasicBlock *MBB, MachineBasicBlock *Succ)
static unsigned	getLdOpcode (unsigned LdSize, bool IsThumb1, bool IsThumb2)
	Return the load opcode for a given load size.
static unsigned	getStOpcode (unsigned StSize, bool IsThumb1, bool IsThumb2)
	Return the store opcode for a given store size.
static void	emitPostLd (MachineBasicBlock *BB, MachineBasicBlock::iterator Pos, const TargetInstrInfo *TII, const DebugLoc &dl, unsigned LdSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2)
	Emit a post-increment load operation with given size.
static void	emitPostSt (MachineBasicBlock *BB, MachineBasicBlock::iterator Pos, const TargetInstrInfo *TII, const DebugLoc &dl, unsigned StSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2)
	Emit a post-increment store operation with given size.
static bool	checkAndUpdateCPSRKill (MachineBasicBlock::iterator SelectItr, MachineBasicBlock *BB, const TargetRegisterInfo *TRI)
static Register	genTPEntry (MachineBasicBlock *TpEntry, MachineBasicBlock *TpLoopBody, MachineBasicBlock *TpExit, Register OpSizeReg, const TargetInstrInfo *TII, DebugLoc Dl, MachineRegisterInfo &MRI)
	Adds logic in loop entry MBB to calculate loop iteration count and adds t2WhileLoopSetup and t2WhileLoopStart to generate WLS loop.
static void	genTPLoopBody (MachineBasicBlock *TpLoopBody, MachineBasicBlock *TpEntry, MachineBasicBlock *TpExit, const TargetInstrInfo *TII, DebugLoc Dl, MachineRegisterInfo &MRI, Register OpSrcReg, Register OpDestReg, Register ElementCountReg, Register TotalIterationsReg, bool IsMemcpy)
	Adds logic in the loopBody MBB to generate MVE_VCTP, t2DoLoopDec and t2DoLoopEnd.
static void	attachMEMCPYScratchRegs (const ARMSubtarget *Subtarget, MachineInstr &MI, const SDNode *Node)
	Attaches vregs to MEMCPY that it will use as scratch registers when it is expanded into LDM/STM.
static bool	isZeroOrAllOnes (SDValue N, bool AllOnes)
static bool	isConditionalZeroOrAllOnes (SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG)
static SDValue	combineSelectAndUse (SDNode *N, SDValue Slct, SDValue OtherOp, TargetLowering::DAGCombinerInfo &DCI, bool AllOnes=false)
static SDValue	combineSelectAndUseCommutative (SDNode *N, bool AllOnes, TargetLowering::DAGCombinerInfo &DCI)
static bool	IsVUZPShuffleNode (SDNode *N)
static SDValue	AddCombineToVPADD (SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	AddCombineVUZPToVPADDL (SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	AddCombineBUILD_VECTORToVPADDL (SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	findMUL_LOHI (SDValue V)
static SDValue	AddCombineTo64BitSMLAL16 (SDNode *AddcNode, SDNode *AddeNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	AddCombineTo64bitMLAL (SDNode *AddeSubeNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	AddCombineTo64bitUMAAL (SDNode *AddeNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	PerformUMLALCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	PerformAddcSubcCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	PerformAddeSubeCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	PerformSELECTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	PerformVQDMULHCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformVSELECTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	PerformVSetCCToVCTPCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	PerformADDECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
	PerformADDECombine - Target-specific dag combine transform from ARMISD::ADDC, ARMISD::ADDE, and ISD::MUL_LOHI to MLAL or ARMISD::ADDC, ARMISD::ADDE and ARMISD::UMLAL to ARMISD::UMAAL.
static SDValue	PerformADDCombineWithOperands (SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
	PerformADDCombineWithOperands - Try DAG combinations for an ADD with operands N0 and N1.
static SDValue	TryDistrubutionADDVecReduce (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformADDVecReduce (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	PerformSHLSimplify (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *ST)
static SDValue	PerformADDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
	PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
static SDValue	PerformSubCSINCCombine (SDNode *N, SelectionDAG &DAG)
static int	getNegationCost (SDValue Op)
static SDValue	performNegCMovCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformSUBCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
	PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
static SDValue	PerformVMULCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
	PerformVMULCombine Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the special multiplier accumulator forwarding.
static SDValue	PerformMVEVMULLCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	PerformMULCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	CombineANDShift (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	PerformANDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	PerformORCombineToSMULWBT (SDNode *OR, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	PerformORCombineToBFI (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static bool	isValidMVECond (unsigned CC, bool IsFloat)
static ARMCC::CondCodes	getVCMPCondCode (SDValue N)
static bool	CanInvertMVEVCMP (SDValue N)
static SDValue	PerformORCombine_i1 (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	PerformORCombineToShiftInsert (SelectionDAG &DAG, SDValue AndOp, SDValue ShiftOp, EVT VT, SDLoc dl)
static SDValue	PerformORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
	PerformORCombine - Target-specific dag combine xforms for ISD::OR.
static SDValue	PerformXORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	ParseBFI (SDNode *N, APInt &ToMask, APInt &FromMask)
static bool	BitsProperlyConcatenate (const APInt &A, const APInt &B)
static SDValue	FindBFIToCombineWith (SDNode *N)
static SDValue	PerformBFICombine (SDNode *N, SelectionDAG &DAG)
static SDValue	IsCMPZCSINC (SDNode *Cmp, ARMCC::CondCodes &CC)
static SDValue	PerformCMPZCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformCSETCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformVMOVRRDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
	PerformVMOVRRDCombine - Target-specific dag combine xforms for ARMISD::VMOVRRD.
static SDValue	PerformVMOVDRRCombine (SDNode *N, SelectionDAG &DAG)
	PerformVMOVDRRCombine - Target-specific dag combine xforms for ARMISD::VMOVDRR.
static SDValue	PerformVMOVhrCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformVMOVrhCombine (SDNode *N, SelectionDAG &DAG)
static bool	hasNormalLoadOperand (SDNode *N)
	hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node are normal, non-volatile loads.
static SDValue	PerformBUILD_VECTORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
	PerformBUILD_VECTORCombine - Target-specific dag combine xforms for ISD::BUILD_VECTOR.
static SDValue	PerformLegalizedVECTOR_DEINTERLEAVECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	PerformVECTOR_DEINTERLEAVECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	PerformARMBUILD_VECTORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
	Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.
static SDValue	PerformPREDICATE_CASTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformVECTOR_REG_CASTCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	PerformVCMPCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	PerformInsertEltCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
	PerformInsertEltCombine - Target-specific dag combine xforms for ISD::INSERT_VECTOR_ELT.
static SDValue	PerformExtractEltToVMOVRRD (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformExtractEltCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *ST)
static SDValue	PerformSignExtendInregCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformInsertSubvectorCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformShuffleVMOVNCombine (ShuffleVectorSDNode *N, SelectionDAG &DAG)
static SDValue	PerformVECTOR_SHUFFLECombine (SDNode *N, SelectionDAG &DAG)
	PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for ISD::VECTOR_SHUFFLE.
static bool	isValidBaseUpdate (SDNode *N, SDNode *User)
static bool	TryCombineBaseUpdate (struct BaseUpdateTarget &Target, struct BaseUpdateUser &User, bool SimpleConstIncOnly, TargetLowering::DAGCombinerInfo &DCI)
static unsigned	getPointerConstIncrement (unsigned Opcode, SDValue Ptr, SDValue Inc, const SelectionDAG &DAG)
static bool	findPointerConstIncrement (SDNode *N, SDValue *Ptr, SDValue *CInc)
static SDValue	CombineBaseUpdate (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
	CombineBaseUpdate - Target-specific DAG combine function for VLDDUP, NEON load/store intrinsics, and generic vector load/stores, to merge base address updates.
static SDValue	PerformVLDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformMVEVLDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static bool	CombineVLDDUP (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
	CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic are also VDUPLANEs.
static SDValue	PerformVDUPLANECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
	PerformVDUPLANECombine - Target-specific dag combine xforms for ARMISD::VDUPLANE.
static SDValue	PerformVDUPCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
	PerformVDUPCombine - Target-specific dag combine xforms for ARMISD::VDUP.
static SDValue	PerformLOADCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
static SDValue	PerformTruncatingStoreCombine (StoreSDNode *St, SelectionDAG &DAG)
static SDValue	PerformSplittingToNarrowingStores (StoreSDNode *St, SelectionDAG &DAG)
static SDValue	PerformSplittingMVETruncToNarrowingStores (StoreSDNode *St, SelectionDAG &DAG)
static SDValue	PerformExtractFpToIntStores (StoreSDNode *St, SelectionDAG &DAG)
static SDValue	PerformLegalizedInterleavedStoreCombine (StoreSDNode *ST, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static bool	isSequentialConcatOfVectorInterleave (SDNode *N, SmallVectorImpl< SDValue > &Ops)
static SDValue	PerformInterleavedStoreCombine (StoreSDNode *ST, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	PerformSTORECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)
	PerformSTORECombine - Target-specific dag combine xforms for ISD::STORE.
static SDValue	PerformVCVTCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
	PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD) can replace combinations of VMUL and VCVT (floating-point to integer) when the VMUL has a constant operand that is a power of 2.
static SDValue	PerformFAddVSelectCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	PerformFADDVCMLACombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformFADDCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	PerformVMulVCTPCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
	PerformVMulVCTPCombine - VCVT (fixed-point to floating-point, Advanced SIMD) can replace combinations of VCVT (integer to floating-point) and VMUL when the VMUL has a constant operand that is a power of 2.
static SDValue	PerformVECREDUCE_ADDCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	PerformReduceShuffleCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformVMOVNCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformVQMOVNCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformVQDMULHCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	PerformLongShiftCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformShiftCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *ST)
	PerformShiftCombine - Checks for immediate versions of vector shifts and lowers them.
static SDValue	PerformSplittingToWideningLoad (SDNode *N, SelectionDAG &DAG)
static SDValue	PerformExtendCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
	PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
static SDValue	PerformFPExtendCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
static SDValue	PerformMinMaxToSatCombine (SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)
static SDValue	PerformMinMaxCombine (SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST)
	PerformMinMaxCombine - Target-specific DAG combining for creating truncating saturates.
static const APInt *	isPowerOf2Constant (SDValue V)
static SDValue	SearchLoopIntrinsic (SDValue N, ISD::CondCode &CC, int &Imm, bool &Negate)
static SDValue	PerformHWLoopCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *ST)
static SDValue	PerformBITCASTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *ST)
static SDValue	PerformSplittingMVEEXTToWideningLoad (SDNode *N, SelectionDAG &DAG)
static bool	isLegalT1AddressImmediate (int64_t V, EVT VT)
static bool	isLegalT2AddressImmediate (int64_t V, EVT VT, const ARMSubtarget *Subtarget)
static bool	isLegalAddressImmediate (int64_t V, EVT VT, const ARMSubtarget *Subtarget)
	isLegalAddressImmediate - Return true if the integer value can be used as the offset of the target addressing mode for load / store of the given type.
static bool	getARMIndexedAddressParts (SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG)
static bool	getT2IndexedAddressParts (SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG)
static bool	getMVEIndexedAddressParts (SDNode *Ptr, EVT VT, Align Alignment, bool isSEXTLoad, bool IsMasked, bool isLE, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG)
static bool	isLegalLogicalImmediate (unsigned Imm, const ARMSubtarget *Subtarget)
static bool	optimizeLogicalImm (SDValue Op, unsigned Imm, const APInt &DemandedBits, const ARMSubtarget *Subtarget, TargetLowering::TargetLoweringOpt &TLO)
	Refine i32 AND/OR/XOR with a constant RHS using demanded bits: replace the immediate with an equivalent constant that ARM/Thumb can encode as a logical immediate (or that selects better lowering), without changing the computed result on those demanded bits.
static bool	isIncompatibleReg (const MCPhysReg &PR, MVT VT)
static RTLIB::Libcall	getDivRemLibcall (const SDNode *N, MVT::SimpleValueType SVT)
static TargetLowering::ArgListTy	getDivRemArgList (const SDNode *N, FunctionType *FuncTy, const AttributeList &FuncAttrs, RTLIB::LibcallImpl LCImpl)
static bool	isHomogeneousAggregate (Type *Ty, HABaseType &Base, uint64_t &Members)

Variables
static cl::opt< bool >	ARMInterworking ("arm-interworking", cl::Hidden, cl::desc("Enable / disable ARM interworking (for debugging only)"), cl::init(true))
static cl::opt< bool >	EnableConstpoolPromotion ("arm-promote-constant", cl::Hidden, cl::desc("Enable / disable promotion of unnamed_addr constants into " "constant pools"), cl::init(false))
static cl::opt< unsigned >	ConstpoolPromotionMaxSize ("arm-promote-constant-max-size", cl::Hidden, cl::desc("Maximum size of constant to promote into a constant pool"), cl::init(64))
static cl::opt< unsigned >	ConstpoolPromotionMaxTotal ("arm-promote-constant-max-total", cl::Hidden, cl::desc("Maximum size of ALL constants to promote into a constant pool"), cl::init(128))
cl::opt< unsigned >	MVEMaxSupportedInterleaveFactor ("mve-max-interleave-factor", cl::Hidden, cl::desc("Maximum interleave factor for MVE VLDn to generate."), cl::init(2))
cl::opt< unsigned >	ArmMaxBaseUpdatesToCheck ("arm-max-base-updates-to-check", cl::Hidden, cl::desc("Maximum number of base-updates to check generating postindex."), cl::init(64))
constexpr MVT	FlagsVT = MVT::i32
	Value type used for "flags" operands / results (either CPSR or FPSCR_NZCV).
static const MCPhysReg	GPRArgRegs []

Macro Definition Documentation

DEBUG_TYPE

#define DEBUG_TYPE   "arm-isel"

Definition at line 117 of file ARMISelLowering.cpp.

Typedef Documentation

RCPair

using RCPair = std::pair<unsigned, const TargetRegisterClass *>

Definition at line 20874 of file ARMISelLowering.cpp.

Enumeration Type Documentation

HABaseType

enum HABaseType

Enumerator
HA_UNKNOWN
HA_FLOAT
HA_DOUBLE
HA_VECT64
HA_VECT128

Definition at line 22450 of file ARMISelLowering.cpp.

ShuffleOpCodes

enum ShuffleOpCodes

Enumerator
OP_COPY
OP_VREV
OP_VDUP0
OP_VDUP1
OP_VDUP2
OP_VDUP3
OP_VEXT1
OP_VEXT2
OP_VEXT3
OP_VUZPL
OP_VUZPR
OP_VZIPL
OP_VZIPR
OP_VTRNL
OP_VTRNR

Definition at line 8068 of file ARMISelLowering.cpp.

Function Documentation

AddCombineBUILD_VECTORToVPADDL()

SDValue AddCombineBUILD_VECTORToVPADDL ( SDNode * N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

Definition at line 12572 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ANY_EXTEND, llvm::EVT::bitsGT(), llvm::ISD::BUILD_VECTOR, C0, C1, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::EVT::isInteger(), llvm_unreachable, N, llvm::MVT::SimpleTy, and llvm::ISD::TRUNCATE.

Referenced by PerformADDCombineWithOperands().

AddCombineTo64bitMLAL()

SDValue AddCombineTo64bitMLAL ( SDNode * AddeSubeNode, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

Definition at line 12753 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, AddCombineTo64BitSMLAL16(), assert(), llvm::ISD::Constant, llvm::TargetLowering::DAGCombinerInfo::DAG, findMUL_LOHI(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getNumValues(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNode::hasAnyUseOfValue(), llvm::SDNode::isPredecessorOf(), Opc, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SMUL_LOHI, llvm::ISD::UMUL_LOHI, and llvm::ARMSubtarget::useMulOps().

Referenced by AddCombineTo64bitUMAAL(), and PerformAddeSubeCombine().

AddCombineTo64BitSMLAL16()

SDValue AddCombineTo64BitSMLAL16 ( SDNode * AddcNode, SDNode * AddeNode, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

Definition at line 12676 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getVTList(), llvm::ARMSubtarget::hasBaseDSP(), llvm::Hi, isS16(), isSRA16(), Lo, llvm::ISD::MUL, Mul, llvm::TargetLowering::DAGCombinerInfo::recursivelyDeleteUnusedNodes(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), and llvm::ISD::SRA.

Referenced by AddCombineTo64bitMLAL().

AddCombineTo64bitUMAAL()

SDValue AddCombineTo64bitUMAAL ( SDNode * AddeNode, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

Definition at line 12919 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, AddCombineTo64bitMLAL(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getVTList(), llvm::isNullConstant(), and llvm::SelectionDAG::ReplaceAllUsesOfValueWith().

Referenced by PerformADDECombine().

AddCombineToVPADD()

SDValue AddCombineToVPADD ( SDNode * N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

Definition at line 12491 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::ISD::INTRINSIC_WO_CHAIN, IsVUZPShuffleNode(), and N.

Referenced by PerformADDCombineWithOperands().

AddCombineVUZPToVPADDL()

SDValue AddCombineVUZPToVPADDL ( SDNode * N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

Definition at line 12519 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, Concat, llvm::ISD::CONCAT_VECTORS, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), IsVUZPShuffleNode(), N, llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.

Referenced by PerformADDCombineWithOperands().

AddRequiredExtensionForVMULL()

SDValue AddRequiredExtensionForVMULL ( SDValue N, SelectionDAG & DAG, const EVT & OrigTy, const EVT & ExtTy, unsigned ExtOpcode )

static

AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total value size to 64 bits.

We need a 64-bit D register as an operand to VMULL. We insert the required extension here to get the vector to fill a D register.

Definition at line 9200 of file ARMISelLowering.cpp.

References assert(), getExtensionTo64Bits(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::EVT::is128BitVector(), and N.

Referenced by SkipExtensionForVMULL().

allUsersAreInFunction()

bool allUsersAreInFunction ( const Value * V, const Function * F )

static

Return true if all users of V are within function F, looking through ConstantExprs.

Definition at line 3560 of file ARMISelLowering.cpp.

References llvm::append_range(), llvm::dyn_cast(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), F, I, llvm::isa(), and llvm::SmallVectorImpl< T >::pop_back_val().

Referenced by promoteToConstantPool().

attachMEMCPYScratchRegs()

void attachMEMCPYScratchRegs ( const ARMSubtarget * Subtarget, MachineInstr & MI, const SDNode * Node )

static

Attaches vregs to MEMCPY that it will use as scratch registers when it is expanded into LDM/STM.

This is done as a post-isel lowering instead of as a custom inserter because we need the use list from the SDNode.

Definition at line 12223 of file ARMISelLowering.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::Dead, llvm::Define, llvm::getImm(), llvm::MachineFunction::getRegInfo(), I, llvm::ARMSubtarget::isThumb1Only(), MI, and MRI.

Referenced by llvm::ARMTargetLowering::AdjustInstrPostInstrSelection().

bitcastf32Toi32()

SDValue bitcastf32Toi32 ( SDValue Op, SelectionDAG & DAG )

static

Definition at line 5540 of file ARMISelLowering.cpp.

References llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getLoad(), isFloatingPointZero(), and llvm_unreachable.

BitsProperlyConcatenate()

bool BitsProperlyConcatenate ( const APInt & A, const APInt & B )

static

Definition at line 14875 of file ARMISelLowering.cpp.

References A(), and B().

Referenced by FindBFIToCombineWith().

canChangeToInt()

bool canChangeToInt ( SDValue Op, bool & SeenZero, const ARMSubtarget * Subtarget )

static

canChangeToInt - Given the fp compare operand, return true if it is suitable to morph to an integer compare sequence.

Definition at line 5519 of file ARMISelLowering.cpp.

References isFloatingPointZero(), llvm::ISD::isNormalLoad(), and N.

canGuaranteeTCO()

bool canGuaranteeTCO ( CallingConv::ID CC, bool GuaranteeTailCalls )

static

Definition at line 2004 of file ARMISelLowering.cpp.

References CC, llvm::CallingConv::Fast, llvm::CallingConv::SwiftTail, and llvm::CallingConv::Tail.

CanInvertMVEVCMP()

bool CanInvertMVEVCMP ( SDValue N )

static

Definition at line 14597 of file ARMISelLowering.cpp.

References CC, llvm::ARMCC::getOppositeCondition(), getVCMPCondCode(), isValidMVECond(), and N.

Referenced by PerformORCombine_i1(), and PerformXORCombine().

carryFlagToValue()

SDValue carryFlagToValue ( SDValue Flags, EVT VT, SelectionDAG & DAG, bool Invert )

static

Definition at line 4908 of file ARMISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), and llvm::ISD::SUB.

checkAndUpdateCPSRKill()

bool checkAndUpdateCPSRKill ( MachineBasicBlock::iterator SelectItr, MachineBasicBlock * BB, const TargetRegisterInfo * TRI )

static

Definition at line 11677 of file ARMISelLowering.cpp.

References llvm::MachineInstr::definesRegister(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::readsRegister(), llvm::MachineBasicBlock::successors(), and TRI.

Referenced by llvm::ARMTargetLowering::EmitInstrWithCustomInserter().

checkVSELConstraints()

void checkVSELConstraints ( ISD::CondCode CC, ARMCC::CondCodes & CondCode, bool & swpCmpOps, bool & swpVselOps )

static

Definition at line 5091 of file ARMISelLowering.cpp.

References CC, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, and llvm::ARMCC::VS.

CombineANDShift()

SDValue CombineANDShift ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

Definition at line 14223 of file ARMISelLowering.cpp.

References llvm::ISD::AND, C1, llvm::countl_zero(), llvm::countr_zero(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::HasLowerConstantMaterializationCost(), llvm::SDNode::hasOneUse(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::isMask_32(), llvm::isShiftedMask_32(), N, llvm::ISD::SHL, and llvm::ISD::SRL.

Referenced by PerformANDCombine().

CombineBaseUpdate()

SDValue CombineBaseUpdate ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI )

static

CombineBaseUpdate - Target-specific DAG combine function for VLDDUP, NEON load/store intrinsics, and generic vector load/stores, to merge base address updates.

For generic load/stores, the memory type is assumed to be a vector. The caller is assumed to have checked legality.

Definition at line 16363 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, ArmMaxBaseUpdatesToCheck, llvm::sampleprof::Base, llvm::TargetLowering::DAGCombinerInfo::DAG, findPointerConstIncrement(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::User::getNumOperands(), llvm::SDNode::getOpcode(), llvm::User::getOperand(), llvm::Use::getOperandNo(), getPointerConstIncrement(), llvm::SDValue::getResNo(), llvm::Use::getUser(), I, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, isIntrinsic(), isStore(), LHS, N, llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), RHS, llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::stable_sort(), llvm::ISD::STORE, TryCombineBaseUpdate(), and llvm::SDNode::uses().

Referenced by PerformLOADCombine(), PerformSTORECombine(), and PerformVLDCombine().

combineSelectAndUse()

SDValue combineSelectAndUse ( SDNode * N, SDValue Slct, SDValue OtherOp, TargetLowering::DAGCombinerInfo & DCI, bool AllOnes = false )

static

Definition at line 12440 of file ARMISelLowering.cpp.

References llvm::AllOnes, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), isConditionalZeroOrAllOnes(), N, llvm::ISD::SELECT, and std::swap().

Referenced by combineSelectAndUseCommutative(), combineSelectAndUseCommutative(), combineSelectAndUseCommutative(), PerformADDCombineWithOperands(), PerformSUBCombine(), PerformSUBCombine(), and performSUBCombine().

combineSelectAndUseCommutative()

SDValue combineSelectAndUseCommutative ( SDNode * N, bool AllOnes, TargetLowering::DAGCombinerInfo & DCI )

static

Definition at line 12466 of file ARMISelLowering.cpp.

References llvm::AllOnes, combineSelectAndUse(), llvm::SDValue::getNode(), llvm::SDNode::hasOneUse(), and N.

Referenced by performADDCombine(), PerformANDCombine(), performANDCombine(), llvm::LanaiTargetLowering::PerformDAGCombine(), PerformORCombine(), performORCombine(), PerformXORCombine(), and performXORCombine().

CombineVLDDUP()

bool CombineVLDDUP ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI )

static

CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic are also VDUPLANEs.

If so, combine them to a vldN-dup operation and return true.

Definition at line 16580 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ArrayRef(), llvm::cast(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDNode::getConstantOperandVal(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::Use::getUser(), llvm::SelectionDAG::getVTList(), llvm::ISD::INTRINSIC_W_CHAIN, llvm::EVT::is64BitVector(), N, llvm::SDNode::uses(), llvm::ARMISD::VLD2DUP, llvm::ARMISD::VLD3DUP, and llvm::ARMISD::VLD4DUP.

Referenced by PerformVDUPLANECombine().

CombineVMOVDRRCandidateWithVecOp()

SDValue CombineVMOVDRRCandidateWithVecOp ( const SDNode * BC, SelectionDAG & DAG )

static

BC is a bitcast that is about to be turned into a VMOVDRR.

When DstVT, the destination type of BC, is on the vector register bank and the source of bitcast, Op, operates on the same bank, it might be possible to combine them, such that everything stays on the vector register bank. return The node that would replace BT, if the combine is possible.

Definition at line 6122 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::SDNode::getValueType(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::APInt::getZExtValue(), and llvm::EVT::isVector().

createGPRPairNode2xi32()

SDValue createGPRPairNode2xi32 ( SelectionDAG & DAG, SDValue V0, SDValue V1 )

static

Definition at line 10154 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), and llvm::V1.

Referenced by createGPRPairNodei64(), and ReplaceCMP_SWAP_64Results().

createGPRPairNodei64()

SDValue createGPRPairNodei64 ( SelectionDAG & DAG, SDValue V )

static

Definition at line 10166 of file ARMISelLowering.cpp.

References createGPRPairNode2xi32(), llvm::SelectionDAG::getDataLayout(), isBigEndian(), llvm::DataLayout::isBigEndian(), llvm::SelectionDAG::SplitScalar(), and std::swap().

Referenced by ReplaceCMP_SWAP_64Results().

emitPostLd()

void emitPostLd ( MachineBasicBlock * BB, MachineBasicBlock::iterator Pos, const TargetInstrInfo * TII, const DebugLoc & dl, unsigned LdSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2 )

static

Emit a post-increment load operation with given size.

The instructions will be added to BB at Pos.

Definition at line 11233 of file ARMISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::Data, llvm::Define, getLdOpcode(), llvm::predOps(), llvm::t1CondCodeOp(), and TII.

emitPostSt()

void emitPostSt ( MachineBasicBlock * BB, MachineBasicBlock::iterator Pos, const TargetInstrInfo * TII, const DebugLoc & dl, unsigned StSize, unsigned Data, unsigned AddrIn, unsigned AddrOut, bool IsThumb1, bool IsThumb2 )

static

Emit a post-increment store operation with given size.

The instructions will be added to BB at Pos.

Definition at line 11274 of file ARMISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::Data, getStOpcode(), llvm::predOps(), llvm::t1CondCodeOp(), and TII.

Expand64BitShift()

SDValue Expand64BitShift ( SDNode * N, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 6624 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BUILD_PAIR, llvm::dyn_cast(), FlagsVT, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::Hi, llvm::isOneConstant(), Lo, N, Opc, llvm::ISD::SHL, llvm::SelectionDAG::SplitScalar(), llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, and llvm::APInt::uge().

Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().

expandf64Toi32()

void expandf64Toi32 ( SDValue Op, SelectionDAG & DAG, SDValue & RetVal1, SDValue & RetVal2 )

static

Definition at line 5552 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::commonAlignment(), llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getFlags(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), isFloatingPointZero(), and llvm_unreachable.

ExpandREAD_REGISTER()

void ExpandREAD_REGISTER ( SDNode * N, SmallVectorImpl< SDValue > & Results, SelectionDAG & DAG )

static

Definition at line 6097 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BUILD_PAIR, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), N, llvm::Read, llvm::ISD::READ_REGISTER, and Results.

Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().

FindBFIToCombineWith()

SDValue FindBFIToCombineWith ( SDNode * N )

static

Definition at line 14881 of file ARMISelLowering.cpp.

References BitsProperlyConcatenate(), N, and ParseBFI().

Referenced by PerformBFICombine().

findMUL_LOHI()

SDValue findMUL_LOHI ( SDValue V )

static

Definition at line 12669 of file ARMISelLowering.cpp.

References llvm::ISD::SMUL_LOHI, and llvm::ISD::UMUL_LOHI.

Referenced by AddCombineTo64bitMLAL().

findPointerConstIncrement()

bool findPointerConstIncrement ( SDNode * N, SDValue * Ptr, SDValue * CInc )

static

Definition at line 16334 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::isa(), N, llvm::ISD::OR, and llvm::ARMISD::VLD1_UPD.

Referenced by CombineBaseUpdate().

FPCCToARMCC()

void FPCCToARMCC ( ISD::CondCode CC, ARMCC::CondCodes & CondCode, ARMCC::CondCodes & CondCode2 )

static

FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.

Definition at line 1653 of file ARMISelLowering.cpp.

References llvm::ARMCC::AL, CC, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::LE, llvm_unreachable, llvm::ARMCC::LS, llvm::ARMCC::LT, llvm::ARMCC::MI, llvm::ARMCC::NE, llvm::ARMCC::PL, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, llvm::ARMCC::VC, and llvm::ARMCC::VS.

GeneratePerfectShuffle()

SDValue GeneratePerfectShuffle ( unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG & DAG, const SDLoc & dl )

static

GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle.

Definition at line 8159 of file ARMISelLowering.cpp.

References assert(), GeneratePerfectShuffle(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), LHS, llvm_unreachable, OP_COPY, OP_VDUP0, OP_VDUP1, OP_VDUP2, OP_VDUP3, OP_VEXT1, OP_VEXT2, OP_VEXT3, OP_VREV, OP_VTRNL, OP_VTRNR, OP_VUZPL, OP_VUZPR, OP_VZIPL, OP_VZIPR, llvm::PerfectShuffleTable, and RHS.

Referenced by GeneratePerfectShuffle(), GeneratePerfectShuffle(), and LowerVECTOR_SHUFFLE().

genTPEntry()

Register genTPEntry ( MachineBasicBlock * TpEntry, MachineBasicBlock * TpLoopBody, MachineBasicBlock * TpExit, Register OpSizeReg, const TargetInstrInfo * TII, DebugLoc Dl, MachineRegisterInfo & MRI )

static

Adds logic in loop entry MBB to calculate loop iteration count and adds t2WhileLoopSetup and t2WhileLoopStart to generate WLS loop.

Definition at line 11706 of file ARMISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addUse(), llvm::ARMCC::AL, llvm::BuildMI(), MRI, llvm::predOps(), and TII.

Referenced by llvm::ARMTargetLowering::EmitInstrWithCustomInserter().

genTPLoopBody()

void genTPLoopBody ( MachineBasicBlock * TpLoopBody, MachineBasicBlock * TpEntry, MachineBasicBlock * TpExit, const TargetInstrInfo * TII, DebugLoc Dl, MachineRegisterInfo & MRI, Register OpSrcReg, Register OpDestReg, Register ElementCountReg, Register TotalIterationsReg, bool IsMemcpy )

static

Adds logic in the loopBody MBB to generate MVE_VCTP, t2DoLoopDec and t2DoLoopEnd.

These are used by later passes to generate tail predicated loops.

Definition at line 11744 of file ARMISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addUse(), llvm::ARMCC::AL, llvm::BuildMI(), MRI, llvm::ARMVCC::None, llvm::predOps(), llvm::ARMVCC::Then, and TII.

Referenced by llvm::ARMTargetLowering::EmitInstrWithCustomInserter().

getARMIndexedAddressParts()

bool getARMIndexedAddressParts ( SDNode * Ptr, EVT VT, bool isSEXTLoad, SDValue & Base, SDValue & Offset, bool & isInc, SelectionDAG & DAG )

static

Definition at line 20141 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::sampleprof::Base, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::ARM_AM::getShiftOpcForNode(), llvm::ARM_AM::no_shift, llvm::Offset, RHS, and llvm::ISD::SUB.

Referenced by llvm::ARMTargetLowering::getPostIndexedAddressParts(), and llvm::ARMTargetLowering::getPreIndexedAddressParts().

getCmpOperandFoldingProfit()

unsigned getCmpOperandFoldingProfit ( SDValue Op, const ARMSubtarget & ST )

static

Returns how profitable it is to fold a comparison's operand's shift and/or extension operations into the comparison instruction's second operand (so_reg_imm / so_reg_reg for ARM, t2_so_reg for Thumb-2).

Definition at line 4583 of file ARMISelLowering.cpp.

References llvm::dyn_cast(), llvm::isa(), Opc, llvm::ISD::ROTR, llvm::ISD::SHL, llvm::ISD::SRA, and llvm::ISD::SRL.

getDivRemArgList()

TargetLowering::ArgListTy getDivRemArgList ( const SDNode * N, FunctionType * FuncTy, const AttributeList & FuncAttrs, RTLIB::LibcallImpl LCImpl )

static

Definition at line 21144 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, assert(), llvm::TargetLowering::getArgListForFunctionType(), N, llvm::ISD::SDIVREM, llvm::ISD::SREM, std::swap(), llvm::ISD::UDIVREM, and llvm::ISD::UREM.

getDivRemLibcall()

RTLIB::Libcall getDivRemLibcall ( const SDNode * N, MVT::SimpleValueType SVT )

static

Definition at line 21125 of file ARMISelLowering.cpp.

References assert(), isSigned(), llvm_unreachable, N, llvm::ISD::SDIVREM, llvm::ISD::SREM, llvm::ISD::UDIVREM, and llvm::ISD::UREM.

getExtensionTo64Bits()

EVT getExtensionTo64Bits ( const EVT & OrigVT )

static

Definition at line 9180 of file ARMISelLowering.cpp.

References assert(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::EVT::isSimple(), llvm_unreachable, and llvm::MVT::SimpleTy.

Referenced by AddRequiredExtensionForVMULL(), and SkipLoadExtensionForVMULL().

getInvertedARMCondCode()

SDValue getInvertedARMCondCode ( SDValue ARMcc, SelectionDAG & DAG )

static

Definition at line 5645 of file ARMISelLowering.cpp.

References llvm::cast(), llvm::SelectionDAG::getConstant(), and llvm::ARMCC::getOppositeCondition().

getLdOpcode()

unsigned getLdOpcode ( unsigned LdSize, bool IsThumb1, bool IsThumb2 )

static

Return the load opcode for a given load size.

If load size >= 8, neon opcode will be returned.

Definition at line 11195 of file ARMISelLowering.cpp.

Referenced by emitPostLd().

getMVEIndexedAddressParts()

bool getMVEIndexedAddressParts ( SDNode * Ptr, EVT VT, Align Alignment, bool isSEXTLoad, bool IsMasked, bool isLE, SDValue & Base, SDValue & Offset, bool & isInc, SelectionDAG & DAG )

static

Definition at line 20225 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::sampleprof::Base, llvm::cast(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::isa(), llvm::Offset, RHS, and llvm::ISD::SUB.

Referenced by llvm::ARMTargetLowering::getPostIndexedAddressParts(), and llvm::ARMTargetLowering::getPreIndexedAddressParts().

getNegationCost()

int getNegationCost ( SDValue Op )

static

Definition at line 13931 of file ARMISelLowering.cpp.

References llvm::dyn_cast(), llvm::ConstantSDNode::getZExtValue(), llvm::isa(), llvm::isNullConstant(), llvm::ISD::SRA, llvm::ISD::SRL, and llvm::ISD::SUB.

Referenced by performNegCMovCombine().

getPointerConstIncrement()

unsigned getPointerConstIncrement ( unsigned Opcode, SDValue Ptr, SDValue Inc, const SelectionDAG & DAG )

static

Definition at line 16312 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::ConstantSDNode::getZExtValue(), llvm::SelectionDAG::haveNoCommonBitsSet(), llvm::ISD::OR, and llvm::ARMISD::VLD1_UPD.

Referenced by CombineBaseUpdate().

getShiftedLowMaskZeroTest()

SDValue getShiftedLowMaskZeroTest ( SDValue Value, SelectionDAG & DAG, const SDLoc & DL )

static

Definition at line 4609 of file ARMISelLowering.cpp.

References llvm::ISD::AND, llvm::countl_zero(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::Value::hasOneUse(), llvm::isMask_32(), and llvm::ISD::SHL.

Referenced by llvm::ARMTargetLowering::PerformCMOVCombine().

getStOpcode()

unsigned getStOpcode ( unsigned StSize, bool IsThumb1, bool IsThumb2 )

static

Return the store opcode for a given store size.

If store size >= 8, neon opcode will be returned.

Definition at line 11214 of file ARMISelLowering.cpp.

Referenced by emitPostSt().

getT2IndexedAddressParts()

bool getT2IndexedAddressParts ( SDNode * Ptr, EVT VT, bool isSEXTLoad, SDValue & Base, SDValue & Offset, bool & isInc, SelectionDAG & DAG )

static

Definition at line 20200 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::sampleprof::Base, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::Offset, RHS, and llvm::ISD::SUB.

Referenced by llvm::ARMTargetLowering::getPostIndexedAddressParts(), and llvm::ARMTargetLowering::getPreIndexedAddressParts().

getVCMPCondCode()

ARMCC::CondCodes getVCMPCondCode ( SDValue N )

static

Definition at line 14588 of file ARMISelLowering.cpp.

References llvm_unreachable, and N.

Referenced by CanInvertMVEVCMP(), and PerformXORCombine().

getVectorTyFromPredicateVector()

EVT getVectorTyFromPredicateVector ( EVT VT )

static

Definition at line 8255 of file ARMISelLowering.cpp.

References llvm::EVT::getSimpleVT(), llvm_unreachable, and llvm::MVT::SimpleTy.

Referenced by LowerCONCAT_VECTORS_i1(), LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_VECTOR_ELT_i1(), LowerINSERT_VECTOR_ELT_i1(), and PromoteMVEPredVector().

getVShiftImm()

bool getVShiftImm ( SDValue Op, unsigned ElementBits, int64_t & Cnt )

static

Getvshiftimm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value.

Definition at line 6531 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::APInt::getSExtValue(), and llvm::BuildVectorSDNode::isConstantSplat().

getZeroVector()

SDValue getZeroVector ( EVT VT, SelectionDAG & DAG, const SDLoc & dl )

static

getZeroVector - Returns a vector of specified type with all zero elements.

Zero vectors are used to represent vector negation and in those cases will be implemented with the NEON VNEG instruction. However, VNEG does not support i64 elements, so sometimes the zero vectors will need to be explicitly constructed. Regardless, use a canonical VMOV to create the zero vector.

Definition at line 6233 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::EVT::is128BitVector(), and llvm::EVT::isVector().

Referenced by canonicalizeShuffleMaskWithHorizOp(), combineAdd(), combineAnd(), combineAndnp(), combineArithReduction(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineINSERT_SUBVECTOR(), combineMulToPMADD52(), combineTargetShuffle(), combineVTRUNCSAT(), combineX86ShuffleChain(), combineX86ShufflesConstants(), combineX86ShufflesRecursively(), createVariablePermute(), getAVX2GatherNode(), getGatherNode(), getNullFPConstForNullVal(), getScalarMaskingNode(), getShuffleVectorZeroOrUndef(), getVectorMaskingNode(), LowerAVXCONCAT_VECTORS(), LowerBuildVectorAsInsert(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), LowerCTTZ(), LowerMGATHER(), LowerMLOAD(), LowerSCALAR_TO_VECTOR(), LowerShift(), lowerShuffleAsBlend(), lowerShuffleAsSpecificExtension(), lowerShuffleAsVALIGN(), lowerShuffleWithEXPAND(), lowerShuffleWithSHUFPD(), lowerV16I8Shuffle(), lowerV2X128Shuffle(), lowerV4X128Shuffle(), lowerV8I16Shuffle(), lowerVECTOR_SHUFFLE(), matchBinaryPermuteShuffle(), matchShuffleWithUNPCK(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), and widenSubVector().

handleCMSEValue()

SDValue handleCMSEValue ( const SDValue & Value, const ISD::InputArg & Arg, SelectionDAG & DAG, const SDLoc & DL )

static

Definition at line 163 of file ARMISelLowering.cpp.

References llvm::ISD::InputArg::ArgVT, assert(), llvm::EVT::bitsLT(), DL, llvm::ISD::InputArg::Flags, llvm::SelectionDAG::getNode(), llvm::EVT::isScalarInteger(), llvm::ISD::ArgFlagsTy::isSExt(), llvm::ISD::SIGN_EXTEND, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

hasNormalLoadOperand()

bool hasNormalLoadOperand ( SDNode * N )

static

hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node are normal, non-volatile loads.

If so, it is profitable to bitcast an i64 vector to have f64 elements, since the value can then be loaded directly into a VFP register.

Definition at line 15260 of file ARMISelLowering.cpp.

References llvm::cast(), llvm::ISD::isNormalLoad(), and N.

Referenced by PerformBUILD_VECTORCombine().

IntCCToARMCC()

ARMCC::CondCodes IntCCToARMCC ( ISD::CondCode CC )

static

IntCCToARMCC - Convert a DAG integer condition code to an ARM CC.

Definition at line 1636 of file ARMISelLowering.cpp.

References CC, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ARMCC::LE, llvm_unreachable, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, llvm::ARMCC::NE, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, and llvm::ISD::SETULT.

Referenced by LowerSETCCCARRY().

isAddSubSExt()

bool isAddSubSExt ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 9296 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::SDNode::hasOneUse(), isSignExtended(), N, and llvm::ISD::SUB.

isAddSubZExt()

bool isAddSubZExt ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 9307 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::SDNode::hasOneUse(), isZeroExtended(), N, and llvm::ISD::SUB.

isCMN()

bool isCMN ( SDValue Op, ISD::CondCode CC, SelectionDAG & DAG )

static

Definition at line 4573 of file ARMISelLowering.cpp.

References CC, llvm::SelectionDAG::isKnownNeverZero(), llvm::isNullConstant(), isSafeSignedCMN(), and llvm::ISD::SUB.

IsCMPZCSINC()

SDValue IsCMPZCSINC ( SDNode * Cmp, ARMCC::CondCodes & CC )

static

Definition at line 14987 of file ARMISelLowering.cpp.

References llvm::ISD::AND, CC, llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ARMCC::getOppositeCondition(), llvm::SDNode::hasOneUse(), llvm::isa(), llvm::isNullConstant(), and llvm::isOneConstant().

Referenced by llvm::ARMTargetLowering::PerformCMOVCombine(), PerformCMPZCombine(), and PerformCSETCombine().

isConditionalZeroOrAllOnes()

bool isConditionalZeroOrAllOnes ( SDNode * N, bool AllOnes, SDValue & CC, bool & Invert, SDValue & OtherOp, SelectionDAG & DAG )

static

Definition at line 12367 of file ARMISelLowering.cpp.

References llvm::AllOnes, CC, llvm::SelectionDAG::getAllOnesConstant(), llvm::SelectionDAG::getConstant(), isZeroOrAllOnes(), N, llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.

Referenced by combineSelectAndUse(), and combineSelectAndUse().

isExtendedBUILD_VECTOR()

bool isExtendedBUILD_VECTOR ( SDNode * N, SelectionDAG & DAG, bool isSigned )

static

isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each element has been zero/sign-extended, depending on the isSigned parameter, from an integer type half its size.

Definition at line 9108 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, C(), llvm::dyn_cast(), llvm::SelectionDAG::getDataLayout(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::ConstantSDNode::getSExtValue(), llvm::SDNode::getValueType(), llvm::DataLayout::isBigEndian(), llvm::isIntN(), isSigned(), llvm::isUIntN(), llvm::ConstantSDNode::isZero(), and N.

isFloatingPointZero()

bool isFloatingPointZero ( SDValue Op )

static

isFloatingPointZero - Return true if this is +0.0.

Definition at line 4534 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::ConstantPoolSDNode::getConstVal(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::isEXTLoad(), llvm::ISD::isNON_EXTLoad(), and llvm::isNullConstant().

Referenced by bitcastf32Toi32(), canChangeToInt(), and expandf64Toi32().

isGTorGE()

bool isGTorGE ( ISD::CondCode CC )

static

Definition at line 5165 of file ARMISelLowering.cpp.

References CC, llvm::ISD::SETGE, and llvm::ISD::SETGT.

Referenced by isLowerSaturate(), and LowerSaturatingConditional().

isHomogeneousAggregate()

bool isHomogeneousAggregate ( Type * Ty, HABaseType & Base, uint64_t & Members )

static

Definition at line 22458 of file ARMISelLowering.cpp.

References llvm::sampleprof::Base, llvm::dyn_cast(), HA_DOUBLE, HA_FLOAT, HA_UNKNOWN, HA_VECT128, HA_VECT64, isHomogeneousAggregate(), and uint64_t.

Referenced by llvm::ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters(), and isHomogeneousAggregate().

isIncompatibleReg()

bool isIncompatibleReg ( const MCPhysReg & PR, MVT VT )

static

Definition at line 20864 of file ARMISelLowering.cpp.

References contains(), and llvm::MVT::is64BitVector().

Referenced by llvm::ARMTargetLowering::getRegForInlineAsmConstraint().

isLegalAddressImmediate()

bool isLegalAddressImmediate ( int64_t V, EVT VT, const ARMSubtarget * Subtarget )

static

isLegalAddressImmediate - Return true if the integer value can be used as the offset of the target addressing mode for load / store of the given type.

Definition at line 19934 of file ARMISelLowering.cpp.

References llvm::EVT::getSimpleVT(), llvm::ARMSubtarget::hasVFP2Base(), isLegalT1AddressImmediate(), isLegalT2AddressImmediate(), llvm::isShiftedUInt(), llvm::EVT::isSimple(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), llvm::isUInt(), and llvm::MVT::SimpleTy.

Referenced by llvm::ARMTargetLowering::isLegalAddressingMode().

isLegalLogicalImmediate()

bool isLegalLogicalImmediate ( unsigned Imm, const ARMSubtarget * Subtarget )

static

Definition at line 20587 of file ARMISelLowering.cpp.

References llvm::ARM_AM::getSOImmVal(), llvm::ARM_AM::getT2SOImmVal(), Imm, and llvm::ARMSubtarget::isThumb2().

Referenced by optimizeLogicalImm().

isLegalMVEShuffleOp()

bool isLegalMVEShuffleOp ( unsigned PFEntry )

static

Definition at line 8086 of file ARMISelLowering.cpp.

References OP_COPY, OP_VDUP0, OP_VDUP1, OP_VDUP2, OP_VDUP3, and OP_VREV.

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

isLegalT1AddressImmediate()

bool isLegalT1AddressImmediate ( int64_t V, EVT VT )

static

Definition at line 19854 of file ARMISelLowering.cpp.

References llvm::EVT::getSimpleVT(), llvm::isUInt(), and llvm::MVT::SimpleTy.

Referenced by isLegalAddressImmediate().

isLegalT2AddressImmediate()

bool isLegalT2AddressImmediate ( int64_t V, EVT VT, const ARMSubtarget * Subtarget )

static

Definition at line 19880 of file ARMISelLowering.cpp.

References llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::ARMSubtarget::hasVFP2Base(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::isShiftedUInt(), llvm::isUInt(), llvm::EVT::isVector(), and llvm::MVT::SimpleTy.

Referenced by isLegalAddressImmediate().

isLowerSaturate()

bool isLowerSaturate ( const SDValue LHS, const SDValue RHS, const SDValue TrueVal, const SDValue FalseVal, const ISD::CondCode CC, const SDValue K )

static

Definition at line 5179 of file ARMISelLowering.cpp.

References CC, isGTorGE(), isLTorLE(), LHS, and RHS.

Referenced by isLowerSaturatingConditional().

isLowerSaturatingConditional()

bool isLowerSaturatingConditional ( const SDValue & Op, SDValue & V, SDValue & SatK )

static

Definition at line 5271 of file ARMISelLowering.cpp.

References llvm::cast(), CC, llvm::isa(), isLowerSaturate(), LHS, and RHS.

isLTorLE()

bool isLTorLE ( ISD::CondCode CC )

static

Definition at line 5169 of file ARMISelLowering.cpp.

References CC, llvm::ISD::SETLE, and llvm::ISD::SETLT.

Referenced by isLowerSaturate(), and LowerSaturatingConditional().

isNEONTwoResultShuffleMask()

unsigned isNEONTwoResultShuffleMask ( ArrayRef< int > ShuffleMask, EVT VT, unsigned & WhichResult, bool & isV_UNDEF )

static

Check if ShuffleMask is a NEON two-result shuffle (VZIP, VUZP, VTRN), and return the corresponding ARMISD opcode if it is, or 0 if it isn't.

Definition at line 7233 of file ARMISelLowering.cpp.

References llvm::isVTRN_v_undef_Mask(), llvm::isVTRNMask(), llvm::isVUZP_v_undef_Mask(), llvm::isVUZPMask(), llvm::isVZIP_v_undef_Mask(), and llvm::isVZIPMask().

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

isPowerOf2Constant()

const APInt * isPowerOf2Constant ( SDValue V )

static

Definition at line 18556 of file ARMISelLowering.cpp.

References C(), llvm::dyn_cast(), and llvm::APInt::isPowerOf2().

Referenced by llvm::ARMTargetLowering::PerformCMOVCombine(), and llvm::ARMTargetLowering::PerformCMOVToBFICombine().

IsQRMVEInstruction()

bool IsQRMVEInstruction ( const SDNode * N, const SDNode * Op )

static

Definition at line 7553 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AVGFLOORS, llvm::ISD::AVGFLOORU, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::MUL, N, llvm::ISD::SADDSAT, llvm::ISD::SSUBSAT, llvm::ISD::SUB, llvm::ISD::UADDSAT, and llvm::ISD::USUBSAT.

isReverseMask()

bool isReverseMask ( ArrayRef< int > M, EVT VT )

static

Returns

true if this is a reverse operation on an vector.

Definition at line 7256 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by llvm::ShuffleVectorInst::isReverse(), llvm::ShuffleVectorInst::isReverseMask(), llvm::ARMTargetLowering::isShuffleMaskLegal(), LowerVECTOR_SHUFFLE(), and LowerVECTOR_SHUFFLE_i1().

isS16()

bool isS16 ( const SDValue & Op, SelectionDAG & DAG )

static

Definition at line 1629 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::ComputeNumSignBits(), isSHL16(), and isSRA16().

Referenced by AddCombineTo64BitSMLAL16(), and PerformORCombineToSMULWBT().

isSafeSignedCMN()

bool isSafeSignedCMN ( SDValue Op, SelectionDAG & DAG )

static

Definition at line 4557 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::computeKnownBits(), llvm::KnownBits::getSignedMinValue(), and llvm::APInt::isMinSignedValue().

isSequentialConcatOfVectorInterleave()

bool isSequentialConcatOfVectorInterleave ( SDNode * N, SmallVectorImpl< SDValue > & Ops )

static

Definition at line 17111 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::CONCAT_VECTORS, I, N, and llvm::ISD::VECTOR_INTERLEAVE.

Referenced by PerformInterleavedStoreCombine().

isSHL16()

bool isSHL16 ( const SDValue & Op )

static

Definition at line 1617 of file ARMISelLowering.cpp.

References llvm::dyn_cast(), and llvm::ISD::SHL.

Referenced by isS16(), and PerformORCombineToSMULWBT().

isSignExtended()

bool isSignExtended ( SDNode * N, SelectionDAG & DAG )

static

isSignExtended - Check if a node is a vector value that is sign-extended or a constant BUILD_VECTOR with sign-extended elements.

Definition at line 9161 of file ARMISelLowering.cpp.

References isExtendedBUILD_VECTOR(), llvm::ISD::isSEXTLoad(), N, and llvm::ISD::SIGN_EXTEND.

IsSingleInstrConstant()

SDValue IsSingleInstrConstant ( SDValue N, SelectionDAG & DAG, const ARMSubtarget * ST, const SDLoc & dl )

static

Definition at line 7439 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::ARM_AM::getSOImmVal(), llvm::isa(), N, and uint64_t.

isSingletonVEXTMask()

bool isSingletonVEXTMask ( ArrayRef< int > M, EVT VT, unsigned & Imm )

static

Definition at line 7160 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements(), and Imm.

Referenced by LowerVECTOR_SHUFFLE().

isSRA16()

bool isSRA16 ( const SDValue & Op )

static

Definition at line 1609 of file ARMISelLowering.cpp.

References llvm::dyn_cast(), and llvm::ISD::SRA.

Referenced by AddCombineTo64BitSMLAL16(), isS16(), and PerformORCombineToSMULWBT().

isSRL16()

bool isSRL16 ( const SDValue & Op )

static

Definition at line 1601 of file ARMISelLowering.cpp.

References llvm::dyn_cast(), and llvm::ISD::SRL.

Referenced by PerformORCombineToSMULWBT().

isTruncMask()

bool isTruncMask ( ArrayRef< int > M, EVT VT, bool Top, bool SingleSource )

static

Definition at line 7270 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements(), and llvm::Upper.

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

isValidBaseUpdate()

bool isValidBaseUpdate ( SDNode * N, SDNode * User )

static

Definition at line 15990 of file ARMISelLowering.cpp.

References llvm::SDNode::hasPredecessorHelper(), MaxSteps, N, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by TryCombineBaseUpdate().

isValidMVECond()

bool isValidMVECond ( unsigned CC, bool IsFloat )

static

Definition at line 14571 of file ARMISelLowering.cpp.

References CC, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ARMCC::LE, llvm::ARMCC::LT, and llvm::ARMCC::NE.

Referenced by CanInvertMVEVCMP(), and PerformVCMPCombine().

isVEXTMask()

bool isVEXTMask ( ArrayRef< int > M, EVT VT, bool & ReverseVEXT, unsigned & Imm )

static

Definition at line 7188 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements(), and Imm.

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

isVMOVModifiedImm()

SDValue isVMOVModifiedImm ( uint64_t SplatBits, uint64_t SplatUndef, unsigned SplatBitSize, SelectionDAG & DAG, const SDLoc & dl, EVT & VT, EVT VectorVT, VMOVModImmType type )

static

isVMOVModifiedImm - Check if the specified splat value corresponds to a valid vector constant for a NEON or MVE instruction with a "modified immediate" operand (e.g., VMOV).

If so, return the encoded value.

Definition at line 6909 of file ARMISelLowering.cpp.

References assert(), llvm::ARM_AM::createVMOVModImm(), llvm::SelectionDAG::getTargetConstant(), Imm, llvm::EVT::is128BitVector(), llvm_unreachable, llvm::MVEVMVNModImm, llvm::OtherModImm, uint64_t, and llvm::VMOVModImm.

Referenced by PerformANDCombine(), and PerformORCombine().

isVMOVNMask()

bool isVMOVNMask ( ArrayRef< int > M, EVT VT, bool Top, bool SingleSource )

static

Definition at line 7292 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements(), N, and llvm::Offset.

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().

isVMOVNTruncMask()

bool isVMOVNTruncMask ( ArrayRef< int > M, EVT ToVT, bool rev )

static

Definition at line 7316 of file ARMISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by llvm::ARMTargetLowering::PerformMVETruncCombine(), and PerformShuffleVMOVNCombine().

isVShiftLImm()

bool isVShiftLImm ( SDValue Op, EVT VT, bool isLong, int64_t & Cnt )

static

isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation.

That value must be in the range: 0 <= Value < ElementBits for a left shift; or 0 <= Value <= ElementBits for a long left shift.

Definition at line 6552 of file ARMISelLowering.cpp.

References assert(), llvm::EVT::getScalarSizeInBits(), getVShiftImm(), and llvm::EVT::isVector().

isVShiftRImm()

bool isVShiftRImm ( SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, int64_t & Cnt )

static

isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation.

For a shift opcode, the value is positive, but for an intrinsic the value count must be negative. The absolute value must be in the range: 1 <= |Value| <= ElementBits for a right shift; or 1 <= |Value| <= ElementBits/2 for a narrow right shift.

Definition at line 6566 of file ARMISelLowering.cpp.

References assert(), llvm::EVT::getScalarSizeInBits(), getVShiftImm(), isIntrinsic(), and llvm::EVT::isVector().

isVTBLMask()

bool isVTBLMask ( ArrayRef< int > M, EVT VT )

static

Definition at line 7224 of file ARMISelLowering.cpp.

Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal().

IsVUZPShuffleNode()

bool IsVUZPShuffleNode ( SDNode * N )

static

Definition at line 12479 of file ARMISelLowering.cpp.

References N.

Referenced by AddCombineToVPADD(), and AddCombineVUZPToVPADDL().

isZeroExtended()

bool isZeroExtended ( SDNode * N, SelectionDAG & DAG )

static

isZeroExtended - Check if a node is a vector value that is zero-extended (or any-extended) or a constant BUILD_VECTOR with zero-extended elements.

Definition at line 9171 of file ARMISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, isExtendedBUILD_VECTOR(), llvm::ISD::isZEXTLoad(), N, and llvm::ISD::ZERO_EXTEND.

isZeroOrAllOnes()

bool isZeroOrAllOnes ( SDValue N, bool AllOnes )

inlinestatic

Definition at line 12351 of file ARMISelLowering.cpp.

References llvm::AllOnes, llvm::isAllOnesConstant(), llvm::isNullConstant(), and N.

Referenced by combineSelectAndUse(), isConditionalZeroOrAllOnes(), and isConditionalZeroOrAllOnes().

isZeroVector()

bool isZeroVector ( SDValue N )

static

Definition at line 9941 of file ARMISelLowering.cpp.

References llvm::ISD::isBuildVectorAllZeros(), llvm::isNullConstant(), and N.

Referenced by findZeroVectorIdx(), LowerMLOAD(), PerformSUBCombine(), and PerformVCMPCombine().

LowerADDSUBO_CARRY()

SDValue LowerADDSUBO_CARRY ( SDValue Op, SelectionDAG & DAG, unsigned Opcode, bool IsSigned )

static

Definition at line 9576 of file ARMISelLowering.cpp.

References carryFlagToValue(), DL, llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), overflowFlagToValue(), and valueToCarryFlag().

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

LowerADDSUBSAT()

SDValue LowerADDSUBSAT ( SDValue Op, SelectionDAG & DAG, const ARMSubtarget * Subtarget )

static

Definition at line 4980 of file ARMISelLowering.cpp.

References llvm::Add, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), llvm::ARMSubtarget::isThumb1Only(), llvm::ISD::SADDSAT, llvm::MVT::SimpleTy, llvm::ISD::SSUBSAT, llvm::ISD::TRUNCATE, llvm::ISD::UADDSAT, and llvm::ISD::USUBSAT.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::ARMTargetLowering::ReplaceNodeResults().

LowerATOMIC_FENCE()

SDValue LowerATOMIC_FENCE ( SDValue Op, SelectionDAG & DAG, const ARMSubtarget * Subtarget )

static

Definition at line 4036 of file ARMISelLowering.cpp.

References assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::INTRINSIC_VOID, llvm::ARM_MB::ISH, llvm::ARM_MB::ISHST, llvm::ARMSubtarget::isMClass(), llvm::Release, llvm::SyncScope::SingleThread, and llvm::ARM_MB::SY.

Referenced by llvm::ARMTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

LowerAtomicLoadStore()

SDValue LowerAtomicLoadStore ( SDValue Op, SelectionDAG & DAG )

static

Definition at line 10121 of file ARMISelLowering.cpp.

References llvm::cast(), and llvm::isStrongerThanMonotonic().

Referenced by llvm::ARMTargetLowering::LowerOperation().

LowerBUILD_VECTOR_i1()

SDValue LowerBUILD_VECTOR_i1 ( SDValue Op, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 7456 of file ARMISelLowering.cpp.

References llvm::all_of(), assert(), llvm::sampleprof::Base, llvm::drop_begin(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ISD::INSERT_VECTOR_ELT, llvm::isa(), and llvm::ISD::SIGN_EXTEND_INREG.

LowerBUILD_VECTORToVIDUP()

SDValue LowerBUILD_VECTORToVIDUP ( SDValue Op, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 7518 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), I, llvm::isa(), and N.

LowerBuildVectorOfFPExt()

SDValue LowerBuildVectorOfFPExt ( SDValue BV, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 7397 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BUILD_VECTOR, Check, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FP_EXTEND, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), and llvm::Offset.

LowerBuildVectorOfFPTrunc()

SDValue LowerBuildVectorOfFPTrunc ( SDValue BV, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 7344 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BUILD_VECTOR, Check, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FP_ROUND, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getUNDEF(), and llvm::SDValue::getValueType().

LowerCONCAT_VECTORS()

SDValue LowerCONCAT_VECTORS ( SDValue Op, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 8917 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BITCAST, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::ISD::INSERT_VECTOR_ELT, llvm::SDValue::isUndef(), and LowerCONCAT_VECTORS_i1().

Referenced by llvm::ARMTargetLowering::LowerOperation(), llvm::X86TargetLowering::LowerOperation(), LowerSDIV(), and LowerUDIV().

LowerCONCAT_VECTORS_i1()

SDValue LowerCONCAT_VECTORS_i1 ( SDValue Op, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 8835 of file ARMISelLowering.cpp.

References assert(), E(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getDoubleNumVectorElementsVT(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::EVT::getVectorNumElements(), getVectorTyFromPredicateVector(), llvm::MVT::getVectorVT(), I, llvm::ISD::INSERT_VECTOR_ELT, llvm::isPowerOf2_32(), llvm::ARMISD::MVETRUNC, llvm::ARMCC::NE, PromoteMVEPredVector(), llvm::SmallVectorImpl< T >::resize(), llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::ISD::UNDEF, and llvm::V1.

Referenced by LowerCONCAT_VECTORS().

LowerCTPOP()

SDValue LowerCTPOP ( SDNode * N, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 6495 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, assert(), llvm::ISD::CTPOP, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::getVectorVT(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::is64BitVector(), and N.

LowerCTTZ()

SDValue LowerCTTZ ( SDNode * N, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 6439 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::BITREVERSE, llvm::ISD::CTLZ, llvm::ISD::CTPOP, llvm::ISD::CTTZ_ZERO_POISON, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::EVT::getVectorElementType(), getZeroVector(), llvm::EVT::isVector(), N, llvm::ISD::SUB, and X.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

LowerEXTRACT_SUBVECTOR()

SDValue LowerEXTRACT_SUBVECTOR ( SDValue Op, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 8942 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SDNode::getAsZExtVal(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::EVT::getVectorNumElements(), getVectorTyFromPredicateVector(), llvm::MVT::getVectorVT(), llvm::ISD::INSERT_VECTOR_ELT, llvm::ARMCC::NE, PromoteMVEPredVector(), llvm::ISD::UNDEF, and llvm::V1.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

LowerEXTRACT_VECTOR_ELT()

SDValue LowerEXTRACT_VECTOR_ELT ( SDValue Op, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 8814 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDValue::getValueType(), llvm::isa(), and LowerEXTRACT_VECTOR_ELT_i1().

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::SparcTargetLowering::LowerOperation().

LowerEXTRACT_VECTOR_ELT_i1()

SDValue LowerEXTRACT_VECTOR_ELT_i1 ( SDValue Op, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 8796 of file ARMISelLowering.cpp.

References assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), getVectorTyFromPredicateVector(), and llvm::ISD::SRL.

Referenced by LowerEXTRACT_VECTOR_ELT().

LowerFP_TO_INT_SAT()

SDValue LowerFP_TO_INT_SAT ( SDValue Op, SelectionDAG & DAG, const ARMSubtarget * Subtarget )

static

Definition at line 5857 of file ARMISelLowering.cpp.

References llvm::cast(), DL, llvm::ISD::FP_TO_SINT_SAT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSignedConstant(), llvm::SelectionDAG::getValueType(), llvm::ISD::SMAX, llvm::ISD::SMIN, and llvm::ISD::UMIN.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::ARMTargetLowering::ReplaceNodeResults().

LowerINSERT_VECTOR_ELT_i1()

SDValue LowerINSERT_VECTOR_ELT_i1 ( SDValue Op, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 8733 of file ARMISelLowering.cpp.

References assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getValueType(), getVectorTyFromPredicateVector(), and llvm::ISD::SIGN_EXTEND_INREG.

LowerInterruptReturn()

SDValue LowerInterruptReturn ( SmallVectorImpl< SDValue > & RetOps, const SDLoc & DL, SelectionDAG & DAG )

static

Definition at line 2923 of file ARMISelLowering.cpp.

References llvm::SmallVectorTemplateCommon< T, typename >::begin(), DL, F, llvm::SelectionDAG::getConstant(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SmallVectorImpl< T >::insert(), and llvm::report_fatal_error().

LowerMLOAD()

SDValue LowerMLOAD ( SDValue Op, SelectionDAG & DAG )

static

Definition at line 9947 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::cast(), llvm::SelectionDAG::getMaskedLoad(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValue(), llvm::SDValue::isUndef(), isZeroVector(), N, and llvm::ISD::VSELECT.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

LowerMUL()

SDValue LowerMUL ( SDValue Op, SelectionDAG & DAG )

static

Definition at line 9318 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BITCAST, DL, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), isAddSubSExt(), isAddSubZExt(), llvm::EVT::isInteger(), isSignExtended(), isZeroExtended(), SkipExtensionForVMULL(), and std::swap().

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

LowerPredicateLoad()

SDValue LowerPredicateLoad ( SDValue Op, SelectionDAG & DAG )

static

Definition at line 9805 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BITREVERSE, llvm::cast(), llvm::ISD::EXTLOAD, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getExtLoad(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::DataLayout::isBigEndian(), llvm::Load, llvm::ISD::NON_EXTLOAD, and llvm::ISD::SRL.

Referenced by llvm::ARMTargetLowering::LowerOperation().

LowerPredicateStore()

SDValue LowerPredicateStore ( SDValue Op, SelectionDAG & DAG )

static

Definition at line 9869 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, assert(), llvm::ISD::BITREVERSE, llvm::ISD::BUILD_VECTOR, llvm::cast(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTruncStore(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::getVectorNumElements(), I, llvm::DataLayout::isBigEndian(), and llvm::ISD::SRL.

LowerPREFETCH()

SDValue LowerPREFETCH ( SDValue Op, SelectionDAG & DAG, const ARMSubtarget * Subtarget )

static

Definition at line 4072 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ARMSubtarget::isThumb1Only(), and llvm::ARMSubtarget::isThumb2().

LowerReverse_VECTOR_SHUFFLE()

SDValue LowerReverse_VECTOR_SHUFFLE ( SDValue Op, SelectionDAG & DAG )

static

Definition at line 8236 of file ARMISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getNode(), llvm::EVT::getVectorNumElements(), and llvm::SelectionDAG::getVectorShuffle().

Referenced by LowerVECTOR_SHUFFLE().

LowerSaturatingConditional()

SDValue LowerSaturatingConditional ( SDValue Op, SelectionDAG & DAG )

static

Definition at line 5205 of file ARMISelLowering.cpp.

References llvm::cast(), llvm::countr_one(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::isa(), isGTorGE(), isLTorLE(), llvm::isPowerOf2_64(), llvm::ISD::SELECT_CC, uint64_t, and llvm::V1.

LowerSDIV()

SDValue LowerSDIV ( SDValue Op, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 9463 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), LowerCONCAT_VECTORS(), LowerSDIV_v4i16(), LowerSDIV_v4i8(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::TRUNCATE.

Referenced by llvm::ARMTargetLowering::LowerOperation().

LowerSDIV_v4i16()

SDValue LowerSDIV_v4i16 ( SDValue N0, SDValue N1, const SDLoc & dl, SelectionDAG & DAG )

static

Definition at line 9424 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, and llvm::ISD::TRUNCATE.

Referenced by LowerSDIV(), and LowerUDIV().

LowerSDIV_v4i8()

SDValue LowerSDIV_v4i8 ( SDValue X, SDValue Y, const SDLoc & dl, SelectionDAG & DAG )

static

Definition at line 9393 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::TRUNCATE, X, and Y.

Referenced by LowerSDIV().

LowerSETCCCARRY()

SDValue LowerSETCCCARRY ( SDValue Op, SelectionDAG & DAG )

static

Definition at line 6881 of file ARMISelLowering.cpp.

References assert(), llvm::cast(), Cond, DL, llvm::get(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), IntCCToARMCC(), LHS, RHS, and valueToCarryFlag().

Referenced by llvm::ARMTargetLowering::LowerOperation().

LowerShift()

SDValue LowerShift ( SDNode * N, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 6581 of file ARMISelLowering.cpp.

References assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), getZeroVector(), llvm::EVT::isVector(), isVShiftLImm(), isVShiftRImm(), N, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, and llvm::ISD::SUB.

Referenced by lowerBuildVectorToBitOp(), llvm::ARMTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().

LowerTruncate()

SDValue LowerTruncate ( SDNode * N, SelectionDAG & DAG, const ARMSubtarget * Subtarget )

static

Definition at line 9012 of file ARMISelLowering.cpp.

References DL, llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::Hi, Lo, LowerTruncatei1(), llvm::ARMISD::MVETRUNC, N, and llvm::SelectionDAG::SplitVectorOperand().

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::ARMTargetLowering::ReplaceNodeResults().

LowerTruncatei1()

SDValue LowerTruncatei1 ( SDNode * N, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 8996 of file ARMISelLowering.cpp.

References llvm::ISD::AND, assert(), DL, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), N, llvm::ISD::SETCC, and llvm::ISD::SETNE.

Referenced by LowerTruncate().

LowerUDIV()

SDValue LowerUDIV ( SDValue Op, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 9499 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::ISD::BITCAST, llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::INTRINSIC_WO_CHAIN, LowerCONCAT_VECTORS(), LowerSDIV_v4i16(), llvm::ISD::SINT_TO_FP, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::ARMTargetLowering::LowerOperation().

LowerVASTART()

SDValue LowerVASTART ( SDValue Op, SelectionDAG & DAG )

static

Definition at line 4099 of file ARMISelLowering.cpp.

References llvm::cast(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetLoweringInfo(), and llvm::ARMFunctionInfo::getVarArgsFrameIndex().

LowerVecReduce()

SDValue LowerVecReduce ( SDValue Op, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 9974 of file ARMISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm::ISD::FMUL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm_unreachable, llvm::ISD::MUL, llvm::ISD::OR, llvm::ISD::VECREDUCE_AND, llvm::ISD::VECREDUCE_FADD, llvm::ISD::VECREDUCE_FMAX, llvm::ISD::VECREDUCE_FMIN, llvm::ISD::VECREDUCE_FMUL, llvm::ISD::VECREDUCE_MUL, llvm::ISD::VECREDUCE_OR, llvm::ISD::VECREDUCE_XOR, and llvm::ISD::XOR.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and LowerVecReduceF().

LowerVecReduceF()

SDValue LowerVecReduceF ( SDValue Op, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 10040 of file ARMISelLowering.cpp.

References LowerVecReduce().

Referenced by llvm::ARMTargetLowering::LowerOperation().

LowerVecReduceMinMax()

SDValue LowerVecReduceMinMax ( SDValue Op, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 10047 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::Hi, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::is128BitVector(), llvm_unreachable, Lo, llvm::ISD::SIGN_EXTEND, llvm::SelectionDAG::SplitVector(), llvm::ISD::VECREDUCE_SMAX, llvm::ISD::VECREDUCE_SMIN, llvm::ISD::VECREDUCE_UMAX, llvm::ISD::VECREDUCE_UMIN, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::ARMTargetLowering::LowerOperation().

LowerVECTOR_SHUFFLE()

SDValue LowerVECTOR_SHUFFLE ( SDValue Op, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 8494 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::all_of(), assert(), llvm::ISD::BITCAST, llvm::ARMISD::BUILD_VECTOR, llvm::ISD::BUILD_VECTOR, llvm::cast(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_VECTOR_ELT, GeneratePerfectShuffle(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getFloatingPointVT(), llvm::MVT::getIntegerVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::Hi, Imm, llvm::isa(), isLegalMVEShuffleOp(), isNEONTwoResultShuffleMask(), isReverseMask(), isSingletonVEXTMask(), llvm::ShuffleVectorSDNode::isSplat(), isTruncMask(), llvm::SDNode::isUndef(), isVEXTMask(), isVMOVNMask(), llvm::isVREVMask(), Lo, LowerReverse_VECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE_i1(), LowerVECTOR_SHUFFLEUsingMovs(), LowerVECTOR_SHUFFLEUsingOneOff(), LowerVECTOR_SHUFFLEv8i8(), llvm::ARMISD::MVETRUNC, llvm::PerfectShuffleTable, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SRL, std::swap(), and llvm::V1.

Referenced by llvm::ARMTargetLowering::LowerOperation().

LowerVECTOR_SHUFFLE_i1()

SDValue LowerVECTOR_SHUFFLE_i1 ( SDValue Op, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 8305 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BITREVERSE, llvm::cast(), llvm::SelectionDAG::getConstant(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorShuffle(), isReverseMask(), llvm::SDValue::isUndef(), llvm::ARMCC::NE, PromoteMVEPredVector(), llvm::ISD::SRL, and llvm::V1.

Referenced by LowerVECTOR_SHUFFLE().

LowerVECTOR_SHUFFLEUsingMovs()

SDValue LowerVECTOR_SHUFFLEUsingMovs ( SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG & DAG )

static

Definition at line 8357 of file ARMISelLowering.cpp.

References assert(), llvm::ARMISD::BUILD_VECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::Length, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by LowerVECTOR_SHUFFLE().

LowerVECTOR_SHUFFLEUsingOneOff()

SDValue LowerVECTOR_SHUFFLEUsingOneOff ( SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG & DAG )

static

Definition at line 8443 of file ARMISelLowering.cpp.

References llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::ISD::INSERT_VECTOR_ELT, and llvm::V1.

Referenced by LowerVECTOR_SHUFFLE().

LowerVECTOR_SHUFFLEv8i8()

SDValue LowerVECTOR_SHUFFLEv8i8 ( SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG & DAG )

static

Definition at line 8216 of file ARMISelLowering.cpp.

References DL, llvm::SelectionDAG::getBuildVector(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSignedConstant(), I, llvm::SDNode::isUndef(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::V1.

Referenced by LowerVECTOR_SHUFFLE().

LowerVectorExtend()

SDValue LowerVectorExtend ( SDNode * N, SelectionDAG & DAG, const ARMSubtarget * Subtarget )

static

Definition at line 9072 of file ARMISelLowering.cpp.

References llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getContext(), llvm::EVT::getHalfNumVectorElementsVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::ARMISD::MVESEXT, llvm::ARMISD::MVEZEXT, N, and llvm::ISD::SIGN_EXTEND.

Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::ARMTargetLowering::ReplaceNodeResults().

LowerVectorFP_TO_INT()

SDValue LowerVectorFP_TO_INT ( SDValue Op, SelectionDAG & DAG )

static

Definition at line 5798 of file ARMISelLowering.cpp.

References llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSubtarget(), llvm_unreachable, llvm::ISD::TRUNCATE, and llvm::SelectionDAG::UnrollVectorOp().

LowerVectorINT_TO_FP()

SDValue LowerVectorINT_TO_FP ( SDValue Op, SelectionDAG & DAG )

static

Definition at line 5894 of file ARMISelLowering.cpp.

References assert(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSubtarget(), llvm::EVT::getVectorElementType(), llvm_unreachable, Opc, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, llvm::SelectionDAG::UnrollVectorOp(), and llvm::ISD::ZERO_EXTEND.

LowerVSETCC()

SDValue LowerVSETCC ( SDValue Op, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 6701 of file ARMISelLowering.cpp.

References llvm::ARMCC::AL, llvm::ISD::AND, assert(), llvm::ISD::BITCAST, llvm::cast(), CC, llvm::EVT::changeVectorElementTypeToInteger(), llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ISD::isBuildVectorAllZeros(), llvm::EVT::isFloatingPoint(), llvm::ARMCC::LE, llvm_unreachable, llvm::ARMCC::LT, llvm::ARMCC::NE, Opc, llvm::ISD::OR, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, Swap, and std::swap().

Referenced by combineSetCC(), and llvm::ARMTargetLowering::LowerOperation().

LowerWRITE_REGISTER()

SDValue LowerWRITE_REGISTER ( SDValue Op, SelectionDAG & DAG )

static

Definition at line 3216 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, assert(), DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::Hi, Lo, llvm::SelectionDAG::SplitScalar(), and llvm::ISD::WRITE_REGISTER.

Referenced by llvm::ARMTargetLowering::LowerOperation().

matchCSET()

SDValue matchCSET ( unsigned & Opcode, bool & InvertCond, SDValue TrueVal, SDValue FalseVal, const ARMSubtarget * Subtarget )

static

Definition at line 5315 of file ARMISelLowering.cpp.

References llvm::dyn_cast(), llvm::ConstantSDNode::getZExtValue(), llvm::HasLowerConstantMaterializationCost(), and std::swap().

Referenced by llvm::ARMTargetLowering::PerformCMOVCombine().

optimizeLogicalImm()

bool optimizeLogicalImm ( SDValue Op, unsigned Imm, const APInt & DemandedBits, const ARMSubtarget * Subtarget, TargetLowering::TargetLoweringOpt & TLO )

static

Refine i32 AND/OR/XOR with a constant RHS using demanded bits: replace the immediate with an equivalent constant that ARM/Thumb can encode as a logical immediate (or that selects better lowering), without changing the computed result on those demanded bits.

Definition at line 20601 of file ARMISelLowering.cpp.

References llvm::ISD::AND, llvm::TargetLowering::TargetLoweringOpt::CombineTo(), llvm::TargetLowering::TargetLoweringOpt::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), Imm, isLegalLogicalImmediate(), and Opc.

OtherSucc()

MachineBasicBlock * OtherSucc ( MachineBasicBlock * MBB, MachineBasicBlock * Succ )

static

Definition at line 11186 of file ARMISelLowering.cpp.

References llvm_unreachable, and MBB.

Referenced by llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), and simplifySwitchOfCmpIntrinsic().

overflowFlagToValue()

SDValue overflowFlagToValue ( SDValue Flags, EVT VT, SelectionDAG & DAG )

static

Definition at line 4928 of file ARMISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), and llvm::ARMCC::VS.

ParseBFI()

SDValue ParseBFI ( SDNode * N, APInt & ToMask, APInt & FromMask )

static

Definition at line 14852 of file ARMISelLowering.cpp.

References assert(), llvm::APInt::getBitWidth(), llvm::SDNode::getConstantOperandAPInt(), llvm::APInt::getLimitedValue(), llvm::APInt::getLowBitsSet(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::isa(), N, llvm::APInt::popcount(), and llvm::ISD::SRL.

Referenced by FindBFIToCombineWith(), and PerformBFICombine().

PerformADDCombine()

SDValue PerformADDCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.

Definition at line 13890 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, N, PerformADDCombineWithOperands(), PerformADDVecReduce(), and PerformSHLSimplify().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformADDCombineWithOperands()

SDValue PerformADDCombineWithOperands ( SDNode * N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

PerformADDCombineWithOperands - Try DAG combinations for an ADD with operands N0 and N1.

This is a helper for PerformADDCombine that is called with the default operands, and if that fails, with commuted operands.

Definition at line 13402 of file ARMISelLowering.cpp.

References AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), combineSelectAndUse(), llvm::SDValue::getNode(), llvm::SDNode::hasOneUse(), and N.

Referenced by PerformADDCombine(), and PerformADDCombine().

PerformAddcSubcCombine()

SDValue PerformAddcSubcCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

Definition at line 12996 of file ARMISelLowering.cpp.

References C(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::ARMSubtarget::isThumb1Only(), LHS, N, and RHS.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformADDECombine()

SDValue PerformADDECombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

PerformADDECombine - Target-specific dag combine transform from ARMISD::ADDC, ARMISD::ADDE, and ISD::MUL_LOHI to MLAL or ARMISD::ADDC, ARMISD::ADDE and ARMISD::UMLAL to ARMISD::UMAAL.

Definition at line 13385 of file ARMISelLowering.cpp.

References AddCombineTo64bitUMAAL(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::ARMSubtarget::isThumb1Only(), N, and PerformAddeSubeCombine().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformAddeSubeCombine()

SDValue PerformAddeSubeCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

Definition at line 13029 of file ARMISelLowering.cpp.

References AddCombineTo64bitMLAL(), C(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ARMSubtarget::isThumb1Only(), N, RHS, and llvm::ISD::SMUL_LOHI.

Referenced by PerformADDECombine(), and llvm::ARMTargetLowering::PerformDAGCombine().

PerformADDVecReduce()

SDValue PerformADDVecReduce ( SDNode * N, SelectionDAG & DAG, const ARMSubtarget * Subtarget )

static

Definition at line 13568 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ADD, llvm::ISD::BUILD_PAIR, E(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), llvm::SelectionDAG::getVTList(), I, N, llvm::SelectionDAG::SplitScalar(), and TryDistrubutionADDVecReduce().

Referenced by PerformADDCombine().

PerformANDCombine()

SDValue PerformANDCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

Definition at line 14335 of file ARMISelLowering.cpp.

References CombineANDShift(), combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::APInt::getZExtValue(), llvm::BuildVectorSDNode::isConstantSplat(), llvm::ARMSubtarget::isThumb1Only(), llvm::TargetLoweringBase::isTypeLegal(), isVMOVModifiedImm(), N, llvm::OtherModImm, and PerformSHLSimplify().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformARMBUILD_VECTORCombine()

SDValue PerformARMBUILD_VECTORCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI )

static

Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.

Definition at line 15475 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), assert(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::ISD::INSERT_VECTOR_ELT, llvm::isa(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), and N.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformBFICombine()

SDValue PerformBFICombine ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 14912 of file ARMISelLowering.cpp.

References llvm::ISD::AND, assert(), llvm::bit_width(), llvm::APInt::countl_zero(), llvm::APInt::countr_zero(), llvm::countr_zero(), llvm::dyn_cast(), FindBFIToCombineWith(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::SDValue::hasOneUse(), N, ParseBFI(), and llvm::ISD::SRL.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformBITCASTCombine()

SDValue PerformBITCASTCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * ST )

static

Definition at line 19057 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::DataLayout::isBigEndian(), N, and PerformExtractEltToVMOVRRD().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformBUILD_VECTORCombine()

SDValue PerformBUILD_VECTORCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

PerformBUILD_VECTORCombine - Target-specific dag combine xforms for ISD::BUILD_VECTOR.

Definition at line 15272 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), hasNormalLoadOperand(), N, and PerformVMOVDRRCombine().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformCMPZCombine()

SDValue PerformCMPZCombine ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 15020 of file ARMISelLowering.cpp.

References C(), Cond, llvm::ARMCC::EQ, IsCMPZCSINC(), and N.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformCSETCombine()

SDValue PerformCSETCombine ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 15033 of file ARMISelLowering.cpp.

References C(), Cond, llvm::ARMCC::EQ, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ARMCC::getOppositeCondition(), IsCMPZCSINC(), N, and llvm::ARMCC::NE.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformExtendCombine()

SDValue PerformExtendCombine ( SDNode * N, SelectionDAG & DAG, const ARMSubtarget * ST )

static

PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.

Definition at line 18302 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::BUILD_VECTOR, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), I, llvm::isa(), llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, N, Opc, PerformSplittingToWideningLoad(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformExtractEltCombine()

SDValue PerformExtractEltCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * ST )

static

Definition at line 15748 of file ARMISelLowering.cpp.

References assert(), llvm::ISD::BITCAST, llvm::ARMISD::BUILD_VECTOR, llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::isa(), llvm::ARMISD::MVETRUNC, N, llvm::Offset, PerformExtractEltToVMOVRRD(), and X.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformExtractEltToVMOVRRD()

SDValue PerformExtractEltToVMOVRRD ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI )

static

Definition at line 15688 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::iterator_range< IteratorT >::end(), llvm::ISD::EXTRACT_VECTOR_ELT, F64, llvm::find_if(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SDNode::hasOneUse(), llvm::isa(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::TargetLoweringBase::isTypeLegal(), N, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, llvm::SDNode::user_begin(), and llvm::SDNode::users().

Referenced by PerformBITCASTCombine(), and PerformExtractEltCombine().

PerformExtractFpToIntStores()

SDValue PerformExtractFpToIntStores ( StoreSDNode * St, SelectionDAG & DAG )

static

Definition at line 16976 of file ARMISelLowering.cpp.

References C(), DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNodeIfExists(), llvm::SDNode::getOpcode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTruncStore(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), and llvm::Store.

Referenced by PerformSTORECombine().

PerformFADDCombine()

SDValue PerformFADDCombine ( SDNode * N, SelectionDAG & DAG, const ARMSubtarget * Subtarget )

static

Definition at line 17424 of file ARMISelLowering.cpp.

References N, PerformFADDVCMLACombine(), and PerformFAddVSelectCombine().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformFADDVCMLACombine()

SDValue PerformFADDVCMLACombine ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 17393 of file ARMISelLowering.cpp.

References A(), B(), DL, llvm::ISD::FADD, llvm::SelectionDAG::getNode(), llvm::ISD::INTRINSIC_WO_CHAIN, LHS, N, Opc, RHS, and llvm::SDNode::setFlags().

Referenced by PerformFADDCombine().

PerformFAddVSelectCombine()

SDValue PerformFAddVSelectCombine ( SDNode * N, SelectionDAG & DAG, const ARMSubtarget * Subtarget )

static

Definition at line 17350 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, DL, llvm::ISD::FADD, llvm::FAdd, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNodeFlags::hasNoSignedZeros(), N, std::swap(), uint64_t, and llvm::ISD::VSELECT.

Referenced by PerformFADDCombine().

PerformFPExtendCombine()

SDValue PerformFPExtendCombine ( SDNode * N, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 18365 of file ARMISelLowering.cpp.

References N, and PerformSplittingToWideningLoad().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformHWLoopCombine()

SDValue PerformHWLoopCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * ST )

static

Definition at line 18696 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, assert(), llvm::ISD::BR, llvm::ISD::BR_CC, llvm::ISD::BRCOND, llvm::cast(), CC, Cond, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::ISD::getSetCCInverse(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getVTList(), Imm, Int, N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SelectionDAG::ReplaceAllUsesWith(), SearchLoopIntrinsic(), llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULT, llvm::Size, and llvm::ISD::TokenFactor.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformInsertEltCombine()

SDValue PerformInsertEltCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI )

static

PerformInsertEltCombine - Target-specific dag combine xforms for ISD::INSERT_VECTOR_ELT.

Definition at line 15659 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, llvm::cast(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::isNormalLoad(), and N.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformInsertSubvectorCombine()

SDValue PerformInsertSubvectorCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI )

static

Definition at line 15853 of file ARMISelLowering.cpp.

References llvm::ISD::CONCAT_VECTORS, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::Hi, llvm::EVT::isFixedLengthVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), Lo, N, and uint64_t.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformInterleavedStoreCombine()

SDValue PerformInterleavedStoreCombine ( StoreSDNode * ST, TargetLowering::DAGCombinerInfo & DCI, SelectionDAG & DAG, const ARMSubtarget * Subtarget )

static

Definition at line 17132 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SDValue::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getVTList(), llvm::SDValue::hasOneUse(), llvm::ISD::INTRINSIC_VOID, llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::ISD::isNormalStore(), isSequentialConcatOfVectorInterleave(), PerformLegalizedInterleavedStoreCombine(), and llvm::SmallVectorTemplateCommon< T, typename >::size().

Referenced by PerformSTORECombine().

PerformLegalizedInterleavedStoreCombine()

SDValue PerformLegalizedInterleavedStoreCombine ( StoreSDNode * ST, TargetLowering::DAGCombinerInfo & DCI, SelectionDAG & DAG, const ARMSubtarget * Subtarget )

static

Definition at line 17012 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::AfterLegalizeTypes, llvm::SelectionDAG::areNonVolatileConsecutiveStores(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), DL, llvm::dyn_cast(), llvm::enumerate(), llvm::MemSDNode::getAlign(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::TargetLowering::DAGCombinerInfo::getDAGCombineLevel(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getStoreSize(), llvm::SelectionDAG::getTargetConstant(), llvm::Use::getUser(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::ISD::INTRINSIC_VOID, llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), llvm::is_contained(), llvm::ISD::isNormalStore(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), llvm::SDNode::op_begin(), llvm::SDNode::op_end(), llvm::Store, llvm::SDNode::uses(), llvm::Align::value(), and llvm::ISD::VECTOR_INTERLEAVE.

Referenced by PerformInterleavedStoreCombine().

PerformLegalizedVECTOR_DEINTERLEAVECombine()

SDValue PerformLegalizedVECTOR_DEINTERLEAVECombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, SelectionDAG & DAG, const ARMSubtarget * Subtarget )

static

Definition at line 15303 of file ARMISelLowering.cpp.

References llvm::AfterLegalizeTypes, llvm::SelectionDAG::areNonVolatileConsecutiveLoads(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), DL, llvm::dyn_cast(), llvm::enumerate(), llvm::MemSDNode::getAlign(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getContext(), llvm::TargetLowering::DAGCombinerInfo::getDAGCombineLevel(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getStoreSize(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValue(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::SDValue::hasOneUse(), I, llvm::ISD::INTRINSIC_W_CHAIN, llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), llvm::Load, llvm::SelectionDAG::makeEquivalentMemoryOrdering(), N, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by PerformVECTOR_DEINTERLEAVECombine().

PerformLOADCombine()

SDValue PerformLOADCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

Definition at line 16736 of file ARMISelLowering.cpp.

References llvm::AfterLegalizeTypes, CombineBaseUpdate(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::TargetLowering::DAGCombinerInfo::getDAGCombineLevel(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::Use::getUser(), llvm::ISD::isNormalLoad(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), N, and llvm::ISD::VECTOR_DEINTERLEAVE.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformLongShiftCombine()

SDValue PerformLongShiftCombine ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 17872 of file ARMISelLowering.cpp.

References C(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), Merge, N, and llvm::SelectionDAG::ReplaceAllUsesWith().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformMinMaxCombine()

SDValue PerformMinMaxCombine ( SDNode * N, SelectionDAG & DAG, const ARMSubtarget * ST )

static

PerformMinMaxCombine - Target-specific DAG combining for creating truncating saturates.

Definition at line 18450 of file ARMISelLowering.cpp.

References llvm::ISD::AND, DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getValueType(), llvm::ISD::isConstantSplatVector(), N, PerformMinMaxToSatCombine(), PerformVQDMULHCombine(), llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SMAX, llvm::ISD::SMIN, std::swap(), and llvm::ISD::UMIN.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformMinMaxToSatCombine()

SDValue PerformMinMaxToSatCombine ( SDValue Op, SelectionDAG & DAG, const ARMSubtarget * Subtarget )

static

Definition at line 18376 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::Center, llvm::SelectionDAG::computeOverflowForSignedAdd(), llvm::APInt::countr_one(), DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandAPInt(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::isa(), llvm::APInt::isOne(), llvm::APInt::isPowerOf2(), llvm::ARMSubtarget::isThumb2(), llvm::APInt::logBase2(), llvm::APInt::lshr(), llvm::SelectionDAG::OFK_Never, llvm::APInt::sgt(), llvm::ISD::SMAX, llvm::ISD::SMIN, and std::swap().

Referenced by PerformMinMaxCombine().

PerformMULCombine()

SDValue PerformMULCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

Definition at line 14137 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, C(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::countr_zero(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::has_single_bit(), llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::ARMSubtarget::isThumb1Only(), llvm::Log2_32(), N, PerformMVEVMULLCombine(), PerformVMULCombine(), llvm::ISD::SHL, llvm::ISD::SUB, and uint64_t.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformMVEVLDCombine()

SDValue PerformMVEVLDCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI )

static

Definition at line 16458 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ADD, llvm::ArrayRef(), llvm::cast(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::User::getOperand(), llvm::SDValue::getResNo(), llvm::EVT::getSizeInBits(), llvm::Use::getUser(), llvm::SelectionDAG::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNode::hasPredecessorHelper(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm_unreachable, MaxSteps, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SDNode::uses(), llvm::ARMISD::VLD2_UPD, and llvm::ARMISD::VLD4_UPD.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformMVEVMULLCombine()

SDValue PerformMVEVMULLCombine ( SDNode * N, SelectionDAG & DAG, const ARMSubtarget * Subtarget )

static

Definition at line 14072 of file ARMISelLowering.cpp.

References llvm::ISD::AND, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::cast(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::isAllOnesConstant(), llvm::ARMSubtarget::isLittle(), llvm::isNullConstant(), N, and llvm::ISD::SIGN_EXTEND_INREG.

Referenced by PerformMULCombine().

performNegCMovCombine()

SDValue performNegCMovCombine ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 13958 of file ARMISelLowering.cpp.

References assert(), DL, getNegationCost(), llvm::SelectionDAG::getNegative(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SDNode::hasOneUse(), llvm::isNullConstant(), N, and llvm::ISD::SUB.

Referenced by PerformSUBCombine().

PerformORCombine()

SDValue PerformORCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

PerformORCombine - Target-specific dag combine xforms for ISD::OR.

Definition at line 14676 of file ARMISelLowering.cpp.

References llvm::ISD::AND, combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::APInt::getBitWidth(), llvm::APInt::getHighBitsSet(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::APInt::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::EVT::is128BitVector(), llvm::BuildVectorSDNode::isConstantSplat(), llvm::isNullConstant(), llvm::ARMSubtarget::isThumb1Only(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), isVMOVModifiedImm(), LHS, llvm::SelectionDAG::MaskedValueIsZero(), N, llvm::Other, llvm::OtherModImm, PerformORCombine_i1(), PerformORCombineToBFI(), PerformORCombineToShiftInsert(), PerformORCombineToSMULWBT(), PerformSHLSimplify(), RHS, and std::swap().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformORCombine_i1()

SDValue PerformORCombine_i1 ( SDNode * N, SelectionDAG & DAG, const ARMSubtarget * Subtarget )

static

Definition at line 14602 of file ARMISelLowering.cpp.

References llvm::ISD::AND, CanInvertMVEVCMP(), DL, llvm::SelectionDAG::getLogicalNOT(), llvm::SelectionDAG::getNode(), and N.

Referenced by PerformORCombine().

PerformORCombineToBFI()

SDValue PerformORCombineToBFI ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

Definition at line 14445 of file ARMISelLowering.cpp.

References llvm::ISD::AND, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::countr_zero(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::dyn_cast(), llvm::ConstantSDNode::getAPIntValue(), llvm::SDNode::getAsZExtVal(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::isa(), llvm::ARM::isBitFieldInvertedMask(), llvm::ARMSubtarget::isThumb1Only(), llvm::SelectionDAG::MaskedValueIsZero(), N, llvm::ISD::SHL, and llvm::ISD::SRL.

Referenced by PerformORCombine().

PerformORCombineToShiftInsert()

SDValue PerformORCombineToShiftInsert ( SelectionDAG & DAG, SDValue AndOp, SDValue ShiftOp, EVT VT, SDLoc dl )

static

Definition at line 14632 of file ARMISelLowering.cpp.

References llvm::ISD::AND, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::APInt::getHighBitsSet(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::isConstOrConstSplat(), Opc, llvm::APInt::trunc(), X, and Y.

Referenced by PerformORCombine().

PerformORCombineToSMULWBT()

SDValue PerformORCombineToSMULWBT ( SDNode * OR, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

Definition at line 14385 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), isS16(), isSHL16(), isSRA16(), isSRL16(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SHL, llvm::ISD::SMUL_LOHI, and llvm::ISD::SRL.

Referenced by PerformORCombine().

PerformPREDICATE_CASTCombine()

SDValue PerformPREDICATE_CASTCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI )

static

Definition at line 15566 of file ARMISelLowering.cpp.

References C(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::isBitwiseNot(), N, llvm::TargetLowering::SimplifyDemandedBits(), X, and llvm::ISD::XOR.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformReduceShuffleCombine()

SDValue PerformReduceShuffleCombine ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 17762 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::dyn_cast(), E(), llvm::SelectionDAG::getNode(), llvm::APInt::isAllOnes(), N, and llvm::APInt::setBit().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformSELECTCombine()

SDValue PerformSELECTCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

Definition at line 13057 of file ARMISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, llvm::cast(), CC, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), LHS, N, RHS, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::ISD::SETUGT, llvm::ISD::SETULT, std::swap(), llvm::ISD::TRUNCATE, llvm::ISD::VECREDUCE_SMAX, llvm::ISD::VECREDUCE_SMIN, llvm::ISD::VECREDUCE_UMAX, and llvm::ISD::VECREDUCE_UMIN.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformShiftCombine()

SDValue PerformShiftCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * ST )

static

PerformShiftCombine - Checks for immediate versions of vector shifts and lowers them.

As with the vector shift intrinsics, this is done during DAG combining instead of DAG legalizing because the build_vectors for 64-bit vector element shift counts are generally not legal, and it is hard to see their values after they get legalized to loads from a constant pool.

Definition at line 18144 of file ARMISelLowering.cpp.

References llvm::ISD::AND, llvm::countl_zero(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::ConstantSDNode::getZExtValue(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::isMask_32(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), isVShiftLImm(), isVShiftRImm(), llvm_unreachable, N, llvm::ISD::SHL, llvm::ISD::SRA, and llvm::ISD::SRL.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformSHLSimplify()

SDValue PerformSHLSimplify ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * ST )

static

Definition at line 13782 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dbgs(), llvm::dump(), llvm::SDValue::dump(), llvm::dyn_cast(), llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::APInt::getHighBitsSet(), llvm::SelectionDAG::getNode(), llvm::APInt::getZExtValue(), Imm, llvm::isa(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), LLVM_DEBUG, llvm::APInt::lshrInPlace(), N, llvm::ISD::OR, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SUB, llvm::APInt::uge(), uint64_t, X, and llvm::ISD::XOR.

Referenced by PerformADDCombine(), PerformANDCombine(), PerformORCombine(), and PerformXORCombine().

PerformShuffleVMOVNCombine()

SDValue PerformShuffleVMOVNCombine ( ShuffleVectorSDNode * N, SelectionDAG & DAG )

static

Definition at line 15894 of file ARMISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), isVMOVNTruncMask(), llvm::ARMISD::MVETRUNC, and N.

Referenced by PerformVECTOR_SHUFFLECombine().

PerformSignExtendInregCombine()

SDValue PerformSignExtendInregCombine ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 15838 of file ARMISelLowering.cpp.

References llvm::cast(), llvm::SelectionDAG::getNode(), and N.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformSplittingMVEEXTToWideningLoad()

SDValue PerformSplittingMVEEXTToWideningLoad ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 19199 of file ARMISelLowering.cpp.

References assert(), C(), DL, llvm::dyn_cast(), llvm::ISD::EXTLOAD, llvm::SelectionDAG::getContext(), llvm::TypeSize::getFixed(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getObjectPtrOffset(), llvm::SelectionDAG::getPOISON(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::EVT::isVector(), llvm::ARMISD::MVESEXT, N, llvm::ISD::NON_EXTLOAD, llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SEXTLOAD, llvm::ISD::TokenFactor, llvm::ISD::UNINDEXED, and llvm::ISD::ZEXTLOAD.

Referenced by llvm::ARMTargetLowering::PerformMVEExtCombine().

PerformSplittingMVETruncToNarrowingStores()

SDValue PerformSplittingMVETruncToNarrowingStores ( StoreSDNode * St, SelectionDAG & DAG )

static

Definition at line 16934 of file ARMISelLowering.cpp.

References C(), DL, llvm::SelectionDAG::getContext(), llvm::TypeSize::getFixed(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SelectionDAG::getObjectPtrOffset(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTruncStore(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::ARMISD::MVETRUNC, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::Store, and llvm::ISD::TokenFactor.

Referenced by PerformSTORECombine().

PerformSplittingToNarrowingStores()

SDValue PerformSplittingToNarrowingStores ( StoreSDNode * St, SelectionDAG & DAG )

static

Definition at line 16841 of file ARMISelLowering.cpp.

References assert(), C(), DL, llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::FP_ROUND, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::TypeSize::getFixed(), llvm::EVT::getIntegerVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getObjectPtrOffset(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTruncStore(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), I, llvm::SDValue::isUndef(), llvm::EVT::isVector(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::Store, and llvm::ISD::TokenFactor.

Referenced by PerformSTORECombine().

PerformSplittingToWideningLoad()

SDValue PerformSplittingToWideningLoad ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 18221 of file ARMISelLowering.cpp.

References assert(), C(), llvm::cast(), llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::TypeSize::getFixed(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getLoad(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getObjectPtrOffset(), llvm::SDValue::getOpcode(), llvm::SelectionDAG::getPOISON(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::isPowerOf2_32(), llvm::EVT::isVector(), llvm::ISD::LOAD, N, llvm::ISD::NON_EXTLOAD, llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SEXTLOAD, llvm::ISD::SIGN_EXTEND, llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::ISD::TokenFactor, llvm::ISD::UNINDEXED, and llvm::ISD::ZEXTLOAD.

Referenced by PerformExtendCombine(), and PerformFPExtendCombine().

PerformSTORECombine()

SDValue PerformSTORECombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

PerformSTORECombine - Target-specific dag combine xforms for ISD::STORE.

Definition at line 17210 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, llvm::cast(), CombineBaseUpdate(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SDNode::getFlags(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDNode::hasOneUse(), isBigEndian(), llvm::DataLayout::isBigEndian(), llvm::ISD::isNormalStore(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), N, PerformExtractFpToIntStores(), PerformInterleavedStoreCombine(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), PerformTruncatingStoreCombine(), and llvm::Store.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformSUBCombine()

SDValue PerformSUBCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.

Definition at line 13985 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, combineSelectAndUse(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::hasOneUse(), isZeroVector(), N, performNegCMovCombine(), PerformSubCSINCCombine(), and llvm::ISD::SUB.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine(), and llvm::LanaiTargetLowering::PerformDAGCombine().

PerformSubCSINCCombine()

SDValue PerformSubCSINCCombine ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 13913 of file ARMISelLowering.cpp.

References llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::isNullConstant(), N, llvm::ISD::SUB, and X.

Referenced by PerformSUBCombine().

PerformTruncatingStoreCombine()

SDValue PerformTruncatingStoreCombine ( StoreSDNode * St, SelectionDAG & DAG )

static

Definition at line 16756 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, assert(), llvm::ISD::BITCAST, DL, E(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), I, llvm::Increment, llvm::MVT::integer_valuetypes(), llvm::DataLayout::isBigEndian(), llvm::isPowerOf2_32(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::ISD::TokenFactor.

Referenced by PerformSTORECombine().

PerformUMLALCombine()

SDValue PerformUMLALCombine ( SDNode * N, SelectionDAG & DAG, const ARMSubtarget * Subtarget )

static

Definition at line 12974 of file ARMISelLowering.cpp.

References llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getVTList(), llvm::isNullConstant(), and N.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVCMPCombine()

SDValue PerformVCMPCombine ( SDNode * N, SelectionDAG & DAG, const ARMSubtarget * Subtarget )

static

Definition at line 15627 of file ARMISelLowering.cpp.

References Cond, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), getSwappedCondition(), llvm::EVT::isFloatingPoint(), isValidMVECond(), isZeroVector(), and N.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVCVTCombine()

SDValue PerformVCVTCombine ( SDNode * N, SelectionDAG & DAG, const ARMSubtarget * Subtarget )

static

PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD) can replace combinations of VMUL and VCVT (floating-point to integer) when the VMUL has a constant operand that is a power of 2.

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vmul.f32 d16, d17, d16 vcvt.s32.f32 d16, d16 becomes: vcvt.s32.f32 d16, d16, #3

Definition at line 17302 of file ARMISelLowering.cpp.

References C(), llvm::cast(), llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::BuildVectorSDNode::getConstantFPSplatPow2ToLog2Int(), llvm::SelectionDAG::getNode(), llvm::MVT::getSizeInBits(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isa(), isSigned(), N, and llvm::ISD::TRUNCATE.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVDUPCombine()

SDValue PerformVDUPCombine ( SDNode * N, SelectionDAG & DAG, const ARMSubtarget * Subtarget )

static

PerformVDUPCombine - Target-specific dag combine xforms for ARMISD::VDUP.

Definition at line 16698 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), and llvm::ARMISD::VLD1DUP.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVDUPLANECombine()

SDValue PerformVDUPLANECombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

PerformVDUPLANECombine - Target-specific dag combine xforms for ARMISD::VDUPLANE.

Definition at line 16655 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, CombineVLDDUP(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ARM_AM::decodeVMOVModImm(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorElementType(), Imm, llvm::TargetLoweringBase::isTypeLegal(), and N.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVECREDUCE_ADDCombine()

SDValue PerformVECREDUCE_ADDCombine ( SDNode * N, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 17500 of file ARMISelLowering.cpp.

References A(), AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ADD, llvm::any_of(), assert(), B(), llvm::EVT::bitsLE(), llvm::ISD::BUILD_PAIR, llvm::EVT::changeVectorElementType(), llvm::SelectionDAG::getContext(), llvm::MVT::getIntegerVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::SDValue::getValueType(), llvm::EVT::getVectorMinNumElements(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), llvm::EVT::is128BitVector(), llvm::ISD::isBuildVectorAllZeros(), llvm::ISD::MUL, Mul, llvm::ARMISD::MVESEXT, llvm::ARMISD::MVEZEXT, N, llvm::ISD::SIGN_EXTEND, llvm::ISD::TRUNCATE, llvm::ISD::VECREDUCE_ADD, llvm::ISD::VSELECT, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVECTOR_DEINTERLEAVECombine()

SDValue PerformVECTOR_DEINTERLEAVECombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

Definition at line 15387 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValue(), llvm::EVT::getVectorMinNumElements(), llvm::SelectionDAG::getVTList(), llvm::SDValue::hasOneUse(), I, llvm::ISD::INTRINSIC_W_CHAIN, llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::ISD::isNormalLoad(), llvm::Load, llvm::SelectionDAG::makeEquivalentMemoryOrdering(), N, PerformLegalizedVECTOR_DEINTERLEAVECombine(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVECTOR_REG_CASTCombine()

SDValue PerformVECTOR_REG_CASTCombine ( SDNode * N, SelectionDAG & DAG, const ARMSubtarget * ST )

static

Definition at line 15599 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), and N.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVECTOR_SHUFFLECombine()

SDValue PerformVECTOR_SHUFFLECombine ( SDNode * N, SelectionDAG & DAG )

static

PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for ISD::VECTOR_SHUFFLE.

Definition at line 15919 of file ARMISelLowering.cpp.

References llvm::cast(), llvm::ISD::CONCAT_VECTORS, llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), N, PerformShuffleVMOVNCombine(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVLDCombine()

SDValue PerformVLDCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI )

static

Definition at line 16450 of file ARMISelLowering.cpp.

References CombineBaseUpdate(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), and N.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVMOVDRRCombine()

SDValue PerformVMOVDRRCombine ( SDNode * N, SelectionDAG & DAG )

static

PerformVMOVDRRCombine - Target-specific dag combine xforms for ARMISD::VMOVDRR.

This is also used for BUILD_VECTORs with 2 operands.

Definition at line 15147 of file ARMISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), and N.

Referenced by PerformBUILD_VECTORCombine(), and llvm::ARMTargetLowering::PerformDAGCombine().

PerformVMOVhrCombine()

SDValue PerformVMOVhrCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI )

static

Definition at line 15163 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ArrayRef(), llvm::ISD::BITCAST, llvm::ISD::CopyFromReg, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::SelectionDAG::getLoad(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::Load, N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), and llvm::TargetLowering::SimplifyDemandedBits().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVMOVNCombine()

SDValue PerformVMOVNCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI )

static

Definition at line 17795 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDNode::getConstantOperandVal(), llvm::APInt::getHighBitsSet(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::APInt::getSplat(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::isUndef(), N, and llvm::TargetLowering::SimplifyDemandedVectorElts().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVMOVrhCombine()

SDValue PerformVMOVrhCombine ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 15225 of file ARMISelLowering.cpp.

References C(), llvm::cast(), llvm::dyn_cast(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getExtLoad(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDValue::hasOneUse(), llvm::isa(), llvm::ISD::isNormalLoad(), llvm::Load, N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), and llvm::ISD::ZEXTLOAD.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVMOVRRDCombine()

SDValue PerformVMOVRRDCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

PerformVMOVRRDCombine - Target-specific dag combine xforms for ARMISD::VMOVRRD.

Definition at line 15055 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::cast(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::commonAlignment(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FrameIndex, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::SDValue::getValueType(), llvm::SDNode::hasOneUse(), llvm::ISD::INSERT_VECTOR_ELT, llvm::isa(), llvm::DataLayout::isBigEndian(), llvm::ARMSubtarget::isLittle(), llvm::ISD::isNormalLoad(), N, llvm::Offset, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), and std::swap().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVMULCombine()

SDValue PerformVMULCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

PerformVMULCombine Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the special multiplier accumulator forwarding.

vmul d3, d0, d2 vmla d3, d1, d2 is faster than vadd d3, d0, d1 vmul d3, d3, d2

Definition at line 14041 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::FADD, llvm::ISD::FSUB, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::MUL, N, llvm::ISD::SUB, and std::swap().

Referenced by PerformMULCombine().

PerformVMulVCTPCombine()

SDValue PerformVMulVCTPCombine ( SDNode * N, SelectionDAG & DAG, const ARMSubtarget * Subtarget )

static

PerformVMulVCTPCombine - VCVT (fixed-point to floating-point, Advanced SIMD) can replace combinations of VCVT (integer to floating-point) and VMUL when the VMUL has a constant operand that is a power of 2.

Example (assume d17 = <float 0.125, float 0.125>): vcvt.f32.s32 d16, d16 vmul.f32 d16, d16, d17 becomes: vcvt.f32.s32 d16, d16, #3

Definition at line 17442 of file ARMISelLowering.cpp.

References C(), llvm::APFloat::convertToInteger(), DL, llvm::SelectionDAG::getConstant(), llvm::APFloat::getExactInverse(), llvm::SelectionDAG::getNode(), llvm::MVT::getSizeInBits(), llvm::ConstantFPSDNode::getValueAPF(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isa(), llvm::isConstOrConstSplatFP(), isSigned(), N, llvm::APFloatBase::opOK, llvm::APFloatBase::rmTowardZero, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVQDMULHCombine() [1/2]

SDValue PerformVQDMULHCombine ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 13168 of file ARMISelLowering.cpp.

References llvm::ISD::ANY_EXTEND, assert(), llvm::cast(), llvm::ISD::CONCAT_VECTORS, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::MVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::ConstantSDNode::getSExtValue(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), I, llvm::isConstOrConstSplat(), llvm::EVT::isPow2VectorType(), llvm::EVT::isVector(), llvm::ISD::MUL, Mul, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SETCC, llvm::ISD::SETLT, llvm::ISD::SIGN_EXTEND, llvm::ISD::SMIN, llvm::ISD::SRA, llvm::ISD::TRUNCATE, and llvm::ISD::VSELECT.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine(), PerformMinMaxCombine(), and PerformVSELECTCombine().

PerformVQDMULHCombine() [2/2]

SDValue PerformVQDMULHCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI )

static

Definition at line 17851 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVectorShuffle(), LHS, N, and RHS.

PerformVQMOVNCombine()

SDValue PerformVQMOVNCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI )

static

Definition at line 17835 of file ARMISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::APInt::getHighBitsSet(), llvm::APInt::getLowBitsSet(), llvm::APInt::getSplat(), llvm::SelectionDAG::getTargetLoweringInfo(), N, and llvm::TargetLowering::SimplifyDemandedVectorElts().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVSELECTCombine()

SDValue PerformVSELECTCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

Definition at line 13276 of file ARMISelLowering.cpp.

References C(), Cond, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getNode(), llvm::isa(), llvm::isConstOrConstSplat(), LHS, N, PerformVQDMULHCombine(), RHS, llvm::ISD::VSELECT, and llvm::ISD::XOR.

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformVSetCCToVCTPCombine()

SDValue PerformVSetCCToVCTPCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

Definition at line 13327 of file ARMISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::cast(), CC, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSplatValue(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getZExtOrTrunc(), I, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isa(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), N, Opc, llvm::ISD::SETUGT, llvm::ISD::SETULT, and std::swap().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PerformXORCombine()

SDValue PerformXORCombine ( SDNode * N, TargetLowering::DAGCombinerInfo & DCI, const ARMSubtarget * Subtarget )

static

Definition at line 14807 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, CanInvertMVEVCMP(), CC, combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ARMCC::getOppositeCondition(), llvm::ARMSubtarget::getTargetLowering(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), getVCMPCondCode(), llvm::TargetLowering::isConstTrueVal(), llvm::ARMSubtarget::isThumb1Only(), llvm::TargetLoweringBase::isTypeLegal(), N, and PerformSHLSimplify().

Referenced by llvm::ARMTargetLowering::PerformDAGCombine().

PromoteMVEPredVector()

SDValue PromoteMVEPredVector ( SDLoc dl, SDValue Pred, EVT VT, SelectionDAG & DAG )

static

Definition at line 8270 of file ARMISelLowering.cpp.

References llvm::AllOnes, llvm::ISD::BITCAST, llvm::ARM_AM::createVMOVModImm(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), getVectorTyFromPredicateVector(), and llvm::ISD::VSELECT.

Referenced by LowerCONCAT_VECTORS_i1(), LowerEXTRACT_SUBVECTOR(), and LowerVECTOR_SHUFFLE_i1().

promoteToConstantPool()

SDValue promoteToConstantPool ( const ARMTargetLowering * TLI, const GlobalValue * GV, SelectionDAG & DAG, EVT PtrVT, const SDLoc & dl )

static

Definition at line 3576 of file ARMISelLowering.cpp.

References allUsersAreInFunction(), llvm::StringRef::bytes_begin(), llvm::StringRef::bytes_end(), ConstpoolPromotionMaxSize, ConstpoolPromotionMaxTotal, llvm::ARMConstantPoolConstant::Create(), llvm::dyn_cast(), EnableConstpoolPromotion, llvm::TargetOptions::EnableFastISel, F, llvm::ConstantDataArray::get(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::MachineFunction::getFunction(), llvm::ARMFunctionInfo::getGlobalsPromotedToConstantPool(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::DataLayout::getPreferredAlign(), llvm::ARMFunctionInfo::getPromotedConstpoolIncrease(), llvm::ARMTargetLowering::getSubtarget(), llvm::MachineFunction::getTarget(), llvm::SelectionDAG::getTargetConstantPool(), llvm::DataLayout::getTypeAllocSize(), llvm::TargetLowering::isPositionIndependent(), llvm::ARMSubtarget::isROPI(), llvm::ARMFunctionInfo::markGlobalAsPromotedToConstantPool(), llvm::TargetMachine::Options, llvm::ARMFunctionInfo::setPromotedConstpoolIncrease(), llvm::Size, and llvm::StringRef::size().

ReplaceCMP_SWAP_64Results()

void ReplaceCMP_SWAP_64Results ( SDNode * N, SmallVectorImpl< SDValue > & Results, SelectionDAG & DAG )

static

Definition at line 10175 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, assert(), llvm::ISD::BUILD_PAIR, llvm::cast(), createGPRPairNode2xi32(), createGPRPairNodei64(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVTList(), llvm::Hi, isBigEndian(), llvm::DataLayout::isBigEndian(), Lo, N, Results, and llvm::SelectionDAG::setNodeMemRefs().

Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().

ReplaceLongIntrinsic()

void ReplaceLongIntrinsic ( SDNode * N, SmallVectorImpl< SDValue > & Results, SelectionDAG & DAG )

static

Definition at line 10552 of file ARMISelLowering.cpp.

References llvm::ISD::BUILD_PAIR, llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::Hi, Lo, N, Opc, Results, and llvm::SelectionDAG::SplitScalar().

Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().

ReplaceREADCYCLECOUNTER()

void ReplaceREADCYCLECOUNTER ( SDNode * N, SmallVectorImpl< SDValue > & Results, SelectionDAG & DAG, const ARMSubtarget * Subtarget )

static

Definition at line 10131 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::BUILD_PAIR, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::ISD::INTRINSIC_W_CHAIN, N, and Results.

Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().

SearchLoopIntrinsic()

SDValue SearchLoopIntrinsic ( SDValue N, ISD::CondCode & CC, int & Imm, bool & Negate )

static

Definition at line 18659 of file ARMISelLowering.cpp.

References llvm::cast(), CC, llvm::dyn_cast(), Imm, llvm::ISD::INTRINSIC_W_CHAIN, llvm::isa(), N, SearchLoopIntrinsic(), llvm::ISD::SETCC, and llvm::ISD::XOR.

Referenced by PerformHWLoopCombine(), and SearchLoopIntrinsic().

SkipExtensionForVMULL()

SDValue SkipExtensionForVMULL ( SDNode * N, SelectionDAG & DAG )

static

SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND, ANY_EXTEND, extending load, or BUILD_VECTOR with extended elements, return the unextended value.

The unextended vector should be 64 bits so that it can be used as an operand to a VMULL instruction. If the original vector size before extension is less than 64 bits we add a an extension to resize the vector to 64 bits.

Definition at line 9246 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, AddRequiredExtensionForVMULL(), llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::dyn_cast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::DataLayout::isBigEndian(), llvm::ISD::isSEXTLoad(), llvm::ISD::isZEXTLoad(), N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SIGN_EXTEND, SkipLoadExtensionForVMULL(), llvm::ISD::ZERO_EXTEND, and llvm::APInt::zextOrTrunc().

Referenced by LowerMUL().

SkipLoadExtensionForVMULL()

SDValue SkipLoadExtensionForVMULL ( LoadSDNode * LD, SelectionDAG & DAG )

static

SkipLoadExtensionForVMULL - return a load of the original vector size that does not do any sign/zero extension.

If the original vector is less than 64 bits, an appropriate extension will be added after the load to reach a total size of 64 bits. We have to add the extension separately because ARM does not have a sign/zero extending load for vectors.

Definition at line 9222 of file ARMISelLowering.cpp.

References getExtensionTo64Bits(), llvm::SelectionDAG::getExtLoad(), and llvm::SelectionDAG::getLoad().

Referenced by SkipExtensionForVMULL().

STATISTIC() [1/5]

STATISTIC	(	NumConstpoolPromoted	,
		"Number of constants with their storage promoted into constant pools"	)

STATISTIC() [2/5]

STATISTIC	(	NumLoopByVals	,
		"Number of loops generated for byval arguments"	)

STATISTIC() [3/5]

STATISTIC	(	NumMovwMovt	,
		"Number of GAs materialized with movw + movt"	)

STATISTIC() [4/5]

STATISTIC	(	NumOptimizedImms	,
		"Number of times immediates were optimized"	)

STATISTIC() [5/5]

STATISTIC	(	NumTailCalls	,
		"Number of tail calls"	)

TryCombineBaseUpdate()

bool TryCombineBaseUpdate ( struct BaseUpdateTarget & Target, struct BaseUpdateUser & User, bool SimpleConstIncOnly, TargetLowering::DAGCombinerInfo & DCI )

static

Definition at line 16006 of file ARMISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ArrayRef(), assert(), llvm::ISD::BITCAST, llvm::cast(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::MemSDNode::getAlign(), llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::isa(), isValidBaseUpdate(), llvm_unreachable, llvm::ISD::LOAD, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::STORE, llvm::ARMISD::VLD1_UPD, llvm::ARMISD::VLD1DUP, llvm::ARMISD::VLD1DUP_UPD, llvm::ARMISD::VLD1x2_UPD, llvm::ARMISD::VLD1x3_UPD, llvm::ARMISD::VLD1x4_UPD, llvm::ARMISD::VLD2_UPD, llvm::ARMISD::VLD2DUP, llvm::ARMISD::VLD2DUP_UPD, llvm::ARMISD::VLD2LN_UPD, llvm::ARMISD::VLD3_UPD, llvm::ARMISD::VLD3DUP, llvm::ARMISD::VLD3DUP_UPD, llvm::ARMISD::VLD3LN_UPD, llvm::ARMISD::VLD4_UPD, llvm::ARMISD::VLD4DUP, llvm::ARMISD::VLD4DUP_UPD, llvm::ARMISD::VLD4LN_UPD, llvm::ARMISD::VST1_UPD, llvm::ARMISD::VST1x2_UPD, llvm::ARMISD::VST1x3_UPD, llvm::ARMISD::VST1x4_UPD, llvm::ARMISD::VST2LN_UPD, llvm::ARMISD::VST3_UPD, llvm::ARMISD::VST3LN_UPD, and llvm::ARMISD::VST4LN_UPD.

Referenced by CombineBaseUpdate().

TryDistrubutionADDVecReduce()

SDValue TryDistrubutionADDVecReduce ( SDNode * N, SelectionDAG & DAG )

static

Definition at line 13423 of file ARMISelLowering.cpp.

References llvm::ISD::ADD, llvm::dyn_cast(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::hasOneUse(), llvm::isa(), llvm::LSBaseSDNode::isIndexed(), llvm::MemSDNode::isSimple(), llvm::BaseIndexOffset::match(), llvm::ISD::MUL, N, llvm::ISD::VECREDUCE_ADD, and X.

Referenced by PerformADDVecReduce().

valueToCarryFlag()

SDValue valueToCarryFlag ( SDValue Value, SelectionDAG & DAG, bool Invert )

static

Definition at line 4895 of file ARMISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), and llvm::ISD::SUB.

WinDBZCheckDenominator()

SDValue WinDBZCheckDenominator ( SelectionDAG & DAG, SDNode * N, SDValue InChain )

static

Definition at line 9687 of file ARMISelLowering.cpp.

References DL, llvm::SelectionDAG::getNode(), llvm::Hi, Lo, N, llvm::ISD::OR, and llvm::SelectionDAG::SplitScalar().

Variable Documentation

ARMInterworking

cl::opt< bool > ARMInterworking("arm-interworking", cl::Hidden, cl::desc("Enable / disable ARM interworking (for debugging only)"), cl::init(true)) ( "arm-interworking" , cl::Hidden , cl::desc("Enable / disable ARM interworking (for debugging only)") , cl::init(true)  )

static

ArmMaxBaseUpdatesToCheck

cl::opt< unsigned > ArmMaxBaseUpdatesToCheck("arm-max-base-updates-to-check", cl::Hidden, cl::desc("Maximum number of base-updates to check generating postindex."), cl::init(64))	(	"arm-max-base-updates-to-check"	,
		cl::Hidden	,
		cl::desc("Maximum number of base-updates to check generating postindex.")	,
		cl::init(64)	)

Referenced by CombineBaseUpdate().

ConstpoolPromotionMaxSize

cl::opt< unsigned > ConstpoolPromotionMaxSize("arm-promote-constant-max-size", cl::Hidden, cl::desc("Maximum size of constant to promote into a constant pool"), cl::init(64)) ( "arm-promote-constant-max-size" , cl::Hidden , cl::desc("Maximum size of constant to promote into a constant pool") , cl::init(64)  )

static

Referenced by promoteToConstantPool().

ConstpoolPromotionMaxTotal

cl::opt< unsigned > ConstpoolPromotionMaxTotal("arm-promote-constant-max-total", cl::Hidden, cl::desc("Maximum size of ALL constants to promote into a constant pool"), cl::init(128)) ( "arm-promote-constant-max-total" , cl::Hidden , cl::desc("Maximum size of ALL constants to promote into a constant pool") , cl::init(128)  )

static

Referenced by promoteToConstantPool().

EnableConstpoolPromotion

cl::opt< bool > EnableConstpoolPromotion("arm-promote-constant", cl::Hidden, cl::desc("Enable / disable promotion of unnamed_addr constants into " "constant pools"), cl::init(false)) ( "arm-promote-constant" , cl::Hidden , cl::desc("Enable / disable promotion of unnamed_addr constants into " "constant pools") , cl::init(false)  )

static

Referenced by promoteToConstantPool().

FlagsVT

MVT FlagsVT = MVT::i32

constexpr

Value type used for "flags" operands / results (either CPSR or FPSCR_NZCV).

Definition at line 156 of file ARMISelLowering.cpp.

GPRArgRegs

const MCPhysReg GPRArgRegs[]

static

Initial value:

= {
  ARM::R0, ARM::R1, ARM::R2, ARM::R3
}

Definition at line 159 of file ARMISelLowering.cpp.

MVEMaxSupportedInterleaveFactor

cl::opt< unsigned > MVEMaxSupportedInterleaveFactor("mve-max-interleave-factor", cl::Hidden, cl::desc("Maximum interleave factor for MVE VLDn to generate."), cl::init(2))	(	"mve-max-interleave-factor"	,
		cl::Hidden	,
		cl::desc("Maximum interleave factor for MVE VLDn to generate.")	,
		cl::init(2)	)

Referenced by canTailPredicateLoop(), and llvm::ARMTargetLowering::getMaxSupportedInterleaveFactor().