ScheduleDAGInstrs.cpp File Reference

#include "llvm/CodeGen/ScheduleDAGInstrs.h"
#include "llvm/ADT/IntEqClasses.h"
#include "llvm/ADT/MapVector.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/SparseSet.h"
#include "llvm/ADT/iterator_range.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBundle.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/CodeGen/RegisterPressure.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/ScheduleDFS.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/Config/llvm-config.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/Value.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cassert>
#include <iterator>
#include <list>
#include <utility>
#include <vector>

Go to the source code of this file.

Classes
class	llvm::ScheduleDAGDependencyBuilder
class	llvm::SchedDFSImpl
	Internal state used to compute SchedDFSResult. More...

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.

Macros
#define	DEBUG_TYPE   "machine-scheduler"

Functions
static bool	getUnderlyingObjectsForInstr (const MachineInstr *MI, const MachineFrameInfo &MFI, UnderlyingObjectsVector &Objects, const DataLayout &DL)
	If this machine instruction has memory reference information, collect the list of underlying objects in Objects.
static void	toggleKills (const MachineRegisterInfo &MRI, LiveRegUnits &LiveRegs, MachineInstr &MI, bool addToLiveRegs)
static bool	hasDataSucc (const SUnit *SU)

Variables
static cl::opt< bool >	EnableAASchedMI ("enable-aa-sched-mi", cl::Hidden, cl::desc("Enable use of AA during MI DAG construction"))
static cl::opt< bool >	UseTBAA ("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
static cl::opt< bool >	EnableSchedModel ("schedmodel", cl::Hidden, cl::init(true), cl::desc("Use TargetSchedModel for latency lookup"))
static cl::opt< bool >	EnableSchedItins ("scheditins", cl::Hidden, cl::init(true), cl::desc("Use InstrItineraryData for latency lookup"))
static cl::opt< unsigned >	HugeRegion ("dag-maps-huge-region", cl::Hidden, cl::init(500), cl::desc("The limit to use while constructing the DAG " "prior to scheduling, at which point a trade-off " "is made to avoid excessive compile time."))
static cl::opt< bool >	EnableStoreSequencing ("enable-unanalyzable-store-sequencing", cl::Hidden, cl::init(false), cl::desc("Enable the store-sequencing DAG construction algorithm. This can " "eliminate a large number of redundant control dependencies and " "spurious alias analysis queries at the cost of some unnecessary " "dependencies."))
static cl::opt< bool >	SchedPrintCycles ("sched-print-cycles", cl::Hidden, cl::init(false), cl::desc("Report top/bottom cycles when dumping SUnit instances"))

Macro Definition Documentation

DEBUG_TYPE

#define DEBUG_TYPE   "machine-scheduler"

Definition at line 64 of file ScheduleDAGInstrs.cpp.

Function Documentation

getUnderlyingObjectsForInstr()

bool getUnderlyingObjectsForInstr ( const MachineInstr * MI, const MachineFrameInfo & MFI, UnderlyingObjectsVector & Objects, const DataLayout & DL )

static

If this machine instruction has memory reference information, collect the list of underlying objects in Objects.

If any of these objects are unknown or may alias anything, return false. Atomic and volatile memory operands are skipped.

Definition at line 121 of file ScheduleDAGInstrs.cpp.

References assert(), DL, llvm::getUnderlyingObjectsForCodeGen(), llvm::MachineFrameInfo::hasTailCall(), llvm::isIdentifiedObject(), MI, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by llvm::ScheduleDAGDependencyBuilder::buildDeps().

hasDataSucc()

bool hasDataSucc ( const SUnit * SU )

static

Definition at line 1611 of file ScheduleDAGInstrs.cpp.

References llvm::SDep::Data, llvm::SDep::getKind(), llvm::SDep::getSUnit(), llvm::SUnit::isBoundaryNode(), and llvm::SUnit::Succs.

Referenced by llvm::SchedDFSResult::compute().

toggleKills()

void toggleKills ( const MachineRegisterInfo & MRI, LiveRegUnits & LiveRegs, MachineInstr & MI, bool addToLiveRegs )

static

Definition at line 1259 of file ScheduleDAGInstrs.cpp.

References llvm::MachineRegisterInfo::isReserved(), MI, and Reg.

Referenced by llvm::ScheduleDAGInstrs::fixupKills().

Variable Documentation

EnableAASchedMI

cl::opt< bool > EnableAASchedMI("enable-aa-sched-mi", cl::Hidden, cl::desc("Enable use of AA during MI DAG construction")) ( "enable-aa-sched-mi" , cl::Hidden , cl::desc("Enable use of AA during MI DAG construction")  )

static

Referenced by llvm::ScheduleDAGInstrs::buildSchedGraph().

EnableSchedItins

cl::opt< bool > EnableSchedItins("scheditins", cl::Hidden, cl::init(true), cl::desc("Use InstrItineraryData for latency lookup")) ( "scheditins" , cl::Hidden , cl::init(true) , cl::desc("Use InstrItineraryData for latency lookup")  )

static

Referenced by llvm::ScheduleDAGInstrs::ScheduleDAGInstrs().

EnableSchedModel

cl::opt< bool > EnableSchedModel("schedmodel", cl::Hidden, cl::init(true), cl::desc("Use TargetSchedModel for latency lookup")) ( "schedmodel" , cl::Hidden , cl::init(true) , cl::desc("Use TargetSchedModel for latency lookup")  )

static

Referenced by llvm::ScheduleDAGInstrs::ScheduleDAGInstrs().

EnableStoreSequencing

cl::opt< bool > EnableStoreSequencing("enable-unanalyzable-store-sequencing", cl::Hidden, cl::init(false), cl::desc("Enable the store-sequencing DAG construction algorithm. This can " "eliminate a large number of redundant control dependencies and " "spurious alias analysis queries at the cost of some unnecessary " "dependencies.")) ( "enable-unanalyzable-store-sequencing" , cl::Hidden , cl::init(false) , cl::desc("Enable the store-sequencing DAG construction algorithm. This can " "eliminate a large number of redundant control dependencies and " "spurious alias analysis queries at the cost of some unnecessary " "dependencies.")  )

static

HugeRegion

cl::opt< unsigned > HugeRegion("dag-maps-huge-region", cl::Hidden, cl::init(500), cl::desc("The limit to use while constructing the DAG " "prior to scheduling, at which point a trade-off " "is made to avoid excessive compile time.")) ( "dag-maps-huge-region" , cl::Hidden , cl::init(500) , cl::desc("The limit to use while constructing the DAG " "prior to scheduling, at which point a trade-off " "is made to avoid excessive compile time.")  )

static

Referenced by llvm::ScheduleDAGDependencyBuilder::buildDeps().

SchedPrintCycles

cl::opt< bool > SchedPrintCycles("sched-print-cycles", cl::Hidden, cl::init(false), cl::desc("Report top/bottom cycles when dumping SUnit instances")) ( "sched-print-cycles" , cl::Hidden , cl::init(false) , cl::desc("Report top/bottom cycles when dumping SUnit instances")  )

static

Referenced by llvm::ScheduleDAGInstrs::dumpNode().

UseTBAA

cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction")) ( "use-tbaa-in-sched-mi" , cl::Hidden , cl::init(true) , cl::desc("Enable use of TBAA during MI DAG construction")  )

static

Referenced by llvm::VLIWPacketizerList::alias(), llvm::MachineInstr::mayAlias(), llvm::MachineInstr::mayAlias(), and MemOperandsHaveAlias().