This file implements the WebAssemblyTargetLowering class. More...

#include "WebAssemblyISelLowering.h"
#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
#include "Utils/WebAssemblyTypeUtilities.h"
#include "WebAssemblyMachineFunctionInfo.h"
#include "WebAssemblySubtarget.h"
#include "WebAssemblyTargetMachine.h"
#include "WebAssemblyUtilities.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SDPatternMatch.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/DiagnosticPrinter.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IntrinsicsWebAssembly.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetOptions.h"

Classes
struct	MaskReduceInfo

Macros
#define	DEBUG_TYPE "wasm-lower"

Functions
static MachineBasicBlock *	LowerFPToInt (MachineInstr &MI, DebugLoc DL, MachineBasicBlock *BB, const TargetInstrInfo &TII, bool IsUnsigned, bool Int64, bool Float64, unsigned LoweredOpcode)
static MachineBasicBlock *	LowerMemcpy (MachineInstr &MI, DebugLoc DL, MachineBasicBlock *BB, const TargetInstrInfo &TII, bool Int64)
static MachineBasicBlock *	LowerMemset (MachineInstr &MI, DebugLoc DL, MachineBasicBlock *BB, const TargetInstrInfo &TII, bool Int64)
static MachineBasicBlock *	LowerCallResults (MachineInstr &CallResults, DebugLoc DL, MachineBasicBlock BB, const WebAssemblySubtarget Subtarget, const TargetInstrInfo &TII)
static void	fail (const SDLoc &DL, SelectionDAG &DAG, const char *Msg)
static bool	callingConvSupported (CallingConv::ID CallConv)
static bool	IsWebAssemblyGlobal (SDValue Op)
static std::optional< unsigned >	IsWebAssemblyLocal (SDValue Op, SelectionDAG &DAG)
static SDValue	GetExtendHigh (SDValue Op, unsigned UserOpc, EVT VT, SelectionDAG &DAG)
static SDValue	LowerConvertLow (SDValue Op, SelectionDAG &DAG)
static SDValue	unrollVectorShift (SDValue Op, SelectionDAG &DAG)
static bool	HasNoSignedZerosOrNaNs (SDValue Op, SelectionDAG &DAG)
static SDValue	performVECTOR_SHUFFLECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	performVectorExtendToFPCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const WebAssemblySubtarget Subtarget)
	Convert ({u,s}itofp vec) --> ({u,s}itofp ({s,z}ext vec)) so it doesn't get split up into scalar instructions during legalization, and the vector extending instructions are selected in performVectorExtendCombine below.
static SDValue	performVectorNonNegToFPCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	performVectorExtendCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	performVectorTruncZeroCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	extractSubVector (SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, const SDLoc &DL, unsigned VectorWidth)
static SDValue	truncateVectorWithNARROW (EVT DstVT, SDValue In, const SDLoc &DL, SelectionDAG &DAG)
static SDValue	performTruncateCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	performBitcastCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	performBitmaskCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performAnyAllCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	combineSmallMaskReduction (SDNode *N, EVT FromVT, unsigned NumElts, const MaskReduceInfo &Info, SelectionDAG &DAG)
static SDValue	combineWideMaskReduction (SDNode *N, SDValue Mask, EVT MaskVT, unsigned NumElts, const MaskReduceInfo &Info, SelectionDAG &DAG)
static std::optional< MaskReduceInfo >	classifyMaskReduction (SDNode *N)
static SDValue	combineVectorSizedSetCCEquality (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const WebAssemblySubtarget Subtarget)
	Try to convert a i128 comparison to a v16i8 comparison before type legalization splits it up into chunks.
static SDValue	performSETCCCombine (SDNode N, TargetLowering::DAGCombinerInfo &DCI, const WebAssemblySubtarget Subtarget)
static SDValue	TryWideExtMulCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performMulCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
SDValue	DoubleVectorWidth (SDValue In, unsigned RequiredNumElems, SelectionDAG &DAG)
SDValue	performConvertFPCombine (SDNode *N, SelectionDAG &DAG)
static SDValue	performShiftCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
static SDValue	performMinMaxF128Combine (SDNode *N, SelectionDAG &DAG)

Detailed Description

This file implements the WebAssemblyTargetLowering class.

Definition in file WebAssemblyISelLowering.cpp.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE "wasm-lower"

Definition at line 42 of file WebAssemblyISelLowering.cpp.

Function Documentation

◆ callingConvSupported()

bool callingConvSupported ( CallingConv::ID CallConv )

static

Definition at line 1266 of file WebAssemblyISelLowering.cpp.

References llvm::CallingConv::C, llvm::CallingConv::Cold, llvm::CallingConv::CXX_FAST_TLS, llvm::CallingConv::Fast, llvm::CallingConv::PreserveAll, llvm::CallingConv::PreserveMost, llvm::CallingConv::Swift, llvm::CallingConv::SwiftTail, and llvm::CallingConv::WASM_EmscriptenInvoke.

◆ classifyMaskReduction()

std::optional< MaskReduceInfo > classifyMaskReduction ( SDNode * N )

static

Definition at line 3626 of file WebAssemblyISelLowering.cpp.

References llvm::ISD::AND, C(), llvm::cast(), llvm::dyn_cast(), N, llvm::ISD::OR, llvm::ISD::SETEQ, and llvm::ISD::SETNE.

Referenced by performSETCCCombine().

◆ combineSmallMaskReduction()

SDValue combineSmallMaskReduction	(	SDNode *	N,
		EVT	FromVT,
		unsigned	NumElts,
		const MaskReduceInfo &	Info,
		SelectionDAG &	DAG )

static

Definition at line 3554 of file WebAssemblyISelLowering.cpp.

References assert(), llvm::EVT::changeVectorElementType(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::ISD::INTRINSIC_WO_CHAIN, N, and llvm::ISD::XOR.

Referenced by performSETCCCombine().

◆ combineVectorSizedSetCCEquality()

SDValue combineVectorSizedSetCCEquality	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const WebAssemblySubtarget *	Subtarget )

static

Try to convert a i128 comparison to a v16i8 comparison before type legalization splits it up into chunks.

Definition at line 3655 of file WebAssemblyISelLowering.cpp.

References llvm::cast(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSetCC(), llvm::Function::hasFnAttribute(), llvm::WebAssemblySubtarget::hasSIMD128(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isa(), llvm::EVT::isByteSized(), llvm::EVT::isScalarInteger(), llvm::ISD::LOAD, N, llvm::peekThroughBitcasts(), SDValue(), llvm::ISD::SETEQ, llvm::ISD::SETNE, X, and Y.

◆ combineWideMaskReduction()

SDValue combineWideMaskReduction	(	SDNode *	N,
		SDValue	Mask,
		EVT	MaskVT,
		unsigned	NumElts,
		const MaskReduceInfo &	Info,
		SelectionDAG &	DAG )

static

◆ DoubleVectorWidth()

SDValue DoubleVectorWidth	(	SDValue	In,
		unsigned	RequiredNumElems,
		SelectionDAG &	DAG )

Definition at line 3880 of file WebAssemblyISelLowering.cpp.

References Concat, llvm::ISD::CONCAT_VECTORS, DL, DoubleVectorWidth(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getPOISON(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), and llvm::EVT::getVectorVT().

Referenced by DoubleVectorWidth(), and performConvertFPCombine().

◆ extractSubVector()

SDValue extractSubVector	(	SDValue	Vec,
		unsigned	IdxVal,
		SelectionDAG &	DAG,
		const SDLoc &	DL,
		unsigned	VectorWidth )

static

Definition at line 3270 of file WebAssemblyISelLowering.cpp.

References assert(), llvm::ISD::BUILD_VECTOR, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::isPowerOf2_32(), and llvm::SDNode::ops().

Referenced by combineBROADCAST_LOAD(), combineConcatVectorOps(), combineConstantPoolLoads(), combineEXTRACT_SUBVECTOR(), combineIntDivRem(), combineLoad(), combineOr(), combineSCALAR_TO_VECTOR(), combineSelect(), combineTargetShuffle(), combineX86ShuffleChain(), combineX86ShuffleChainWithExtract(), createVariablePermute(), extract128BitVector(), extract256BitVector(), getAVX512Node(), getAVX512TruncNode(), getEXTEND_VECTOR_INREG(), lowerBuildVectorAsBroadcast(), LowerEXTEND_VECTOR_INREG(), lowerShuffleAsBroadcast(), lowerShuffleWithPERMV(), performBitcastCombine(), performConvertFPCombine(), performMulCombine(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), SplitOpsAndApply(), splitVector(), truncateVectorWithNARROW(), and truncateVectorWithPACK().

◆ fail()

void fail	(	const SDLoc &	DL,
		SelectionDAG &	DAG,
		const char *	Msg )

static

Definition at line 1259 of file WebAssemblyISelLowering.cpp.

References llvm::LLVMContext::diagnose(), DL, llvm::SelectionDAG::getContext(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), and Msg.

◆ GetExtendHigh()

SDValue GetExtendHigh	(	SDValue	Op,
		unsigned	UserOpc,
		EVT	VT,
		SelectionDAG &	DAG )

static

Definition at line 2339 of file WebAssemblyISelLowering.cpp.

References assert(), llvm::ISD::BITCAST, llvm::cast(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), Opc, llvm::peekThroughBitcasts(), SDValue(), and llvm::ISD::VECTOR_SHUFFLE.

Referenced by TryWideExtMulCombine().

◆ HasNoSignedZerosOrNaNs()

bool HasNoSignedZerosOrNaNs	(	SDValue	Op,
		SelectionDAG &	DAG )

static

Definition at line 2958 of file WebAssemblyISelLowering.cpp.

References llvm::SelectionDAG::isKnownNeverLogicalZero(), and llvm::SelectionDAG::isKnownNeverNaN().

◆ IsWebAssemblyGlobal()

bool IsWebAssemblyGlobal ( SDValue Op )

static

Definition at line 1826 of file WebAssemblyISelLowering.cpp.

References llvm::dyn_cast(), llvm::GlobalAddressSDNode::getAddressSpace(), and llvm::WebAssembly::isWasmVarAddressSpace().

◆ IsWebAssemblyLocal()

std::optional< unsigned > IsWebAssemblyLocal	(	SDValue	Op,
		SelectionDAG &	DAG )

static

Definition at line 1833 of file WebAssemblyISelLowering.cpp.

References llvm::dyn_cast(), llvm::FrameIndexSDNode::getIndex(), llvm::WebAssemblyFrameLowering::getLocalForStackObject(), and llvm::SelectionDAG::getMachineFunction().

◆ LowerCallResults()

MachineBasicBlock * LowerCallResults	(	MachineInstr &	CallResults,
		DebugLoc	DL,
		MachineBasicBlock *	BB,
		const WebAssemblySubtarget *	Subtarget,
		const TargetInstrInfo &	TII )

static

Definition at line 788 of file WebAssemblyISelLowering.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addOperand(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addSym(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineInstr::defs(), DL, llvm::MachineInstr::eraseFromParent(), llvm::MachineFunction::getContext(), llvm::MachineInstrBuilder::getInstr(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::WebAssembly::getOrCreateFuncrefCallTableSymbol(), llvm::WebAssembly::getOrCreateFunctionTableSymbol(), llvm::MachineBasicBlock::getParent(), llvm::ilist_node_with_parent< NodeTy, ParentTy, Options >::getPrevNode(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::WebAssemblySubtarget::hasCallIndirectOverlong(), llvm::WebAssemblySubtarget::hasReferenceTypes(), llvm::MachineBasicBlock::insert(), llvm::MachineBasicBlock::insertAfter(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isReg(), Reg, llvm::MachineInstr::removeOperand(), llvm::Table, TII, and llvm::MachineInstr::uses().

◆ LowerConvertLow()

SDValue LowerConvertLow	(	SDValue	Op,
		SelectionDAG &	DAG )

static

Definition at line 2421 of file WebAssemblyISelLowering.cpp.

References DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FP16_TO_FP, llvm::ISD::FP_EXTEND, llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorShuffle(), llvm::isa(), SDValue(), llvm::ISD::SINT_TO_FP, and llvm::ISD::UINT_TO_FP.

◆ LowerFPToInt()

MachineBasicBlock * LowerFPToInt	(	MachineInstr &	MI,
		DebugLoc	DL,
		MachineBasicBlock *	BB,
		const TargetInstrInfo &	TII,
		bool	IsUnsigned,
		bool	Int64,
		bool	Float64,
		unsigned	LoweredOpcode )

static

Definition at line 517 of file WebAssemblyISelLowering.cpp.

References llvm::MachineInstrBuilder::addFPImm(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::cast(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::MachineBasicBlock::end(), F, llvm::MachineBasicBlock::getBasicBlock(), llvm::Function::getContext(), llvm::Type::getDoubleTy(), llvm::Type::getFloatTy(), llvm::MachineFunction::getFunction(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), INT64_MIN, MI, llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

◆ LowerMemcpy()

MachineBasicBlock * LowerMemcpy	(	MachineInstr &	MI,
		DebugLoc	DL,
		MachineBasicBlock *	BB,
		const TargetInstrInfo &	TII,
		bool	Int64 )

static

◆ LowerMemset()

MachineBasicBlock * LowerMemset	(	MachineInstr &	MI,
		DebugLoc	DL,
		MachineBasicBlock *	BB,
		const TargetInstrInfo &	TII,
		bool	Int64 )

static

◆ performAnyAllCombine()

SDValue performAnyAllCombine	(	SDNode *	N,
		SelectionDAG &	DAG )

static

◆ performBitcastCombine()

SDValue performBitcastCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI )

static

Definition at line 3377 of file WebAssemblyISelLowering.cpp.

References assert(), Concat, llvm::ISD::CONCAT_VECTORS, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, extractSubVector(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::ElementCount::getFixed(), llvm::EVT::getIntegerVT(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSetCC(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SelectionDAG::getZExtOrTrunc(), I, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::EVT::isFixedLengthVectorOf(), llvm::EVT::isScalarInteger(), llvm::PatternMatch::m_BitCast(), llvm::SDPatternMatch::m_c_SetCC(), llvm::SDPatternMatch::m_CondCode(), llvm::PatternMatch::m_Value(), N, llvm::ISD::OR, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::ISD::SHL, and llvm::size().

◆ performBitmaskCombine()

SDValue performBitmaskCombine	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 3476 of file WebAssemblyISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getNode(), llvm::ISD::INTRINSIC_WO_CHAIN, LHS, llvm::SDPatternMatch::m_c_SetCC(), llvm::SDPatternMatch::m_SpecificCondCode(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_Zero(), N, llvm::SDPatternMatch::sd_match(), SDValue(), and llvm::ISD::SETLT.

◆ performConvertFPCombine()

SDValue performConvertFPCombine	(	SDNode *	N,
		SelectionDAG &	DAG )

◆ performMinMaxF128Combine()

SDValue performMinMaxF128Combine	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 4008 of file WebAssemblyISelLowering.cpp.

References llvm::TargetLowering::expandFMINIMUM_FMAXIMUM(), llvm::TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(), llvm::ISD::FMAXIMUM, llvm::ISD::FMAXIMUMNUM, llvm::ISD::FMINIMUM, llvm::ISD::FMINIMUMNUM, llvm::SelectionDAG::getTargetLoweringInfo(), N, and SDValue().

◆ performMulCombine()

SDValue performMulCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI )

static

Definition at line 3822 of file WebAssemblyISelLowering.cpp.

References assert(), llvm::ISD::CONCAT_VECTORS, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, extractSubVector(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::isVector(), LHS, llvm::ISD::MUL, N, RHS, SDValue(), and TryWideExtMulCombine().

◆ performSETCCCombine()

SDValue performSETCCCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const WebAssemblySubtarget *	Subtarget )

static

Definition at line 3699 of file WebAssemblyISelLowering.cpp.

References llvm::ISD::BITCAST, classifyMaskReduction(), combineSmallMaskReduction(), combineVectorSizedSetCCEquality(), combineWideMaskReduction(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::EVT::getVectorNumElements(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::EVT::isFixedLengthVectorOf(), llvm::EVT::isScalarInteger(), LHS, N, and SDValue().

◆ performShiftCombine()

SDValue performShiftCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI )

static

◆ performTruncateCombine()

SDValue performTruncateCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI )

static

Definition at line 3350 of file WebAssemblyISelLowering.cpp.

References llvm::ISD::AND, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::is128BitVector(), llvm::EVT::isSimple(), llvm::EVT::isVector(), N, SDValue(), and truncateVectorWithNARROW().

◆ performVECTOR_SHUFFLECombine()

SDValue performVECTOR_SHUFFLECombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI )

static

Definition at line 2989 of file WebAssemblyISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::cast(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorShuffle(), N, and SDValue().

◆ performVectorExtendCombine()

SDValue performVectorExtendCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI )

static

Definition at line 3061 of file WebAssemblyISelLowering.cpp.

References assert(), llvm::ISD::CONCAT_VECTORS, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), N, SDValue(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.

◆ performVectorExtendToFPCombine()

SDValue performVectorExtendToFPCombine	(	SDNode *	N,
		TargetLowering::DAGCombinerInfo &	DCI,
		const WebAssemblySubtarget *	Subtarget )

static

Convert ({u,s}itofp vec) --> ({u,s}itofp ({s,z}ext vec)) so it doesn't get split up into scalar instructions during legalization, and the vector extending instructions are selected in performVectorExtendCombine below.

Definition at line 3017 of file WebAssemblyISelLowering.cpp.

References assert(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getNode(), llvm::WebAssemblySubtarget::hasFP16(), N, SDValue(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, and llvm::ISD::ZERO_EXTEND.