15#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYISELLOWERING_H
16#define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYISELLOWERING_H
22namespace WebAssemblyISD {
26#define HANDLE_NODETYPE(NODE) NODE,
27#define HANDLE_MEM_NODETYPE(NODE)
28#include "WebAssemblyISD.def"
31#undef HANDLE_MEM_NODETYPE
32#define HANDLE_NODETYPE(NODE)
33#define HANDLE_MEM_NODETYPE(NODE) NODE,
34#include "WebAssemblyISD.def"
36#undef HANDLE_MEM_NODETYPE
41class WebAssemblySubtarget;
57 bool shouldScalarizeBinop(
SDValue VecOp)
const override;
64 const char *getTargetNodeName(
unsigned Opcode)
const override;
65 std::pair<unsigned, const TargetRegisterClass *>
68 bool isCheapToSpeculateCttz(
Type *Ty)
const override;
69 bool isCheapToSpeculateCtlz(
Type *Ty)
const override;
73 bool allowsMisalignedMemoryAccesses(
EVT,
unsigned AddrSpace,
Align Alignment,
75 unsigned *
Fast)
const override;
77 bool isVectorLoadExtDesirable(
SDValue ExtVal)
const override;
82 EVT VT)
const override;
85 unsigned Intrinsic)
const override;
88 const APInt &DemandedElts,
90 unsigned Depth)
const override;
93 getPreferredVectorAction(
MVT VT)
const override;
115 shouldSimplifyDemandedVectorElts(
SDValue Op,
148namespace WebAssembly {
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
Analysis containing CSE Info
unsigned const TargetRegisterInfo * TRI
This file describes how to lower LLVM code to machine code.
Class for arbitrary precision integers.
an instruction that atomically reads a memory location, combines it with another value,...
This class represents a function call, abstracting a target machine's calling convention.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
This is an important class for using LLVM in a threaded context.
Representation of each machine instruction.
Flags
Flags values. These may be or'd together.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
StringRef - Represent a constant reference to a string, i.e.
Provides information about what library functions are available for the current target.
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const override
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
MVT getPointerMemTy(const DataLayout &DL, uint32_t AS=0) const override
Return the in-memory pointer type for the given address space, defaults to the pointer type from the ...
@ Fast
Attempts to make calls as fast as possible (e.g.
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
This is an optimization pass for GlobalISel generic memory operations.
This struct is a compact representation of a valid (non-zero power of two) alignment.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg + ScalableOffset*...
This structure contains all information that is necessary for lowering calls.
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...