LLVM 17.0.0git
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1//===--- WebAssemblyOptimizeLiveIntervals.cpp - LiveInterval processing ---===//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
9/// \file
10/// Optimize LiveIntervals for use in a post-RA context.
12/// LiveIntervals normally runs before register allocation when the code is
13/// only recently lowered out of SSA form, so it's uncommon for registers to
14/// have multiple defs, and when they do, the defs are usually closely related.
15/// Later, after coalescing, tail duplication, and other optimizations, it's
16/// more common to see registers with multiple unrelated defs. This pass
17/// updates LiveIntervals to distribute the value numbers across separate
18/// LiveIntervals.
22#include "WebAssembly.h"
28#include "llvm/CodeGen/Passes.h"
29#include "llvm/Support/Debug.h"
31using namespace llvm;
33#define DEBUG_TYPE "wasm-optimize-live-intervals"
35namespace {
36class WebAssemblyOptimizeLiveIntervals final : public MachineFunctionPass {
37 StringRef getPassName() const override {
38 return "WebAssembly Optimize Live Intervals";
39 }
41 void getAnalysisUsage(AnalysisUsage &AU) const override {
42 AU.setPreservesCFG();
50 }
54 MachineFunctionProperties::Property::TracksLiveness);
55 }
57 bool runOnMachineFunction(MachineFunction &MF) override;
60 static char ID; // Pass identification, replacement for typeid
61 WebAssemblyOptimizeLiveIntervals() : MachineFunctionPass(ID) {}
63} // end anonymous namespace
65char WebAssemblyOptimizeLiveIntervals::ID = 0;
66INITIALIZE_PASS(WebAssemblyOptimizeLiveIntervals, DEBUG_TYPE,
67 "Optimize LiveIntervals for WebAssembly", false, false)
70 return new WebAssemblyOptimizeLiveIntervals();
73bool WebAssemblyOptimizeLiveIntervals::runOnMachineFunction(
74 MachineFunction &MF) {
75 LLVM_DEBUG(dbgs() << "********** Optimize LiveIntervals **********\n"
76 "********** Function: "
77 << MF.getName() << '\n');
80 auto &LIS = getAnalysis<LiveIntervals>();
82 // We don't preserve SSA form.
83 MRI.leaveSSA();
85 assert(MRI.tracksLiveness() && "OptimizeLiveIntervals expects liveness");
87 // Split multiple-VN LiveIntervals into multiple LiveIntervals.
89 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I < E; ++I) {
91 auto &TRI = *MF.getSubtarget<WebAssemblySubtarget>().getRegisterInfo();
93 if (MRI.reg_nodbg_empty(Reg))
94 continue;
96 LIS.splitSeparateComponents(LIS.getInterval(Reg), SplitLIs);
97 if (Reg == TRI.getFrameRegister(MF) && SplitLIs.size() > 0) {
98 // The live interval for the frame register was split, resulting in a new
99 // VReg. For now we only support debug info output for a single frame base
100 // value for the function, so just use the last one. It will certainly be
101 // wrong for some part of the function, but until we are able to track
102 // values through live-range splitting and stackification, it will have to
103 // do.
104 MF.getInfo<WebAssemblyFunctionInfo>()->setFrameBaseVreg(
105 SplitLIs.back()->reg());
106 }
107 SplitLIs.clear();
108 }
110 // In FixIrreducibleControlFlow, we conservatively inserted IMPLICIT_DEF
111 // instructions to satisfy LiveIntervals' requirement that all uses be
112 // dominated by defs. Now that LiveIntervals has computed which of these
113 // defs are actually needed and which are dead, remove the dead ones.
115 if (MI.isImplicitDef() && MI.getOperand(0).isDead()) {
116 LiveInterval &LI = LIS.getInterval(MI.getOperand(0).getReg());
117 LIS.removeVRegDefAt(LI, LIS.getInstructionIndex(MI).getRegSlot());
118 LIS.RemoveMachineInstrFromMaps(MI);
119 MI.eraseFromParent();
120 }
121 }
123 return true;
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_DEBUG(X)
Definition: Debug.h:101
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file declares WebAssembly-specific per-machine-function information.
This file declares the WebAssembly-specific subclass of TargetSubtarget.
This file contains the entry points for global functions defined in the LLVM WebAssembly back-end.
Represent the analysis usage information of a pass.
AnalysisUsage & addPreservedID(const void *ID)
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:265
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:686
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineBasicBlock & front() const
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
Definition: Register.h:84
SlotIndexes pass.
Definition: SlotIndexes.h:319
size_t size() const
Definition: SmallVector.h:91
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
This class is derived from MachineFunctionInfo and contains private WebAssembly-specific information ...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:748
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
FunctionPass * createWebAssemblyOptimizeLiveIntervals()
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...