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HexagonInstrInfo.cpp
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00001 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the Hexagon implementation of the TargetInstrInfo class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "HexagonInstrInfo.h"
00015 #include "Hexagon.h"
00016 #include "HexagonRegisterInfo.h"
00017 #include "HexagonSubtarget.h"
00018 #include "llvm/ADT/STLExtras.h"
00019 #include "llvm/ADT/SmallVector.h"
00020 #include "llvm/CodeGen/DFAPacketizer.h"
00021 #include "llvm/CodeGen/MachineFrameInfo.h"
00022 #include "llvm/CodeGen/MachineInstrBuilder.h"
00023 #include "llvm/CodeGen/MachineMemOperand.h"
00024 #include "llvm/CodeGen/MachineRegisterInfo.h"
00025 #include "llvm/CodeGen/PseudoSourceValue.h"
00026 #include "llvm/MC/MCAsmInfo.h"
00027 #include "llvm/Support/Debug.h"
00028 #include "llvm/Support/MathExtras.h"
00029 #include "llvm/Support/raw_ostream.h"
00030 #include <cctype>
00031 
00032 using namespace llvm;
00033 
00034 #define DEBUG_TYPE "hexagon-instrinfo"
00035 
00036 #define GET_INSTRINFO_CTOR_DTOR
00037 #define GET_INSTRMAP_INFO
00038 #include "HexagonGenInstrInfo.inc"
00039 #include "HexagonGenDFAPacketizer.inc"
00040 
00041 using namespace llvm;
00042 
00043 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
00044   cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
00045                             "packetization boundary."));
00046 
00047 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
00048   cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"));
00049 
00050 static cl::opt<bool> DisableNVSchedule("disable-hexagon-nv-schedule",
00051   cl::Hidden, cl::ZeroOrMore, cl::init(false),
00052   cl::desc("Disable schedule adjustment for new value stores."));
00053 
00054 static cl::opt<bool> EnableTimingClassLatency(
00055   "enable-timing-class-latency", cl::Hidden, cl::init(false),
00056   cl::desc("Enable timing class latency"));
00057 
00058 static cl::opt<bool> EnableALUForwarding(
00059   "enable-alu-forwarding", cl::Hidden, cl::init(true),
00060   cl::desc("Enable vec alu forwarding"));
00061 
00062 static cl::opt<bool> EnableACCForwarding(
00063   "enable-acc-forwarding", cl::Hidden, cl::init(true),
00064   cl::desc("Enable vec acc forwarding"));
00065 
00066 static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
00067   cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"));
00068 
00069 ///
00070 /// Constants for Hexagon instructions.
00071 ///
00072 const int Hexagon_MEMV_OFFSET_MAX_128B = 2047;  // #s7
00073 const int Hexagon_MEMV_OFFSET_MIN_128B = -2048; // #s7
00074 const int Hexagon_MEMV_OFFSET_MAX = 1023;  // #s6
00075 const int Hexagon_MEMV_OFFSET_MIN = -1024; // #s6
00076 const int Hexagon_MEMW_OFFSET_MAX = 4095;
00077 const int Hexagon_MEMW_OFFSET_MIN = -4096;
00078 const int Hexagon_MEMD_OFFSET_MAX = 8191;
00079 const int Hexagon_MEMD_OFFSET_MIN = -8192;
00080 const int Hexagon_MEMH_OFFSET_MAX = 2047;
00081 const int Hexagon_MEMH_OFFSET_MIN = -2048;
00082 const int Hexagon_MEMB_OFFSET_MAX = 1023;
00083 const int Hexagon_MEMB_OFFSET_MIN = -1024;
00084 const int Hexagon_ADDI_OFFSET_MAX = 32767;
00085 const int Hexagon_ADDI_OFFSET_MIN = -32768;
00086 const int Hexagon_MEMD_AUTOINC_MAX = 56;
00087 const int Hexagon_MEMD_AUTOINC_MIN = -64;
00088 const int Hexagon_MEMW_AUTOINC_MAX = 28;
00089 const int Hexagon_MEMW_AUTOINC_MIN = -32;
00090 const int Hexagon_MEMH_AUTOINC_MAX = 14;
00091 const int Hexagon_MEMH_AUTOINC_MIN = -16;
00092 const int Hexagon_MEMB_AUTOINC_MAX = 7;
00093 const int Hexagon_MEMB_AUTOINC_MIN = -8;
00094 const int Hexagon_MEMV_AUTOINC_MAX = 192;
00095 const int Hexagon_MEMV_AUTOINC_MIN = -256;
00096 const int Hexagon_MEMV_AUTOINC_MAX_128B = 384;
00097 const int Hexagon_MEMV_AUTOINC_MIN_128B = -512;
00098 
00099 // Pin the vtable to this file.
00100 void HexagonInstrInfo::anchor() {}
00101 
00102 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
00103     : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
00104       RI() {}
00105 
00106 
00107 static bool isIntRegForSubInst(unsigned Reg) {
00108   return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
00109          (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
00110 }
00111 
00112 
00113 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
00114   return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_loreg)) &&
00115          isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_hireg));
00116 }
00117 
00118 
00119 /// Calculate number of instructions excluding the debug instructions.
00120 static unsigned nonDbgMICount(MachineBasicBlock::const_instr_iterator MIB,
00121                               MachineBasicBlock::const_instr_iterator MIE) {
00122   unsigned Count = 0;
00123   for (; MIB != MIE; ++MIB) {
00124     if (!MIB->isDebugValue())
00125       ++Count;
00126   }
00127   return Count;
00128 }
00129 
00130 
00131 /// Find the hardware loop instruction used to set-up the specified loop.
00132 /// On Hexagon, we have two instructions used to set-up the hardware loop
00133 /// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
00134 /// to indicate the end of a loop.
00135 static MachineInstr *findLoopInstr(MachineBasicBlock *BB, int EndLoopOp,
00136       SmallPtrSet<MachineBasicBlock *, 8> &Visited) {
00137   int LOOPi;
00138   int LOOPr;
00139   if (EndLoopOp == Hexagon::ENDLOOP0) {
00140     LOOPi = Hexagon::J2_loop0i;
00141     LOOPr = Hexagon::J2_loop0r;
00142   } else { // EndLoopOp == Hexagon::EndLOOP1
00143     LOOPi = Hexagon::J2_loop1i;
00144     LOOPr = Hexagon::J2_loop1r;
00145   }
00146 
00147   // The loop set-up instruction will be in a predecessor block
00148   for (MachineBasicBlock::pred_iterator PB = BB->pred_begin(),
00149          PE = BB->pred_end(); PB != PE; ++PB) {
00150     // If this has been visited, already skip it.
00151     if (!Visited.insert(*PB).second)
00152       continue;
00153     if (*PB == BB)
00154       continue;
00155     for (MachineBasicBlock::reverse_instr_iterator I = (*PB)->instr_rbegin(),
00156            E = (*PB)->instr_rend(); I != E; ++I) {
00157       int Opc = I->getOpcode();
00158       if (Opc == LOOPi || Opc == LOOPr)
00159         return &*I;
00160       // We've reached a different loop, which means the loop0 has been removed.
00161       if (Opc == EndLoopOp)
00162         return 0;
00163     }
00164     // Check the predecessors for the LOOP instruction.
00165     MachineInstr *loop = findLoopInstr(*PB, EndLoopOp, Visited);
00166     if (loop)
00167       return loop;
00168   }
00169   return 0;
00170 }
00171 
00172 
00173 /// Gather register def/uses from MI.
00174 /// This treats possible (predicated) defs as actually happening ones
00175 /// (conservatively).
00176 static inline void parseOperands(const MachineInstr *MI,
00177       SmallVector<unsigned, 4> &Defs, SmallVector<unsigned, 8> &Uses) {
00178   Defs.clear();
00179   Uses.clear();
00180 
00181   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
00182     const MachineOperand &MO = MI->getOperand(i);
00183 
00184     if (!MO.isReg())
00185       continue;
00186 
00187     unsigned Reg = MO.getReg();
00188     if (!Reg)
00189       continue;
00190 
00191     if (MO.isUse())
00192       Uses.push_back(MO.getReg());
00193 
00194     if (MO.isDef())
00195       Defs.push_back(MO.getReg());
00196   }
00197 }
00198 
00199 
00200 // Position dependent, so check twice for swap.
00201 static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
00202   switch (Ga) {
00203   case HexagonII::HSIG_None:
00204   default:
00205     return false;
00206   case HexagonII::HSIG_L1:
00207     return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
00208   case HexagonII::HSIG_L2:
00209     return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
00210             Gb == HexagonII::HSIG_A);
00211   case HexagonII::HSIG_S1:
00212     return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
00213             Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
00214   case HexagonII::HSIG_S2:
00215     return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
00216             Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
00217             Gb == HexagonII::HSIG_A);
00218   case HexagonII::HSIG_A:
00219     return (Gb == HexagonII::HSIG_A);
00220   case HexagonII::HSIG_Compound:
00221     return (Gb == HexagonII::HSIG_Compound);
00222   }
00223   return false;
00224 }
00225 
00226 
00227 
00228 /// isLoadFromStackSlot - If the specified machine instruction is a direct
00229 /// load from a stack slot, return the virtual or physical register number of
00230 /// the destination along with the FrameIndex of the loaded stack slot.  If
00231 /// not, return 0.  This predicate must return 0 if the instruction has
00232 /// any side effects other than loading from the stack slot.
00233 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
00234                                                int &FrameIndex) const {
00235   switch (MI->getOpcode()) {
00236   default: break;
00237   case Hexagon::L2_loadri_io:
00238   case Hexagon::L2_loadrd_io:
00239   case Hexagon::L2_loadrh_io:
00240   case Hexagon::L2_loadrb_io:
00241   case Hexagon::L2_loadrub_io:
00242     if (MI->getOperand(2).isFI() &&
00243         MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
00244       FrameIndex = MI->getOperand(2).getIndex();
00245       return MI->getOperand(0).getReg();
00246     }
00247     break;
00248   }
00249   return 0;
00250 }
00251 
00252 
00253 /// isStoreToStackSlot - If the specified machine instruction is a direct
00254 /// store to a stack slot, return the virtual or physical register number of
00255 /// the source reg along with the FrameIndex of the loaded stack slot.  If
00256 /// not, return 0.  This predicate must return 0 if the instruction has
00257 /// any side effects other than storing to the stack slot.
00258 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
00259                                               int &FrameIndex) const {
00260   switch (MI->getOpcode()) {
00261   default: break;
00262   case Hexagon::S2_storeri_io:
00263   case Hexagon::S2_storerd_io:
00264   case Hexagon::S2_storerh_io:
00265   case Hexagon::S2_storerb_io:
00266     if (MI->getOperand(2).isFI() &&
00267         MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
00268       FrameIndex = MI->getOperand(0).getIndex();
00269       return MI->getOperand(2).getReg();
00270     }
00271     break;
00272   }
00273   return 0;
00274 }
00275 
00276 
00277 /// This function can analyze one/two way branching only and should (mostly) be
00278 /// called by target independent side.
00279 /// First entry is always the opcode of the branching instruction, except when
00280 /// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
00281 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
00282 /// e.g. Jump_c p will have
00283 /// Cond[0] = Jump_c
00284 /// Cond[1] = p
00285 /// HW-loop ENDLOOP:
00286 /// Cond[0] = ENDLOOP
00287 /// Cond[1] = MBB
00288 /// New value jump:
00289 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
00290 /// Cond[1] = R
00291 /// Cond[2] = Imm
00292 ///
00293 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
00294                                      MachineBasicBlock *&TBB,
00295                                      MachineBasicBlock *&FBB,
00296                                      SmallVectorImpl<MachineOperand> &Cond,
00297                                      bool AllowModify) const {
00298   TBB = nullptr;
00299   FBB = nullptr;
00300   Cond.clear();
00301 
00302   // If the block has no terminators, it just falls into the block after it.
00303   MachineBasicBlock::instr_iterator I = MBB.instr_end();
00304   if (I == MBB.instr_begin())
00305     return false;
00306 
00307   // A basic block may looks like this:
00308   //
00309   //  [   insn
00310   //     EH_LABEL
00311   //      insn
00312   //      insn
00313   //      insn
00314   //     EH_LABEL
00315   //      insn     ]
00316   //
00317   // It has two succs but does not have a terminator
00318   // Don't know how to handle it.
00319   do {
00320     --I;
00321     if (I->isEHLabel())
00322       // Don't analyze EH branches.
00323       return true;
00324   } while (I != MBB.instr_begin());
00325 
00326   I = MBB.instr_end();
00327   --I;
00328 
00329   while (I->isDebugValue()) {
00330     if (I == MBB.instr_begin())
00331       return false;
00332     --I;
00333   }
00334 
00335   bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
00336                      I->getOperand(0).isMBB();
00337   // Delete the J2_jump if it's equivalent to a fall-through.
00338   if (AllowModify && JumpToBlock &&
00339       MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
00340     DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
00341     I->eraseFromParent();
00342     I = MBB.instr_end();
00343     if (I == MBB.instr_begin())
00344       return false;
00345     --I;
00346   }
00347   if (!isUnpredicatedTerminator(&*I))
00348     return false;
00349 
00350   // Get the last instruction in the block.
00351   MachineInstr *LastInst = &*I;
00352   MachineInstr *SecondLastInst = nullptr;
00353   // Find one more terminator if present.
00354   for (;;) {
00355     if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(&*I)) {
00356       if (!SecondLastInst)
00357         SecondLastInst = &*I;
00358       else
00359         // This is a third branch.
00360         return true;
00361     }
00362     if (I == MBB.instr_begin())
00363       break;
00364     --I;
00365   }
00366 
00367   int LastOpcode = LastInst->getOpcode();
00368   int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
00369   // If the branch target is not a basic block, it could be a tail call.
00370   // (It is, if the target is a function.)
00371   if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
00372     return true;
00373   if (SecLastOpcode == Hexagon::J2_jump &&
00374       !SecondLastInst->getOperand(0).isMBB())
00375     return true;
00376 
00377   bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
00378   bool LastOpcodeHasNVJump = isNewValueJump(LastInst);
00379 
00380   if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
00381     return true;
00382 
00383   // If there is only one terminator instruction, process it.
00384   if (LastInst && !SecondLastInst) {
00385     if (LastOpcode == Hexagon::J2_jump) {
00386       TBB = LastInst->getOperand(0).getMBB();
00387       return false;
00388     }
00389     if (isEndLoopN(LastOpcode)) {
00390       TBB = LastInst->getOperand(0).getMBB();
00391       Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
00392       Cond.push_back(LastInst->getOperand(0));
00393       return false;
00394     }
00395     if (LastOpcodeHasJMP_c) {
00396       TBB = LastInst->getOperand(1).getMBB();
00397       Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
00398       Cond.push_back(LastInst->getOperand(0));
00399       return false;
00400     }
00401     // Only supporting rr/ri versions of new-value jumps.
00402     if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
00403       TBB = LastInst->getOperand(2).getMBB();
00404       Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
00405       Cond.push_back(LastInst->getOperand(0));
00406       Cond.push_back(LastInst->getOperand(1));
00407       return false;
00408     }
00409     DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
00410                  << " with one jump\n";);
00411     // Otherwise, don't know what this is.
00412     return true;
00413   }
00414 
00415   bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
00416   bool SecLastOpcodeHasNVJump = isNewValueJump(SecondLastInst);
00417   if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
00418     if (!SecondLastInst->getOperand(1).isMBB())
00419       return true;
00420     TBB =  SecondLastInst->getOperand(1).getMBB();
00421     Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
00422     Cond.push_back(SecondLastInst->getOperand(0));
00423     FBB = LastInst->getOperand(0).getMBB();
00424     return false;
00425   }
00426 
00427   // Only supporting rr/ri versions of new-value jumps.
00428   if (SecLastOpcodeHasNVJump &&
00429       (SecondLastInst->getNumExplicitOperands() == 3) &&
00430       (LastOpcode == Hexagon::J2_jump)) {
00431     TBB = SecondLastInst->getOperand(2).getMBB();
00432     Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
00433     Cond.push_back(SecondLastInst->getOperand(0));
00434     Cond.push_back(SecondLastInst->getOperand(1));
00435     FBB = LastInst->getOperand(0).getMBB();
00436     return false;
00437   }
00438 
00439   // If the block ends with two Hexagon:JMPs, handle it.  The second one is not
00440   // executed, so remove it.
00441   if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
00442     TBB = SecondLastInst->getOperand(0).getMBB();
00443     I = LastInst->getIterator();
00444     if (AllowModify)
00445       I->eraseFromParent();
00446     return false;
00447   }
00448 
00449   // If the block ends with an ENDLOOP, and J2_jump, handle it.
00450   if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
00451     TBB = SecondLastInst->getOperand(0).getMBB();
00452     Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
00453     Cond.push_back(SecondLastInst->getOperand(0));
00454     FBB = LastInst->getOperand(0).getMBB();
00455     return false;
00456   }
00457   DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
00458                << " with two jumps";);
00459   // Otherwise, can't handle this.
00460   return true;
00461 }
00462 
00463 
00464 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
00465   DEBUG(dbgs() << "\nRemoving branches out of BB#" << MBB.getNumber());
00466   MachineBasicBlock::iterator I = MBB.end();
00467   unsigned Count = 0;
00468   while (I != MBB.begin()) {
00469     --I;
00470     if (I->isDebugValue())
00471       continue;
00472     // Only removing branches from end of MBB.
00473     if (!I->isBranch())
00474       return Count;
00475     if (Count && (I->getOpcode() == Hexagon::J2_jump))
00476       llvm_unreachable("Malformed basic block: unconditional branch not last");
00477     MBB.erase(&MBB.back());
00478     I = MBB.end();
00479     ++Count;
00480   }
00481   return Count;
00482 }
00483 
00484 
00485 unsigned HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,
00486       MachineBasicBlock *TBB, MachineBasicBlock *FBB,
00487       ArrayRef<MachineOperand> Cond, DebugLoc DL) const {
00488   unsigned BOpc   = Hexagon::J2_jump;
00489   unsigned BccOpc = Hexagon::J2_jumpt;
00490   assert(validateBranchCond(Cond) && "Invalid branching condition");
00491   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
00492 
00493   // Check if ReverseBranchCondition has asked to reverse this branch
00494   // If we want to reverse the branch an odd number of times, we want
00495   // J2_jumpf.
00496   if (!Cond.empty() && Cond[0].isImm())
00497     BccOpc = Cond[0].getImm();
00498 
00499   if (!FBB) {
00500     if (Cond.empty()) {
00501       // Due to a bug in TailMerging/CFG Optimization, we need to add a
00502       // special case handling of a predicated jump followed by an
00503       // unconditional jump. If not, Tail Merging and CFG Optimization go
00504       // into an infinite loop.
00505       MachineBasicBlock *NewTBB, *NewFBB;
00506       SmallVector<MachineOperand, 4> Cond;
00507       MachineInstr *Term = MBB.getFirstTerminator();
00508       if (Term != MBB.end() && isPredicated(Term) &&
00509           !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond, false)) {
00510         MachineBasicBlock *NextBB = &*++MBB.getIterator();
00511         if (NewTBB == NextBB) {
00512           ReverseBranchCondition(Cond);
00513           RemoveBranch(MBB);
00514           return InsertBranch(MBB, TBB, nullptr, Cond, DL);
00515         }
00516       }
00517       BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
00518     } else if (isEndLoopN(Cond[0].getImm())) {
00519       int EndLoopOp = Cond[0].getImm();
00520       assert(Cond[1].isMBB());
00521       // Since we're adding an ENDLOOP, there better be a LOOP instruction.
00522       // Check for it, and change the BB target if needed.
00523       SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
00524       MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, VisitedBBs);
00525       assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP");
00526       Loop->getOperand(0).setMBB(TBB);
00527       // Add the ENDLOOP after the finding the LOOP0.
00528       BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
00529     } else if (isNewValueJump(Cond[0].getImm())) {
00530       assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
00531       // New value jump
00532       // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
00533       // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
00534       unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
00535       DEBUG(dbgs() << "\nInserting NVJump for BB#" << MBB.getNumber(););
00536       if (Cond[2].isReg()) {
00537         unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
00538         BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
00539           addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
00540       } else if(Cond[2].isImm()) {
00541         BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
00542           addImm(Cond[2].getImm()).addMBB(TBB);
00543       } else
00544         llvm_unreachable("Invalid condition for branching");
00545     } else {
00546       assert((Cond.size() == 2) && "Malformed cond vector");
00547       const MachineOperand &RO = Cond[1];
00548       unsigned Flags = getUndefRegState(RO.isUndef());
00549       BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
00550     }
00551     return 1;
00552   }
00553   assert((!Cond.empty()) &&
00554          "Cond. cannot be empty when multiple branchings are required");
00555   assert((!isNewValueJump(Cond[0].getImm())) &&
00556          "NV-jump cannot be inserted with another branch");
00557   // Special case for hardware loops.  The condition is a basic block.
00558   if (isEndLoopN(Cond[0].getImm())) {
00559     int EndLoopOp = Cond[0].getImm();
00560     assert(Cond[1].isMBB());
00561     // Since we're adding an ENDLOOP, there better be a LOOP instruction.
00562     // Check for it, and change the BB target if needed.
00563     SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
00564     MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, VisitedBBs);
00565     assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP");
00566     Loop->getOperand(0).setMBB(TBB);
00567     // Add the ENDLOOP after the finding the LOOP0.
00568     BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
00569   } else {
00570     const MachineOperand &RO = Cond[1];
00571     unsigned Flags = getUndefRegState(RO.isUndef());
00572     BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
00573   }
00574   BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
00575 
00576   return 2;
00577 }
00578 
00579 
00580 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
00581       unsigned NumCycles, unsigned ExtraPredCycles,
00582       BranchProbability Probability) const {
00583   return nonDbgBBSize(&MBB) <= 3;
00584 }
00585 
00586 
00587 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
00588       unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
00589       unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
00590       const {
00591   return nonDbgBBSize(&TMBB) <= 3 && nonDbgBBSize(&FMBB) <= 3;
00592 }
00593 
00594 
00595 bool HexagonInstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
00596       unsigned NumInstrs, BranchProbability Probability) const {
00597   return NumInstrs <= 4;
00598 }
00599 
00600 
00601 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
00602       MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg,
00603       unsigned SrcReg, bool KillSrc) const {
00604   auto &HRI = getRegisterInfo();
00605   if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
00606     BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg).addReg(SrcReg);
00607     return;
00608   }
00609   if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
00610     BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg).addReg(SrcReg);
00611     return;
00612   }
00613   if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
00614     // Map Pd = Ps to Pd = or(Ps, Ps).
00615     BuildMI(MBB, I, DL, get(Hexagon::C2_or),
00616             DestReg).addReg(SrcReg).addReg(SrcReg);
00617     return;
00618   }
00619   if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
00620       Hexagon::IntRegsRegClass.contains(SrcReg)) {
00621     // We can have an overlap between single and double reg: r1:0 = r0.
00622     if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
00623         // r1:0 = r0
00624         BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
00625                 Hexagon::subreg_hireg))).addImm(0);
00626     } else {
00627         // r1:0 = r1 or no overlap.
00628         BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), (RI.getSubReg(DestReg,
00629                 Hexagon::subreg_loreg))).addReg(SrcReg);
00630         BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
00631                 Hexagon::subreg_hireg))).addImm(0);
00632     }
00633     return;
00634   }
00635   if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
00636       Hexagon::IntRegsRegClass.contains(SrcReg)) {
00637     BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg).addReg(SrcReg);
00638     return;
00639   }
00640   if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
00641       Hexagon::IntRegsRegClass.contains(DestReg)) {
00642     BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg).
00643       addReg(SrcReg, getKillRegState(KillSrc));
00644     return;
00645   }
00646   if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
00647       Hexagon::PredRegsRegClass.contains(DestReg)) {
00648     BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg).
00649       addReg(SrcReg, getKillRegState(KillSrc));
00650     return;
00651   }
00652   if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
00653       Hexagon::IntRegsRegClass.contains(DestReg)) {
00654     BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg).
00655       addReg(SrcReg, getKillRegState(KillSrc));
00656     return;
00657   }
00658   if (Hexagon::VectorRegsRegClass.contains(SrcReg, DestReg)) {
00659     BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
00660       addReg(SrcReg, getKillRegState(KillSrc));
00661     return;
00662   }
00663   if (Hexagon::VecDblRegsRegClass.contains(SrcReg, DestReg)) {
00664     BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg).
00665       addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg),
00666              getKillRegState(KillSrc)).
00667       addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg),
00668              getKillRegState(KillSrc));
00669     return;
00670   }
00671   if (Hexagon::VecPredRegsRegClass.contains(SrcReg, DestReg)) {
00672     BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg).
00673       addReg(SrcReg).
00674       addReg(SrcReg, getKillRegState(KillSrc));
00675     return;
00676   }
00677   if (Hexagon::VecPredRegsRegClass.contains(SrcReg) &&
00678     Hexagon::VectorRegsRegClass.contains(DestReg)) {
00679     llvm_unreachable("Unimplemented pred to vec");
00680     return;
00681   }
00682   if (Hexagon::VecPredRegsRegClass.contains(DestReg) &&
00683       Hexagon::VectorRegsRegClass.contains(SrcReg)) {
00684     llvm_unreachable("Unimplemented vec to pred");
00685     return;
00686   }
00687   if (Hexagon::VecPredRegs128BRegClass.contains(SrcReg, DestReg)) {
00688     BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and),
00689       HRI.getSubReg(DestReg, Hexagon::subreg_hireg)).
00690       addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg),
00691              getKillRegState(KillSrc));
00692     BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and),
00693       HRI.getSubReg(DestReg, Hexagon::subreg_loreg)).
00694       addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg),
00695              getKillRegState(KillSrc));
00696     return;
00697   }
00698 
00699 #ifndef NDEBUG
00700   // Show the invalid registers to ease debugging.
00701   dbgs() << "Invalid registers for copy in BB#" << MBB.getNumber()
00702          << ": " << PrintReg(DestReg, &HRI)
00703          << " = " << PrintReg(SrcReg, &HRI) << '\n';
00704 #endif
00705   llvm_unreachable("Unimplemented");
00706 }
00707 
00708 
00709 void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
00710       MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI,
00711       const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
00712   DebugLoc DL = MBB.findDebugLoc(I);
00713   MachineFunction &MF = *MBB.getParent();
00714   MachineFrameInfo &MFI = *MF.getFrameInfo();
00715   unsigned Align = MFI.getObjectAlignment(FI);
00716 
00717   MachineMemOperand *MMO = MF.getMachineMemOperand(
00718       MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
00719       MFI.getObjectSize(FI), Align);
00720 
00721   if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
00722     BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
00723           .addFrameIndex(FI).addImm(0)
00724           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00725   } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
00726     BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
00727           .addFrameIndex(FI).addImm(0)
00728           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00729   } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
00730     BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
00731       .addFrameIndex(FI).addImm(0)
00732       .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00733   } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
00734     BuildMI(MBB, I, DL, get(Hexagon::STriw_mod))
00735       .addFrameIndex(FI).addImm(0)
00736       .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00737   } else {
00738     llvm_unreachable("Unimplemented");
00739   }
00740 }
00741 
00742 
00743 void HexagonInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
00744       MachineBasicBlock::iterator I, unsigned DestReg, int FI,
00745       const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
00746   DebugLoc DL = MBB.findDebugLoc(I);
00747   MachineFunction &MF = *MBB.getParent();
00748   MachineFrameInfo &MFI = *MF.getFrameInfo();
00749   unsigned Align = MFI.getObjectAlignment(FI);
00750 
00751   MachineMemOperand *MMO = MF.getMachineMemOperand(
00752       MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
00753       MFI.getObjectSize(FI), Align);
00754   if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
00755     BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
00756           .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00757   } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
00758     BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
00759           .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00760   } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
00761     BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
00762       .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00763   } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
00764     BuildMI(MBB, I, DL, get(Hexagon::LDriw_mod), DestReg)
00765       .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00766   } else {
00767     llvm_unreachable("Can't store this register to stack slot");
00768   }
00769 }
00770 
00771 
00772 /// expandPostRAPseudo - This function is called for all pseudo instructions
00773 /// that remain after register allocation. Many pseudo instructions are
00774 /// created to help register allocation. This is the place to convert them
00775 /// into real instructions. The target can edit MI in place, or it can insert
00776 /// new instructions and erase MI. The function should return true if
00777 /// anything was changed.
00778 bool HexagonInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI)
00779       const {
00780   const HexagonRegisterInfo &HRI = getRegisterInfo();
00781   MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
00782   MachineBasicBlock &MBB = *MI->getParent();
00783   DebugLoc DL = MI->getDebugLoc();
00784   unsigned Opc = MI->getOpcode();
00785   const unsigned VecOffset = 1;
00786   bool Is128B = false;
00787 
00788   switch (Opc) {
00789     case Hexagon::ALIGNA:
00790       BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI->getOperand(0).getReg())
00791           .addReg(HRI.getFrameRegister())
00792           .addImm(-MI->getOperand(1).getImm());
00793       MBB.erase(MI);
00794       return true;
00795     case Hexagon::HEXAGON_V6_vassignp_128B:
00796     case Hexagon::HEXAGON_V6_vassignp: {
00797       unsigned SrcReg = MI->getOperand(1).getReg();
00798       unsigned DstReg = MI->getOperand(0).getReg();
00799       if (SrcReg != DstReg)
00800         copyPhysReg(MBB, MI, DL, DstReg, SrcReg, MI->getOperand(1).isKill());
00801       MBB.erase(MI);
00802       return true;
00803     }
00804     case Hexagon::HEXAGON_V6_lo_128B:
00805     case Hexagon::HEXAGON_V6_lo: {
00806       unsigned SrcReg = MI->getOperand(1).getReg();
00807       unsigned DstReg = MI->getOperand(0).getReg();
00808       unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::subreg_loreg);
00809       copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI->getOperand(1).isKill());
00810       MBB.erase(MI);
00811       MRI.clearKillFlags(SrcSubLo);
00812       return true;
00813     }
00814     case Hexagon::HEXAGON_V6_hi_128B:
00815     case Hexagon::HEXAGON_V6_hi: {
00816       unsigned SrcReg = MI->getOperand(1).getReg();
00817       unsigned DstReg = MI->getOperand(0).getReg();
00818       unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::subreg_hireg);
00819       copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI->getOperand(1).isKill());
00820       MBB.erase(MI);
00821       MRI.clearKillFlags(SrcSubHi);
00822       return true;
00823     }
00824     case Hexagon::STrivv_indexed_128B:
00825       Is128B = true;
00826     case Hexagon::STrivv_indexed: {
00827       unsigned SrcReg = MI->getOperand(2).getReg();
00828       unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::subreg_hireg);
00829       unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::subreg_loreg);
00830       unsigned NewOpcd = Is128B ? Hexagon::V6_vS32b_ai_128B
00831                                 : Hexagon::V6_vS32b_ai;
00832       unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6;
00833       MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpcd))
00834           .addOperand(MI->getOperand(0))
00835           .addImm(MI->getOperand(1).getImm())
00836           .addReg(SrcSubLo)
00837           .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
00838       MI1New->getOperand(0).setIsKill(false);
00839       BuildMI(MBB, MI, DL, get(NewOpcd))
00840         .addOperand(MI->getOperand(0))
00841         // The Vectors are indexed in multiples of vector size.
00842         .addImm(MI->getOperand(1).getImm()+Offset)
00843         .addReg(SrcSubHi)
00844         .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
00845       MBB.erase(MI);
00846       return true;
00847     }
00848     case Hexagon::LDrivv_pseudo_V6_128B:
00849     case Hexagon::LDrivv_indexed_128B:
00850       Is128B = true;
00851     case Hexagon::LDrivv_pseudo_V6:
00852     case Hexagon::LDrivv_indexed: {
00853       unsigned NewOpcd = Is128B ? Hexagon::V6_vL32b_ai_128B
00854                                 : Hexagon::V6_vL32b_ai;
00855       unsigned DstReg = MI->getOperand(0).getReg();
00856       unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6;
00857       MachineInstr *MI1New =
00858           BuildMI(MBB, MI, DL, get(NewOpcd),
00859                   HRI.getSubReg(DstReg, Hexagon::subreg_loreg))
00860               .addOperand(MI->getOperand(1))
00861               .addImm(MI->getOperand(2).getImm());
00862       MI1New->getOperand(1).setIsKill(false);
00863       BuildMI(MBB, MI, DL, get(NewOpcd),
00864               HRI.getSubReg(DstReg, Hexagon::subreg_hireg))
00865           .addOperand(MI->getOperand(1))
00866           // The Vectors are indexed in multiples of vector size.
00867           .addImm(MI->getOperand(2).getImm() + Offset)
00868           .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
00869       MBB.erase(MI);
00870       return true;
00871     }
00872     case Hexagon::LDriv_pseudo_V6_128B:
00873       Is128B = true;
00874     case Hexagon::LDriv_pseudo_V6: {
00875       unsigned DstReg = MI->getOperand(0).getReg();
00876       unsigned NewOpc = Is128B ? Hexagon::V6_vL32b_ai_128B
00877                                : Hexagon::V6_vL32b_ai;
00878       int32_t Off = MI->getOperand(2).getImm();
00879       int32_t Idx = Off;
00880       BuildMI(MBB, MI, DL, get(NewOpc), DstReg)
00881         .addOperand(MI->getOperand(1))
00882         .addImm(Idx)
00883         .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
00884       MBB.erase(MI);
00885       return true;
00886     }
00887     case Hexagon::STriv_pseudo_V6_128B:
00888       Is128B = true;
00889     case Hexagon::STriv_pseudo_V6: {
00890       unsigned NewOpc = Is128B ? Hexagon::V6_vS32b_ai_128B
00891                                : Hexagon::V6_vS32b_ai;
00892       int32_t Off = MI->getOperand(1).getImm();
00893       int32_t Idx = Is128B ? (Off >> 7) : (Off >> 6);
00894       BuildMI(MBB, MI, DL, get(NewOpc))
00895         .addOperand(MI->getOperand(0))
00896         .addImm(Idx)
00897         .addOperand(MI->getOperand(2))
00898         .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
00899       MBB.erase(MI);
00900       return true;
00901     }
00902     case Hexagon::TFR_PdTrue: {
00903       unsigned Reg = MI->getOperand(0).getReg();
00904       BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
00905         .addReg(Reg, RegState::Undef)
00906         .addReg(Reg, RegState::Undef);
00907       MBB.erase(MI);
00908       return true;
00909     }
00910     case Hexagon::TFR_PdFalse: {
00911       unsigned Reg = MI->getOperand(0).getReg();
00912       BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
00913         .addReg(Reg, RegState::Undef)
00914         .addReg(Reg, RegState::Undef);
00915       MBB.erase(MI);
00916       return true;
00917     }
00918     case Hexagon::VMULW: {
00919       // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
00920       unsigned DstReg = MI->getOperand(0).getReg();
00921       unsigned Src1Reg = MI->getOperand(1).getReg();
00922       unsigned Src2Reg = MI->getOperand(2).getReg();
00923       unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
00924       unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
00925       unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
00926       unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
00927       BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
00928               HRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
00929           .addReg(Src2SubHi);
00930       BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
00931               HRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
00932           .addReg(Src2SubLo);
00933       MBB.erase(MI);
00934       MRI.clearKillFlags(Src1SubHi);
00935       MRI.clearKillFlags(Src1SubLo);
00936       MRI.clearKillFlags(Src2SubHi);
00937       MRI.clearKillFlags(Src2SubLo);
00938       return true;
00939     }
00940     case Hexagon::VMULW_ACC: {
00941       // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
00942       unsigned DstReg = MI->getOperand(0).getReg();
00943       unsigned Src1Reg = MI->getOperand(1).getReg();
00944       unsigned Src2Reg = MI->getOperand(2).getReg();
00945       unsigned Src3Reg = MI->getOperand(3).getReg();
00946       unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
00947       unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
00948       unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
00949       unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
00950       unsigned Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::subreg_hireg);
00951       unsigned Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::subreg_loreg);
00952       BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
00953               HRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
00954           .addReg(Src2SubHi).addReg(Src3SubHi);
00955       BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
00956               HRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
00957           .addReg(Src2SubLo).addReg(Src3SubLo);
00958       MBB.erase(MI);
00959       MRI.clearKillFlags(Src1SubHi);
00960       MRI.clearKillFlags(Src1SubLo);
00961       MRI.clearKillFlags(Src2SubHi);
00962       MRI.clearKillFlags(Src2SubLo);
00963       MRI.clearKillFlags(Src3SubHi);
00964       MRI.clearKillFlags(Src3SubLo);
00965       return true;
00966     }
00967     case Hexagon::Insert4: {
00968       unsigned DstReg = MI->getOperand(0).getReg();
00969       unsigned Src1Reg = MI->getOperand(1).getReg();
00970       unsigned Src2Reg = MI->getOperand(2).getReg();
00971       unsigned Src3Reg = MI->getOperand(3).getReg();
00972       unsigned Src4Reg = MI->getOperand(4).getReg();
00973       unsigned Src1RegIsKill = getKillRegState(MI->getOperand(1).isKill());
00974       unsigned Src2RegIsKill = getKillRegState(MI->getOperand(2).isKill());
00975       unsigned Src3RegIsKill = getKillRegState(MI->getOperand(3).isKill());
00976       unsigned Src4RegIsKill = getKillRegState(MI->getOperand(4).isKill());
00977       unsigned DstSubHi = HRI.getSubReg(DstReg, Hexagon::subreg_hireg);
00978       unsigned DstSubLo = HRI.getSubReg(DstReg, Hexagon::subreg_loreg);
00979       BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::S2_insert),
00980               HRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(DstSubLo)
00981           .addReg(Src1Reg, Src1RegIsKill).addImm(16).addImm(0);
00982       BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::S2_insert),
00983               HRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(DstSubLo)
00984           .addReg(Src2Reg, Src2RegIsKill).addImm(16).addImm(16);
00985       BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::S2_insert),
00986               HRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(DstSubHi)
00987           .addReg(Src3Reg, Src3RegIsKill).addImm(16).addImm(0);
00988       BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::S2_insert),
00989               HRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(DstSubHi)
00990           .addReg(Src4Reg, Src4RegIsKill).addImm(16).addImm(16);
00991       MBB.erase(MI);
00992       MRI.clearKillFlags(DstReg);
00993       MRI.clearKillFlags(DstSubHi);
00994       MRI.clearKillFlags(DstSubLo);
00995       return true;
00996     }
00997     case Hexagon::MUX64_rr: {
00998       const MachineOperand &Op0 = MI->getOperand(0);
00999       const MachineOperand &Op1 = MI->getOperand(1);
01000       const MachineOperand &Op2 = MI->getOperand(2);
01001       const MachineOperand &Op3 = MI->getOperand(3);
01002       unsigned Rd = Op0.getReg();
01003       unsigned Pu = Op1.getReg();
01004       unsigned Rs = Op2.getReg();
01005       unsigned Rt = Op3.getReg();
01006       DebugLoc DL = MI->getDebugLoc();
01007       unsigned K1 = getKillRegState(Op1.isKill());
01008       unsigned K2 = getKillRegState(Op2.isKill());
01009       unsigned K3 = getKillRegState(Op3.isKill());
01010       if (Rd != Rs)
01011         BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
01012           .addReg(Pu, (Rd == Rt) ? K1 : 0)
01013           .addReg(Rs, K2);
01014       if (Rd != Rt)
01015         BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
01016           .addReg(Pu, K1)
01017           .addReg(Rt, K3);
01018       MBB.erase(MI);
01019       return true;
01020     }
01021     case Hexagon::TCRETURNi:
01022       MI->setDesc(get(Hexagon::J2_jump));
01023       return true;
01024     case Hexagon::TCRETURNr:
01025       MI->setDesc(get(Hexagon::J2_jumpr));
01026       return true;
01027     case Hexagon::TFRI_f:
01028     case Hexagon::TFRI_cPt_f:
01029     case Hexagon::TFRI_cNotPt_f: {
01030       unsigned Opx = (Opc == Hexagon::TFRI_f) ? 1 : 2;
01031       APFloat FVal = MI->getOperand(Opx).getFPImm()->getValueAPF();
01032       APInt IVal = FVal.bitcastToAPInt();
01033       MI->RemoveOperand(Opx);
01034       unsigned NewOpc = (Opc == Hexagon::TFRI_f)     ? Hexagon::A2_tfrsi   :
01035                         (Opc == Hexagon::TFRI_cPt_f) ? Hexagon::C2_cmoveit :
01036                                                        Hexagon::C2_cmoveif;
01037       MI->setDesc(get(NewOpc));
01038       MI->addOperand(MachineOperand::CreateImm(IVal.getZExtValue()));
01039       return true;
01040     }
01041   }
01042 
01043   return false;
01044 }
01045 
01046 
01047 // We indicate that we want to reverse the branch by
01048 // inserting the reversed branching opcode.
01049 bool HexagonInstrInfo::ReverseBranchCondition(
01050       SmallVectorImpl<MachineOperand> &Cond) const {
01051   if (Cond.empty())
01052     return true;
01053   assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
01054   unsigned opcode = Cond[0].getImm();
01055   //unsigned temp;
01056   assert(get(opcode).isBranch() && "Should be a branching condition.");
01057   if (isEndLoopN(opcode))
01058     return true;
01059   unsigned NewOpcode = getInvertedPredicatedOpcode(opcode);
01060   Cond[0].setImm(NewOpcode);
01061   return false;
01062 }
01063 
01064 
01065 void HexagonInstrInfo::insertNoop(MachineBasicBlock &MBB,
01066       MachineBasicBlock::iterator MI) const {
01067   DebugLoc DL;
01068   BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
01069 }
01070 
01071 
01072 // Returns true if an instruction is predicated irrespective of the predicate
01073 // sense. For example, all of the following will return true.
01074 // if (p0) R1 = add(R2, R3)
01075 // if (!p0) R1 = add(R2, R3)
01076 // if (p0.new) R1 = add(R2, R3)
01077 // if (!p0.new) R1 = add(R2, R3)
01078 // Note: New-value stores are not included here as in the current
01079 // implementation, we don't need to check their predicate sense.
01080 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
01081   const uint64_t F = MI->getDesc().TSFlags;
01082   return (F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask;
01083 }
01084 
01085 
01086 bool HexagonInstrInfo::PredicateInstruction(MachineInstr *MI,
01087       ArrayRef<MachineOperand> Cond) const {
01088   if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
01089       isEndLoopN(Cond[0].getImm())) {
01090     DEBUG(dbgs() << "\nCannot predicate:"; MI->dump(););
01091     return false;
01092   }
01093   int Opc = MI->getOpcode();
01094   assert (isPredicable(MI) && "Expected predicable instruction");
01095   bool invertJump = predOpcodeHasNot(Cond);
01096 
01097   // We have to predicate MI "in place", i.e. after this function returns,
01098   // MI will need to be transformed into a predicated form. To avoid com-
01099   // plicated manipulations with the operands (handling tied operands,
01100   // etc.), build a new temporary instruction, then overwrite MI with it.
01101 
01102   MachineBasicBlock &B = *MI->getParent();
01103   DebugLoc DL = MI->getDebugLoc();
01104   unsigned PredOpc = getCondOpcode(Opc, invertJump);
01105   MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
01106   unsigned NOp = 0, NumOps = MI->getNumOperands();
01107   while (NOp < NumOps) {
01108     MachineOperand &Op = MI->getOperand(NOp);
01109     if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
01110       break;
01111     T.addOperand(Op);
01112     NOp++;
01113   }
01114 
01115   unsigned PredReg, PredRegPos, PredRegFlags;
01116   bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
01117   (void)GotPredReg;
01118   assert(GotPredReg);
01119   T.addReg(PredReg, PredRegFlags);
01120   while (NOp < NumOps)
01121     T.addOperand(MI->getOperand(NOp++));
01122 
01123   MI->setDesc(get(PredOpc));
01124   while (unsigned n = MI->getNumOperands())
01125     MI->RemoveOperand(n-1);
01126   for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
01127     MI->addOperand(T->getOperand(i));
01128 
01129   MachineBasicBlock::instr_iterator TI = T->getIterator();
01130   B.erase(TI);
01131 
01132   MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
01133   MRI.clearKillFlags(PredReg);
01134   return true;
01135 }
01136 
01137 
01138 bool HexagonInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
01139       ArrayRef<MachineOperand> Pred2) const {
01140   // TODO: Fix this
01141   return false;
01142 }
01143 
01144 
01145 bool HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
01146                                    std::vector<MachineOperand> &Pred) const {
01147   auto &HRI = getRegisterInfo();
01148   for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
01149     MachineOperand MO = MI->getOperand(oper);
01150     if (MO.isReg() && MO.isDef()) {
01151       const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
01152       if (RC == &Hexagon::PredRegsRegClass) {
01153         Pred.push_back(MO);
01154         return true;
01155       }
01156     }
01157   }
01158   return false;
01159 }
01160 
01161 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
01162   bool isPred = MI->getDesc().isPredicable();
01163 
01164   if (!isPred)
01165     return false;
01166 
01167   const int Opc = MI->getOpcode();
01168   int NumOperands = MI->getNumOperands();
01169 
01170   // Keep a flag for upto 4 operands in the instructions, to indicate if
01171   // that operand has been constant extended.
01172   bool OpCExtended[4];
01173   if (NumOperands > 4)
01174     NumOperands = 4;
01175 
01176   for (int i = 0; i < NumOperands; i++)
01177     OpCExtended[i] = (isOperandExtended(MI, i) && isConstExtended(MI));
01178 
01179   switch(Opc) {
01180   case Hexagon::A2_tfrsi:
01181     return (isOperandExtended(MI, 1) && isConstExtended(MI)) ||
01182            isInt<12>(MI->getOperand(1).getImm());
01183 
01184   case Hexagon::S2_storerd_io:
01185     return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
01186 
01187   case Hexagon::S2_storeri_io:
01188   case Hexagon::S2_storerinew_io:
01189     return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
01190 
01191   case Hexagon::S2_storerh_io:
01192   case Hexagon::S2_storerhnew_io:
01193     return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
01194 
01195   case Hexagon::S2_storerb_io:
01196   case Hexagon::S2_storerbnew_io:
01197     return isUInt<6>(MI->getOperand(1).getImm());
01198 
01199   case Hexagon::L2_loadrd_io:
01200     return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
01201 
01202   case Hexagon::L2_loadri_io:
01203     return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
01204 
01205   case Hexagon::L2_loadrh_io:
01206   case Hexagon::L2_loadruh_io:
01207     return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
01208 
01209   case Hexagon::L2_loadrb_io:
01210   case Hexagon::L2_loadrub_io:
01211     return isUInt<6>(MI->getOperand(2).getImm());
01212 
01213   case Hexagon::L2_loadrd_pi:
01214     return isShiftedInt<4,3>(MI->getOperand(3).getImm());
01215 
01216   case Hexagon::L2_loadri_pi:
01217     return isShiftedInt<4,2>(MI->getOperand(3).getImm());
01218 
01219   case Hexagon::L2_loadrh_pi:
01220   case Hexagon::L2_loadruh_pi:
01221     return isShiftedInt<4,1>(MI->getOperand(3).getImm());
01222 
01223   case Hexagon::L2_loadrb_pi:
01224   case Hexagon::L2_loadrub_pi:
01225     return isInt<4>(MI->getOperand(3).getImm());
01226 
01227   case Hexagon::S4_storeirb_io:
01228   case Hexagon::S4_storeirh_io:
01229   case Hexagon::S4_storeiri_io:
01230     return (OpCExtended[1] || isUInt<6>(MI->getOperand(1).getImm())) &&
01231            (OpCExtended[2] || isInt<6>(MI->getOperand(2).getImm()));
01232 
01233   case Hexagon::A2_addi:
01234     return isInt<8>(MI->getOperand(2).getImm());
01235 
01236   case Hexagon::A2_aslh:
01237   case Hexagon::A2_asrh:
01238   case Hexagon::A2_sxtb:
01239   case Hexagon::A2_sxth:
01240   case Hexagon::A2_zxtb:
01241   case Hexagon::A2_zxth:
01242     return true;
01243   }
01244 
01245   return true;
01246 }
01247 
01248 
01249 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
01250       const MachineBasicBlock *MBB, const MachineFunction &MF) const {
01251   // Debug info is never a scheduling boundary. It's necessary to be explicit
01252   // due to the special treatment of IT instructions below, otherwise a
01253   // dbg_value followed by an IT will result in the IT instruction being
01254   // considered a scheduling hazard, which is wrong. It should be the actual
01255   // instruction preceding the dbg_value instruction(s), just like it is
01256   // when debug info is not present.
01257   if (MI->isDebugValue())
01258     return false;
01259 
01260   // Throwing call is a boundary.
01261   if (MI->isCall()) {
01262     // If any of the block's successors is a landing pad, this could be a
01263     // throwing call.
01264     for (auto I : MBB->successors())
01265       if (I->isEHPad())
01266         return true;
01267   }
01268 
01269   // Don't mess around with no return calls.
01270   if (MI->getOpcode() == Hexagon::CALLv3nr)
01271     return true;
01272 
01273   // Terminators and labels can't be scheduled around.
01274   if (MI->getDesc().isTerminator() || MI->isPosition())
01275     return true;
01276 
01277   if (MI->isInlineAsm() && !ScheduleInlineAsm)
01278       return true;
01279 
01280   return false;
01281 }
01282 
01283 
01284 /// Measure the specified inline asm to determine an approximation of its
01285 /// length.
01286 /// Comments (which run till the next SeparatorString or newline) do not
01287 /// count as an instruction.
01288 /// Any other non-whitespace text is considered an instruction, with
01289 /// multiple instructions separated by SeparatorString or newlines.
01290 /// Variable-length instructions are not handled here; this function
01291 /// may be overloaded in the target code to do that.
01292 /// Hexagon counts the number of ##'s and adjust for that many
01293 /// constant exenders.
01294 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
01295       const MCAsmInfo &MAI) const {
01296   StringRef AStr(Str);
01297   // Count the number of instructions in the asm.
01298   bool atInsnStart = true;
01299   unsigned Length = 0;
01300   for (; *Str; ++Str) {
01301     if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
01302                                 strlen(MAI.getSeparatorString())) == 0)
01303       atInsnStart = true;
01304     if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
01305       Length += MAI.getMaxInstLength();
01306       atInsnStart = false;
01307     }
01308     if (atInsnStart && strncmp(Str, MAI.getCommentString(),
01309                                strlen(MAI.getCommentString())) == 0)
01310       atInsnStart = false;
01311   }
01312 
01313   // Add to size number of constant extenders seen * 4.
01314   StringRef Occ("##");
01315   Length += AStr.count(Occ)*4;
01316   return Length;
01317 }
01318 
01319 
01320 ScheduleHazardRecognizer*
01321 HexagonInstrInfo::CreateTargetPostRAHazardRecognizer(
01322       const InstrItineraryData *II, const ScheduleDAG *DAG) const {
01323   return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
01324 }
01325 
01326 
01327 /// \brief For a comparison instruction, return the source registers in
01328 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
01329 /// compares against in CmpValue. Return true if the comparison instruction
01330 /// can be analyzed.
01331 bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
01332       unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const {
01333   unsigned Opc = MI->getOpcode();
01334 
01335   // Set mask and the first source register.
01336   switch (Opc) {
01337     case Hexagon::C2_cmpeq:
01338     case Hexagon::C2_cmpeqp:
01339     case Hexagon::C2_cmpgt:
01340     case Hexagon::C2_cmpgtp:
01341     case Hexagon::C2_cmpgtu:
01342     case Hexagon::C2_cmpgtup:
01343     case Hexagon::C4_cmpneq:
01344     case Hexagon::C4_cmplte:
01345     case Hexagon::C4_cmplteu:
01346     case Hexagon::C2_cmpeqi:
01347     case Hexagon::C2_cmpgti:
01348     case Hexagon::C2_cmpgtui:
01349     case Hexagon::C4_cmpneqi:
01350     case Hexagon::C4_cmplteui:
01351     case Hexagon::C4_cmpltei:
01352       SrcReg = MI->getOperand(1).getReg();
01353       Mask = ~0;
01354       break;
01355     case Hexagon::A4_cmpbeq:
01356     case Hexagon::A4_cmpbgt:
01357     case Hexagon::A4_cmpbgtu:
01358     case Hexagon::A4_cmpbeqi:
01359     case Hexagon::A4_cmpbgti:
01360     case Hexagon::A4_cmpbgtui:
01361       SrcReg = MI->getOperand(1).getReg();
01362       Mask = 0xFF;
01363       break;
01364     case Hexagon::A4_cmpheq:
01365     case Hexagon::A4_cmphgt:
01366     case Hexagon::A4_cmphgtu:
01367     case Hexagon::A4_cmpheqi:
01368     case Hexagon::A4_cmphgti:
01369     case Hexagon::A4_cmphgtui:
01370       SrcReg = MI->getOperand(1).getReg();
01371       Mask = 0xFFFF;
01372       break;
01373   }
01374 
01375   // Set the value/second source register.
01376   switch (Opc) {
01377     case Hexagon::C2_cmpeq:
01378     case Hexagon::C2_cmpeqp:
01379     case Hexagon::C2_cmpgt:
01380     case Hexagon::C2_cmpgtp:
01381     case Hexagon::C2_cmpgtu:
01382     case Hexagon::C2_cmpgtup:
01383     case Hexagon::A4_cmpbeq:
01384     case Hexagon::A4_cmpbgt:
01385     case Hexagon::A4_cmpbgtu:
01386     case Hexagon::A4_cmpheq:
01387     case Hexagon::A4_cmphgt:
01388     case Hexagon::A4_cmphgtu:
01389     case Hexagon::C4_cmpneq:
01390     case Hexagon::C4_cmplte:
01391     case Hexagon::C4_cmplteu:
01392       SrcReg2 = MI->getOperand(2).getReg();
01393       return true;
01394 
01395     case Hexagon::C2_cmpeqi:
01396     case Hexagon::C2_cmpgtui:
01397     case Hexagon::C2_cmpgti:
01398     case Hexagon::C4_cmpneqi:
01399     case Hexagon::C4_cmplteui:
01400     case Hexagon::C4_cmpltei:
01401     case Hexagon::A4_cmpbeqi:
01402     case Hexagon::A4_cmpbgti:
01403     case Hexagon::A4_cmpbgtui:
01404     case Hexagon::A4_cmpheqi:
01405     case Hexagon::A4_cmphgti:
01406     case Hexagon::A4_cmphgtui:
01407       SrcReg2 = 0;
01408       Value = MI->getOperand(2).getImm();
01409       return true;
01410   }
01411 
01412   return false;
01413 }
01414 
01415 
01416 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
01417       const MachineInstr *MI, unsigned *PredCost) const {
01418   return getInstrTimingClassLatency(ItinData, MI);
01419 }
01420 
01421 
01422 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
01423     const TargetSubtargetInfo &STI) const {
01424   const InstrItineraryData *II = STI.getInstrItineraryData();
01425   return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
01426 }
01427 
01428 
01429 // Inspired by this pair:
01430 //  %R13<def> = L2_loadri_io %R29, 136; mem:LD4[FixedStack0]
01431 //  S2_storeri_io %R29, 132, %R1<kill>; flags:  mem:ST4[FixedStack1]
01432 // Currently AA considers the addresses in these instructions to be aliasing.
01433 bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
01434       MachineInstr *MIb, AliasAnalysis *AA) const {
01435   int OffsetA = 0, OffsetB = 0;
01436   unsigned SizeA = 0, SizeB = 0;
01437 
01438   if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects() ||
01439       MIa->hasOrderedMemoryRef() || MIa->hasOrderedMemoryRef())
01440     return false;
01441 
01442   // Instructions that are pure loads, not loads and stores like memops are not
01443   // dependent.
01444   if (MIa->mayLoad() && !isMemOp(MIa) && MIb->mayLoad() && !isMemOp(MIb))
01445     return true;
01446 
01447   // Get base, offset, and access size in MIa.
01448   unsigned BaseRegA = getBaseAndOffset(MIa, OffsetA, SizeA);
01449   if (!BaseRegA || !SizeA)
01450     return false;
01451 
01452   // Get base, offset, and access size in MIb.
01453   unsigned BaseRegB = getBaseAndOffset(MIb, OffsetB, SizeB);
01454   if (!BaseRegB || !SizeB)
01455     return false;
01456 
01457   if (BaseRegA != BaseRegB)
01458     return false;
01459 
01460   // This is a mem access with the same base register and known offsets from it.
01461   // Reason about it.
01462   if (OffsetA > OffsetB) {
01463     uint64_t offDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
01464     return (SizeB <= offDiff);
01465   } else if (OffsetA < OffsetB) {
01466     uint64_t offDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
01467     return (SizeA <= offDiff);
01468   }
01469 
01470   return false;
01471 }
01472 
01473 
01474 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
01475   MachineRegisterInfo &MRI = MF->getRegInfo();
01476   const TargetRegisterClass *TRC;
01477   if (VT == MVT::i1) {
01478     TRC = &Hexagon::PredRegsRegClass;
01479   } else if (VT == MVT::i32 || VT == MVT::f32) {
01480     TRC = &Hexagon::IntRegsRegClass;
01481   } else if (VT == MVT::i64 || VT == MVT::f64) {
01482     TRC = &Hexagon::DoubleRegsRegClass;
01483   } else {
01484     llvm_unreachable("Cannot handle this register class");
01485   }
01486 
01487   unsigned NewReg = MRI.createVirtualRegister(TRC);
01488   return NewReg;
01489 }
01490 
01491 
01492 bool HexagonInstrInfo::isAbsoluteSet(const MachineInstr* MI) const {
01493   return (getAddrMode(MI) == HexagonII::AbsoluteSet);
01494 }
01495 
01496 
01497 bool HexagonInstrInfo::isAccumulator(const MachineInstr *MI) const {
01498   const uint64_t F = MI->getDesc().TSFlags;
01499   return((F >> HexagonII::AccumulatorPos) & HexagonII::AccumulatorMask);
01500 }
01501 
01502 
01503 bool HexagonInstrInfo::isComplex(const MachineInstr *MI) const {
01504   const MachineFunction *MF = MI->getParent()->getParent();
01505   const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
01506   const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
01507 
01508   if (!(isTC1(MI))
01509       && !(QII->isTC2Early(MI))
01510       && !(MI->getDesc().mayLoad())
01511       && !(MI->getDesc().mayStore())
01512       && (MI->getDesc().getOpcode() != Hexagon::S2_allocframe)
01513       && (MI->getDesc().getOpcode() != Hexagon::L2_deallocframe)
01514       && !(QII->isMemOp(MI))
01515       && !(MI->isBranch())
01516       && !(MI->isReturn())
01517       && !MI->isCall())
01518     return true;
01519 
01520   return false;
01521 }
01522 
01523 
01524 // Return true if the instruction is a compund branch instruction.
01525 bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr *MI) const {
01526   return (getType(MI) == HexagonII::TypeCOMPOUND && MI->isBranch());
01527 }
01528 
01529 
01530 bool HexagonInstrInfo::isCondInst(const MachineInstr *MI) const {
01531   return (MI->isBranch() && isPredicated(MI)) ||
01532          isConditionalTransfer(MI) ||
01533          isConditionalALU32(MI)    ||
01534          isConditionalLoad(MI)     ||
01535          // Predicated stores which don't have a .new on any operands.
01536          (MI->mayStore() && isPredicated(MI) && !isNewValueStore(MI) &&
01537           !isPredicatedNew(MI));
01538 }
01539 
01540 
01541 bool HexagonInstrInfo::isConditionalALU32(const MachineInstr* MI) const {
01542   switch (MI->getOpcode()) {
01543     case Hexagon::A2_paddf:
01544     case Hexagon::A2_paddfnew:
01545     case Hexagon::A2_paddif:
01546     case Hexagon::A2_paddifnew:
01547     case Hexagon::A2_paddit:
01548     case Hexagon::A2_padditnew:
01549     case Hexagon::A2_paddt:
01550     case Hexagon::A2_paddtnew:
01551     case Hexagon::A2_pandf:
01552     case Hexagon::A2_pandfnew:
01553     case Hexagon::A2_pandt:
01554     case Hexagon::A2_pandtnew:
01555     case Hexagon::A2_porf:
01556     case Hexagon::A2_porfnew:
01557     case Hexagon::A2_port:
01558     case Hexagon::A2_portnew:
01559     case Hexagon::A2_psubf:
01560     case Hexagon::A2_psubfnew:
01561     case Hexagon::A2_psubt:
01562     case Hexagon::A2_psubtnew:
01563     case Hexagon::A2_pxorf:
01564     case Hexagon::A2_pxorfnew:
01565     case Hexagon::A2_pxort:
01566     case Hexagon::A2_pxortnew:
01567     case Hexagon::A4_paslhf:
01568     case Hexagon::A4_paslhfnew:
01569     case Hexagon::A4_paslht:
01570     case Hexagon::A4_paslhtnew:
01571     case Hexagon::A4_pasrhf:
01572     case Hexagon::A4_pasrhfnew:
01573     case Hexagon::A4_pasrht:
01574     case Hexagon::A4_pasrhtnew:
01575     case Hexagon::A4_psxtbf:
01576     case Hexagon::A4_psxtbfnew:
01577     case Hexagon::A4_psxtbt:
01578     case Hexagon::A4_psxtbtnew:
01579     case Hexagon::A4_psxthf:
01580     case Hexagon::A4_psxthfnew:
01581     case Hexagon::A4_psxtht:
01582     case Hexagon::A4_psxthtnew:
01583     case Hexagon::A4_pzxtbf:
01584     case Hexagon::A4_pzxtbfnew:
01585     case Hexagon::A4_pzxtbt:
01586     case Hexagon::A4_pzxtbtnew:
01587     case Hexagon::A4_pzxthf:
01588     case Hexagon::A4_pzxthfnew:
01589     case Hexagon::A4_pzxtht:
01590     case Hexagon::A4_pzxthtnew:
01591     case Hexagon::C2_ccombinewf:
01592     case Hexagon::C2_ccombinewt:
01593       return true;
01594   }
01595   return false;
01596 }
01597 
01598 
01599 // FIXME - Function name and it's functionality don't match.
01600 // It should be renamed to hasPredNewOpcode()
01601 bool HexagonInstrInfo::isConditionalLoad(const MachineInstr* MI) const {
01602   if (!MI->getDesc().mayLoad() || !isPredicated(MI))
01603     return false;
01604 
01605   int PNewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
01606   // Instruction with valid predicated-new opcode can be promoted to .new.
01607   return PNewOpcode >= 0;
01608 }
01609 
01610 
01611 // Returns true if an instruction is a conditional store.
01612 //
01613 // Note: It doesn't include conditional new-value stores as they can't be
01614 // converted to .new predicate.
01615 bool HexagonInstrInfo::isConditionalStore(const MachineInstr* MI) const {
01616   switch (MI->getOpcode()) {
01617     default: return false;
01618     case Hexagon::S4_storeirbt_io:
01619     case Hexagon::S4_storeirbf_io:
01620     case Hexagon::S4_pstorerbt_rr:
01621     case Hexagon::S4_pstorerbf_rr:
01622     case Hexagon::S2_pstorerbt_io:
01623     case Hexagon::S2_pstorerbf_io:
01624     case Hexagon::S2_pstorerbt_pi:
01625     case Hexagon::S2_pstorerbf_pi:
01626     case Hexagon::S2_pstorerdt_io:
01627     case Hexagon::S2_pstorerdf_io:
01628     case Hexagon::S4_pstorerdt_rr:
01629     case Hexagon::S4_pstorerdf_rr:
01630     case Hexagon::S2_pstorerdt_pi:
01631     case Hexagon::S2_pstorerdf_pi:
01632     case Hexagon::S2_pstorerht_io:
01633     case Hexagon::S2_pstorerhf_io:
01634     case Hexagon::S4_storeirht_io:
01635     case Hexagon::S4_storeirhf_io:
01636     case Hexagon::S4_pstorerht_rr:
01637     case Hexagon::S4_pstorerhf_rr:
01638     case Hexagon::S2_pstorerht_pi:
01639     case Hexagon::S2_pstorerhf_pi:
01640     case Hexagon::S2_pstorerit_io:
01641     case Hexagon::S2_pstorerif_io:
01642     case Hexagon::S4_storeirit_io:
01643     case Hexagon::S4_storeirif_io:
01644     case Hexagon::S4_pstorerit_rr:
01645     case Hexagon::S4_pstorerif_rr:
01646     case Hexagon::S2_pstorerit_pi:
01647     case Hexagon::S2_pstorerif_pi:
01648 
01649     // V4 global address store before promoting to dot new.
01650     case Hexagon::S4_pstorerdt_abs:
01651     case Hexagon::S4_pstorerdf_abs:
01652     case Hexagon::S4_pstorerbt_abs:
01653     case Hexagon::S4_pstorerbf_abs:
01654     case Hexagon::S4_pstorerht_abs:
01655     case Hexagon::S4_pstorerhf_abs:
01656     case Hexagon::S4_pstorerit_abs:
01657     case Hexagon::S4_pstorerif_abs:
01658       return true;
01659 
01660     // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
01661     // from the "Conditional Store" list. Because a predicated new value store
01662     // would NOT be promoted to a double dot new store.
01663     // This function returns yes for those stores that are predicated but not
01664     // yet promoted to predicate dot new instructions.
01665   }
01666 }
01667 
01668 
01669 bool HexagonInstrInfo::isConditionalTransfer(const MachineInstr *MI) const {
01670   switch (MI->getOpcode()) {
01671     case Hexagon::A2_tfrt:
01672     case Hexagon::A2_tfrf:
01673     case Hexagon::C2_cmoveit:
01674     case Hexagon::C2_cmoveif:
01675     case Hexagon::A2_tfrtnew:
01676     case Hexagon::A2_tfrfnew:
01677     case Hexagon::C2_cmovenewit:
01678     case Hexagon::C2_cmovenewif:
01679     case Hexagon::A2_tfrpt:
01680     case Hexagon::A2_tfrpf:
01681       return true;
01682 
01683     default:
01684       return false;
01685   }
01686   return false;
01687 }
01688 
01689 
01690 // TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
01691 // isFPImm and later getFPImm as well.
01692 bool HexagonInstrInfo::isConstExtended(const MachineInstr *MI) const {
01693   const uint64_t F = MI->getDesc().TSFlags;
01694   unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
01695   if (isExtended) // Instruction must be extended.
01696     return true;
01697 
01698   unsigned isExtendable =
01699     (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
01700   if (!isExtendable)
01701     return false;
01702 
01703   if (MI->isCall())
01704     return false;
01705 
01706   short ExtOpNum = getCExtOpNum(MI);
01707   const MachineOperand &MO = MI->getOperand(ExtOpNum);
01708   // Use MO operand flags to determine if MO
01709   // has the HMOTF_ConstExtended flag set.
01710   if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
01711     return true;
01712   // If this is a Machine BB address we are talking about, and it is
01713   // not marked as extended, say so.
01714   if (MO.isMBB())
01715     return false;
01716 
01717   // We could be using an instruction with an extendable immediate and shoehorn
01718   // a global address into it. If it is a global address it will be constant
01719   // extended. We do this for COMBINE.
01720   // We currently only handle isGlobal() because it is the only kind of
01721   // object we are going to end up with here for now.
01722   // In the future we probably should add isSymbol(), etc.
01723   if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
01724       MO.isJTI() || MO.isCPI())
01725     return true;
01726 
01727   // If the extendable operand is not 'Immediate' type, the instruction should
01728   // have 'isExtended' flag set.
01729   assert(MO.isImm() && "Extendable operand must be Immediate type");
01730 
01731   int MinValue = getMinValue(MI);
01732   int MaxValue = getMaxValue(MI);
01733   int ImmValue = MO.getImm();
01734 
01735   return (ImmValue < MinValue || ImmValue > MaxValue);
01736 }
01737 
01738 
01739 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
01740   switch (MI->getOpcode()) {
01741   case Hexagon::L4_return :
01742   case Hexagon::L4_return_t :
01743   case Hexagon::L4_return_f :
01744   case Hexagon::L4_return_tnew_pnt :
01745   case Hexagon::L4_return_fnew_pnt :
01746   case Hexagon::L4_return_tnew_pt :
01747   case Hexagon::L4_return_fnew_pt :
01748    return true;
01749   }
01750   return false;
01751 }
01752 
01753 
01754 // Return true when ConsMI uses a register defined by ProdMI.
01755 bool HexagonInstrInfo::isDependent(const MachineInstr *ProdMI,
01756       const MachineInstr *ConsMI) const {
01757   const MCInstrDesc &ProdMCID = ProdMI->getDesc();
01758   if (!ProdMCID.getNumDefs())
01759     return false;
01760 
01761   auto &HRI = getRegisterInfo();
01762 
01763   SmallVector<unsigned, 4> DefsA;
01764   SmallVector<unsigned, 4> DefsB;
01765   SmallVector<unsigned, 8> UsesA;
01766   SmallVector<unsigned, 8> UsesB;
01767 
01768   parseOperands(ProdMI, DefsA, UsesA);
01769   parseOperands(ConsMI, DefsB, UsesB);
01770 
01771   for (auto &RegA : DefsA)
01772     for (auto &RegB : UsesB) {
01773       // True data dependency.
01774       if (RegA == RegB)
01775         return true;
01776 
01777       if (Hexagon::DoubleRegsRegClass.contains(RegA))
01778         for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
01779           if (RegB == *SubRegs)
01780             return true;
01781 
01782       if (Hexagon::DoubleRegsRegClass.contains(RegB))
01783         for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
01784           if (RegA == *SubRegs)
01785             return true;
01786     }
01787 
01788   return false;
01789 }
01790 
01791 
01792 // Returns true if the instruction is alread a .cur.
01793 bool HexagonInstrInfo::isDotCurInst(const MachineInstr* MI) const {
01794   switch (MI->getOpcode()) {
01795   case Hexagon::V6_vL32b_cur_pi:
01796   case Hexagon::V6_vL32b_cur_ai:
01797   case Hexagon::V6_vL32b_cur_pi_128B:
01798   case Hexagon::V6_vL32b_cur_ai_128B:
01799     return true;
01800   }
01801   return false;
01802 }
01803 
01804 
01805 // Returns true, if any one of the operands is a dot new
01806 // insn, whether it is predicated dot new or register dot new.
01807 bool HexagonInstrInfo::isDotNewInst(const MachineInstr* MI) const {
01808   if (isNewValueInst(MI) ||
01809      (isPredicated(MI) && isPredicatedNew(MI)))
01810     return true;
01811 
01812   return false;
01813 }
01814 
01815 
01816 /// Symmetrical. See if these two instructions are fit for duplex pair.
01817 bool HexagonInstrInfo::isDuplexPair(const MachineInstr *MIa,
01818       const MachineInstr *MIb) const {
01819   HexagonII::SubInstructionGroup MIaG = getDuplexCandidateGroup(MIa);
01820   HexagonII::SubInstructionGroup MIbG = getDuplexCandidateGroup(MIb);
01821   return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
01822 }
01823 
01824 
01825 bool HexagonInstrInfo::isEarlySourceInstr(const MachineInstr *MI) const {
01826   if (!MI)
01827     return false;
01828 
01829   if (MI->mayLoad() || MI->mayStore() || MI->isCompare())
01830     return true;
01831 
01832   // Multiply
01833   unsigned SchedClass = MI->getDesc().getSchedClass();
01834   if (SchedClass == Hexagon::Sched::M_tc_3or4x_SLOT23)
01835     return true;
01836   return false;
01837 }
01838 
01839 
01840 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
01841   return (Opcode == Hexagon::ENDLOOP0 ||
01842           Opcode == Hexagon::ENDLOOP1);
01843 }
01844 
01845 
01846 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
01847   switch(OpType) {
01848   case MachineOperand::MO_MachineBasicBlock:
01849   case MachineOperand::MO_GlobalAddress:
01850   case MachineOperand::MO_ExternalSymbol:
01851   case MachineOperand::MO_JumpTableIndex:
01852   case MachineOperand::MO_ConstantPoolIndex:
01853   case MachineOperand::MO_BlockAddress:
01854     return true;
01855   default:
01856     return false;
01857   }
01858 }
01859 
01860 
01861 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
01862   const MCInstrDesc &MID = MI->getDesc();
01863   const uint64_t F = MID.TSFlags;
01864   if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
01865     return true;
01866 
01867   // TODO: This is largely obsolete now. Will need to be removed
01868   // in consecutive patches.
01869   switch(MI->getOpcode()) {
01870     // TFR_FI Remains a special case.
01871     case Hexagon::TFR_FI:
01872       return true;
01873     default:
01874       return false;
01875   }
01876   return  false;
01877 }
01878 
01879 
01880 // This returns true in two cases:
01881 // - The OP code itself indicates that this is an extended instruction.
01882 // - One of MOs has been marked with HMOTF_ConstExtended flag.
01883 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
01884   // First check if this is permanently extended op code.
01885   const uint64_t F = MI->getDesc().TSFlags;
01886   if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
01887     return true;
01888   // Use MO operand flags to determine if one of MI's operands
01889   // has HMOTF_ConstExtended flag set.
01890   for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
01891        E = MI->operands_end(); I != E; ++I) {
01892     if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
01893       return true;
01894   }
01895   return  false;
01896 }
01897 
01898 
01899 bool HexagonInstrInfo::isFloat(const MachineInstr *MI) const {
01900   unsigned Opcode = MI->getOpcode();
01901   const uint64_t F = get(Opcode).TSFlags;
01902   return (F >> HexagonII::FPPos) & HexagonII::FPMask;
01903 }
01904 
01905 
01906 // No V60 HVX VMEM with A_INDIRECT.
01907 bool HexagonInstrInfo::isHVXMemWithAIndirect(const MachineInstr *I,
01908       const MachineInstr *J) const {
01909   if (!isV60VectorInstruction(I))
01910     return false;
01911   if (!I->mayLoad() && !I->mayStore())
01912     return false;
01913   return J->isIndirectBranch() || isIndirectCall(J) || isIndirectL4Return(J);
01914 }
01915 
01916 
01917 bool HexagonInstrInfo::isIndirectCall(const MachineInstr *MI) const {
01918   switch (MI->getOpcode()) {
01919   case Hexagon::J2_callr :
01920   case Hexagon::J2_callrf :
01921   case Hexagon::J2_callrt :
01922     return true;
01923   }
01924   return false;
01925 }
01926 
01927 
01928 bool HexagonInstrInfo::isIndirectL4Return(const MachineInstr *MI) const {
01929   switch (MI->getOpcode()) {
01930   case Hexagon::L4_return :
01931   case Hexagon::L4_return_t :
01932   case Hexagon::L4_return_f :
01933   case Hexagon::L4_return_fnew_pnt :
01934   case Hexagon::L4_return_fnew_pt :
01935   case Hexagon::L4_return_tnew_pnt :
01936   case Hexagon::L4_return_tnew_pt :
01937     return true;
01938   }
01939   return false;
01940 }
01941 
01942 
01943 bool HexagonInstrInfo::isJumpR(const MachineInstr *MI) const {
01944   switch (MI->getOpcode()) {
01945   case Hexagon::J2_jumpr :
01946   case Hexagon::J2_jumprt :
01947   case Hexagon::J2_jumprf :
01948   case Hexagon::J2_jumprtnewpt :
01949   case Hexagon::J2_jumprfnewpt  :
01950   case Hexagon::J2_jumprtnew :
01951   case Hexagon::J2_jumprfnew :
01952     return true;
01953   }
01954   return false;
01955 }
01956 
01957 
01958 // Return true if a given MI can accomodate given offset.
01959 // Use abs estimate as oppose to the exact number.
01960 // TODO: This will need to be changed to use MC level
01961 // definition of instruction extendable field size.
01962 bool HexagonInstrInfo::isJumpWithinBranchRange(const MachineInstr *MI,
01963       unsigned offset) const {
01964   // This selection of jump instructions matches to that what
01965   // AnalyzeBranch can parse, plus NVJ.
01966   if (isNewValueJump(MI)) // r9:2
01967     return isInt<11>(offset);
01968 
01969   switch (MI->getOpcode()) {
01970   // Still missing Jump to address condition on register value.
01971   default:
01972     return false;
01973   case Hexagon::J2_jump: // bits<24> dst; // r22:2
01974   case Hexagon::J2_call:
01975   case Hexagon::CALLv3nr:
01976     return isInt<24>(offset);
01977   case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
01978   case Hexagon::J2_jumpf:
01979   case Hexagon::J2_jumptnew:
01980   case Hexagon::J2_jumptnewpt:
01981   case Hexagon::J2_jumpfnew:
01982   case Hexagon::J2_jumpfnewpt:
01983   case Hexagon::J2_callt:
01984   case Hexagon::J2_callf:
01985     return isInt<17>(offset);
01986   case Hexagon::J2_loop0i:
01987   case Hexagon::J2_loop0iext:
01988   case Hexagon::J2_loop0r:
01989   case Hexagon::J2_loop0rext:
01990   case Hexagon::J2_loop1i:
01991   case Hexagon::J2_loop1iext:
01992   case Hexagon::J2_loop1r:
01993   case Hexagon::J2_loop1rext:
01994     return isInt<9>(offset);
01995   // TODO: Add all the compound branches here. Can we do this in Relation model?
01996   case Hexagon::J4_cmpeqi_tp0_jump_nt:
01997   case Hexagon::J4_cmpeqi_tp1_jump_nt:
01998     return isInt<11>(offset);
01999   }
02000 }
02001 
02002 
02003 bool HexagonInstrInfo::isLateInstrFeedsEarlyInstr(const MachineInstr *LRMI,
02004       const MachineInstr *ESMI) const {
02005   if (!LRMI || !ESMI)
02006     return false;
02007 
02008   bool isLate = isLateResultInstr(LRMI);
02009   bool isEarly = isEarlySourceInstr(ESMI);
02010 
02011   DEBUG(dbgs() << "V60" <<  (isLate ? "-LR  " : " --  "));
02012   DEBUG(LRMI->dump());
02013   DEBUG(dbgs() << "V60" <<  (isEarly ? "-ES  " : " --  "));
02014   DEBUG(ESMI->dump());
02015 
02016   if (isLate && isEarly) {
02017     DEBUG(dbgs() << "++Is Late Result feeding Early Source\n");
02018     return true;
02019   }
02020 
02021   return false;
02022 }
02023 
02024 
02025 bool HexagonInstrInfo::isLateResultInstr(const MachineInstr *MI) const {
02026   if (!MI)
02027     return false;
02028 
02029   switch (MI->getOpcode()) {
02030   case TargetOpcode::EXTRACT_SUBREG:
02031   case TargetOpcode::INSERT_SUBREG:
02032   case TargetOpcode::SUBREG_TO_REG:
02033   case TargetOpcode::REG_SEQUENCE:
02034   case TargetOpcode::IMPLICIT_DEF:
02035   case TargetOpcode::COPY:
02036   case TargetOpcode::INLINEASM:
02037   case TargetOpcode::PHI:
02038     return false;
02039   default:
02040     break;
02041   }
02042 
02043   unsigned SchedClass = MI->getDesc().getSchedClass();
02044 
02045   switch (SchedClass) {
02046   case Hexagon::Sched::ALU32_2op_tc_1_SLOT0123:
02047   case Hexagon::Sched::ALU32_3op_tc_1_SLOT0123:
02048   case Hexagon::Sched::ALU32_ADDI_tc_1_SLOT0123:
02049   case Hexagon::Sched::ALU64_tc_1_SLOT23:
02050   case Hexagon::Sched::EXTENDER_tc_1_SLOT0123:
02051   case Hexagon::Sched::S_2op_tc_1_SLOT23:
02052   case Hexagon::Sched::S_3op_tc_1_SLOT23:
02053   case Hexagon::Sched::V2LDST_tc_ld_SLOT01:
02054   case Hexagon::Sched::V2LDST_tc_st_SLOT0:
02055   case Hexagon::Sched::V2LDST_tc_st_SLOT01:
02056   case Hexagon::Sched::V4LDST_tc_ld_SLOT01:
02057   case Hexagon::Sched::V4LDST_tc_st_SLOT0:
02058   case Hexagon::Sched::V4LDST_tc_st_SLOT01:
02059     return false;
02060   }
02061   return true;
02062 }
02063 
02064 
02065 bool HexagonInstrInfo::isLateSourceInstr(const MachineInstr *MI) const {
02066   if (!MI)
02067     return false;
02068 
02069   // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
02070   // resource, but all operands can be received late like an ALU instruction.
02071   return MI->getDesc().getSchedClass() == Hexagon::Sched::CVI_VX_LATE;
02072 }
02073 
02074 
02075 bool HexagonInstrInfo::isLoopN(const MachineInstr *MI) const {
02076   unsigned Opcode = MI->getOpcode();
02077   return Opcode == Hexagon::J2_loop0i    ||
02078          Opcode == Hexagon::J2_loop0r    ||
02079          Opcode == Hexagon::J2_loop0iext ||
02080          Opcode == Hexagon::J2_loop0rext ||
02081          Opcode == Hexagon::J2_loop1i    ||
02082          Opcode == Hexagon::J2_loop1r    ||
02083          Opcode == Hexagon::J2_loop1iext ||
02084          Opcode == Hexagon::J2_loop1rext;
02085 }
02086 
02087 
02088 bool HexagonInstrInfo::isMemOp(const MachineInstr *MI) const {
02089   switch (MI->getOpcode()) {
02090     default: return false;
02091     case Hexagon::L4_iadd_memopw_io :
02092     case Hexagon::L4_isub_memopw_io :
02093     case Hexagon::L4_add_memopw_io :
02094     case Hexagon::L4_sub_memopw_io :
02095     case Hexagon::L4_and_memopw_io :
02096     case Hexagon::L4_or_memopw_io :
02097     case Hexagon::L4_iadd_memoph_io :
02098     case Hexagon::L4_isub_memoph_io :
02099     case Hexagon::L4_add_memoph_io :
02100     case Hexagon::L4_sub_memoph_io :
02101     case Hexagon::L4_and_memoph_io :
02102     case Hexagon::L4_or_memoph_io :
02103     case Hexagon::L4_iadd_memopb_io :
02104     case Hexagon::L4_isub_memopb_io :
02105     case Hexagon::L4_add_memopb_io :
02106     case Hexagon::L4_sub_memopb_io :
02107     case Hexagon::L4_and_memopb_io :
02108     case Hexagon::L4_or_memopb_io :
02109     case Hexagon::L4_ior_memopb_io:
02110     case Hexagon::L4_ior_memoph_io:
02111     case Hexagon::L4_ior_memopw_io:
02112     case Hexagon::L4_iand_memopb_io:
02113     case Hexagon::L4_iand_memoph_io:
02114     case Hexagon::L4_iand_memopw_io:
02115     return true;
02116   }
02117   return false;
02118 }
02119 
02120 
02121 bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
02122   const uint64_t F = MI->getDesc().TSFlags;
02123   return (F >> HexagonII::NewValuePos) & HexagonII::NewValueMask;
02124 }
02125 
02126 
02127 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
02128   const uint64_t F = get(Opcode).TSFlags;
02129   return (F >> HexagonII::NewValuePos) & HexagonII::NewValueMask;
02130 }
02131 
02132 
02133 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
02134   return isNewValueJump(MI) || isNewValueStore(MI);
02135 }
02136 
02137 
02138 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
02139   return isNewValue(MI) && MI->isBranch();
02140 }
02141 
02142 
02143 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
02144   return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
02145 }
02146 
02147 
02148 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
02149   const uint64_t F = MI->getDesc().TSFlags;
02150   return (F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask;
02151 }
02152 
02153 
02154 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
02155   const uint64_t F = get(Opcode).TSFlags;
02156   return (F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask;
02157 }
02158 
02159 
02160 // Returns true if a particular operand is extendable for an instruction.
02161 bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
02162     unsigned OperandNum) const {
02163   const uint64_t F = MI->getDesc().TSFlags;
02164   return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
02165           == OperandNum;
02166 }
02167 
02168 
02169 bool HexagonInstrInfo::isPostIncrement(const MachineInstr* MI) const {
02170   return getAddrMode(MI) == HexagonII::PostInc;
02171 }
02172 
02173 
02174 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
02175   const uint64_t F = MI->getDesc().TSFlags;
02176   assert(isPredicated(MI));
02177   return (F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask;
02178 }
02179 
02180 
02181 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
02182   const uint64_t F = get(Opcode).TSFlags;
02183   assert(isPredicated(Opcode));
02184   return (F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask;
02185 }
02186 
02187 
02188 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
02189   const uint64_t F = MI->getDesc().TSFlags;
02190   return !((F >> HexagonII::PredicatedFalsePos) &
02191            HexagonII::PredicatedFalseMask);
02192 }
02193 
02194 
02195 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
02196   const uint64_t F = get(Opcode).TSFlags;
02197   // Make sure that the instruction is predicated.
02198   assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
02199   return !((F >> HexagonII::PredicatedFalsePos) &
02200            HexagonII::PredicatedFalseMask);
02201 }
02202 
02203 
02204 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
02205   const uint64_t F = get(Opcode).TSFlags;
02206   return (F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask;
02207 }
02208 
02209 
02210 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
02211   const uint64_t F = get(Opcode).TSFlags;
02212   return ~(F >> HexagonII::PredicateLatePos) & HexagonII::PredicateLateMask;
02213 }
02214 
02215 
02216 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
02217   const uint64_t F = get(Opcode).TSFlags;
02218   assert(get(Opcode).isBranch() &&
02219          (isPredicatedNew(Opcode) || isNewValue(Opcode)));
02220   return (F >> HexagonII::TakenPos) & HexagonII::TakenMask;
02221 }
02222 
02223 
02224 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
02225   return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
02226          MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT;
02227 }
02228 
02229 
02230 bool HexagonInstrInfo::isSolo(const MachineInstr* MI) const {
02231   const uint64_t F = MI->getDesc().TSFlags;
02232   return (F >> HexagonII::SoloPos) & HexagonII::SoloMask;
02233 }
02234 
02235 
02236 bool HexagonInstrInfo::isSpillPredRegOp(const MachineInstr *MI) const {
02237   switch (MI->getOpcode()) {
02238   case Hexagon::STriw_pred :
02239   case Hexagon::LDriw_pred :
02240     return true;
02241   default:
02242     return false;
02243   }
02244 }
02245 
02246 
02247 // Returns true when SU has a timing class TC1.
02248 bool HexagonInstrInfo::isTC1(const MachineInstr *MI) const {
02249   unsigned SchedClass = MI->getDesc().getSchedClass();
02250   switch (SchedClass) {
02251   case Hexagon::Sched::ALU32_2op_tc_1_SLOT0123:
02252   case Hexagon::Sched::ALU32_3op_tc_1_SLOT0123:
02253   case Hexagon::Sched::ALU32_ADDI_tc_1_SLOT0123:
02254   case Hexagon::Sched::ALU64_tc_1_SLOT23:
02255   case Hexagon::Sched::EXTENDER_tc_1_SLOT0123:
02256   //case Hexagon::Sched::M_tc_1_SLOT23:
02257   case Hexagon::Sched::S_2op_tc_1_SLOT23:
02258   case Hexagon::Sched::S_3op_tc_1_SLOT23:
02259     return true;
02260 
02261   default:
02262     return false;
02263   }
02264 }
02265 
02266 
02267 bool HexagonInstrInfo::isTC2(const MachineInstr *MI) const {
02268   unsigned SchedClass = MI->getDesc().getSchedClass();
02269   switch (SchedClass) {
02270   case Hexagon::Sched::ALU32_3op_tc_2_SLOT0123:
02271   case Hexagon::Sched::ALU64_tc_2_SLOT23:
02272   case Hexagon::Sched::CR_tc_2_SLOT3:
02273   case Hexagon::Sched::M_tc_2_SLOT23:
02274   case Hexagon::Sched::S_2op_tc_2_SLOT23:
02275   case Hexagon::Sched::S_3op_tc_2_SLOT23:
02276     return true;
02277 
02278   default:
02279     return false;
02280   }
02281 }
02282 
02283 
02284 bool HexagonInstrInfo::isTC2Early(const MachineInstr *MI) const {
02285   unsigned SchedClass = MI->getDesc().getSchedClass();
02286   switch (SchedClass) {
02287   case Hexagon::Sched::ALU32_2op_tc_2early_SLOT0123:
02288   case Hexagon::Sched::ALU32_3op_tc_2early_SLOT0123:
02289   case Hexagon::Sched::ALU64_tc_2early_SLOT23:
02290   case Hexagon::Sched::CR_tc_2early_SLOT23:
02291   case Hexagon::Sched::CR_tc_2early_SLOT3:
02292   case Hexagon::Sched::J_tc_2early_SLOT0123:
02293   case Hexagon::Sched::J_tc_2early_SLOT2:
02294   case Hexagon::Sched::J_tc_2early_SLOT23:
02295   case Hexagon::Sched::S_2op_tc_2early_SLOT23:
02296   case Hexagon::Sched::S_3op_tc_2early_SLOT23:
02297     return true;
02298 
02299   default:
02300     return false;
02301   }
02302 }
02303 
02304 
02305 bool HexagonInstrInfo::isTC4x(const MachineInstr *MI) const {
02306   if (!MI)
02307     return false;
02308 
02309   unsigned SchedClass = MI->getDesc().getSchedClass();
02310   return SchedClass == Hexagon::Sched::M_tc_3or4x_SLOT23;
02311 }
02312 
02313 
02314 bool HexagonInstrInfo::isV60VectorInstruction(const MachineInstr *MI) const {
02315   if (!MI)
02316     return false;
02317 
02318   const uint64_t V = getType(MI);
02319   return HexagonII::TypeCVI_FIRST <= V && V <= HexagonII::TypeCVI_LAST;
02320 }
02321 
02322 
02323 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
02324 //
02325 bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, const int Offset) const {
02326   if (VT == MVT::v16i32 || VT == MVT::v8i64 ||
02327       VT == MVT::v32i16 || VT == MVT::v64i8) {
02328       return (Offset >= Hexagon_MEMV_AUTOINC_MIN &&
02329               Offset <= Hexagon_MEMV_AUTOINC_MAX &&
02330               (Offset & 0x3f) == 0);
02331   }
02332   // 128B
02333   if (VT == MVT::v32i32 || VT == MVT::v16i64 ||
02334       VT == MVT::v64i16 || VT == MVT::v128i8) {
02335       return (Offset >= Hexagon_MEMV_AUTOINC_MIN_128B &&
02336               Offset <= Hexagon_MEMV_AUTOINC_MAX_128B &&
02337               (Offset & 0x7f) == 0);
02338   }
02339   if (VT == MVT::i64) {
02340       return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
02341               Offset <= Hexagon_MEMD_AUTOINC_MAX &&
02342               (Offset & 0x7) == 0);
02343   }
02344   if (VT == MVT::i32) {
02345       return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
02346               Offset <= Hexagon_MEMW_AUTOINC_MAX &&
02347               (Offset & 0x3) == 0);
02348   }
02349   if (VT == MVT::i16) {
02350       return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
02351               Offset <= Hexagon_MEMH_AUTOINC_MAX &&
02352               (Offset & 0x1) == 0);
02353   }
02354   if (VT == MVT::i8) {
02355       return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
02356               Offset <= Hexagon_MEMB_AUTOINC_MAX);
02357   }
02358   llvm_unreachable("Not an auto-inc opc!");
02359 }
02360 
02361 
02362 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
02363       bool Extend) const {
02364   // This function is to check whether the "Offset" is in the correct range of
02365   // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
02366   // inserted to calculate the final address. Due to this reason, the function
02367   // assumes that the "Offset" has correct alignment.
02368   // We used to assert if the offset was not properly aligned, however,
02369   // there are cases where a misaligned pointer recast can cause this
02370   // problem, and we need to allow for it. The front end warns of such
02371   // misaligns with respect to load size.
02372 
02373   switch (Opcode) {
02374   case Hexagon::STriq_pred_V6:
02375   case Hexagon::STriq_pred_vec_V6:
02376   case Hexagon::STriv_pseudo_V6:
02377   case Hexagon::STrivv_pseudo_V6:
02378   case Hexagon::LDriq_pred_V6:
02379   case Hexagon::LDriq_pred_vec_V6:
02380   case Hexagon::LDriv_pseudo_V6:
02381   case Hexagon::LDrivv_pseudo_V6:
02382   case Hexagon::LDrivv_indexed:
02383   case Hexagon::STrivv_indexed:
02384   case Hexagon::V6_vL32b_ai:
02385   case Hexagon::V6_vS32b_ai:
02386   case Hexagon::V6_vL32Ub_ai:
02387   case Hexagon::V6_vS32Ub_ai:
02388     return (Offset >= Hexagon_MEMV_OFFSET_MIN) &&
02389       (Offset <= Hexagon_MEMV_OFFSET_MAX);
02390 
02391   case Hexagon::STriq_pred_V6_128B:
02392   case Hexagon::STriq_pred_vec_V6_128B:
02393   case Hexagon::STriv_pseudo_V6_128B:
02394   case Hexagon::STrivv_pseudo_V6_128B:
02395   case Hexagon::LDriq_pred_V6_128B:
02396   case Hexagon::LDriq_pred_vec_V6_128B:
02397   case Hexagon::LDriv_pseudo_V6_128B:
02398   case Hexagon::LDrivv_pseudo_V6_128B:
02399   case Hexagon::LDrivv_indexed_128B:
02400   case Hexagon::STrivv_indexed_128B:
02401   case Hexagon::V6_vL32b_ai_128B:
02402   case Hexagon::V6_vS32b_ai_128B:
02403   case Hexagon::V6_vL32Ub_ai_128B:
02404   case Hexagon::V6_vS32Ub_ai_128B:
02405     return (Offset >= Hexagon_MEMV_OFFSET_MIN_128B) &&
02406       (Offset <= Hexagon_MEMV_OFFSET_MAX_128B);
02407 
02408   case Hexagon::J2_loop0i:
02409   case Hexagon::J2_loop1i:
02410     return isUInt<10>(Offset);
02411   }
02412 
02413   if (Extend)
02414     return true;
02415 
02416   switch (Opcode) {
02417   case Hexagon::L2_loadri_io:
02418   case Hexagon::S2_storeri_io:
02419     return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
02420       (Offset <= Hexagon_MEMW_OFFSET_MAX);
02421 
02422   case Hexagon::L2_loadrd_io:
02423   case Hexagon::S2_storerd_io:
02424     return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
02425       (Offset <= Hexagon_MEMD_OFFSET_MAX);
02426 
02427   case Hexagon::L2_loadrh_io:
02428   case Hexagon::L2_loadruh_io:
02429   case Hexagon::S2_storerh_io:
02430     return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
02431       (Offset <= Hexagon_MEMH_OFFSET_MAX);
02432 
02433   case Hexagon::L2_loadrb_io:
02434   case Hexagon::L2_loadrub_io:
02435   case Hexagon::S2_storerb_io:
02436     return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
02437       (Offset <= Hexagon_MEMB_OFFSET_MAX);
02438 
02439   case Hexagon::A2_addi:
02440     return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
02441       (Offset <= Hexagon_ADDI_OFFSET_MAX);
02442 
02443   case Hexagon::L4_iadd_memopw_io :
02444   case Hexagon::L4_isub_memopw_io :
02445   case Hexagon::L4_add_memopw_io :
02446   case Hexagon::L4_sub_memopw_io :
02447   case Hexagon::L4_and_memopw_io :
02448   case Hexagon::L4_or_memopw_io :
02449     return (0 <= Offset && Offset <= 255);
02450 
02451   case Hexagon::L4_iadd_memoph_io :
02452   case Hexagon::L4_isub_memoph_io :
02453   case Hexagon::L4_add_memoph_io :
02454   case Hexagon::L4_sub_memoph_io :
02455   case Hexagon::L4_and_memoph_io :
02456   case Hexagon::L4_or_memoph_io :
02457     return (0 <= Offset && Offset <= 127);
02458 
02459   case Hexagon::L4_iadd_memopb_io :
02460   case Hexagon::L4_isub_memopb_io :
02461   case Hexagon::L4_add_memopb_io :
02462   case Hexagon::L4_sub_memopb_io :
02463   case Hexagon::L4_and_memopb_io :
02464   case Hexagon::L4_or_memopb_io :
02465     return (0 <= Offset && Offset <= 63);
02466 
02467   // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
02468   // any size. Later pass knows how to handle it.
02469   case Hexagon::STriw_pred:
02470   case Hexagon::LDriw_pred:
02471   case Hexagon::STriw_mod:
02472   case Hexagon::LDriw_mod:
02473     return true;
02474 
02475   case Hexagon::TFR_FI:
02476   case Hexagon::TFR_FIA:
02477   case Hexagon::INLINEASM:
02478     return true;
02479 
02480   case Hexagon::L2_ploadrbt_io:
02481   case Hexagon::L2_ploadrbf_io:
02482   case Hexagon::L2_ploadrubt_io:
02483   case Hexagon::L2_ploadrubf_io:
02484   case Hexagon::S2_pstorerbt_io:
02485   case Hexagon::S2_pstorerbf_io:
02486   case Hexagon::S4_storeirb_io:
02487   case Hexagon::S4_storeirbt_io:
02488   case Hexagon::S4_storeirbf_io:
02489     return isUInt<6>(Offset);
02490 
02491   case Hexagon::L2_ploadrht_io:
02492   case Hexagon::L2_ploadrhf_io:
02493   case Hexagon::L2_ploadruht_io:
02494   case Hexagon::L2_ploadruhf_io:
02495   case Hexagon::S2_pstorerht_io:
02496   case Hexagon::S2_pstorerhf_io:
02497   case Hexagon::S4_storeirh_io:
02498   case Hexagon::S4_storeirht_io:
02499   case Hexagon::S4_storeirhf_io:
02500     return isShiftedUInt<6,1>(Offset);
02501 
02502   case Hexagon::L2_ploadrit_io:
02503   case Hexagon::L2_ploadrif_io:
02504   case Hexagon::S2_pstorerit_io:
02505   case Hexagon::S2_pstorerif_io:
02506   case Hexagon::S4_storeiri_io:
02507   case Hexagon::S4_storeirit_io:
02508   case Hexagon::S4_storeirif_io:
02509     return isShiftedUInt<6,2>(Offset);
02510 
02511   case Hexagon::L2_ploadrdt_io:
02512   case Hexagon::L2_ploadrdf_io:
02513   case Hexagon::S2_pstorerdt_io:
02514   case Hexagon::S2_pstorerdf_io:
02515     return isShiftedUInt<6,3>(Offset);
02516   } // switch
02517 
02518   llvm_unreachable("No offset range is defined for this opcode. "
02519                    "Please define it in the above switch statement!");
02520 }
02521 
02522 
02523 bool HexagonInstrInfo::isVecAcc(const MachineInstr *MI) const {
02524   return MI && isV60VectorInstruction(MI) && isAccumulator(MI);
02525 }
02526 
02527 
02528 bool HexagonInstrInfo::isVecALU(const MachineInstr *MI) const {
02529   if (!MI)
02530     return false;
02531   const uint64_t F = get(MI->getOpcode()).TSFlags;
02532   const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
02533   return
02534     V == HexagonII::TypeCVI_VA         ||
02535     V == HexagonII::TypeCVI_VA_DV;
02536 }
02537 
02538 
02539 bool HexagonInstrInfo::isVecUsableNextPacket(const MachineInstr *ProdMI,
02540       const MachineInstr *ConsMI) const {
02541   if (EnableACCForwarding && isVecAcc(ProdMI) && isVecAcc(ConsMI))
02542     return true;
02543 
02544   if (EnableALUForwarding && (isVecALU(ConsMI) || isLateSourceInstr(ConsMI)))
02545     return true;
02546 
02547   if (mayBeNewStore(ConsMI))
02548     return true;
02549 
02550   return false;
02551 }
02552 
02553 
02554 /// \brief Can these instructions execute at the same time in a bundle.
02555 bool HexagonInstrInfo::canExecuteInBundle(const MachineInstr *First,
02556       const MachineInstr *Second) const {
02557   if (DisableNVSchedule)
02558     return false;
02559   if (mayBeNewStore(Second)) {
02560     // Make sure the definition of the first instruction is the value being
02561     // stored.
02562     const MachineOperand &Stored =
02563       Second->getOperand(Second->getNumOperands() - 1);
02564     if (!Stored.isReg())
02565       return false;
02566     for (unsigned i = 0, e = First->getNumOperands(); i < e; ++i) {
02567       const MachineOperand &Op = First->getOperand(i);
02568       if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
02569         return true;
02570     }
02571   }
02572   return false;
02573 }
02574 
02575 
02576 bool HexagonInstrInfo::hasEHLabel(const MachineBasicBlock *B) const {
02577   for (auto &I : *B)
02578     if (I.isEHLabel())
02579       return true;
02580   return false;
02581 }
02582 
02583 
02584 // Returns true if an instruction can be converted into a non-extended
02585 // equivalent instruction.
02586 bool HexagonInstrInfo::hasNonExtEquivalent(const MachineInstr *MI) const {
02587   short NonExtOpcode;
02588   // Check if the instruction has a register form that uses register in place
02589   // of the extended operand, if so return that as the non-extended form.
02590   if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
02591     return true;
02592 
02593   if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
02594     // Check addressing mode and retrieve non-ext equivalent instruction.
02595 
02596     switch (getAddrMode(MI)) {
02597     case HexagonII::Absolute :
02598       // Load/store with absolute addressing mode can be converted into
02599       // base+offset mode.
02600       NonExtOpcode = Hexagon::getBaseWithImmOffset(MI->getOpcode());
02601       break;
02602     case HexagonII::BaseImmOffset :
02603       // Load/store with base+offset addressing mode can be converted into
02604       // base+register offset addressing mode. However left shift operand should
02605       // be set to 0.
02606       NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
02607       break;
02608     case HexagonII::BaseLongOffset:
02609       NonExtOpcode = Hexagon::getRegShlForm(MI->getOpcode());
02610       break;
02611     default:
02612       return false;
02613     }
02614     if (NonExtOpcode < 0)
02615       return false;
02616     return true;
02617   }
02618   return false;
02619 }
02620 
02621 
02622 bool HexagonInstrInfo::hasPseudoInstrPair(const MachineInstr *MI) const {
02623   return Hexagon::getRealHWInstr(MI->getOpcode(),
02624                                  Hexagon::InstrType_Pseudo) >= 0;
02625 }
02626 
02627 
02628 bool HexagonInstrInfo::hasUncondBranch(const MachineBasicBlock *B)
02629       const {
02630   MachineBasicBlock::const_iterator I = B->getFirstTerminator(), E = B->end();
02631   while (I != E) {
02632     if (I->isBarrier())
02633       return true;
02634     ++I;
02635   }
02636   return false;
02637 }
02638 
02639 
02640 // Returns true, if a LD insn can be promoted to a cur load.
02641 bool HexagonInstrInfo::mayBeCurLoad(const MachineInstr *MI) const {
02642   auto &HST = MI->getParent()->getParent()->getSubtarget<HexagonSubtarget>();
02643   const uint64_t F = MI->getDesc().TSFlags;
02644   return ((F >> HexagonII::mayCVLoadPos) & HexagonII::mayCVLoadMask) &&
02645          HST.hasV60TOps();
02646 }
02647 
02648 
02649 // Returns true, if a ST insn can be promoted to a new-value store.
02650 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const {
02651   const uint64_t F = MI->getDesc().TSFlags;
02652   return (F >> HexagonII::mayNVStorePos) & HexagonII::mayNVStoreMask;
02653 }
02654 
02655 
02656 bool HexagonInstrInfo::producesStall(const MachineInstr *ProdMI,
02657       const MachineInstr *ConsMI) const {
02658   // There is no stall when ProdMI is not a V60 vector.
02659   if (!isV60VectorInstruction(ProdMI))
02660     return false;
02661 
02662   // There is no stall when ProdMI and ConsMI are not dependent.
02663   if (!isDependent(ProdMI, ConsMI))
02664     return false;
02665 
02666   // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
02667   // are scheduled in consecutive packets.
02668   if (isVecUsableNextPacket(ProdMI, ConsMI))
02669     return false;
02670 
02671   return true;
02672 }
02673 
02674 
02675 bool HexagonInstrInfo::producesStall(const MachineInstr *MI,
02676       MachineBasicBlock::const_instr_iterator BII) const {
02677   // There is no stall when I is not a V60 vector.
02678   if (!isV60VectorInstruction(MI))
02679     return false;
02680 
02681   MachineBasicBlock::const_instr_iterator MII = BII;
02682   MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
02683 
02684   if (!(*MII).isBundle()) {
02685     const MachineInstr *J = &*MII;
02686     if (!isV60VectorInstruction(J))
02687       return false;
02688     else if (isVecUsableNextPacket(J, MI))
02689       return false;
02690     return true;
02691   }
02692 
02693   for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
02694     const MachineInstr *J = &*MII;
02695     if (producesStall(J, MI))
02696       return true;
02697   }
02698   return false;
02699 }
02700 
02701 
02702 bool HexagonInstrInfo::predCanBeUsedAsDotNew(const MachineInstr *MI,
02703       unsigned PredReg) const {
02704   for (unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
02705     const MachineOperand &MO = MI->getOperand(opNum);
02706     if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
02707       return false; // Predicate register must be explicitly defined.
02708   }
02709 
02710   // Hexagon Programmer's Reference says that decbin, memw_locked, and
02711   // memd_locked cannot be used as .new as well,
02712   // but we don't seem to have these instructions defined.
02713   return MI->getOpcode() != Hexagon::A4_tlbmatch;
02714 }
02715 
02716 
02717 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
02718   return (Opcode == Hexagon::J2_jumpt)      ||
02719          (Opcode == Hexagon::J2_jumpf)      ||
02720          (Opcode == Hexagon::J2_jumptnew)   ||
02721          (Opcode == Hexagon::J2_jumpfnew)   ||
02722          (Opcode == Hexagon::J2_jumptnewpt) ||
02723          (Opcode == Hexagon::J2_jumpfnewpt);
02724 }
02725 
02726 
02727 bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const {
02728   if (Cond.empty() || !isPredicated(Cond[0].getImm()))
02729     return false;
02730   return !isPredicatedTrue(Cond[0].getImm());
02731 }
02732 
02733 
02734 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
02735   const uint64_t F = MI->getDesc().TSFlags;
02736   return (F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask;
02737 }
02738 
02739 
02740 // Returns the base register in a memory access (load/store). The offset is
02741 // returned in Offset and the access size is returned in AccessSize.
02742 unsigned HexagonInstrInfo::getBaseAndOffset(const MachineInstr *MI,
02743       int &Offset, unsigned &AccessSize) const {
02744   // Return if it is not a base+offset type instruction or a MemOp.
02745   if (getAddrMode(MI) != HexagonII::BaseImmOffset &&
02746       getAddrMode(MI) != HexagonII::BaseLongOffset &&
02747       !isMemOp(MI) && !isPostIncrement(MI))
02748     return 0;
02749 
02750   // Since it is a memory access instruction, getMemAccessSize() should never
02751   // return 0.
02752   assert (getMemAccessSize(MI) &&
02753           "BaseImmOffset or BaseLongOffset or MemOp without accessSize");
02754 
02755   // Return Values of getMemAccessSize() are
02756   // 0 - Checked in the assert above.
02757   // 1, 2, 3, 4 & 7, 8 - The statement below is correct for all these.
02758   // MemAccessSize is represented as 1+log2(N) where N is size in bits.
02759   AccessSize = (1U << (getMemAccessSize(MI) - 1));
02760 
02761   unsigned basePos = 0, offsetPos = 0;
02762   if (!getBaseAndOffsetPosition(MI, basePos, offsetPos))
02763     return 0;
02764 
02765   // Post increment updates its EA after the mem access,
02766   // so we need to treat its offset as zero.
02767   if (isPostIncrement(MI))
02768     Offset = 0;
02769   else {
02770     Offset = MI->getOperand(offsetPos).getImm();
02771   }
02772 
02773   return MI->getOperand(basePos).getReg();
02774 }
02775 
02776 
02777 /// Return the position of the base and offset operands for this instruction.
02778 bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr *MI,
02779       unsigned &BasePos, unsigned &OffsetPos) const {
02780   // Deal with memops first.
02781   if (isMemOp(MI)) {
02782     assert (MI->getOperand(0).isReg() && MI->getOperand(1).isImm() &&
02783             "Bad Memop.");
02784     BasePos = 0;
02785     OffsetPos = 1;
02786   } else if (MI->mayStore()) {
02787     BasePos = 0;
02788     OffsetPos = 1;
02789   } else if (MI->mayLoad()) {
02790     BasePos = 1;
02791     OffsetPos = 2;
02792   } else
02793     return false;
02794 
02795   if (isPredicated(MI)) {
02796     BasePos++;
02797     OffsetPos++;
02798   }
02799   if (isPostIncrement(MI)) {
02800     BasePos++;
02801     OffsetPos++;
02802   }
02803 
02804   if (!MI->getOperand(BasePos).isReg() || !MI->getOperand(OffsetPos).isImm())
02805     return false;
02806 
02807   return true;
02808 }
02809 
02810 
02811 // Inserts branching instructions in reverse order of their occurence.
02812 // e.g. jump_t t1 (i1)
02813 // jump t2        (i2)
02814 // Jumpers = {i2, i1}
02815 SmallVector<MachineInstr*, 2> HexagonInstrInfo::getBranchingInstrs(
02816       MachineBasicBlock& MBB) const {
02817   SmallVector<MachineInstr*, 2> Jumpers;
02818   // If the block has no terminators, it just falls into the block after it.
02819   MachineBasicBlock::instr_iterator I = MBB.instr_end();
02820   if (I == MBB.instr_begin())
02821     return Jumpers;
02822 
02823   // A basic block may looks like this:
02824   //
02825   //  [   insn
02826   //     EH_LABEL
02827   //      insn
02828   //      insn
02829   //      insn
02830   //     EH_LABEL
02831   //      insn     ]
02832   //
02833   // It has two succs but does not have a terminator
02834   // Don't know how to handle it.
02835   do {
02836     --I;
02837     if (I->isEHLabel())
02838       return Jumpers;
02839   } while (I != MBB.instr_begin());
02840 
02841   I = MBB.instr_end();
02842   --I;
02843 
02844   while (I->isDebugValue()) {
02845     if (I == MBB.instr_begin())
02846       return Jumpers;
02847     --I;
02848   }
02849   if (!isUnpredicatedTerminator(&*I))
02850     return Jumpers;
02851 
02852   // Get the last instruction in the block.
02853   MachineInstr *LastInst = &*I;
02854   Jumpers.push_back(LastInst);
02855   MachineInstr *SecondLastInst = nullptr;
02856   // Find one more terminator if present.
02857   do {
02858     if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(&*I)) {
02859       if (!SecondLastInst) {
02860         SecondLastInst = &*I;
02861         Jumpers.push_back(SecondLastInst);
02862       } else // This is a third branch.
02863         return Jumpers;
02864     }
02865     if (I == MBB.instr_begin())
02866       break;
02867     --I;
02868   } while (true);
02869   return Jumpers;
02870 }
02871 
02872 
02873 // Returns Operand Index for the constant extended instruction.
02874 unsigned HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
02875   const uint64_t F = MI->getDesc().TSFlags;
02876   return (F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask;
02877 }
02878 
02879 // See if instruction could potentially be a duplex candidate.
02880 // If so, return its group. Zero otherwise.
02881 HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup(
02882       const MachineInstr *MI) const {
02883   unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
02884 
02885   switch (MI->getOpcode()) {
02886   default:
02887     return HexagonII::HCG_None;
02888   //
02889   // Compound pairs.
02890   // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
02891   // "Rd16=#U6 ; jump #r9:2"
02892   // "Rd16=Rs16 ; jump #r9:2"
02893   //
02894   case Hexagon::C2_cmpeq:
02895   case Hexagon::C2_cmpgt:
02896   case Hexagon::C2_cmpgtu:
02897     DstReg = MI->getOperand(0).getReg();
02898     Src1Reg = MI->getOperand(1).getReg();
02899     Src2Reg = MI->getOperand(2).getReg();
02900     if (Hexagon::PredRegsRegClass.contains(DstReg) &&
02901         (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
02902         isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
02903       return HexagonII::HCG_A;
02904     break;
02905   case Hexagon::C2_cmpeqi:
02906   case Hexagon::C2_cmpgti:
02907   case Hexagon::C2_cmpgtui:
02908     // P0 = cmp.eq(Rs,#u2)
02909     DstReg = MI->getOperand(0).getReg();
02910     SrcReg = MI->getOperand(1).getReg();
02911     if (Hexagon::PredRegsRegClass.contains(DstReg) &&
02912         (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
02913         isIntRegForSubInst(SrcReg) && MI->getOperand(2).isImm() &&
02914         ((isUInt<5>(MI->getOperand(2).getImm())) ||
02915          (MI->getOperand(2).getImm() == -1)))
02916       return HexagonII::HCG_A;
02917     break;
02918   case Hexagon::A2_tfr:
02919     // Rd = Rs
02920     DstReg = MI->getOperand(0).getReg();
02921     SrcReg = MI->getOperand(1).getReg();
02922     if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
02923       return HexagonII::HCG_A;
02924     break;
02925   case Hexagon::A2_tfrsi:
02926     // Rd = #u6
02927     // Do not test for #u6 size since the const is getting extended
02928     // regardless and compound could be formed.
02929     DstReg = MI->getOperand(0).getReg();
02930     if (isIntRegForSubInst(DstReg))
02931       return HexagonII::HCG_A;
02932     break;
02933   case Hexagon::S2_tstbit_i:
02934     DstReg = MI->getOperand(0).getReg();
02935     Src1Reg = MI->getOperand(1).getReg();
02936     if (Hexagon::PredRegsRegClass.contains(DstReg) &&
02937         (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
02938         MI->getOperand(2).isImm() &&
02939         isIntRegForSubInst(Src1Reg) && (MI->getOperand(2).getImm() == 0))
02940       return HexagonII::HCG_A;
02941     break;
02942   // The fact that .new form is used pretty much guarantees
02943   // that predicate register will match. Nevertheless,
02944   // there could be some false positives without additional
02945   // checking.
02946   case Hexagon::J2_jumptnew:
02947   case Hexagon::J2_jumpfnew:
02948   case Hexagon::J2_jumptnewpt:
02949   case Hexagon::J2_jumpfnewpt:
02950     Src1Reg = MI->getOperand(0).getReg();
02951     if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
02952         (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
02953       return HexagonII::HCG_B;
02954     break;
02955   // Transfer and jump:
02956   // Rd=#U6 ; jump #r9:2
02957   // Rd=Rs ; jump #r9:2
02958   // Do not test for jump range here.
02959   case Hexagon::J2_jump:
02960   case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
02961     return HexagonII::HCG_C;
02962     break;
02963   }
02964 
02965   return HexagonII::HCG_None;
02966 }
02967 
02968 
02969 // Returns -1 when there is no opcode found.
02970 unsigned HexagonInstrInfo::getCompoundOpcode(const MachineInstr *GA,
02971       const MachineInstr *GB) const {
02972   assert(getCompoundCandidateGroup(GA) == HexagonII::HCG_A);
02973   assert(getCompoundCandidateGroup(GB) == HexagonII::HCG_B);
02974   if ((GA->getOpcode() != Hexagon::C2_cmpeqi) ||
02975       (GB->getOpcode() != Hexagon::J2_jumptnew))
02976     return -1;
02977   unsigned DestReg = GA->getOperand(0).getReg();
02978   if (!GB->readsRegister(DestReg))
02979     return -1;
02980   if (DestReg == Hexagon::P0)
02981     return Hexagon::J4_cmpeqi_tp0_jump_nt;
02982   if (DestReg == Hexagon::P1)
02983     return Hexagon::J4_cmpeqi_tp1_jump_nt;
02984   return -1;
02985 }
02986 
02987 
02988 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
02989   enum Hexagon::PredSense inPredSense;
02990   inPredSense = invertPredicate ? Hexagon::PredSense_false :
02991                                   Hexagon::PredSense_true;
02992   int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
02993   if (CondOpcode >= 0) // Valid Conditional opcode/instruction
02994     return CondOpcode;
02995 
02996   // This switch case will be removed once all the instructions have been
02997   // modified to use relation maps.
02998   switch(Opc) {
02999   case Hexagon::TFRI_f:
03000     return !invertPredicate ? Hexagon::TFRI_cPt_f :
03001                               Hexagon::TFRI_cNotPt_f;
03002   }
03003 
03004   llvm_unreachable("Unexpected predicable instruction");
03005 }
03006 
03007 
03008 // Return the cur value instruction for a given store.
03009 int HexagonInstrInfo::getDotCurOp(const MachineInstr* MI) const {
03010   switch (MI->getOpcode()) {
03011   default: llvm_unreachable("Unknown .cur type");
03012   case Hexagon::V6_vL32b_pi:
03013     return Hexagon::V6_vL32b_cur_pi;
03014   case Hexagon::V6_vL32b_ai:
03015     return Hexagon::V6_vL32b_cur_ai;
03016   //128B
03017   case Hexagon::V6_vL32b_pi_128B:
03018     return Hexagon::V6_vL32b_cur_pi_128B;
03019   case Hexagon::V6_vL32b_ai_128B:
03020     return Hexagon::V6_vL32b_cur_ai_128B;
03021   }
03022   return 0;
03023 }
03024 
03025 
03026 
03027 // The diagram below shows the steps involved in the conversion of a predicated
03028 // store instruction to its .new predicated new-value form.
03029 //
03030 //               p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
03031 //                ^           ^
03032 //               /             \ (not OK. it will cause new-value store to be
03033 //              /               X conditional on p0.new while R2 producer is
03034 //             /                 \ on p0)
03035 //            /                   \.
03036 //     p.new store                 p.old NV store
03037 // [if(p0.new)memw(R0+#0)=R2]    [if(p0)memw(R0+#0)=R2.new]
03038 //            ^                  ^
03039 //             \                /
03040 //              \              /
03041 //               \            /
03042 //                 p.old store
03043 //             [if (p0)memw(R0+#0)=R2]
03044 //
03045 //
03046 // The following set of instructions further explains the scenario where
03047 // conditional new-value store becomes invalid when promoted to .new predicate
03048 // form.
03049 //
03050 // { 1) if (p0) r0 = add(r1, r2)
03051 //   2) p0 = cmp.eq(r3, #0) }
03052 //
03053 //   3) if (p0) memb(r1+#0) = r0  --> this instruction can't be grouped with
03054 // the first two instructions because in instr 1, r0 is conditional on old value
03055 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
03056 // is not valid for new-value stores.
03057 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
03058 // from the "Conditional Store" list. Because a predicated new value store
03059 // would NOT be promoted to a double dot new store. See diagram below:
03060 // This function returns yes for those stores that are predicated but not
03061 // yet promoted to predicate dot new instructions.
03062 //
03063 //                          +---------------------+
03064 //                    /-----| if (p0) memw(..)=r0 |---------\~
03065 //                   ||     +---------------------+         ||
03066 //          promote  ||       /\       /\                   ||  promote
03067 //                   ||      /||\     /||\                  ||
03068 //                  \||/    demote     ||                  \||/
03069 //                   \/       ||       ||                   \/
03070 //       +-------------------------+   ||   +-------------------------+
03071 //       | if (p0.new) memw(..)=r0 |   ||   | if (p0) memw(..)=r0.new |
03072 //       +-------------------------+   ||   +-------------------------+
03073 //                        ||           ||         ||
03074 //                        ||         demote      \||/
03075 //                      promote        ||         \/ NOT possible
03076 //                        ||           ||         /\~
03077 //                       \||/          ||        /||\~
03078 //                        \/           ||         ||
03079 //                      +-----------------------------+
03080 //                      | if (p0.new) memw(..)=r0.new |
03081 //                      +-----------------------------+
03082 //                           Double Dot New Store
03083 //
03084 // Returns the most basic instruction for the .new predicated instructions and
03085 // new-value stores.
03086 // For example, all of the following instructions will be converted back to the
03087 // same instruction:
03088 // 1) if (p0.new) memw(R0+#0) = R1.new  --->
03089 // 2) if (p0) memw(R0+#0)= R1.new      -------> if (p0) memw(R0+#0) = R1
03090 // 3) if (p0.new) memw(R0+#0) = R1      --->
03091 //
03092 // To understand the translation of instruction 1 to its original form, consider
03093 // a packet with 3 instructions.
03094 // { p0 = cmp.eq(R0,R1)
03095 //   if (p0.new) R2 = add(R3, R4)
03096 //   R5 = add (R3, R1)
03097 // }
03098 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
03099 //
03100 // This instruction can be part of the previous packet only if both p0 and R2
03101 // are promoted to .new values. This promotion happens in steps, first
03102 // predicate register is promoted to .new and in the next iteration R2 is
03103 // promoted. Therefore, in case of dependence check failure (due to R5) during
03104 // next iteration, it should be converted back to its most basic form.
03105 
03106 
03107 // Return the new value instruction for a given store.
03108 int HexagonInstrInfo::getDotNewOp(const MachineInstr* MI) const {
03109   int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
03110   if (NVOpcode >= 0) // Valid new-value store instruction.
03111     return NVOpcode;
03112 
03113   switch (MI->getOpcode()) {
03114   default: llvm_unreachable("Unknown .new type");
03115   case Hexagon::S4_storerb_ur:
03116     return Hexagon::S4_storerbnew_ur;
03117 
03118   case Hexagon::S2_storerb_pci:
03119     return Hexagon::S2_storerb_pci;
03120 
03121   case Hexagon::S2_storeri_pci:
03122     return Hexagon::S2_storeri_pci;
03123 
03124   case Hexagon::S2_storerh_pci:
03125     return Hexagon::S2_storerh_pci;
03126 
03127   case Hexagon::S2_storerd_pci:
03128     return Hexagon::S2_storerd_pci;
03129 
03130   case Hexagon::S2_storerf_pci:
03131     return Hexagon::S2_storerf_pci;
03132 
03133   case Hexagon::V6_vS32b_ai:
03134     return Hexagon::V6_vS32b_new_ai;
03135 
03136   case Hexagon::V6_vS32b_pi:
03137     return Hexagon::V6_vS32b_new_pi;
03138 
03139   // 128B
03140   case Hexagon::V6_vS32b_ai_128B:
03141     return Hexagon::V6_vS32b_new_ai_128B;
03142 
03143   case Hexagon::V6_vS32b_pi_128B:
03144     return Hexagon::V6_vS32b_new_pi_128B;
03145   }
03146   return 0;
03147 }
03148 
03149 // Returns the opcode to use when converting MI, which is a conditional jump,
03150 // into a conditional instruction which uses the .new value of the predicate.
03151 // We also use branch probabilities to add a hint to the jump.
03152 int HexagonInstrInfo::getDotNewPredJumpOp(const MachineInstr *MI,
03153       const MachineBranchProbabilityInfo *MBPI) const {
03154   // We assume that block can have at most two successors.
03155   bool taken = false;
03156   const MachineBasicBlock *Src = MI->getParent();
03157   const MachineOperand *BrTarget = &MI->getOperand(1);
03158   const MachineBasicBlock *Dst = BrTarget->getMBB();
03159 
03160   const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
03161   if (Prediction >= BranchProbability(1,2))
03162     taken = true;
03163 
03164   switch (MI->getOpcode()) {
03165   case Hexagon::J2_jumpt:
03166     return taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
03167   case Hexagon::J2_jumpf:
03168     return taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
03169 
03170   default:
03171     llvm_unreachable("Unexpected jump instruction.");
03172   }
03173 }
03174 
03175 
03176 // Return .new predicate version for an instruction.
03177 int HexagonInstrInfo::getDotNewPredOp(const MachineInstr *MI,
03178       const MachineBranchProbabilityInfo *MBPI) const {
03179   int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
03180   if (NewOpcode >= 0) // Valid predicate new instruction
03181     return NewOpcode;
03182 
03183   switch (MI->getOpcode()) {
03184   // Condtional Jumps
03185   case Hexagon::J2_jumpt:
03186   case Hexagon::J2_jumpf:
03187     return getDotNewPredJumpOp(MI, MBPI);
03188 
03189   default:
03190     assert(0 && "Unknown .new type");
03191   }
03192   return 0;
03193 }
03194 
03195 
03196 int HexagonInstrInfo::getDotOldOp(const int opc) const {
03197   int NewOp = opc;
03198   if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
03199     NewOp = Hexagon::getPredOldOpcode(NewOp);
03200     assert(NewOp >= 0 &&
03201            "Couldn't change predicate new instruction to its old form.");
03202   }
03203 
03204   if (isNewValueStore(NewOp)) { // Convert into non-new-value format
03205     NewOp = Hexagon::getNonNVStore(NewOp);
03206     assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
03207   }
03208   return NewOp;
03209 }
03210 
03211 
03212 // See if instruction could potentially be a duplex candidate.
03213 // If so, return its group. Zero otherwise.
03214 HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
03215       const MachineInstr *MI) const {
03216   unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
03217   auto &HRI = getRegisterInfo();
03218 
03219   switch (MI->getOpcode()) {
03220   default:
03221     return HexagonII::HSIG_None;
03222   //
03223   // Group L1:
03224   //
03225   // Rd = memw(Rs+#u4:2)
03226   // Rd = memub(Rs+#u4:0)
03227   case Hexagon::L2_loadri_io:
03228     DstReg = MI->getOperand(0).getReg();
03229     SrcReg = MI->getOperand(1).getReg();
03230     // Special case this one from Group L2.
03231     // Rd = memw(r29+#u5:2)
03232     if (isIntRegForSubInst(DstReg)) {
03233       if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
03234           HRI.getStackRegister() == SrcReg &&
03235           MI->getOperand(2).isImm() &&
03236           isShiftedUInt<5,2>(MI->getOperand(2).getImm()))
03237         return HexagonII::HSIG_L2;
03238       // Rd = memw(Rs+#u4:2)
03239       if (isIntRegForSubInst(SrcReg) &&
03240           (MI->getOperand(2).isImm() &&
03241           isShiftedUInt<4,2>(MI->getOperand(2).getImm())))
03242         return HexagonII::HSIG_L1;
03243     }
03244     break;
03245   case Hexagon::L2_loadrub_io:
03246     // Rd = memub(Rs+#u4:0)
03247     DstReg = MI->getOperand(0).getReg();
03248     SrcReg = MI->getOperand(1).getReg();
03249     if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
03250         MI->getOperand(2).isImm() && isUInt<4>(MI->getOperand(2).getImm()))
03251       return HexagonII::HSIG_L1;
03252     break;
03253   //
03254   // Group L2:
03255   //
03256   // Rd = memh/memuh(Rs+#u3:1)
03257   // Rd = memb(Rs+#u3:0)
03258   // Rd = memw(r29+#u5:2) - Handled above.
03259   // Rdd = memd(r29+#u5:3)
03260   // deallocframe
03261   // [if ([!]p0[.new])] dealloc_return
03262   // [if ([!]p0[.new])] jumpr r31
03263   case Hexagon::L2_loadrh_io:
03264   case Hexagon::L2_loadruh_io:
03265     // Rd = memh/memuh(Rs+#u3:1)
03266     DstReg = MI->getOperand(0).getReg();
03267     SrcReg = MI->getOperand(1).getReg();
03268     if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
03269         MI->getOperand(2).isImm() &&
03270         isShiftedUInt<3,1>(MI->getOperand(2).getImm()))
03271       return HexagonII::HSIG_L2;
03272     break;
03273   case Hexagon::L2_loadrb_io:
03274     // Rd = memb(Rs+#u3:0)
03275     DstReg = MI->getOperand(0).getReg();
03276     SrcReg = MI->getOperand(1).getReg();
03277     if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
03278         MI->getOperand(2).isImm() &&
03279         isUInt<3>(MI->getOperand(2).getImm()))
03280       return HexagonII::HSIG_L2;
03281     break;
03282   case Hexagon::L2_loadrd_io:
03283     // Rdd = memd(r29+#u5:3)
03284     DstReg = MI->getOperand(0).getReg();
03285     SrcReg = MI->getOperand(1).getReg();
03286     if (isDblRegForSubInst(DstReg, HRI) &&
03287         Hexagon::IntRegsRegClass.contains(SrcReg) &&
03288         HRI.getStackRegister() == SrcReg &&
03289         MI->getOperand(2).isImm() &&
03290         isShiftedUInt<5,3>(MI->getOperand(2).getImm()))
03291       return HexagonII::HSIG_L2;
03292     break;
03293   // dealloc_return is not documented in Hexagon Manual, but marked
03294   // with A_SUBINSN attribute in iset_v4classic.py.
03295   case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
03296   case Hexagon::L4_return:
03297   case Hexagon::L2_deallocframe:
03298     return HexagonII::HSIG_L2;
03299   case Hexagon::EH_RETURN_JMPR:
03300   case Hexagon::JMPret :
03301     // jumpr r31
03302     // Actual form JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,internal>.
03303     DstReg = MI->getOperand(0).getReg();
03304     if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
03305       return HexagonII::HSIG_L2;
03306     break;
03307   case Hexagon::JMPrett:
03308   case Hexagon::JMPretf:
03309   case Hexagon::JMPrettnewpt:
03310   case Hexagon::JMPretfnewpt :
03311   case Hexagon::JMPrettnew :
03312   case Hexagon::JMPretfnew :
03313     DstReg = MI->getOperand(1).getReg();
03314     SrcReg = MI->getOperand(0).getReg();
03315     // [if ([!]p0[.new])] jumpr r31
03316     if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
03317         (Hexagon::P0 == SrcReg)) &&
03318         (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
03319       return HexagonII::HSIG_L2;
03320      break;
03321   case Hexagon::L4_return_t :
03322   case Hexagon::L4_return_f :
03323   case Hexagon::L4_return_tnew_pnt :
03324   case Hexagon::L4_return_fnew_pnt :
03325   case Hexagon::L4_return_tnew_pt :
03326   case Hexagon::L4_return_fnew_pt :
03327     // [if ([!]p0[.new])] dealloc_return
03328     SrcReg = MI->getOperand(0).getReg();
03329     if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
03330       return HexagonII::HSIG_L2;
03331     break;
03332   //
03333   // Group S1:
03334   //
03335   // memw(Rs+#u4:2) = Rt
03336   // memb(Rs+#u4:0) = Rt
03337   case Hexagon::S2_storeri_io:
03338     // Special case this one from Group S2.
03339     // memw(r29+#u5:2) = Rt
03340     Src1Reg = MI->getOperand(0).getReg();
03341     Src2Reg = MI->getOperand(2).getReg();
03342     if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
03343         isIntRegForSubInst(Src2Reg) &&
03344         HRI.getStackRegister() == Src1Reg && MI->getOperand(1).isImm() &&
03345         isShiftedUInt<5,2>(MI->getOperand(1).getImm()))
03346       return HexagonII::HSIG_S2;
03347     // memw(Rs+#u4:2) = Rt
03348     if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
03349         MI->getOperand(1).isImm() &&
03350         isShiftedUInt<4,2>(MI->getOperand(1).getImm()))
03351       return HexagonII::HSIG_S1;
03352     break;
03353   case Hexagon::S2_storerb_io:
03354     // memb(Rs+#u4:0) = Rt
03355     Src1Reg = MI->getOperand(0).getReg();
03356     Src2Reg = MI->getOperand(2).getReg();
03357     if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
03358         MI->getOperand(1).isImm() && isUInt<4>(MI->getOperand(1).getImm()))
03359       return HexagonII::HSIG_S1;
03360     break;
03361   //
03362   // Group S2:
03363   //
03364   // memh(Rs+#u3:1) = Rt
03365   // memw(r29+#u5:2) = Rt
03366   // memd(r29+#s6:3) = Rtt
03367   // memw(Rs+#u4:2) = #U1
03368   // memb(Rs+#u4) = #U1
03369   // allocframe(#u5:3)
03370   case Hexagon::S2_storerh_io:
03371     // memh(Rs+#u3:1) = Rt
03372     Src1Reg = MI->getOperand(0).getReg();
03373     Src2Reg = MI->getOperand(2).getReg();
03374     if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
03375         MI->getOperand(1).isImm() &&
03376         isShiftedUInt<3,1>(MI->getOperand(1).getImm()))
03377       return HexagonII::HSIG_S1;
03378     break;
03379   case Hexagon::S2_storerd_io:
03380     // memd(r29+#s6:3) = Rtt
03381     Src1Reg = MI->getOperand(0).getReg();
03382     Src2Reg = MI->getOperand(2).getReg();
03383     if (isDblRegForSubInst(Src2Reg, HRI) &&
03384         Hexagon::IntRegsRegClass.contains(Src1Reg) &&
03385         HRI.getStackRegister() == Src1Reg && MI->getOperand(1).isImm() &&
03386         isShiftedInt<6,3>(MI->getOperand(1).getImm()))
03387       return HexagonII::HSIG_S2;
03388     break;
03389   case Hexagon::S4_storeiri_io:
03390     // memw(Rs+#u4:2) = #U1
03391     Src1Reg = MI->getOperand(0).getReg();
03392     if (isIntRegForSubInst(Src1Reg) && MI->getOperand(1).isImm() &&
03393         isShiftedUInt<4,2>(MI->getOperand(1).getImm()) &&
03394         MI->getOperand(2).isImm() && isUInt<1>(MI->getOperand(2).getImm()))
03395       return HexagonII::HSIG_S2;
03396     break;
03397   case Hexagon::S4_storeirb_io:
03398     // memb(Rs+#u4) = #U1
03399     Src1Reg = MI->getOperand(0).getReg();
03400     if (isIntRegForSubInst(Src1Reg) && MI->getOperand(1).isImm() &&
03401         isUInt<4>(MI->getOperand(1).getImm()) && MI->getOperand(2).isImm() &&
03402         MI->getOperand(2).isImm() && isUInt<1>(MI->getOperand(2).getImm()))
03403       return HexagonII::HSIG_S2;
03404     break;
03405   case Hexagon::S2_allocframe:
03406     if (MI->getOperand(0).isImm() &&
03407         isShiftedUInt<5,3>(MI->getOperand(0).getImm()))
03408       return HexagonII::HSIG_S1;
03409     break;
03410   //
03411   // Group A:
03412   //
03413   // Rx = add(Rx,#s7)
03414   // Rd = Rs
03415   // Rd = #u6
03416   // Rd = #-1
03417   // if ([!]P0[.new]) Rd = #0
03418   // Rd = add(r29,#u6:2)
03419   // Rx = add(Rx,Rs)
03420   // P0 = cmp.eq(Rs,#u2)
03421   // Rdd = combine(#0,Rs)
03422   // Rdd = combine(Rs,#0)
03423   // Rdd = combine(#u2,#U2)
03424   // Rd = add(Rs,#1)
03425   // Rd = add(Rs,#-1)
03426   // Rd = sxth/sxtb/zxtb/zxth(Rs)
03427   // Rd = and(Rs,#1)
03428   case Hexagon::A2_addi:
03429     DstReg = MI->getOperand(0).getReg();
03430     SrcReg = MI->getOperand(1).getReg();
03431     if (isIntRegForSubInst(DstReg)) {
03432       // Rd = add(r29,#u6:2)
03433       if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
03434         HRI.getStackRegister() == SrcReg && MI->getOperand(2).isImm() &&
03435         isShiftedUInt<6,2>(MI->getOperand(2).getImm()))
03436         return HexagonII::HSIG_A;
03437       // Rx = add(Rx,#s7)
03438       if ((DstReg == SrcReg) && MI->getOperand(2).isImm() &&
03439           isInt<7>(MI->getOperand(2).getImm()))
03440         return HexagonII::HSIG_A;
03441       // Rd = add(Rs,#1)
03442       // Rd = add(Rs,#-1)
03443       if (isIntRegForSubInst(SrcReg) && MI->getOperand(2).isImm() &&
03444           ((MI->getOperand(2).getImm() == 1) ||
03445           (MI->getOperand(2).getImm() == -1)))
03446         return HexagonII::HSIG_A;
03447     }
03448     break;
03449   case Hexagon::A2_add:
03450     // Rx = add(Rx,Rs)
03451     DstReg = MI->getOperand(0).getReg();
03452     Src1Reg = MI->getOperand(1).getReg();
03453     Src2Reg = MI->getOperand(2).getReg();
03454     if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
03455         isIntRegForSubInst(Src2Reg))
03456       return HexagonII::HSIG_A;
03457     break;
03458   case Hexagon::A2_andir:
03459     // Same as zxtb.
03460     // Rd16=and(Rs16,#255)
03461     // Rd16=and(Rs16,#1)
03462     DstReg = MI->getOperand(0).getReg();
03463     SrcReg = MI->getOperand(1).getReg();
03464     if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
03465         MI->getOperand(2).isImm() &&
03466         ((MI->getOperand(2).getImm() == 1) ||
03467         (MI->getOperand(2).getImm() == 255)))
03468       return HexagonII::HSIG_A;
03469     break;
03470   case Hexagon::A2_tfr:
03471     // Rd = Rs
03472     DstReg = MI->getOperand(0).getReg();
03473     SrcReg = MI->getOperand(1).getReg();
03474     if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
03475       return HexagonII::HSIG_A;
03476     break;
03477   case Hexagon::A2_tfrsi:
03478     // Rd = #u6
03479     // Do not test for #u6 size since the const is getting extended
03480     // regardless and compound could be formed.
03481     // Rd = #-1
03482     DstReg = MI->getOperand(0).getReg();
03483     if (isIntRegForSubInst(DstReg))
03484       return HexagonII::HSIG_A;
03485     break;
03486   case Hexagon::C2_cmoveit:
03487   case Hexagon::C2_cmovenewit:
03488   case Hexagon::C2_cmoveif:
03489   case Hexagon::C2_cmovenewif:
03490     // if ([!]P0[.new]) Rd = #0
03491     // Actual form:
03492     // %R16<def> = C2_cmovenewit %P0<internal>, 0, %R16<imp-use,undef>;
03493     DstReg = MI->getOperand(0).getReg();
03494     SrcReg = MI->getOperand(1).getReg();
03495     if (isIntRegForSubInst(DstReg) &&
03496         Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
03497         MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0)
03498       return HexagonII::HSIG_A;
03499     break;
03500   case Hexagon::C2_cmpeqi:
03501     // P0 = cmp.eq(Rs,#u2)
03502     DstReg = MI->getOperand(0).getReg();
03503     SrcReg = MI->getOperand(1).getReg();
03504     if (Hexagon::PredRegsRegClass.contains(DstReg) &&
03505         Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) &&
03506         MI->getOperand(2).isImm() && isUInt<2>(MI->getOperand(2).getImm()))
03507       return HexagonII::HSIG_A;
03508     break;
03509   case Hexagon::A2_combineii:
03510   case Hexagon::A4_combineii:
03511     // Rdd = combine(#u2,#U2)
03512     DstReg = MI->getOperand(0).getReg();
03513     if (isDblRegForSubInst(DstReg, HRI) &&
03514         ((MI->getOperand(1).isImm() && isUInt<2>(MI->getOperand(1).getImm())) ||
03515         (MI->getOperand(1).isGlobal() &&
03516         isUInt<2>(MI->getOperand(1).getOffset()))) &&
03517         ((MI->getOperand(2).isImm() && isUInt<2>(MI->getOperand(2).getImm())) ||
03518         (MI->getOperand(2).isGlobal() &&
03519         isUInt<2>(MI->getOperand(2).getOffset()))))
03520       return HexagonII::HSIG_A;
03521     break;
03522   case Hexagon::A4_combineri:
03523     // Rdd = combine(Rs,#0)
03524     DstReg = MI->getOperand(0).getReg();
03525     SrcReg = MI->getOperand(1).getReg();
03526     if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
03527         ((MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0) ||
03528         (MI->getOperand(2).isGlobal() && MI->getOperand(2).getOffset() == 0)))
03529       return HexagonII::HSIG_A;
03530     break;
03531   case Hexagon::A4_combineir:
03532     // Rdd = combine(#0,Rs)
03533     DstReg = MI->getOperand(0).getReg();
03534     SrcReg = MI->getOperand(2).getReg();
03535     if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
03536         ((MI->getOperand(1).isImm() && MI->getOperand(1).getImm() == 0) ||
03537         (MI->getOperand(1).isGlobal() && MI->getOperand(1).getOffset() == 0)))
03538       return HexagonII::HSIG_A;
03539     break;
03540   case Hexagon::A2_sxtb:
03541   case Hexagon::A2_sxth:
03542   case Hexagon::A2_zxtb:
03543   case Hexagon::A2_zxth:
03544     // Rd = sxth/sxtb/zxtb/zxth(Rs)
03545     DstReg = MI->getOperand(0).getReg();
03546     SrcReg = MI->getOperand(1).getReg();
03547     if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
03548       return HexagonII::HSIG_A;
03549     break;
03550   }
03551 
03552   return HexagonII::HSIG_None;
03553 }
03554 
03555 
03556 short HexagonInstrInfo::getEquivalentHWInstr(const MachineInstr *MI) const {
03557   return Hexagon::getRealHWInstr(MI->getOpcode(), Hexagon::InstrType_Real);
03558 }
03559 
03560 
03561 // Return first non-debug instruction in the basic block.
03562 MachineInstr *HexagonInstrInfo::getFirstNonDbgInst(MachineBasicBlock *BB)
03563       const {
03564   for (auto MII = BB->instr_begin(), End = BB->instr_end(); MII != End; MII++) {
03565     MachineInstr *MI = &*MII;
03566     if (MI->isDebugValue())
03567       continue;
03568     return MI;
03569   }
03570   return nullptr;
03571 }
03572 
03573 
03574 unsigned HexagonInstrInfo::getInstrTimingClassLatency(
03575       const InstrItineraryData *ItinData, const MachineInstr *MI) const {
03576   // Default to one cycle for no itinerary. However, an "empty" itinerary may
03577   // still have a MinLatency property, which getStageLatency checks.
03578   if (!ItinData)
03579     return getInstrLatency(ItinData, MI);
03580 
03581   // Get the latency embedded in the itinerary. If we're not using timing class
03582   // latencies or if we using BSB scheduling, then restrict the maximum latency
03583   // to 1 (that is, either 0 or 1).
03584   if (MI->isTransient())
03585     return 0;
03586   unsigned Latency = ItinData->getStageLatency(MI->getDesc().getSchedClass());
03587   if (!EnableTimingClassLatency ||
03588       MI->getParent()->getParent()->getSubtarget<HexagonSubtarget>().
03589       useBSBScheduling())
03590     if (Latency > 1)
03591       Latency = 1;
03592   return Latency;
03593 }
03594 
03595 
03596 // inverts the predication logic.
03597 // p -> NotP
03598 // NotP -> P
03599 bool HexagonInstrInfo::getInvertedPredSense(
03600       SmallVectorImpl<MachineOperand> &Cond) const {
03601   if (Cond.empty())
03602     return false;
03603   unsigned Opc = getInvertedPredicatedOpcode(Cond[0].getImm());
03604   Cond[0].setImm(Opc);
03605   return true;
03606 }
03607 
03608 
03609 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
03610   int InvPredOpcode;
03611   InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
03612                                         : Hexagon::getTruePredOpcode(Opc);
03613   if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
03614     return InvPredOpcode;
03615 
03616   llvm_unreachable("Unexpected predicated instruction");
03617 }
03618 
03619 
03620 // Returns the max value that doesn't need to be extended.
03621 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
03622   const uint64_t F = MI->getDesc().TSFlags;
03623   unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
03624                     & HexagonII::ExtentSignedMask;
03625   unsigned bits =  (F >> HexagonII::ExtentBitsPos)
03626                     & HexagonII::ExtentBitsMask;
03627 
03628   if (isSigned) // if value is signed
03629     return ~(-1U << (bits - 1));
03630   else
03631     return ~(-1U << bits);
03632 }
03633 
03634 
03635 unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr* MI) const {
03636   const uint64_t F = MI->getDesc().TSFlags;
03637   return (F >> HexagonII::MemAccessSizePos) & HexagonII::MemAccesSizeMask;
03638 }
03639 
03640 
03641 // Returns the min value that doesn't need to be extended.
03642 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
03643   const uint64_t F = MI->getDesc().TSFlags;
03644   unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
03645                     & HexagonII::ExtentSignedMask;
03646   unsigned bits =  (F >> HexagonII::ExtentBitsPos)
03647                     & HexagonII::ExtentBitsMask;
03648 
03649   if (isSigned) // if value is signed
03650     return -1U << (bits - 1);
03651   else
03652     return 0;
03653 }
03654 
03655 
03656 // Returns opcode of the non-extended equivalent instruction.
03657 short HexagonInstrInfo::getNonExtOpcode(const MachineInstr *MI) const {
03658   // Check if the instruction has a register form that uses register in place
03659   // of the extended operand, if so return that as the non-extended form.
03660   short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
03661     if (NonExtOpcode >= 0)
03662       return NonExtOpcode;
03663 
03664   if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
03665     // Check addressing mode and retrieve non-ext equivalent instruction.
03666     switch (getAddrMode(MI)) {
03667     case HexagonII::Absolute :
03668       return Hexagon::getBaseWithImmOffset(MI->getOpcode());
03669     case HexagonII::BaseImmOffset :
03670       return Hexagon::getBaseWithRegOffset(MI->getOpcode());
03671     case HexagonII::BaseLongOffset:
03672       return Hexagon::getRegShlForm(MI->getOpcode());
03673 
03674     default:
03675       return -1;
03676     }
03677   }
03678   return -1;
03679 }
03680 
03681 
03682 bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
03683       unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
03684   if (Cond.empty())
03685     return false;
03686   assert(Cond.size() == 2);
03687   if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
03688      DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
03689      return false;
03690   }
03691   PredReg = Cond[1].getReg();
03692   PredRegPos = 1;
03693   // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
03694   PredRegFlags = 0;
03695   if (Cond[1].isImplicit())
03696     PredRegFlags = RegState::Implicit;
03697   if (Cond[1].isUndef())
03698     PredRegFlags |= RegState::Undef;
03699   return true;
03700 }
03701 
03702 
03703 short HexagonInstrInfo::getPseudoInstrPair(const MachineInstr *MI) const {
03704   return Hexagon::getRealHWInstr(MI->getOpcode(), Hexagon::InstrType_Pseudo);
03705 }
03706 
03707 
03708 short HexagonInstrInfo::getRegForm(const MachineInstr *MI) const {
03709   return Hexagon::getRegForm(MI->getOpcode());
03710 }
03711 
03712 
03713 // Return the number of bytes required to encode the instruction.
03714 // Hexagon instructions are fixed length, 4 bytes, unless they
03715 // use a constant extender, which requires another 4 bytes.
03716 // For debug instructions and prolog labels, return 0.
03717 unsigned HexagonInstrInfo::getSize(const MachineInstr *MI) const {
03718   if (MI->isDebugValue() || MI->isPosition())
03719     return 0;
03720 
03721   unsigned Size = MI->getDesc().getSize();
03722   if (!Size)
03723     // Assume the default insn size in case it cannot be determined
03724     // for whatever reason.
03725     Size = HEXAGON_INSTR_SIZE;
03726 
03727   if (isConstExtended(MI) || isExtended(MI))
03728     Size += HEXAGON_INSTR_SIZE;
03729 
03730   // Try and compute number of instructions in asm.
03731   if (BranchRelaxAsmLarge && MI->getOpcode() == Hexagon::INLINEASM) {
03732     const MachineBasicBlock &MBB = *MI->getParent();
03733     const MachineFunction *MF = MBB.getParent();
03734     const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
03735 
03736     // Count the number of register definitions to find the asm string.
03737     unsigned NumDefs = 0;
03738     for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef();
03739          ++NumDefs)
03740       assert(NumDefs != MI->getNumOperands()-2 && "No asm string?");
03741 
03742     assert(MI->getOperand(NumDefs).isSymbol() && "No asm string?");
03743     // Disassemble the AsmStr and approximate number of instructions.
03744     const char *AsmStr = MI->getOperand(NumDefs).getSymbolName();
03745     Size = getInlineAsmLength(AsmStr, *MAI);
03746   }
03747 
03748   return Size;
03749 }
03750 
03751 
03752 uint64_t HexagonInstrInfo::getType(const MachineInstr* MI) const {
03753   const uint64_t F = MI->getDesc().TSFlags;
03754   return (F >> HexagonII::TypePos) & HexagonII::TypeMask;
03755 }
03756 
03757 
03758 unsigned HexagonInstrInfo::getUnits(const MachineInstr* MI) const {
03759   const TargetSubtargetInfo &ST = MI->getParent()->getParent()->getSubtarget();
03760   const InstrItineraryData &II = *ST.getInstrItineraryData();
03761   const InstrStage &IS = *II.beginStage(MI->getDesc().getSchedClass());
03762 
03763   return IS.getUnits();
03764 }
03765 
03766 
03767 unsigned HexagonInstrInfo::getValidSubTargets(const unsigned Opcode) const {
03768   const uint64_t F = get(Opcode).TSFlags;
03769   return (F >> HexagonII::validSubTargetPos) & HexagonII::validSubTargetMask;
03770 }
03771 
03772 
03773 // Calculate size of the basic block without debug instructions.
03774 unsigned HexagonInstrInfo::nonDbgBBSize(const MachineBasicBlock *BB) const {
03775   return nonDbgMICount(BB->instr_begin(), BB->instr_end());
03776 }
03777 
03778 
03779 unsigned HexagonInstrInfo::nonDbgBundleSize(
03780       MachineBasicBlock::const_iterator BundleHead) const {
03781   assert(BundleHead->isBundle() && "Not a bundle header");
03782   auto MII = BundleHead.getInstrIterator();
03783   // Skip the bundle header.
03784   return nonDbgMICount(++MII, getBundleEnd(BundleHead));
03785 }
03786 
03787 
03788 /// immediateExtend - Changes the instruction in place to one using an immediate
03789 /// extender.
03790 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
03791   assert((isExtendable(MI)||isConstExtended(MI)) &&
03792                                "Instruction must be extendable");
03793   // Find which operand is extendable.
03794   short ExtOpNum = getCExtOpNum(MI);
03795   MachineOperand &MO = MI->getOperand(ExtOpNum);
03796   // This needs to be something we understand.
03797   assert((MO.isMBB() || MO.isImm()) &&
03798          "Branch with unknown extendable field type");
03799   // Mark given operand as extended.
03800   MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
03801 }
03802 
03803 
03804 bool HexagonInstrInfo::invertAndChangeJumpTarget(
03805       MachineInstr* MI, MachineBasicBlock* NewTarget) const {
03806   DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to BB#"
03807                << NewTarget->getNumber(); MI->dump(););
03808   assert(MI->isBranch());
03809   unsigned NewOpcode = getInvertedPredicatedOpcode(MI->getOpcode());
03810   int TargetPos = MI->getNumOperands() - 1;
03811   // In general branch target is the last operand,
03812   // but some implicit defs added at the end might change it.
03813   while ((TargetPos > -1) && !MI->getOperand(TargetPos).isMBB())
03814     --TargetPos;
03815   assert((TargetPos >= 0) && MI->getOperand(TargetPos).isMBB());
03816   MI->getOperand(TargetPos).setMBB(NewTarget);
03817   if (EnableBranchPrediction && isPredicatedNew(MI)) {
03818     NewOpcode = reversePrediction(NewOpcode);
03819   }
03820   MI->setDesc(get(NewOpcode));
03821   return true;
03822 }
03823 
03824 
03825 void HexagonInstrInfo::genAllInsnTimingClasses(MachineFunction &MF) const {
03826   /* +++ The code below is used to generate complete set of Hexagon Insn +++ */
03827   MachineFunction::iterator A = MF.begin();
03828   MachineBasicBlock &B = *A;
03829   MachineBasicBlock::iterator I = B.begin();
03830   MachineInstr *MI = &*I;
03831   DebugLoc DL = MI->getDebugLoc();
03832   MachineInstr *NewMI;
03833 
03834   for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
03835        insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
03836     NewMI = BuildMI(B, MI, DL, get(insn));
03837     DEBUG(dbgs() << "\n" << getName(NewMI->getOpcode()) <<
03838           "  Class: " << NewMI->getDesc().getSchedClass());
03839     NewMI->eraseFromParent();
03840   }
03841   /* --- The code above is used to generate complete set of Hexagon Insn --- */
03842 }
03843 
03844 
03845 // inverts the predication logic.
03846 // p -> NotP
03847 // NotP -> P
03848 bool HexagonInstrInfo::reversePredSense(MachineInstr* MI) const {
03849   DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI->dump());
03850   MI->setDesc(get(getInvertedPredicatedOpcode(MI->getOpcode())));
03851   return true;
03852 }
03853 
03854 
03855 // Reverse the branch prediction.
03856 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
03857   int PredRevOpcode = -1;
03858   if (isPredictedTaken(Opcode))
03859     PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
03860   else
03861     PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
03862   assert(PredRevOpcode > 0);
03863   return PredRevOpcode;
03864 }
03865 
03866 
03867 // TODO: Add more rigorous validation.
03868 bool HexagonInstrInfo::validateBranchCond(const ArrayRef<MachineOperand> &Cond)
03869       const {
03870   return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
03871 }
03872