LLVM  mainline
HexagonInstrInfo.cpp
Go to the documentation of this file.
00001 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the Hexagon implementation of the TargetInstrInfo class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "HexagonInstrInfo.h"
00015 #include "Hexagon.h"
00016 #include "HexagonRegisterInfo.h"
00017 #include "HexagonSubtarget.h"
00018 #include "llvm/ADT/STLExtras.h"
00019 #include "llvm/ADT/SmallVector.h"
00020 #include "llvm/CodeGen/DFAPacketizer.h"
00021 #include "llvm/CodeGen/MachineFrameInfo.h"
00022 #include "llvm/CodeGen/MachineInstrBuilder.h"
00023 #include "llvm/CodeGen/MachineMemOperand.h"
00024 #include "llvm/CodeGen/MachineRegisterInfo.h"
00025 #include "llvm/CodeGen/PseudoSourceValue.h"
00026 #include "llvm/Support/Debug.h"
00027 #include "llvm/Support/MathExtras.h"
00028 #include "llvm/Support/raw_ostream.h"
00029 
00030 using namespace llvm;
00031 
00032 #define DEBUG_TYPE "hexagon-instrinfo"
00033 
00034 #define GET_INSTRINFO_CTOR_DTOR
00035 #define GET_INSTRMAP_INFO
00036 #include "HexagonGenInstrInfo.inc"
00037 #include "HexagonGenDFAPacketizer.inc"
00038 
00039 ///
00040 /// Constants for Hexagon instructions.
00041 ///
00042 const int Hexagon_MEMW_OFFSET_MAX = 4095;
00043 const int Hexagon_MEMW_OFFSET_MIN = -4096;
00044 const int Hexagon_MEMD_OFFSET_MAX = 8191;
00045 const int Hexagon_MEMD_OFFSET_MIN = -8192;
00046 const int Hexagon_MEMH_OFFSET_MAX = 2047;
00047 const int Hexagon_MEMH_OFFSET_MIN = -2048;
00048 const int Hexagon_MEMB_OFFSET_MAX = 1023;
00049 const int Hexagon_MEMB_OFFSET_MIN = -1024;
00050 const int Hexagon_ADDI_OFFSET_MAX = 32767;
00051 const int Hexagon_ADDI_OFFSET_MIN = -32768;
00052 const int Hexagon_MEMD_AUTOINC_MAX = 56;
00053 const int Hexagon_MEMD_AUTOINC_MIN = -64;
00054 const int Hexagon_MEMW_AUTOINC_MAX = 28;
00055 const int Hexagon_MEMW_AUTOINC_MIN = -32;
00056 const int Hexagon_MEMH_AUTOINC_MAX = 14;
00057 const int Hexagon_MEMH_AUTOINC_MIN = -16;
00058 const int Hexagon_MEMB_AUTOINC_MAX = 7;
00059 const int Hexagon_MEMB_AUTOINC_MIN = -8;
00060 
00061 // Pin the vtable to this file.
00062 void HexagonInstrInfo::anchor() {}
00063 
00064 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
00065     : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
00066       RI(), Subtarget(ST) {}
00067 
00068 /// isLoadFromStackSlot - If the specified machine instruction is a direct
00069 /// load from a stack slot, return the virtual or physical register number of
00070 /// the destination along with the FrameIndex of the loaded stack slot.  If
00071 /// not, return 0.  This predicate must return 0 if the instruction has
00072 /// any side effects other than loading from the stack slot.
00073 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
00074                                              int &FrameIndex) const {
00075 
00076 
00077   switch (MI->getOpcode()) {
00078   default: break;
00079   case Hexagon::L2_loadri_io:
00080   case Hexagon::L2_loadrd_io:
00081   case Hexagon::L2_loadrh_io:
00082   case Hexagon::L2_loadrb_io:
00083   case Hexagon::L2_loadrub_io:
00084     if (MI->getOperand(2).isFI() &&
00085         MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
00086       FrameIndex = MI->getOperand(2).getIndex();
00087       return MI->getOperand(0).getReg();
00088     }
00089     break;
00090   }
00091   return 0;
00092 }
00093 
00094 
00095 /// isStoreToStackSlot - If the specified machine instruction is a direct
00096 /// store to a stack slot, return the virtual or physical register number of
00097 /// the source reg along with the FrameIndex of the loaded stack slot.  If
00098 /// not, return 0.  This predicate must return 0 if the instruction has
00099 /// any side effects other than storing to the stack slot.
00100 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
00101                                             int &FrameIndex) const {
00102   switch (MI->getOpcode()) {
00103   default: break;
00104   case Hexagon::S2_storeri_io:
00105   case Hexagon::S2_storerd_io:
00106   case Hexagon::S2_storerh_io:
00107   case Hexagon::S2_storerb_io:
00108     if (MI->getOperand(2).isFI() &&
00109         MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
00110       FrameIndex = MI->getOperand(0).getIndex();
00111       return MI->getOperand(2).getReg();
00112     }
00113     break;
00114   }
00115   return 0;
00116 }
00117 
00118 
00119 unsigned
00120 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
00121                              MachineBasicBlock *FBB,
00122                              const SmallVectorImpl<MachineOperand> &Cond,
00123                              DebugLoc DL) const{
00124 
00125     int BOpc   = Hexagon::J2_jump;
00126     int BccOpc = Hexagon::J2_jumpt;
00127 
00128     assert(TBB && "InsertBranch must not be told to insert a fallthrough");
00129 
00130     int regPos = 0;
00131     // Check if ReverseBranchCondition has asked to reverse this branch
00132     // If we want to reverse the branch an odd number of times, we want
00133     // JMP_f.
00134     if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
00135       BccOpc = Hexagon::J2_jumpf;
00136       regPos = 1;
00137     }
00138 
00139     if (!FBB) {
00140       if (Cond.empty()) {
00141         // Due to a bug in TailMerging/CFG Optimization, we need to add a
00142         // special case handling of a predicated jump followed by an
00143         // unconditional jump. If not, Tail Merging and CFG Optimization go
00144         // into an infinite loop.
00145         MachineBasicBlock *NewTBB, *NewFBB;
00146         SmallVector<MachineOperand, 4> Cond;
00147         MachineInstr *Term = MBB.getFirstTerminator();
00148         if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
00149                                                  false)) {
00150           MachineBasicBlock *NextBB =
00151             std::next(MachineFunction::iterator(&MBB));
00152           if (NewTBB == NextBB) {
00153             ReverseBranchCondition(Cond);
00154             RemoveBranch(MBB);
00155             return InsertBranch(MBB, TBB, nullptr, Cond, DL);
00156           }
00157         }
00158         BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
00159       } else {
00160         // If Cond[0] is a basic block, insert ENDLOOP0.
00161         if (Cond[0].isMBB())
00162           BuildMI(&MBB, DL, get(Hexagon::ENDLOOP0)).addMBB(Cond[0].getMBB());
00163         else
00164           BuildMI(&MBB, DL,
00165                   get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
00166       }
00167       return 1;
00168     }
00169 
00170     // We don't handle ENDLOOP0 with a conditional branch in AnalyzeBranch.
00171     BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
00172     BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
00173     return 2;
00174 }
00175 
00176 
00177 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
00178                                      MachineBasicBlock *&TBB,
00179                                  MachineBasicBlock *&FBB,
00180                                  SmallVectorImpl<MachineOperand> &Cond,
00181                                  bool AllowModify) const {
00182   TBB = nullptr;
00183   FBB = nullptr;
00184 
00185   // If the block has no terminators, it just falls into the block after it.
00186   MachineBasicBlock::instr_iterator I = MBB.instr_end();
00187   if (I == MBB.instr_begin())
00188     return false;
00189 
00190   // A basic block may looks like this:
00191   //
00192   //  [   insn
00193   //     EH_LABEL
00194   //      insn
00195   //      insn
00196   //      insn
00197   //     EH_LABEL
00198   //      insn     ]
00199   //
00200   // It has two succs but does not have a terminator
00201   // Don't know how to handle it.
00202   do {
00203     --I;
00204     if (I->isEHLabel())
00205       return true;
00206   } while (I != MBB.instr_begin());
00207 
00208   I = MBB.instr_end();
00209   --I;
00210 
00211   while (I->isDebugValue()) {
00212     if (I == MBB.instr_begin())
00213       return false;
00214     --I;
00215   }
00216   
00217   bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
00218                      I->getOperand(0).isMBB();
00219   // Delete the JMP if it's equivalent to a fall-through.
00220   if (AllowModify && JumpToBlock &&
00221       MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
00222     DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
00223     I->eraseFromParent();
00224     I = MBB.instr_end();
00225     if (I == MBB.instr_begin())
00226       return false;
00227     --I;
00228   }
00229   if (!isUnpredicatedTerminator(I))
00230     return false;
00231 
00232   // Get the last instruction in the block.
00233   MachineInstr *LastInst = I;
00234   MachineInstr *SecondLastInst = nullptr;
00235   // Find one more terminator if present.
00236   do {
00237     if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(I)) {
00238       if (!SecondLastInst)
00239         SecondLastInst = I;
00240       else
00241         // This is a third branch.
00242         return true;
00243     }
00244     if (I == MBB.instr_begin())
00245       break;
00246     --I;
00247   } while(I);
00248 
00249   int LastOpcode = LastInst->getOpcode();
00250   int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
00251   // If the branch target is not a basic block, it could be a tail call.
00252   // (It is, if the target is a function.)
00253   if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
00254     return true;
00255   if (SecLastOpcode == Hexagon::J2_jump &&
00256       !SecondLastInst->getOperand(0).isMBB())
00257     return true;
00258 
00259   bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
00260   bool LastOpcodeHasNot = PredOpcodeHasNot(LastOpcode);
00261 
00262   // If there is only one terminator instruction, process it.
00263   if (LastInst && !SecondLastInst) {
00264     if (LastOpcode == Hexagon::J2_jump) {
00265       TBB = LastInst->getOperand(0).getMBB();
00266       return false;
00267     }
00268     if (LastOpcode == Hexagon::ENDLOOP0) {
00269       TBB = LastInst->getOperand(0).getMBB();
00270       Cond.push_back(LastInst->getOperand(0));
00271       return false;
00272     }
00273     if (LastOpcodeHasJMP_c) {
00274       TBB = LastInst->getOperand(1).getMBB();
00275       if (LastOpcodeHasNot) {
00276         Cond.push_back(MachineOperand::CreateImm(0));
00277       }
00278       Cond.push_back(LastInst->getOperand(0));
00279       return false;
00280     }
00281     // Otherwise, don't know what this is.
00282     return true;
00283   }
00284 
00285   bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
00286   bool SecLastOpcodeHasNot = PredOpcodeHasNot(SecLastOpcode);
00287   if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
00288     TBB =  SecondLastInst->getOperand(1).getMBB();
00289     if (SecLastOpcodeHasNot)
00290       Cond.push_back(MachineOperand::CreateImm(0));
00291     Cond.push_back(SecondLastInst->getOperand(0));
00292     FBB = LastInst->getOperand(0).getMBB();
00293     return false;
00294   }
00295 
00296   // If the block ends with two Hexagon:JMPs, handle it.  The second one is not
00297   // executed, so remove it.
00298   if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
00299     TBB = SecondLastInst->getOperand(0).getMBB();
00300     I = LastInst;
00301     if (AllowModify)
00302       I->eraseFromParent();
00303     return false;
00304   }
00305 
00306   // If the block ends with an ENDLOOP, and JMP, handle it.
00307   if (SecLastOpcode == Hexagon::ENDLOOP0 &&
00308       LastOpcode == Hexagon::J2_jump) {
00309     TBB = SecondLastInst->getOperand(0).getMBB();
00310     Cond.push_back(SecondLastInst->getOperand(0));
00311     FBB = LastInst->getOperand(0).getMBB();
00312     return false;
00313   }
00314 
00315   // Otherwise, can't handle this.
00316   return true;
00317 }
00318 
00319 
00320 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
00321   MachineBasicBlock::iterator I = MBB.end();
00322   if (I == MBB.begin()) return 0;
00323   --I;
00324   unsigned Opc1 = I->getOpcode();
00325   switch (Opc1) {
00326     case Hexagon::J2_jump:
00327     case Hexagon::J2_jumpt:
00328     case Hexagon::J2_jumpf:
00329     case Hexagon::ENDLOOP0:
00330       I->eraseFromParent();
00331       break;
00332     default:
00333       return 0;
00334   }
00335 
00336   I = MBB.end();
00337 
00338   if (I == MBB.begin()) return 1;
00339   --I;
00340   unsigned Opc2 = I->getOpcode();
00341   switch (Opc2) {
00342     case Hexagon::J2_jumpt:
00343     case Hexagon::J2_jumpf:
00344     case Hexagon::ENDLOOP0:
00345       I->eraseFromParent();
00346       return 2;
00347     default:
00348       return 1;
00349   }
00350 }
00351 
00352 
00353 /// \brief For a comparison instruction, return the source registers in
00354 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
00355 /// compares against in CmpValue. Return true if the comparison instruction
00356 /// can be analyzed.
00357 bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
00358                                       unsigned &SrcReg, unsigned &SrcReg2,
00359                                       int &Mask, int &Value) const {
00360   unsigned Opc = MI->getOpcode();
00361 
00362   // Set mask and the first source register.
00363   switch (Opc) {
00364     case Hexagon::C2_cmpeqp:
00365     case Hexagon::C2_cmpeqi:
00366     case Hexagon::C2_cmpeq:
00367     case Hexagon::C2_cmpgtp:
00368     case Hexagon::C2_cmpgtup:
00369     case Hexagon::C2_cmpgtui:
00370     case Hexagon::C2_cmpgtu:
00371     case Hexagon::C2_cmpgti:
00372     case Hexagon::C2_cmpgt:
00373       SrcReg = MI->getOperand(1).getReg();
00374       Mask = ~0;
00375       break;
00376     case Hexagon::A4_cmpbeqi:
00377     case Hexagon::A4_cmpbeq:
00378     case Hexagon::A4_cmpbgtui:
00379     case Hexagon::A4_cmpbgtu:
00380     case Hexagon::A4_cmpbgt:
00381       SrcReg = MI->getOperand(1).getReg();
00382       Mask = 0xFF;
00383       break;
00384     case Hexagon::A4_cmpheqi:
00385     case Hexagon::A4_cmpheq:
00386     case Hexagon::A4_cmphgtui:
00387     case Hexagon::A4_cmphgtu:
00388     case Hexagon::A4_cmphgt:
00389       SrcReg = MI->getOperand(1).getReg();
00390       Mask = 0xFFFF;
00391       break;
00392   }
00393 
00394   // Set the value/second source register.
00395   switch (Opc) {
00396     case Hexagon::C2_cmpeqp:
00397     case Hexagon::C2_cmpeq:
00398     case Hexagon::C2_cmpgtp:
00399     case Hexagon::C2_cmpgtup:
00400     case Hexagon::C2_cmpgtu:
00401     case Hexagon::C2_cmpgt:
00402     case Hexagon::A4_cmpbeq:
00403     case Hexagon::A4_cmpbgtu:
00404     case Hexagon::A4_cmpbgt:
00405     case Hexagon::A4_cmpheq:
00406     case Hexagon::A4_cmphgtu:
00407     case Hexagon::A4_cmphgt:
00408       SrcReg2 = MI->getOperand(2).getReg();
00409       return true;
00410 
00411     case Hexagon::C2_cmpeqi:
00412     case Hexagon::C2_cmpgtui:
00413     case Hexagon::C2_cmpgti:
00414     case Hexagon::A4_cmpbeqi:
00415     case Hexagon::A4_cmpbgtui:
00416     case Hexagon::A4_cmpheqi:
00417     case Hexagon::A4_cmphgtui:
00418       SrcReg2 = 0;
00419       Value = MI->getOperand(2).getImm();
00420       return true;
00421   }
00422 
00423   return false;
00424 }
00425 
00426 
00427 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
00428                                  MachineBasicBlock::iterator I, DebugLoc DL,
00429                                  unsigned DestReg, unsigned SrcReg,
00430                                  bool KillSrc) const {
00431   if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
00432     BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg).addReg(SrcReg);
00433     return;
00434   }
00435   if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
00436     BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg).addReg(SrcReg);
00437     return;
00438   }
00439   if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
00440     // Map Pd = Ps to Pd = or(Ps, Ps).
00441     BuildMI(MBB, I, DL, get(Hexagon::C2_or),
00442             DestReg).addReg(SrcReg).addReg(SrcReg);
00443     return;
00444   }
00445   if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
00446       Hexagon::IntRegsRegClass.contains(SrcReg)) {
00447     // We can have an overlap between single and double reg: r1:0 = r0.
00448     if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
00449         // r1:0 = r0
00450         BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
00451                 Hexagon::subreg_hireg))).addImm(0);
00452     } else {
00453         // r1:0 = r1 or no overlap.
00454         BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), (RI.getSubReg(DestReg,
00455                 Hexagon::subreg_loreg))).addReg(SrcReg);
00456         BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
00457                 Hexagon::subreg_hireg))).addImm(0);
00458     }
00459     return;
00460   }
00461   if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
00462       Hexagon::IntRegsRegClass.contains(SrcReg)) {
00463     BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg).addReg(SrcReg);
00464     return;
00465   }
00466   if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
00467       Hexagon::IntRegsRegClass.contains(DestReg)) {
00468     BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg).
00469       addReg(SrcReg, getKillRegState(KillSrc));
00470     return;
00471   }
00472   if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
00473       Hexagon::PredRegsRegClass.contains(DestReg)) {
00474     BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg).
00475       addReg(SrcReg, getKillRegState(KillSrc));
00476     return;
00477   }
00478 
00479   llvm_unreachable("Unimplemented");
00480 }
00481 
00482 
00483 void HexagonInstrInfo::
00484 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
00485                     unsigned SrcReg, bool isKill, int FI,
00486                     const TargetRegisterClass *RC,
00487                     const TargetRegisterInfo *TRI) const {
00488 
00489   DebugLoc DL = MBB.findDebugLoc(I);
00490   MachineFunction &MF = *MBB.getParent();
00491   MachineFrameInfo &MFI = *MF.getFrameInfo();
00492   unsigned Align = MFI.getObjectAlignment(FI);
00493 
00494   MachineMemOperand *MMO =
00495       MF.getMachineMemOperand(
00496                       MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
00497                       MachineMemOperand::MOStore,
00498                       MFI.getObjectSize(FI),
00499                       Align);
00500 
00501   if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
00502     BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
00503           .addFrameIndex(FI).addImm(0)
00504           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00505   } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
00506     BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
00507           .addFrameIndex(FI).addImm(0)
00508           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00509   } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
00510     BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
00511           .addFrameIndex(FI).addImm(0)
00512           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00513   } else {
00514     llvm_unreachable("Unimplemented");
00515   }
00516 }
00517 
00518 
00519 void HexagonInstrInfo::storeRegToAddr(
00520                                  MachineFunction &MF, unsigned SrcReg,
00521                                  bool isKill,
00522                                  SmallVectorImpl<MachineOperand> &Addr,
00523                                  const TargetRegisterClass *RC,
00524                                  SmallVectorImpl<MachineInstr*> &NewMIs) const
00525 {
00526   llvm_unreachable("Unimplemented");
00527 }
00528 
00529 
00530 void HexagonInstrInfo::
00531 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
00532                      unsigned DestReg, int FI,
00533                      const TargetRegisterClass *RC,
00534                      const TargetRegisterInfo *TRI) const {
00535   DebugLoc DL = MBB.findDebugLoc(I);
00536   MachineFunction &MF = *MBB.getParent();
00537   MachineFrameInfo &MFI = *MF.getFrameInfo();
00538   unsigned Align = MFI.getObjectAlignment(FI);
00539 
00540   MachineMemOperand *MMO =
00541       MF.getMachineMemOperand(
00542                       MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
00543                       MachineMemOperand::MOLoad,
00544                       MFI.getObjectSize(FI),
00545                       Align);
00546   if (RC == &Hexagon::IntRegsRegClass) {
00547     BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
00548           .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00549   } else if (RC == &Hexagon::DoubleRegsRegClass) {
00550     BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
00551           .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00552   } else if (RC == &Hexagon::PredRegsRegClass) {
00553     BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
00554           .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00555   } else {
00556     llvm_unreachable("Can't store this register to stack slot");
00557   }
00558 }
00559 
00560 
00561 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
00562                                         SmallVectorImpl<MachineOperand> &Addr,
00563                                         const TargetRegisterClass *RC,
00564                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
00565   llvm_unreachable("Unimplemented");
00566 }
00567 bool
00568 HexagonInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
00569   const HexagonRegisterInfo &TRI = getRegisterInfo();
00570   MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
00571   MachineBasicBlock &MBB = *MI->getParent();
00572   DebugLoc DL = MI->getDebugLoc();
00573   unsigned Opc = MI->getOpcode();
00574 
00575   switch (Opc) {
00576     case Hexagon::ALIGNA:
00577       BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI->getOperand(0).getReg())
00578           .addReg(TRI.getFrameRegister())
00579           .addImm(-MI->getOperand(1).getImm());
00580       MBB.erase(MI);
00581       return true;
00582     case Hexagon::TFR_PdTrue: {
00583       unsigned Reg = MI->getOperand(0).getReg();
00584       BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
00585         .addReg(Reg, RegState::Undef)
00586         .addReg(Reg, RegState::Undef);
00587       MBB.erase(MI);
00588       return true;
00589     }
00590     case Hexagon::TFR_PdFalse: {
00591       unsigned Reg = MI->getOperand(0).getReg();
00592       BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
00593         .addReg(Reg, RegState::Undef)
00594         .addReg(Reg, RegState::Undef);
00595       MBB.erase(MI);
00596       return true;
00597     }
00598     case Hexagon::VMULW: {
00599       // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
00600       unsigned DstReg = MI->getOperand(0).getReg();
00601       unsigned Src1Reg = MI->getOperand(1).getReg();
00602       unsigned Src2Reg = MI->getOperand(2).getReg();
00603       unsigned Src1SubHi = TRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
00604       unsigned Src1SubLo = TRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
00605       unsigned Src2SubHi = TRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
00606       unsigned Src2SubLo = TRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
00607       BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
00608               TRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
00609           .addReg(Src2SubHi);
00610       BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
00611               TRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
00612           .addReg(Src2SubLo);
00613       MBB.erase(MI);
00614       MRI.clearKillFlags(Src1SubHi);
00615       MRI.clearKillFlags(Src1SubLo);
00616       MRI.clearKillFlags(Src2SubHi);
00617       MRI.clearKillFlags(Src2SubLo);
00618       return true;
00619     }
00620     case Hexagon::VMULW_ACC: {
00621       // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
00622       unsigned DstReg = MI->getOperand(0).getReg();
00623       unsigned Src1Reg = MI->getOperand(1).getReg();
00624       unsigned Src2Reg = MI->getOperand(2).getReg();
00625       unsigned Src3Reg = MI->getOperand(3).getReg();
00626       unsigned Src1SubHi = TRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
00627       unsigned Src1SubLo = TRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
00628       unsigned Src2SubHi = TRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
00629       unsigned Src2SubLo = TRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
00630       unsigned Src3SubHi = TRI.getSubReg(Src3Reg, Hexagon::subreg_hireg);
00631       unsigned Src3SubLo = TRI.getSubReg(Src3Reg, Hexagon::subreg_loreg);
00632       BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
00633               TRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
00634           .addReg(Src2SubHi).addReg(Src3SubHi);
00635       BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
00636               TRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
00637           .addReg(Src2SubLo).addReg(Src3SubLo);
00638       MBB.erase(MI);
00639       MRI.clearKillFlags(Src1SubHi);
00640       MRI.clearKillFlags(Src1SubLo);
00641       MRI.clearKillFlags(Src2SubHi);
00642       MRI.clearKillFlags(Src2SubLo);
00643       MRI.clearKillFlags(Src3SubHi);
00644       MRI.clearKillFlags(Src3SubLo);
00645       return true;
00646     }
00647     case Hexagon::TCRETURNi:
00648       MI->setDesc(get(Hexagon::J2_jump));
00649       return true;
00650     case Hexagon::TCRETURNr:
00651       MI->setDesc(get(Hexagon::J2_jumpr));
00652       return true;
00653   }
00654 
00655   return false;
00656 }
00657 
00658 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
00659                                                       MachineInstr *MI,
00660                                                       ArrayRef<unsigned> Ops,
00661                                                       int FI) const {
00662   // Hexagon_TODO: Implement.
00663   return nullptr;
00664 }
00665 
00666 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
00667 
00668   MachineRegisterInfo &RegInfo = MF->getRegInfo();
00669   const TargetRegisterClass *TRC;
00670   if (VT == MVT::i1) {
00671     TRC = &Hexagon::PredRegsRegClass;
00672   } else if (VT == MVT::i32 || VT == MVT::f32) {
00673     TRC = &Hexagon::IntRegsRegClass;
00674   } else if (VT == MVT::i64 || VT == MVT::f64) {
00675     TRC = &Hexagon::DoubleRegsRegClass;
00676   } else {
00677     llvm_unreachable("Cannot handle this register class");
00678   }
00679 
00680   unsigned NewReg = RegInfo.createVirtualRegister(TRC);
00681   return NewReg;
00682 }
00683 
00684 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
00685   const MCInstrDesc &MID = MI->getDesc();
00686   const uint64_t F = MID.TSFlags;
00687   if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
00688     return true;
00689 
00690   // TODO: This is largely obsolete now. Will need to be removed
00691   // in consecutive patches.
00692   switch(MI->getOpcode()) {
00693     // TFR_FI Remains a special case.
00694     case Hexagon::TFR_FI:
00695       return true;
00696     default:
00697       return false;
00698   }
00699   return  false;
00700 }
00701 
00702 // This returns true in two cases:
00703 // - The OP code itself indicates that this is an extended instruction.
00704 // - One of MOs has been marked with HMOTF_ConstExtended flag.
00705 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
00706   // First check if this is permanently extended op code.
00707   const uint64_t F = MI->getDesc().TSFlags;
00708   if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
00709     return true;
00710   // Use MO operand flags to determine if one of MI's operands
00711   // has HMOTF_ConstExtended flag set.
00712   for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
00713        E = MI->operands_end(); I != E; ++I) {
00714     if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
00715       return true;
00716   }
00717   return  false;
00718 }
00719 
00720 bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const {
00721   return MI->getDesc().isBranch();
00722 }
00723 
00724 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
00725   if (isNewValueJump(MI))
00726     return true;
00727 
00728   if (isNewValueStore(MI))
00729     return true;
00730 
00731   return false;
00732 }
00733 
00734 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
00735   return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
00736 }
00737 
00738 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
00739   bool isPred = MI->getDesc().isPredicable();
00740 
00741   if (!isPred)
00742     return false;
00743 
00744   const int Opc = MI->getOpcode();
00745 
00746   switch(Opc) {
00747   case Hexagon::A2_tfrsi:
00748     return (isOperandExtended(MI, 1) && isConstExtended(MI)) || isInt<12>(MI->getOperand(1).getImm());
00749 
00750   case Hexagon::S2_storerd_io:
00751     return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
00752 
00753   case Hexagon::S2_storeri_io:
00754   case Hexagon::S2_storerinew_io:
00755     return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
00756 
00757   case Hexagon::S2_storerh_io:
00758   case Hexagon::S2_storerhnew_io:
00759     return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
00760 
00761   case Hexagon::S2_storerb_io:
00762   case Hexagon::S2_storerbnew_io:
00763     return isUInt<6>(MI->getOperand(1).getImm());
00764 
00765   case Hexagon::L2_loadrd_io:
00766     return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
00767 
00768   case Hexagon::L2_loadri_io:
00769     return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
00770 
00771   case Hexagon::L2_loadrh_io:
00772   case Hexagon::L2_loadruh_io:
00773     return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
00774 
00775   case Hexagon::L2_loadrb_io:
00776   case Hexagon::L2_loadrub_io:
00777     return isUInt<6>(MI->getOperand(2).getImm());
00778 
00779   case Hexagon::L2_loadrd_pi:
00780     return isShiftedInt<4,3>(MI->getOperand(3).getImm());
00781 
00782   case Hexagon::L2_loadri_pi:
00783     return isShiftedInt<4,2>(MI->getOperand(3).getImm());
00784 
00785   case Hexagon::L2_loadrh_pi:
00786   case Hexagon::L2_loadruh_pi:
00787     return isShiftedInt<4,1>(MI->getOperand(3).getImm());
00788 
00789   case Hexagon::L2_loadrb_pi:
00790   case Hexagon::L2_loadrub_pi:
00791     return isInt<4>(MI->getOperand(3).getImm());
00792 
00793   case Hexagon::S4_storeirb_io:
00794   case Hexagon::S4_storeirh_io:
00795   case Hexagon::S4_storeiri_io:
00796     return (isUInt<6>(MI->getOperand(1).getImm()) &&
00797             isInt<6>(MI->getOperand(2).getImm()));
00798 
00799   case Hexagon::A2_addi:
00800     return isInt<8>(MI->getOperand(2).getImm());
00801 
00802   case Hexagon::A2_aslh:
00803   case Hexagon::A2_asrh:
00804   case Hexagon::A2_sxtb:
00805   case Hexagon::A2_sxth:
00806   case Hexagon::A2_zxtb:
00807   case Hexagon::A2_zxth:
00808     return true;
00809   }
00810 
00811   return true;
00812 }
00813 
00814 // This function performs the following inversiones:
00815 //
00816 //  cPt    ---> cNotPt
00817 //  cNotPt ---> cPt
00818 //
00819 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
00820   int InvPredOpcode;
00821   InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
00822                                         : Hexagon::getTruePredOpcode(Opc);
00823   if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
00824     return InvPredOpcode;
00825 
00826   switch(Opc) {
00827     default: llvm_unreachable("Unexpected predicated instruction");
00828     case Hexagon::C2_ccombinewt:
00829       return Hexagon::C2_ccombinewf;
00830     case Hexagon::C2_ccombinewf:
00831       return Hexagon::C2_ccombinewt;
00832 
00833       // Dealloc_return.
00834     case Hexagon::L4_return_t:
00835       return Hexagon::L4_return_f;
00836     case Hexagon::L4_return_f:
00837       return Hexagon::L4_return_t;
00838   }
00839 }
00840 
00841 // New Value Store instructions.
00842 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
00843   const uint64_t F = MI->getDesc().TSFlags;
00844 
00845   return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
00846 }
00847 
00848 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
00849   const uint64_t F = get(Opcode).TSFlags;
00850 
00851   return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
00852 }
00853 
00854 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
00855   enum Hexagon::PredSense inPredSense;
00856   inPredSense = invertPredicate ? Hexagon::PredSense_false :
00857                                   Hexagon::PredSense_true;
00858   int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
00859   if (CondOpcode >= 0) // Valid Conditional opcode/instruction
00860     return CondOpcode;
00861 
00862   // This switch case will be removed once all the instructions have been
00863   // modified to use relation maps.
00864   switch(Opc) {
00865   case Hexagon::TFRI_f:
00866     return !invertPredicate ? Hexagon::TFRI_cPt_f :
00867                               Hexagon::TFRI_cNotPt_f;
00868   case Hexagon::A2_combinew:
00869     return !invertPredicate ? Hexagon::C2_ccombinewt :
00870                               Hexagon::C2_ccombinewf;
00871 
00872   // DEALLOC_RETURN.
00873   case Hexagon::L4_return:
00874     return !invertPredicate ? Hexagon::L4_return_t:
00875                               Hexagon::L4_return_f;
00876   }
00877   llvm_unreachable("Unexpected predicable instruction");
00878 }
00879 
00880 
00881 bool HexagonInstrInfo::
00882 PredicateInstruction(MachineInstr *MI,
00883                      const SmallVectorImpl<MachineOperand> &Cond) const {
00884   int Opc = MI->getOpcode();
00885   assert (isPredicable(MI) && "Expected predicable instruction");
00886   bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
00887                      (Cond[0].getImm() == 0));
00888 
00889   // This will change MI's opcode to its predicate version.
00890   // However, its operand list is still the old one, i.e. the
00891   // non-predicate one.
00892   MI->setDesc(get(getCondOpcode(Opc, invertJump)));
00893 
00894   int oper = -1;
00895   unsigned int GAIdx = 0;
00896 
00897   // Indicates whether the current MI has a GlobalAddress operand
00898   bool hasGAOpnd = false;
00899   std::vector<MachineOperand> tmpOpnds;
00900 
00901   // Indicates whether we need to shift operands to right.
00902   bool needShift = true;
00903 
00904   // The predicate is ALWAYS the FIRST input operand !!!
00905   if (MI->getNumOperands() == 0) {
00906     // The non-predicate version of MI does not take any operands,
00907     // i.e. no outs and no ins. In this condition, the predicate
00908     // operand will be directly placed at Operands[0]. No operand
00909     // shift is needed.
00910     // Example: BARRIER
00911     needShift = false;
00912     oper = -1;
00913   }
00914   else if (   MI->getOperand(MI->getNumOperands()-1).isReg()
00915            && MI->getOperand(MI->getNumOperands()-1).isDef()
00916            && !MI->getOperand(MI->getNumOperands()-1).isImplicit()) {
00917     // The non-predicate version of MI does not have any input operands.
00918     // In this condition, we extend the length of Operands[] by one and
00919     // copy the original last operand to the newly allocated slot.
00920     // At this moment, it is just a place holder. Later, we will put
00921     // predicate operand directly into it. No operand shift is needed.
00922     // Example: r0=BARRIER (this is a faked insn used here for illustration)
00923     MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
00924     needShift = false;
00925     oper = MI->getNumOperands() - 2;
00926   }
00927   else {
00928     // We need to right shift all input operands by one. Duplicate the
00929     // last operand into the newly allocated slot.
00930     MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
00931   }
00932 
00933   if (needShift)
00934   {
00935     // Operands[ MI->getNumOperands() - 2 ] has been copied into
00936     // Operands[ MI->getNumOperands() - 1 ], so we start from
00937     // Operands[ MI->getNumOperands() - 3 ].
00938     // oper is a signed int.
00939     // It is ok if "MI->getNumOperands()-3" is -3, -2, or -1.
00940     for (oper = MI->getNumOperands() - 3; oper >= 0; --oper)
00941     {
00942       MachineOperand &MO = MI->getOperand(oper);
00943 
00944       // Opnd[0] Opnd[1] Opnd[2] Opnd[3] Opnd[4]   Opnd[5]   Opnd[6]   Opnd[7]
00945       // <Def0>  <Def1>  <Use0>  <Use1>  <ImpDef0> <ImpDef1> <ImpUse0> <ImpUse1>
00946       //               /\~
00947       //              /||\~
00948       //               ||
00949       //        Predicate Operand here
00950       if (MO.isReg() && !MO.isUse() && !MO.isImplicit()) {
00951         break;
00952       }
00953       if (MO.isReg()) {
00954         MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
00955                                                 MO.isImplicit(), MO.isKill(),
00956                                                 MO.isDead(), MO.isUndef(),
00957                                                 MO.isDebug());
00958       }
00959       else if (MO.isImm()) {
00960         MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
00961       }
00962       else if (MO.isGlobal()) {
00963         // MI can not have more than one GlobalAddress operand.
00964         assert(hasGAOpnd == false && "MI can only have one GlobalAddress opnd");
00965 
00966         // There is no member function called "ChangeToGlobalAddress" in the
00967         // MachineOperand class (not like "ChangeToRegister" and
00968         // "ChangeToImmediate"). So we have to remove them from Operands[] list
00969         // first, and then add them back after we have inserted the predicate
00970         // operand. tmpOpnds[] is to remember these operands before we remove
00971         // them.
00972         tmpOpnds.push_back(MO);
00973 
00974         // Operands[oper] is a GlobalAddress operand;
00975         // Operands[oper+1] has been copied into Operands[oper+2];
00976         hasGAOpnd = true;
00977         GAIdx = oper;
00978         continue;
00979       }
00980       else {
00981         llvm_unreachable("Unexpected operand type");
00982       }
00983     }
00984   }
00985 
00986   int regPos = invertJump ? 1 : 0;
00987   MachineOperand PredMO = Cond[regPos];
00988 
00989   // [oper] now points to the last explicit Def. Predicate operand must be
00990   // located at [oper+1]. See diagram above.
00991   // This assumes that the predicate is always the first operand,
00992   // i.e. Operands[0+numResults], in the set of inputs
00993   // It is better to have an assert here to check this. But I don't know how
00994   // to write this assert because findFirstPredOperandIdx() would return -1
00995   if (oper < -1) oper = -1;
00996 
00997   MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
00998                                           PredMO.isImplicit(), false,
00999                                           PredMO.isDead(), PredMO.isUndef(),
01000                                           PredMO.isDebug());
01001 
01002   MachineRegisterInfo &RegInfo = MI->getParent()->getParent()->getRegInfo();
01003   RegInfo.clearKillFlags(PredMO.getReg());
01004 
01005   if (hasGAOpnd)
01006   {
01007     unsigned int i;
01008 
01009     // Operands[GAIdx] is the original GlobalAddress operand, which is
01010     // already copied into tmpOpnds[0].
01011     // Operands[GAIdx] now stores a copy of Operands[GAIdx-1]
01012     // Operands[GAIdx+1] has already been copied into Operands[GAIdx+2],
01013     // so we start from [GAIdx+2]
01014     for (i = GAIdx + 2; i < MI->getNumOperands(); ++i)
01015       tmpOpnds.push_back(MI->getOperand(i));
01016 
01017     // Remove all operands in range [ (GAIdx+1) ... (MI->getNumOperands()-1) ]
01018     // It is very important that we always remove from the end of Operands[]
01019     // MI->getNumOperands() is at least 2 if program goes to here.
01020     for (i = MI->getNumOperands() - 1; i > GAIdx; --i)
01021       MI->RemoveOperand(i);
01022 
01023     for (i = 0; i < tmpOpnds.size(); ++i)
01024       MI->addOperand(tmpOpnds[i]);
01025   }
01026 
01027   return true;
01028 }
01029 
01030 
01031 bool
01032 HexagonInstrInfo::
01033 isProfitableToIfCvt(MachineBasicBlock &MBB,
01034                     unsigned NumCycles,
01035                     unsigned ExtraPredCycles,
01036                     const BranchProbability &Probability) const {
01037   return true;
01038 }
01039 
01040 
01041 bool
01042 HexagonInstrInfo::
01043 isProfitableToIfCvt(MachineBasicBlock &TMBB,
01044                     unsigned NumTCycles,
01045                     unsigned ExtraTCycles,
01046                     MachineBasicBlock &FMBB,
01047                     unsigned NumFCycles,
01048                     unsigned ExtraFCycles,
01049                     const BranchProbability &Probability) const {
01050   return true;
01051 }
01052 
01053 // Returns true if an instruction is predicated irrespective of the predicate
01054 // sense. For example, all of the following will return true.
01055 // if (p0) R1 = add(R2, R3)
01056 // if (!p0) R1 = add(R2, R3)
01057 // if (p0.new) R1 = add(R2, R3)
01058 // if (!p0.new) R1 = add(R2, R3)
01059 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
01060   const uint64_t F = MI->getDesc().TSFlags;
01061 
01062   return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
01063 }
01064 
01065 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
01066   const uint64_t F = get(Opcode).TSFlags;
01067 
01068   return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
01069 }
01070 
01071 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
01072   const uint64_t F = MI->getDesc().TSFlags;
01073 
01074   assert(isPredicated(MI));
01075   return (!((F >> HexagonII::PredicatedFalsePos) &
01076             HexagonII::PredicatedFalseMask));
01077 }
01078 
01079 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
01080   const uint64_t F = get(Opcode).TSFlags;
01081 
01082   // Make sure that the instruction is predicated.
01083   assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
01084   return (!((F >> HexagonII::PredicatedFalsePos) &
01085             HexagonII::PredicatedFalseMask));
01086 }
01087 
01088 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
01089   const uint64_t F = MI->getDesc().TSFlags;
01090 
01091   assert(isPredicated(MI));
01092   return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
01093 }
01094 
01095 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
01096   const uint64_t F = get(Opcode).TSFlags;
01097 
01098   assert(isPredicated(Opcode));
01099   return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
01100 }
01101 
01102 // Returns true, if a ST insn can be promoted to a new-value store.
01103 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const {
01104   const uint64_t F = MI->getDesc().TSFlags;
01105 
01106   return ((F >> HexagonII::mayNVStorePos) &
01107            HexagonII::mayNVStoreMask);
01108 }
01109 
01110 bool
01111 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
01112                                    std::vector<MachineOperand> &Pred) const {
01113   for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
01114     MachineOperand MO = MI->getOperand(oper);
01115     if (MO.isReg() && MO.isDef()) {
01116       const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
01117       if (RC == &Hexagon::PredRegsRegClass) {
01118         Pred.push_back(MO);
01119         return true;
01120       }
01121     }
01122   }
01123   return false;
01124 }
01125 
01126 
01127 bool
01128 HexagonInstrInfo::
01129 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
01130                   const SmallVectorImpl<MachineOperand> &Pred2) const {
01131   // TODO: Fix this
01132   return false;
01133 }
01134 
01135 
01136 //
01137 // We indicate that we want to reverse the branch by
01138 // inserting a 0 at the beginning of the Cond vector.
01139 //
01140 bool HexagonInstrInfo::
01141 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
01142   if (!Cond.empty() && Cond[0].isMBB())
01143     return true;
01144   if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
01145     Cond.erase(Cond.begin());
01146   } else {
01147     Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
01148   }
01149   return false;
01150 }
01151 
01152 
01153 bool HexagonInstrInfo::
01154 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
01155                           const BranchProbability &Probability) const {
01156   return (NumInstrs <= 4);
01157 }
01158 
01159 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
01160   switch (MI->getOpcode()) {
01161   default: return false;
01162   case Hexagon::L4_return:
01163   case Hexagon::L4_return_t:
01164   case Hexagon::L4_return_f:
01165   case Hexagon::L4_return_tnew_pnt:
01166   case Hexagon::L4_return_fnew_pnt:
01167   case Hexagon::L4_return_tnew_pt:
01168   case Hexagon::L4_return_fnew_pt:
01169    return true;
01170   }
01171 }
01172 
01173 
01174 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
01175       bool Extend) const {
01176   // This function is to check whether the "Offset" is in the correct range of
01177   // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
01178   // inserted to calculate the final address. Due to this reason, the function
01179   // assumes that the "Offset" has correct alignment.
01180   // We used to assert if the offset was not properly aligned, however,
01181   // there are cases where a misaligned pointer recast can cause this
01182   // problem, and we need to allow for it. The front end warns of such
01183   // misaligns with respect to load size.
01184 
01185   switch (Opcode) {
01186   case Hexagon::J2_loop0i:
01187   case Hexagon::J2_loop1i:
01188     return isUInt<10>(Offset);
01189   }
01190 
01191   if (Extend)
01192     return true;
01193 
01194   switch (Opcode) {
01195   case Hexagon::L2_loadri_io:
01196   case Hexagon::S2_storeri_io:
01197     return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
01198       (Offset <= Hexagon_MEMW_OFFSET_MAX);
01199 
01200   case Hexagon::L2_loadrd_io:
01201   case Hexagon::S2_storerd_io:
01202     return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
01203       (Offset <= Hexagon_MEMD_OFFSET_MAX);
01204 
01205   case Hexagon::L2_loadrh_io:
01206   case Hexagon::L2_loadruh_io:
01207   case Hexagon::S2_storerh_io:
01208     return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
01209       (Offset <= Hexagon_MEMH_OFFSET_MAX);
01210 
01211   case Hexagon::L2_loadrb_io:
01212   case Hexagon::S2_storerb_io:
01213   case Hexagon::L2_loadrub_io:
01214     return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
01215       (Offset <= Hexagon_MEMB_OFFSET_MAX);
01216 
01217   case Hexagon::A2_addi:
01218     return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
01219       (Offset <= Hexagon_ADDI_OFFSET_MAX);
01220 
01221   case Hexagon::L4_iadd_memopw_io:
01222   case Hexagon::L4_isub_memopw_io:
01223   case Hexagon::L4_add_memopw_io:
01224   case Hexagon::L4_sub_memopw_io:
01225   case Hexagon::L4_and_memopw_io:
01226   case Hexagon::L4_or_memopw_io:
01227     return (0 <= Offset && Offset <= 255);
01228 
01229   case Hexagon::L4_iadd_memoph_io:
01230   case Hexagon::L4_isub_memoph_io:
01231   case Hexagon::L4_add_memoph_io:
01232   case Hexagon::L4_sub_memoph_io:
01233   case Hexagon::L4_and_memoph_io:
01234   case Hexagon::L4_or_memoph_io:
01235     return (0 <= Offset && Offset <= 127);
01236 
01237   case Hexagon::L4_iadd_memopb_io:
01238   case Hexagon::L4_isub_memopb_io:
01239   case Hexagon::L4_add_memopb_io:
01240   case Hexagon::L4_sub_memopb_io:
01241   case Hexagon::L4_and_memopb_io:
01242   case Hexagon::L4_or_memopb_io:
01243     return (0 <= Offset && Offset <= 63);
01244 
01245   // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
01246   // any size. Later pass knows how to handle it.
01247   case Hexagon::STriw_pred:
01248   case Hexagon::LDriw_pred:
01249     return true;
01250 
01251   case Hexagon::TFR_FI:
01252   case Hexagon::TFR_FIA:
01253   case Hexagon::INLINEASM:
01254     return true;
01255   }
01256 
01257   llvm_unreachable("No offset range is defined for this opcode. "
01258                    "Please define it in the above switch statement!");
01259 }
01260 
01261 
01262 //
01263 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
01264 //
01265 bool HexagonInstrInfo::
01266 isValidAutoIncImm(const EVT VT, const int Offset) const {
01267 
01268   if (VT == MVT::i64) {
01269       return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
01270               Offset <= Hexagon_MEMD_AUTOINC_MAX &&
01271               (Offset & 0x7) == 0);
01272   }
01273   if (VT == MVT::i32) {
01274       return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
01275               Offset <= Hexagon_MEMW_AUTOINC_MAX &&
01276               (Offset & 0x3) == 0);
01277   }
01278   if (VT == MVT::i16) {
01279       return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
01280               Offset <= Hexagon_MEMH_AUTOINC_MAX &&
01281               (Offset & 0x1) == 0);
01282   }
01283   if (VT == MVT::i8) {
01284       return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
01285               Offset <= Hexagon_MEMB_AUTOINC_MAX);
01286   }
01287   llvm_unreachable("Not an auto-inc opc!");
01288 }
01289 
01290 
01291 bool HexagonInstrInfo::
01292 isMemOp(const MachineInstr *MI) const {
01293 //  return MI->getDesc().mayLoad() && MI->getDesc().mayStore();
01294 
01295   switch (MI->getOpcode())
01296   {
01297   default: return false;
01298   case Hexagon::L4_iadd_memopw_io:
01299   case Hexagon::L4_isub_memopw_io:
01300   case Hexagon::L4_add_memopw_io:
01301   case Hexagon::L4_sub_memopw_io:
01302   case Hexagon::L4_and_memopw_io:
01303   case Hexagon::L4_or_memopw_io:
01304   case Hexagon::L4_iadd_memoph_io:
01305   case Hexagon::L4_isub_memoph_io:
01306   case Hexagon::L4_add_memoph_io:
01307   case Hexagon::L4_sub_memoph_io:
01308   case Hexagon::L4_and_memoph_io:
01309   case Hexagon::L4_or_memoph_io:
01310   case Hexagon::L4_iadd_memopb_io:
01311   case Hexagon::L4_isub_memopb_io:
01312   case Hexagon::L4_add_memopb_io:
01313   case Hexagon::L4_sub_memopb_io:
01314   case Hexagon::L4_and_memopb_io:
01315   case Hexagon::L4_or_memopb_io:
01316   case Hexagon::L4_ior_memopb_io:
01317   case Hexagon::L4_ior_memoph_io:
01318   case Hexagon::L4_ior_memopw_io:
01319   case Hexagon::L4_iand_memopb_io:
01320   case Hexagon::L4_iand_memoph_io:
01321   case Hexagon::L4_iand_memopw_io:
01322     return true;
01323   }
01324   return false;
01325 }
01326 
01327 
01328 bool HexagonInstrInfo::
01329 isSpillPredRegOp(const MachineInstr *MI) const {
01330   switch (MI->getOpcode()) {
01331     default: return false;
01332     case Hexagon::STriw_pred :
01333     case Hexagon::LDriw_pred :
01334       return true;
01335   }
01336 }
01337 
01338 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
01339   switch (MI->getOpcode()) {
01340     default: return false;
01341     case Hexagon::C2_cmpeq:
01342     case Hexagon::C2_cmpeqi:
01343     case Hexagon::C2_cmpgt:
01344     case Hexagon::C2_cmpgti:
01345     case Hexagon::C2_cmpgtu:
01346     case Hexagon::C2_cmpgtui:
01347       return true;
01348   }
01349 }
01350 
01351 bool HexagonInstrInfo::
01352 isConditionalTransfer (const MachineInstr *MI) const {
01353   switch (MI->getOpcode()) {
01354     default: return false;
01355     case Hexagon::A2_tfrt:
01356     case Hexagon::A2_tfrf:
01357     case Hexagon::C2_cmoveit:
01358     case Hexagon::C2_cmoveif:
01359     case Hexagon::A2_tfrtnew:
01360     case Hexagon::A2_tfrfnew:
01361     case Hexagon::C2_cmovenewit:
01362     case Hexagon::C2_cmovenewif:
01363       return true;
01364   }
01365 }
01366 
01367 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
01368   switch (MI->getOpcode())
01369   {
01370     default: return false;
01371     case Hexagon::A2_paddf:
01372     case Hexagon::A2_paddfnew:
01373     case Hexagon::A2_paddt:
01374     case Hexagon::A2_paddtnew:
01375     case Hexagon::A2_pandf:
01376     case Hexagon::A2_pandfnew:
01377     case Hexagon::A2_pandt:
01378     case Hexagon::A2_pandtnew:
01379     case Hexagon::A4_paslhf:
01380     case Hexagon::A4_paslhfnew:
01381     case Hexagon::A4_paslht:
01382     case Hexagon::A4_paslhtnew:
01383     case Hexagon::A4_pasrhf:
01384     case Hexagon::A4_pasrhfnew:
01385     case Hexagon::A4_pasrht:
01386     case Hexagon::A4_pasrhtnew:
01387     case Hexagon::A2_porf:
01388     case Hexagon::A2_porfnew:
01389     case Hexagon::A2_port:
01390     case Hexagon::A2_portnew:
01391     case Hexagon::A2_psubf:
01392     case Hexagon::A2_psubfnew:
01393     case Hexagon::A2_psubt:
01394     case Hexagon::A2_psubtnew:
01395     case Hexagon::A2_pxorf:
01396     case Hexagon::A2_pxorfnew:
01397     case Hexagon::A2_pxort:
01398     case Hexagon::A2_pxortnew:
01399     case Hexagon::A4_psxthf:
01400     case Hexagon::A4_psxthfnew:
01401     case Hexagon::A4_psxtht:
01402     case Hexagon::A4_psxthtnew:
01403     case Hexagon::A4_psxtbf:
01404     case Hexagon::A4_psxtbfnew:
01405     case Hexagon::A4_psxtbt:
01406     case Hexagon::A4_psxtbtnew:
01407     case Hexagon::A4_pzxtbf:
01408     case Hexagon::A4_pzxtbfnew:
01409     case Hexagon::A4_pzxtbt:
01410     case Hexagon::A4_pzxtbtnew:
01411     case Hexagon::A4_pzxthf:
01412     case Hexagon::A4_pzxthfnew:
01413     case Hexagon::A4_pzxtht:
01414     case Hexagon::A4_pzxthtnew:
01415     case Hexagon::A2_paddit:
01416     case Hexagon::A2_paddif:
01417     case Hexagon::C2_ccombinewt:
01418     case Hexagon::C2_ccombinewf:
01419       return true;
01420   }
01421 }
01422 
01423 bool HexagonInstrInfo::
01424 isConditionalLoad (const MachineInstr* MI) const {
01425   switch (MI->getOpcode())
01426   {
01427     default: return false;
01428     case Hexagon::L2_ploadrdt_io :
01429     case Hexagon::L2_ploadrdf_io:
01430     case Hexagon::L2_ploadrit_io:
01431     case Hexagon::L2_ploadrif_io:
01432     case Hexagon::L2_ploadrht_io:
01433     case Hexagon::L2_ploadrhf_io:
01434     case Hexagon::L2_ploadrbt_io:
01435     case Hexagon::L2_ploadrbf_io:
01436     case Hexagon::L2_ploadruht_io:
01437     case Hexagon::L2_ploadruhf_io:
01438     case Hexagon::L2_ploadrubt_io:
01439     case Hexagon::L2_ploadrubf_io:
01440     case Hexagon::L2_ploadrdt_pi:
01441     case Hexagon::L2_ploadrdf_pi:
01442     case Hexagon::L2_ploadrit_pi:
01443     case Hexagon::L2_ploadrif_pi:
01444     case Hexagon::L2_ploadrht_pi:
01445     case Hexagon::L2_ploadrhf_pi:
01446     case Hexagon::L2_ploadrbt_pi:
01447     case Hexagon::L2_ploadrbf_pi:
01448     case Hexagon::L2_ploadruht_pi:
01449     case Hexagon::L2_ploadruhf_pi:
01450     case Hexagon::L2_ploadrubt_pi:
01451     case Hexagon::L2_ploadrubf_pi:
01452     case Hexagon::L4_ploadrdt_rr:
01453     case Hexagon::L4_ploadrdf_rr:
01454     case Hexagon::L4_ploadrbt_rr:
01455     case Hexagon::L4_ploadrbf_rr:
01456     case Hexagon::L4_ploadrubt_rr:
01457     case Hexagon::L4_ploadrubf_rr:
01458     case Hexagon::L4_ploadrht_rr:
01459     case Hexagon::L4_ploadrhf_rr:
01460     case Hexagon::L4_ploadruht_rr:
01461     case Hexagon::L4_ploadruhf_rr:
01462     case Hexagon::L4_ploadrit_rr:
01463     case Hexagon::L4_ploadrif_rr:
01464       return true;
01465   }
01466 }
01467 
01468 // Returns true if an instruction is a conditional store.
01469 //
01470 // Note: It doesn't include conditional new-value stores as they can't be
01471 // converted to .new predicate.
01472 //
01473 //               p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
01474 //                ^           ^
01475 //               /             \ (not OK. it will cause new-value store to be
01476 //              /               X conditional on p0.new while R2 producer is
01477 //             /                 \ on p0)
01478 //            /                   \.
01479 //     p.new store                 p.old NV store
01480 // [if(p0.new)memw(R0+#0)=R2]    [if(p0)memw(R0+#0)=R2.new]
01481 //            ^                  ^
01482 //             \                /
01483 //              \              /
01484 //               \            /
01485 //                 p.old store
01486 //             [if (p0)memw(R0+#0)=R2]
01487 //
01488 // The above diagram shows the steps involoved in the conversion of a predicated
01489 // store instruction to its .new predicated new-value form.
01490 //
01491 // The following set of instructions further explains the scenario where
01492 // conditional new-value store becomes invalid when promoted to .new predicate
01493 // form.
01494 //
01495 // { 1) if (p0) r0 = add(r1, r2)
01496 //   2) p0 = cmp.eq(r3, #0) }
01497 //
01498 //   3) if (p0) memb(r1+#0) = r0  --> this instruction can't be grouped with
01499 // the first two instructions because in instr 1, r0 is conditional on old value
01500 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
01501 // is not valid for new-value stores.
01502 bool HexagonInstrInfo::
01503 isConditionalStore (const MachineInstr* MI) const {
01504   switch (MI->getOpcode())
01505   {
01506     default: return false;
01507     case Hexagon::S4_storeirbt_io:
01508     case Hexagon::S4_storeirbf_io:
01509     case Hexagon::S4_pstorerbt_rr:
01510     case Hexagon::S4_pstorerbf_rr:
01511     case Hexagon::S2_pstorerbt_io:
01512     case Hexagon::S2_pstorerbf_io:
01513     case Hexagon::S2_pstorerbt_pi:
01514     case Hexagon::S2_pstorerbf_pi:
01515     case Hexagon::S2_pstorerdt_io:
01516     case Hexagon::S2_pstorerdf_io:
01517     case Hexagon::S4_pstorerdt_rr:
01518     case Hexagon::S4_pstorerdf_rr:
01519     case Hexagon::S2_pstorerdt_pi:
01520     case Hexagon::S2_pstorerdf_pi:
01521     case Hexagon::S2_pstorerht_io:
01522     case Hexagon::S2_pstorerhf_io:
01523     case Hexagon::S4_storeirht_io:
01524     case Hexagon::S4_storeirhf_io:
01525     case Hexagon::S4_pstorerht_rr:
01526     case Hexagon::S4_pstorerhf_rr:
01527     case Hexagon::S2_pstorerht_pi:
01528     case Hexagon::S2_pstorerhf_pi:
01529     case Hexagon::S2_pstorerit_io:
01530     case Hexagon::S2_pstorerif_io:
01531     case Hexagon::S4_storeirit_io:
01532     case Hexagon::S4_storeirif_io:
01533     case Hexagon::S4_pstorerit_rr:
01534     case Hexagon::S4_pstorerif_rr:
01535     case Hexagon::S2_pstorerit_pi:
01536     case Hexagon::S2_pstorerif_pi:
01537 
01538     // V4 global address store before promoting to dot new.
01539     case Hexagon::S4_pstorerdt_abs:
01540     case Hexagon::S4_pstorerdf_abs:
01541     case Hexagon::S4_pstorerbt_abs:
01542     case Hexagon::S4_pstorerbf_abs:
01543     case Hexagon::S4_pstorerht_abs:
01544     case Hexagon::S4_pstorerhf_abs:
01545     case Hexagon::S4_pstorerit_abs:
01546     case Hexagon::S4_pstorerif_abs:
01547       return true;
01548 
01549     // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
01550     // from the "Conditional Store" list. Because a predicated new value store
01551     // would NOT be promoted to a double dot new store. See diagram below:
01552     // This function returns yes for those stores that are predicated but not
01553     // yet promoted to predicate dot new instructions.
01554     //
01555     //                          +---------------------+
01556     //                    /-----| if (p0) memw(..)=r0 |---------\~
01557     //                   ||     +---------------------+         ||
01558     //          promote  ||       /\       /\                   ||  promote
01559     //                   ||      /||\     /||\                  ||
01560     //                  \||/    demote     ||                  \||/
01561     //                   \/       ||       ||                   \/
01562     //       +-------------------------+   ||   +-------------------------+
01563     //       | if (p0.new) memw(..)=r0 |   ||   | if (p0) memw(..)=r0.new |
01564     //       +-------------------------+   ||   +-------------------------+
01565     //                        ||           ||         ||
01566     //                        ||         demote      \||/
01567     //                      promote        ||         \/ NOT possible
01568     //                        ||           ||         /\~
01569     //                       \||/          ||        /||\~
01570     //                        \/           ||         ||
01571     //                      +-----------------------------+
01572     //                      | if (p0.new) memw(..)=r0.new |
01573     //                      +-----------------------------+
01574     //                           Double Dot New Store
01575     //
01576   }
01577 }
01578 
01579 
01580 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
01581   if (isNewValue(MI) && isBranch(MI))
01582     return true;
01583   return false;
01584 }
01585 
01586 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
01587   return (getAddrMode(MI) == HexagonII::PostInc);
01588 }
01589 
01590 bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
01591   const uint64_t F = MI->getDesc().TSFlags;
01592   return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
01593 }
01594 
01595 // Returns true, if any one of the operands is a dot new
01596 // insn, whether it is predicated dot new or register dot new.
01597 bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
01598   return (isNewValueInst(MI) ||
01599      (isPredicated(MI) && isPredicatedNew(MI)));
01600 }
01601 
01602 // Returns the most basic instruction for the .new predicated instructions and
01603 // new-value stores.
01604 // For example, all of the following instructions will be converted back to the
01605 // same instruction:
01606 // 1) if (p0.new) memw(R0+#0) = R1.new  --->
01607 // 2) if (p0) memw(R0+#0)= R1.new      -------> if (p0) memw(R0+#0) = R1
01608 // 3) if (p0.new) memw(R0+#0) = R1      --->
01609 //
01610 
01611 int HexagonInstrInfo::GetDotOldOp(const int opc) const {
01612   int NewOp = opc;
01613   if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
01614     NewOp = Hexagon::getPredOldOpcode(NewOp);
01615     assert(NewOp >= 0 &&
01616            "Couldn't change predicate new instruction to its old form.");
01617   }
01618 
01619   if (isNewValueStore(NewOp)) { // Convert into non-new-value format
01620     NewOp = Hexagon::getNonNVStore(NewOp);
01621     assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
01622   }
01623   return NewOp;
01624 }
01625 
01626 // Return the new value instruction for a given store.
01627 int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const {
01628   int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
01629   if (NVOpcode >= 0) // Valid new-value store instruction.
01630     return NVOpcode;
01631 
01632   switch (MI->getOpcode()) {
01633   default: llvm_unreachable("Unknown .new type");
01634   case Hexagon::S4_storerb_ur:
01635     return Hexagon::S4_storerbnew_ur;
01636 
01637   case Hexagon::S4_storerh_ur:
01638     return Hexagon::S4_storerhnew_ur;
01639 
01640   case Hexagon::S4_storeri_ur:
01641     return Hexagon::S4_storerinew_ur;
01642 
01643   case Hexagon::S2_storerb_pci:
01644     return Hexagon::S2_storerb_pci;
01645 
01646   case Hexagon::S2_storeri_pci:
01647     return Hexagon::S2_storeri_pci;
01648 
01649   case Hexagon::S2_storerh_pci:
01650     return Hexagon::S2_storerh_pci;
01651 
01652   case Hexagon::S2_storerd_pci:
01653     return Hexagon::S2_storerd_pci;
01654 
01655   case Hexagon::S2_storerf_pci:
01656     return Hexagon::S2_storerf_pci;
01657   }
01658   return 0;
01659 }
01660 
01661 // Return .new predicate version for an instruction.
01662 int HexagonInstrInfo::GetDotNewPredOp(MachineInstr *MI,
01663                                       const MachineBranchProbabilityInfo
01664                                       *MBPI) const {
01665 
01666   int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
01667   if (NewOpcode >= 0) // Valid predicate new instruction
01668     return NewOpcode;
01669 
01670   switch (MI->getOpcode()) {
01671   default: llvm_unreachable("Unknown .new type");
01672   // Condtional Jumps
01673   case Hexagon::J2_jumpt:
01674   case Hexagon::J2_jumpf:
01675     return getDotNewPredJumpOp(MI, MBPI);
01676 
01677   case Hexagon::J2_jumprt:
01678     return Hexagon::J2_jumptnewpt;
01679 
01680   case Hexagon::J2_jumprf:
01681     return Hexagon::J2_jumprfnewpt;
01682 
01683   case Hexagon::JMPrett:
01684     return Hexagon::J2_jumprtnewpt;
01685 
01686   case Hexagon::JMPretf:
01687     return Hexagon::J2_jumprfnewpt;
01688 
01689 
01690   // Conditional combine
01691   case Hexagon::C2_ccombinewt:
01692     return Hexagon::C2_ccombinewnewt;
01693   case Hexagon::C2_ccombinewf:
01694     return Hexagon::C2_ccombinewnewf;
01695   }
01696 }
01697 
01698 
01699 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
01700   const uint64_t F = MI->getDesc().TSFlags;
01701 
01702   return((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
01703 }
01704 
01705 /// immediateExtend - Changes the instruction in place to one using an immediate
01706 /// extender.
01707 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
01708   assert((isExtendable(MI)||isConstExtended(MI)) &&
01709                                "Instruction must be extendable");
01710   // Find which operand is extendable.
01711   short ExtOpNum = getCExtOpNum(MI);
01712   MachineOperand &MO = MI->getOperand(ExtOpNum);
01713   // This needs to be something we understand.
01714   assert((MO.isMBB() || MO.isImm()) &&
01715          "Branch with unknown extendable field type");
01716   // Mark given operand as extended.
01717   MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
01718 }
01719 
01720 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
01721     const TargetSubtargetInfo &STI) const {
01722   const InstrItineraryData *II = STI.getInstrItineraryData();
01723   return static_cast<const HexagonSubtarget &>(STI).createDFAPacketizer(II);
01724 }
01725 
01726 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
01727                                             const MachineBasicBlock *MBB,
01728                                             const MachineFunction &MF) const {
01729   // Debug info is never a scheduling boundary. It's necessary to be explicit
01730   // due to the special treatment of IT instructions below, otherwise a
01731   // dbg_value followed by an IT will result in the IT instruction being
01732   // considered a scheduling hazard, which is wrong. It should be the actual
01733   // instruction preceding the dbg_value instruction(s), just like it is
01734   // when debug info is not present.
01735   if (MI->isDebugValue())
01736     return false;
01737 
01738   // Terminators and labels can't be scheduled around.
01739   if (MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm())
01740     return true;
01741 
01742   return false;
01743 }
01744 
01745 bool HexagonInstrInfo::isConstExtended(MachineInstr *MI) const {
01746   const uint64_t F = MI->getDesc().TSFlags;
01747   unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
01748   if (isExtended) // Instruction must be extended.
01749     return true;
01750 
01751   unsigned isExtendable = (F >> HexagonII::ExtendablePos)
01752                           & HexagonII::ExtendableMask;
01753   if (!isExtendable)
01754     return false;
01755 
01756   short ExtOpNum = getCExtOpNum(MI);
01757   const MachineOperand &MO = MI->getOperand(ExtOpNum);
01758   // Use MO operand flags to determine if MO
01759   // has the HMOTF_ConstExtended flag set.
01760   if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
01761     return true;
01762   // If this is a Machine BB address we are talking about, and it is
01763   // not marked as extended, say so.
01764   if (MO.isMBB())
01765     return false;
01766 
01767   // We could be using an instruction with an extendable immediate and shoehorn
01768   // a global address into it. If it is a global address it will be constant
01769   // extended. We do this for COMBINE.
01770   // We currently only handle isGlobal() because it is the only kind of
01771   // object we are going to end up with here for now.
01772   // In the future we probably should add isSymbol(), etc.
01773   if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
01774       MO.isJTI() || MO.isCPI())
01775     return true;
01776 
01777   // If the extendable operand is not 'Immediate' type, the instruction should
01778   // have 'isExtended' flag set.
01779   assert(MO.isImm() && "Extendable operand must be Immediate type");
01780 
01781   int MinValue = getMinValue(MI);
01782   int MaxValue = getMaxValue(MI);
01783   int ImmValue = MO.getImm();
01784 
01785   return (ImmValue < MinValue || ImmValue > MaxValue);
01786 }
01787 
01788 // Returns the opcode to use when converting MI, which is a conditional jump,
01789 // into a conditional instruction which uses the .new value of the predicate.
01790 // We also use branch probabilities to add a hint to the jump.
01791 int
01792 HexagonInstrInfo::getDotNewPredJumpOp(MachineInstr *MI,
01793                                   const
01794                                   MachineBranchProbabilityInfo *MBPI) const {
01795 
01796   // We assume that block can have at most two successors.
01797   bool taken = false;
01798   MachineBasicBlock *Src = MI->getParent();
01799   MachineOperand *BrTarget = &MI->getOperand(1);
01800   MachineBasicBlock *Dst = BrTarget->getMBB();
01801 
01802   const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
01803   if (Prediction >= BranchProbability(1,2))
01804     taken = true;
01805 
01806   switch (MI->getOpcode()) {
01807   case Hexagon::J2_jumpt:
01808     return taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
01809   case Hexagon::J2_jumpf:
01810     return taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
01811 
01812   default:
01813     llvm_unreachable("Unexpected jump instruction.");
01814   }
01815 }
01816 // Returns true if a particular operand is extendable for an instruction.
01817 bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
01818                                          unsigned short OperandNum) const {
01819   const uint64_t F = MI->getDesc().TSFlags;
01820 
01821   return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
01822           == OperandNum;
01823 }
01824 
01825 // Returns Operand Index for the constant extended instruction.
01826 unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
01827   const uint64_t F = MI->getDesc().TSFlags;
01828   return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
01829 }
01830 
01831 // Returns the min value that doesn't need to be extended.
01832 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
01833   const uint64_t F = MI->getDesc().TSFlags;
01834   unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
01835                     & HexagonII::ExtentSignedMask;
01836   unsigned bits =  (F >> HexagonII::ExtentBitsPos)
01837                     & HexagonII::ExtentBitsMask;
01838 
01839   if (isSigned) // if value is signed
01840     return -1U << (bits - 1);
01841   else
01842     return 0;
01843 }
01844 
01845 // Returns the max value that doesn't need to be extended.
01846 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
01847   const uint64_t F = MI->getDesc().TSFlags;
01848   unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
01849                     & HexagonII::ExtentSignedMask;
01850   unsigned bits =  (F >> HexagonII::ExtentBitsPos)
01851                     & HexagonII::ExtentBitsMask;
01852 
01853   if (isSigned) // if value is signed
01854     return ~(-1U << (bits - 1));
01855   else
01856     return ~(-1U << bits);
01857 }
01858 
01859 // Returns true if an instruction can be converted into a non-extended
01860 // equivalent instruction.
01861 bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr *MI) const {
01862 
01863   short NonExtOpcode;
01864   // Check if the instruction has a register form that uses register in place
01865   // of the extended operand, if so return that as the non-extended form.
01866   if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
01867     return true;
01868 
01869   if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
01870     // Check addressing mode and retrieve non-ext equivalent instruction.
01871 
01872     switch (getAddrMode(MI)) {
01873     case HexagonII::Absolute :
01874       // Load/store with absolute addressing mode can be converted into
01875       // base+offset mode.
01876       NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode());
01877       break;
01878     case HexagonII::BaseImmOffset :
01879       // Load/store with base+offset addressing mode can be converted into
01880       // base+register offset addressing mode. However left shift operand should
01881       // be set to 0.
01882       NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
01883       break;
01884     default:
01885       return false;
01886     }
01887     if (NonExtOpcode < 0)
01888       return false;
01889     return true;
01890   }
01891   return false;
01892 }
01893 
01894 // Returns opcode of the non-extended equivalent instruction.
01895 short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const {
01896 
01897   // Check if the instruction has a register form that uses register in place
01898   // of the extended operand, if so return that as the non-extended form.
01899   short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
01900     if (NonExtOpcode >= 0)
01901       return NonExtOpcode;
01902 
01903   if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
01904     // Check addressing mode and retrieve non-ext equivalent instruction.
01905     switch (getAddrMode(MI)) {
01906     case HexagonII::Absolute :
01907       return Hexagon::getBasedWithImmOffset(MI->getOpcode());
01908     case HexagonII::BaseImmOffset :
01909       return Hexagon::getBaseWithRegOffset(MI->getOpcode());
01910     default:
01911       return -1;
01912     }
01913   }
01914   return -1;
01915 }
01916 
01917 bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode) const {
01918   return (Opcode == Hexagon::J2_jumpt) ||
01919          (Opcode == Hexagon::J2_jumpf) ||
01920          (Opcode == Hexagon::J2_jumptnewpt) ||
01921          (Opcode == Hexagon::J2_jumpfnewpt) ||
01922          (Opcode == Hexagon::J2_jumpt) ||
01923          (Opcode == Hexagon::J2_jumpf);
01924 }
01925 
01926 bool HexagonInstrInfo::PredOpcodeHasNot(Opcode_t Opcode) const {
01927   return (Opcode == Hexagon::J2_jumpf) ||
01928          (Opcode == Hexagon::J2_jumpfnewpt) ||
01929          (Opcode == Hexagon::J2_jumpfnew);
01930 }