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HexagonInstrInfo.cpp
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00001 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the Hexagon implementation of the TargetInstrInfo class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "HexagonInstrInfo.h"
00015 #include "Hexagon.h"
00016 #include "HexagonRegisterInfo.h"
00017 #include "HexagonSubtarget.h"
00018 #include "llvm/ADT/STLExtras.h"
00019 #include "llvm/ADT/SmallVector.h"
00020 #include "llvm/CodeGen/DFAPacketizer.h"
00021 #include "llvm/CodeGen/MachineFrameInfo.h"
00022 #include "llvm/CodeGen/MachineInstrBuilder.h"
00023 #include "llvm/CodeGen/MachineMemOperand.h"
00024 #include "llvm/CodeGen/MachineRegisterInfo.h"
00025 #include "llvm/CodeGen/PseudoSourceValue.h"
00026 #include "llvm/Support/Debug.h"
00027 #include "llvm/Support/MathExtras.h"
00028 #include "llvm/Support/raw_ostream.h"
00029 
00030 using namespace llvm;
00031 
00032 #define DEBUG_TYPE "hexagon-instrinfo"
00033 
00034 #define GET_INSTRINFO_CTOR_DTOR
00035 #define GET_INSTRMAP_INFO
00036 #include "HexagonGenInstrInfo.inc"
00037 #include "HexagonGenDFAPacketizer.inc"
00038 
00039 ///
00040 /// Constants for Hexagon instructions.
00041 ///
00042 const int Hexagon_MEMW_OFFSET_MAX = 4095;
00043 const int Hexagon_MEMW_OFFSET_MIN = -4096;
00044 const int Hexagon_MEMD_OFFSET_MAX = 8191;
00045 const int Hexagon_MEMD_OFFSET_MIN = -8192;
00046 const int Hexagon_MEMH_OFFSET_MAX = 2047;
00047 const int Hexagon_MEMH_OFFSET_MIN = -2048;
00048 const int Hexagon_MEMB_OFFSET_MAX = 1023;
00049 const int Hexagon_MEMB_OFFSET_MIN = -1024;
00050 const int Hexagon_ADDI_OFFSET_MAX = 32767;
00051 const int Hexagon_ADDI_OFFSET_MIN = -32768;
00052 const int Hexagon_MEMD_AUTOINC_MAX = 56;
00053 const int Hexagon_MEMD_AUTOINC_MIN = -64;
00054 const int Hexagon_MEMW_AUTOINC_MAX = 28;
00055 const int Hexagon_MEMW_AUTOINC_MIN = -32;
00056 const int Hexagon_MEMH_AUTOINC_MAX = 14;
00057 const int Hexagon_MEMH_AUTOINC_MIN = -16;
00058 const int Hexagon_MEMB_AUTOINC_MAX = 7;
00059 const int Hexagon_MEMB_AUTOINC_MIN = -8;
00060 
00061 // Pin the vtable to this file.
00062 void HexagonInstrInfo::anchor() {}
00063 
00064 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
00065     : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
00066       RI(), Subtarget(ST) {}
00067 
00068 /// isLoadFromStackSlot - If the specified machine instruction is a direct
00069 /// load from a stack slot, return the virtual or physical register number of
00070 /// the destination along with the FrameIndex of the loaded stack slot.  If
00071 /// not, return 0.  This predicate must return 0 if the instruction has
00072 /// any side effects other than loading from the stack slot.
00073 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
00074                                              int &FrameIndex) const {
00075 
00076 
00077   switch (MI->getOpcode()) {
00078   default: break;
00079   case Hexagon::L2_loadri_io:
00080   case Hexagon::L2_loadrd_io:
00081   case Hexagon::L2_loadrh_io:
00082   case Hexagon::L2_loadrb_io:
00083   case Hexagon::L2_loadrub_io:
00084     if (MI->getOperand(2).isFI() &&
00085         MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
00086       FrameIndex = MI->getOperand(2).getIndex();
00087       return MI->getOperand(0).getReg();
00088     }
00089     break;
00090   }
00091   return 0;
00092 }
00093 
00094 
00095 /// isStoreToStackSlot - If the specified machine instruction is a direct
00096 /// store to a stack slot, return the virtual or physical register number of
00097 /// the source reg along with the FrameIndex of the loaded stack slot.  If
00098 /// not, return 0.  This predicate must return 0 if the instruction has
00099 /// any side effects other than storing to the stack slot.
00100 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
00101                                             int &FrameIndex) const {
00102   switch (MI->getOpcode()) {
00103   default: break;
00104   case Hexagon::S2_storeri_io:
00105   case Hexagon::S2_storerd_io:
00106   case Hexagon::S2_storerh_io:
00107   case Hexagon::S2_storerb_io:
00108     if (MI->getOperand(2).isFI() &&
00109         MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
00110       FrameIndex = MI->getOperand(0).getIndex();
00111       return MI->getOperand(2).getReg();
00112     }
00113     break;
00114   }
00115   return 0;
00116 }
00117 
00118 // Find the hardware loop instruction used to set-up the specified loop.
00119 // On Hexagon, we have two instructions used to set-up the hardware loop
00120 // (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
00121 // to indicate the end of a loop.
00122 static MachineInstr *
00123 findLoopInstr(MachineBasicBlock *BB, int EndLoopOp,
00124               SmallPtrSet<MachineBasicBlock *, 8> &Visited) {
00125   int LOOPi;
00126   int LOOPr;
00127   if (EndLoopOp == Hexagon::ENDLOOP0) {
00128     LOOPi = Hexagon::J2_loop0i;
00129     LOOPr = Hexagon::J2_loop0r;
00130   } else { // EndLoopOp == Hexagon::EndLOOP1
00131     LOOPi = Hexagon::J2_loop1i;
00132     LOOPr = Hexagon::J2_loop1r;
00133   }
00134 
00135   // The loop set-up instruction will be in a predecessor block
00136   for (MachineBasicBlock::pred_iterator PB = BB->pred_begin(),
00137          PE = BB->pred_end(); PB != PE; ++PB) {
00138     // If this has been visited, already skip it.
00139     if (!Visited.insert(*PB).second)
00140       continue;
00141     if (*PB == BB)
00142       continue;
00143     for (MachineBasicBlock::reverse_instr_iterator I = (*PB)->instr_rbegin(),
00144            E = (*PB)->instr_rend(); I != E; ++I) {
00145       int Opc = I->getOpcode();
00146       if (Opc == LOOPi || Opc == LOOPr)
00147         return &*I;
00148       // We've reached a different loop, which means the loop0 has been removed.
00149       if (Opc == EndLoopOp)
00150         return 0;
00151     }
00152     // Check the predecessors for the LOOP instruction.
00153     MachineInstr *loop = findLoopInstr(*PB, EndLoopOp, Visited);
00154     if (loop)
00155       return loop;
00156   }
00157   return 0;
00158 }
00159 
00160 unsigned HexagonInstrInfo::InsertBranch(
00161     MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB,
00162     ArrayRef<MachineOperand> Cond, DebugLoc DL) const {
00163 
00164   Opcode_t BOpc   = Hexagon::J2_jump;
00165   Opcode_t BccOpc = Hexagon::J2_jumpt;
00166 
00167   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
00168 
00169   // Check if ReverseBranchCondition has asked to reverse this branch
00170   // If we want to reverse the branch an odd number of times, we want
00171   // J2_jumpf.
00172   if (!Cond.empty() && Cond[0].isImm())
00173     BccOpc = Cond[0].getImm();
00174 
00175   if (!FBB) {
00176     if (Cond.empty()) {
00177       // Due to a bug in TailMerging/CFG Optimization, we need to add a
00178       // special case handling of a predicated jump followed by an
00179       // unconditional jump. If not, Tail Merging and CFG Optimization go
00180       // into an infinite loop.
00181       MachineBasicBlock *NewTBB, *NewFBB;
00182       SmallVector<MachineOperand, 4> Cond;
00183       MachineInstr *Term = MBB.getFirstTerminator();
00184       if (Term != MBB.end() && isPredicated(Term) &&
00185           !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond, false)) {
00186         MachineBasicBlock *NextBB =
00187           std::next(MachineFunction::iterator(&MBB));
00188         if (NewTBB == NextBB) {
00189           ReverseBranchCondition(Cond);
00190           RemoveBranch(MBB);
00191           return InsertBranch(MBB, TBB, nullptr, Cond, DL);
00192         }
00193       }
00194       BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
00195     } else if (isEndLoopN(Cond[0].getImm())) {
00196       int EndLoopOp = Cond[0].getImm();
00197       assert(Cond[1].isMBB());
00198       // Since we're adding an ENDLOOP, there better be a LOOP instruction.
00199       // Check for it, and change the BB target if needed.
00200       SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
00201       MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, VisitedBBs);
00202       assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP");
00203       Loop->getOperand(0).setMBB(TBB);
00204       // Add the ENDLOOP after the finding the LOOP0.
00205       BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
00206     } else if (isNewValueJump(Cond[0].getImm())) {
00207       assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
00208       // New value jump
00209       // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
00210       // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
00211       unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
00212       DEBUG(dbgs() << "\nInserting NVJump for BB#" << MBB.getNumber(););
00213       if (Cond[2].isReg()) {
00214         unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
00215         BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
00216           addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
00217       } else if(Cond[2].isImm()) {
00218         BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
00219           addImm(Cond[2].getImm()).addMBB(TBB);
00220       } else
00221         llvm_unreachable("Invalid condition for branching");
00222     } else {
00223       assert((Cond.size() == 2) && "Malformed cond vector");
00224       const MachineOperand &RO = Cond[1];
00225       unsigned Flags = getUndefRegState(RO.isUndef());
00226       BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
00227     }
00228     return 1;
00229   }
00230   assert((!Cond.empty()) &&
00231          "Cond. cannot be empty when multiple branchings are required");
00232   assert((!isNewValueJump(Cond[0].getImm())) &&
00233          "NV-jump cannot be inserted with another branch");
00234   // Special case for hardware loops.  The condition is a basic block.
00235   if (isEndLoopN(Cond[0].getImm())) {
00236     int EndLoopOp = Cond[0].getImm();
00237     assert(Cond[1].isMBB());
00238     // Since we're adding an ENDLOOP, there better be a LOOP instruction.
00239     // Check for it, and change the BB target if needed.
00240     SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
00241     MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, VisitedBBs);
00242     assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP");
00243     Loop->getOperand(0).setMBB(TBB);
00244     // Add the ENDLOOP after the finding the LOOP0.
00245     BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
00246   } else {
00247     const MachineOperand &RO = Cond[1];
00248     unsigned Flags = getUndefRegState(RO.isUndef());
00249     BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
00250   }
00251   BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
00252 
00253   return 2;
00254 }
00255 
00256 
00257 /// This function can analyze one/two way branching only and should (mostly) be
00258 /// called by target independent side.
00259 /// First entry is always the opcode of the branching instruction, except when
00260 /// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
00261 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
00262 /// e.g. Jump_c p will have
00263 /// Cond[0] = Jump_c
00264 /// Cond[1] = p
00265 /// HW-loop ENDLOOP:
00266 /// Cond[0] = ENDLOOP
00267 /// Cond[1] = MBB
00268 /// New value jump:
00269 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
00270 /// Cond[1] = R
00271 /// Cond[2] = Imm
00272 /// @note Related function is \fn findInstrPredicate which fills in
00273 /// Cond. vector when a predicated instruction is passed to it.
00274 /// We follow same protocol in that case too.
00275 ///
00276 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
00277                                      MachineBasicBlock *&TBB,
00278                                      MachineBasicBlock *&FBB,
00279                                      SmallVectorImpl<MachineOperand> &Cond,
00280                                      bool AllowModify) const {
00281   TBB = nullptr;
00282   FBB = nullptr;
00283   Cond.clear();
00284 
00285   // If the block has no terminators, it just falls into the block after it.
00286   MachineBasicBlock::instr_iterator I = MBB.instr_end();
00287   if (I == MBB.instr_begin())
00288     return false;
00289 
00290   // A basic block may looks like this:
00291   //
00292   //  [   insn
00293   //     EH_LABEL
00294   //      insn
00295   //      insn
00296   //      insn
00297   //     EH_LABEL
00298   //      insn     ]
00299   //
00300   // It has two succs but does not have a terminator
00301   // Don't know how to handle it.
00302   do {
00303     --I;
00304     if (I->isEHLabel())
00305       // Don't analyze EH branches.
00306       return true;
00307   } while (I != MBB.instr_begin());
00308 
00309   I = MBB.instr_end();
00310   --I;
00311 
00312   while (I->isDebugValue()) {
00313     if (I == MBB.instr_begin())
00314       return false;
00315     --I;
00316   }
00317   
00318   bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
00319                      I->getOperand(0).isMBB();
00320   // Delete the J2_jump if it's equivalent to a fall-through.
00321   if (AllowModify && JumpToBlock &&
00322       MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
00323     DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
00324     I->eraseFromParent();
00325     I = MBB.instr_end();
00326     if (I == MBB.instr_begin())
00327       return false;
00328     --I;
00329   }
00330   if (!isUnpredicatedTerminator(I))
00331     return false;
00332 
00333   // Get the last instruction in the block.
00334   MachineInstr *LastInst = I;
00335   MachineInstr *SecondLastInst = nullptr;
00336   // Find one more terminator if present.
00337   do {
00338     if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(I)) {
00339       if (!SecondLastInst)
00340         SecondLastInst = I;
00341       else
00342         // This is a third branch.
00343         return true;
00344     }
00345     if (I == MBB.instr_begin())
00346       break;
00347     --I;
00348   } while(I);
00349 
00350   int LastOpcode = LastInst->getOpcode();
00351   int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
00352   // If the branch target is not a basic block, it could be a tail call.
00353   // (It is, if the target is a function.)
00354   if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
00355     return true;
00356   if (SecLastOpcode == Hexagon::J2_jump &&
00357       !SecondLastInst->getOperand(0).isMBB())
00358     return true;
00359 
00360   bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
00361   bool LastOpcodeHasNVJump = isNewValueJump(LastInst);
00362 
00363   // If there is only one terminator instruction, process it.
00364   if (LastInst && !SecondLastInst) {
00365     if (LastOpcode == Hexagon::J2_jump) {
00366       TBB = LastInst->getOperand(0).getMBB();
00367       return false;
00368     }
00369     if (isEndLoopN(LastOpcode)) {
00370       TBB = LastInst->getOperand(0).getMBB();
00371       Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
00372       Cond.push_back(LastInst->getOperand(0));
00373       return false;
00374     }
00375     if (LastOpcodeHasJMP_c) {
00376       TBB = LastInst->getOperand(1).getMBB();
00377       Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
00378       Cond.push_back(LastInst->getOperand(0));
00379       return false;
00380     }
00381     // Only supporting rr/ri versions of new-value jumps.
00382     if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
00383       TBB = LastInst->getOperand(2).getMBB();
00384       Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
00385       Cond.push_back(LastInst->getOperand(0));
00386       Cond.push_back(LastInst->getOperand(1));
00387       return false;
00388     }
00389     DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
00390                  << " with one jump\n";);
00391     // Otherwise, don't know what this is.
00392     return true;
00393   }
00394 
00395   bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
00396   bool SecLastOpcodeHasNVJump = isNewValueJump(SecondLastInst);
00397   if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
00398     TBB =  SecondLastInst->getOperand(1).getMBB();
00399     Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
00400     Cond.push_back(SecondLastInst->getOperand(0));
00401     FBB = LastInst->getOperand(0).getMBB();
00402     return false;
00403   }
00404 
00405   // Only supporting rr/ri versions of new-value jumps.
00406   if (SecLastOpcodeHasNVJump &&
00407       (SecondLastInst->getNumExplicitOperands() == 3) &&
00408       (LastOpcode == Hexagon::J2_jump)) {
00409     TBB = SecondLastInst->getOperand(2).getMBB();
00410     Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
00411     Cond.push_back(SecondLastInst->getOperand(0));
00412     Cond.push_back(SecondLastInst->getOperand(1));
00413     FBB = LastInst->getOperand(0).getMBB();
00414     return false;
00415   }
00416 
00417   // If the block ends with two Hexagon:JMPs, handle it.  The second one is not
00418   // executed, so remove it.
00419   if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
00420     TBB = SecondLastInst->getOperand(0).getMBB();
00421     I = LastInst;
00422     if (AllowModify)
00423       I->eraseFromParent();
00424     return false;
00425   }
00426 
00427   // If the block ends with an ENDLOOP, and J2_jump, handle it.
00428   if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
00429     TBB = SecondLastInst->getOperand(0).getMBB();
00430     Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
00431     Cond.push_back(SecondLastInst->getOperand(0));
00432     FBB = LastInst->getOperand(0).getMBB();
00433     return false;
00434   }
00435   DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
00436                << " with two jumps";);
00437   // Otherwise, can't handle this.
00438   return true;
00439 }
00440 
00441 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
00442   DEBUG(dbgs() << "\nRemoving branches out of BB#" << MBB.getNumber());
00443   MachineBasicBlock::iterator I = MBB.end();
00444   unsigned Count = 0;
00445   while (I != MBB.begin()) {
00446     --I;
00447     if (I->isDebugValue())
00448       continue;
00449     // Only removing branches from end of MBB.
00450     if (!I->isBranch())
00451       return Count;
00452     if (Count && (I->getOpcode() == Hexagon::J2_jump))
00453       llvm_unreachable("Malformed basic block: unconditional branch not last");
00454     MBB.erase(&MBB.back());
00455     I = MBB.end();
00456     ++Count;
00457   }
00458   return Count;
00459 }
00460 
00461 /// \brief For a comparison instruction, return the source registers in
00462 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
00463 /// compares against in CmpValue. Return true if the comparison instruction
00464 /// can be analyzed.
00465 bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
00466                                       unsigned &SrcReg, unsigned &SrcReg2,
00467                                       int &Mask, int &Value) const {
00468   unsigned Opc = MI->getOpcode();
00469 
00470   // Set mask and the first source register.
00471   switch (Opc) {
00472     case Hexagon::C2_cmpeq:
00473     case Hexagon::C2_cmpeqp:
00474     case Hexagon::C2_cmpgt:
00475     case Hexagon::C2_cmpgtp:
00476     case Hexagon::C2_cmpgtu:
00477     case Hexagon::C2_cmpgtup:
00478     case Hexagon::C4_cmpneq:
00479     case Hexagon::C4_cmplte:
00480     case Hexagon::C4_cmplteu:
00481     case Hexagon::C2_cmpeqi:
00482     case Hexagon::C2_cmpgti:
00483     case Hexagon::C2_cmpgtui:
00484     case Hexagon::C4_cmpneqi:
00485     case Hexagon::C4_cmplteui:
00486     case Hexagon::C4_cmpltei:
00487       SrcReg = MI->getOperand(1).getReg();
00488       Mask = ~0;
00489       break;
00490     case Hexagon::A4_cmpbeq:
00491     case Hexagon::A4_cmpbgt:
00492     case Hexagon::A4_cmpbgtu:
00493     case Hexagon::A4_cmpbeqi:
00494     case Hexagon::A4_cmpbgti:
00495     case Hexagon::A4_cmpbgtui:
00496       SrcReg = MI->getOperand(1).getReg();
00497       Mask = 0xFF;
00498       break;
00499     case Hexagon::A4_cmpheq:
00500     case Hexagon::A4_cmphgt:
00501     case Hexagon::A4_cmphgtu:
00502     case Hexagon::A4_cmpheqi:
00503     case Hexagon::A4_cmphgti:
00504     case Hexagon::A4_cmphgtui:
00505       SrcReg = MI->getOperand(1).getReg();
00506       Mask = 0xFFFF;
00507       break;
00508   }
00509 
00510   // Set the value/second source register.
00511   switch (Opc) {
00512     case Hexagon::C2_cmpeq:
00513     case Hexagon::C2_cmpeqp:
00514     case Hexagon::C2_cmpgt:
00515     case Hexagon::C2_cmpgtp:
00516     case Hexagon::C2_cmpgtu:
00517     case Hexagon::C2_cmpgtup:
00518     case Hexagon::A4_cmpbeq:
00519     case Hexagon::A4_cmpbgt:
00520     case Hexagon::A4_cmpbgtu:
00521     case Hexagon::A4_cmpheq:
00522     case Hexagon::A4_cmphgt:
00523     case Hexagon::A4_cmphgtu:
00524     case Hexagon::C4_cmpneq:
00525     case Hexagon::C4_cmplte:
00526     case Hexagon::C4_cmplteu:
00527       SrcReg2 = MI->getOperand(2).getReg();
00528       return true;
00529 
00530     case Hexagon::C2_cmpeqi:
00531     case Hexagon::C2_cmpgtui:
00532     case Hexagon::C2_cmpgti:
00533     case Hexagon::C4_cmpneqi:
00534     case Hexagon::C4_cmplteui:
00535     case Hexagon::C4_cmpltei:
00536     case Hexagon::A4_cmpbeqi:
00537     case Hexagon::A4_cmpbgti:
00538     case Hexagon::A4_cmpbgtui:
00539     case Hexagon::A4_cmpheqi:
00540     case Hexagon::A4_cmphgti:
00541     case Hexagon::A4_cmphgtui:
00542       SrcReg2 = 0;
00543       Value = MI->getOperand(2).getImm();
00544       return true;
00545   }
00546 
00547   return false;
00548 }
00549 
00550 
00551 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
00552                                  MachineBasicBlock::iterator I, DebugLoc DL,
00553                                  unsigned DestReg, unsigned SrcReg,
00554                                  bool KillSrc) const {
00555   if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
00556     BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg).addReg(SrcReg);
00557     return;
00558   }
00559   if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
00560     BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg).addReg(SrcReg);
00561     return;
00562   }
00563   if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
00564     // Map Pd = Ps to Pd = or(Ps, Ps).
00565     BuildMI(MBB, I, DL, get(Hexagon::C2_or),
00566             DestReg).addReg(SrcReg).addReg(SrcReg);
00567     return;
00568   }
00569   if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
00570       Hexagon::IntRegsRegClass.contains(SrcReg)) {
00571     // We can have an overlap between single and double reg: r1:0 = r0.
00572     if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
00573         // r1:0 = r0
00574         BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
00575                 Hexagon::subreg_hireg))).addImm(0);
00576     } else {
00577         // r1:0 = r1 or no overlap.
00578         BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), (RI.getSubReg(DestReg,
00579                 Hexagon::subreg_loreg))).addReg(SrcReg);
00580         BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
00581                 Hexagon::subreg_hireg))).addImm(0);
00582     }
00583     return;
00584   }
00585   if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
00586       Hexagon::IntRegsRegClass.contains(SrcReg)) {
00587     BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg).addReg(SrcReg);
00588     return;
00589   }
00590   if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
00591       Hexagon::IntRegsRegClass.contains(DestReg)) {
00592     BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg).
00593       addReg(SrcReg, getKillRegState(KillSrc));
00594     return;
00595   }
00596   if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
00597       Hexagon::PredRegsRegClass.contains(DestReg)) {
00598     BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg).
00599       addReg(SrcReg, getKillRegState(KillSrc));
00600     return;
00601   }
00602 
00603   llvm_unreachable("Unimplemented");
00604 }
00605 
00606 
00607 void HexagonInstrInfo::
00608 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
00609                     unsigned SrcReg, bool isKill, int FI,
00610                     const TargetRegisterClass *RC,
00611                     const TargetRegisterInfo *TRI) const {
00612 
00613   DebugLoc DL = MBB.findDebugLoc(I);
00614   MachineFunction &MF = *MBB.getParent();
00615   MachineFrameInfo &MFI = *MF.getFrameInfo();
00616   unsigned Align = MFI.getObjectAlignment(FI);
00617 
00618   MachineMemOperand *MMO =
00619       MF.getMachineMemOperand(
00620                       MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
00621                       MachineMemOperand::MOStore,
00622                       MFI.getObjectSize(FI),
00623                       Align);
00624 
00625   if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
00626     BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
00627           .addFrameIndex(FI).addImm(0)
00628           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00629   } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
00630     BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
00631           .addFrameIndex(FI).addImm(0)
00632           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00633   } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
00634     BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
00635           .addFrameIndex(FI).addImm(0)
00636           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00637   } else {
00638     llvm_unreachable("Unimplemented");
00639   }
00640 }
00641 
00642 
00643 void HexagonInstrInfo::storeRegToAddr(
00644                                  MachineFunction &MF, unsigned SrcReg,
00645                                  bool isKill,
00646                                  SmallVectorImpl<MachineOperand> &Addr,
00647                                  const TargetRegisterClass *RC,
00648                                  SmallVectorImpl<MachineInstr*> &NewMIs) const
00649 {
00650   llvm_unreachable("Unimplemented");
00651 }
00652 
00653 
00654 void HexagonInstrInfo::
00655 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
00656                      unsigned DestReg, int FI,
00657                      const TargetRegisterClass *RC,
00658                      const TargetRegisterInfo *TRI) const {
00659   DebugLoc DL = MBB.findDebugLoc(I);
00660   MachineFunction &MF = *MBB.getParent();
00661   MachineFrameInfo &MFI = *MF.getFrameInfo();
00662   unsigned Align = MFI.getObjectAlignment(FI);
00663 
00664   MachineMemOperand *MMO =
00665       MF.getMachineMemOperand(
00666                       MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
00667                       MachineMemOperand::MOLoad,
00668                       MFI.getObjectSize(FI),
00669                       Align);
00670   if (RC == &Hexagon::IntRegsRegClass) {
00671     BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
00672           .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00673   } else if (RC == &Hexagon::DoubleRegsRegClass) {
00674     BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
00675           .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00676   } else if (RC == &Hexagon::PredRegsRegClass) {
00677     BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
00678           .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00679   } else {
00680     llvm_unreachable("Can't store this register to stack slot");
00681   }
00682 }
00683 
00684 
00685 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
00686                                         SmallVectorImpl<MachineOperand> &Addr,
00687                                         const TargetRegisterClass *RC,
00688                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
00689   llvm_unreachable("Unimplemented");
00690 }
00691 bool
00692 HexagonInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
00693   const HexagonRegisterInfo &TRI = getRegisterInfo();
00694   MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
00695   MachineBasicBlock &MBB = *MI->getParent();
00696   DebugLoc DL = MI->getDebugLoc();
00697   unsigned Opc = MI->getOpcode();
00698 
00699   switch (Opc) {
00700     case Hexagon::ALIGNA:
00701       BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI->getOperand(0).getReg())
00702           .addReg(TRI.getFrameRegister())
00703           .addImm(-MI->getOperand(1).getImm());
00704       MBB.erase(MI);
00705       return true;
00706     case Hexagon::TFR_PdTrue: {
00707       unsigned Reg = MI->getOperand(0).getReg();
00708       BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
00709         .addReg(Reg, RegState::Undef)
00710         .addReg(Reg, RegState::Undef);
00711       MBB.erase(MI);
00712       return true;
00713     }
00714     case Hexagon::TFR_PdFalse: {
00715       unsigned Reg = MI->getOperand(0).getReg();
00716       BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
00717         .addReg(Reg, RegState::Undef)
00718         .addReg(Reg, RegState::Undef);
00719       MBB.erase(MI);
00720       return true;
00721     }
00722     case Hexagon::VMULW: {
00723       // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
00724       unsigned DstReg = MI->getOperand(0).getReg();
00725       unsigned Src1Reg = MI->getOperand(1).getReg();
00726       unsigned Src2Reg = MI->getOperand(2).getReg();
00727       unsigned Src1SubHi = TRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
00728       unsigned Src1SubLo = TRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
00729       unsigned Src2SubHi = TRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
00730       unsigned Src2SubLo = TRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
00731       BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
00732               TRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
00733           .addReg(Src2SubHi);
00734       BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
00735               TRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
00736           .addReg(Src2SubLo);
00737       MBB.erase(MI);
00738       MRI.clearKillFlags(Src1SubHi);
00739       MRI.clearKillFlags(Src1SubLo);
00740       MRI.clearKillFlags(Src2SubHi);
00741       MRI.clearKillFlags(Src2SubLo);
00742       return true;
00743     }
00744     case Hexagon::VMULW_ACC: {
00745       // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
00746       unsigned DstReg = MI->getOperand(0).getReg();
00747       unsigned Src1Reg = MI->getOperand(1).getReg();
00748       unsigned Src2Reg = MI->getOperand(2).getReg();
00749       unsigned Src3Reg = MI->getOperand(3).getReg();
00750       unsigned Src1SubHi = TRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
00751       unsigned Src1SubLo = TRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
00752       unsigned Src2SubHi = TRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
00753       unsigned Src2SubLo = TRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
00754       unsigned Src3SubHi = TRI.getSubReg(Src3Reg, Hexagon::subreg_hireg);
00755       unsigned Src3SubLo = TRI.getSubReg(Src3Reg, Hexagon::subreg_loreg);
00756       BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
00757               TRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
00758           .addReg(Src2SubHi).addReg(Src3SubHi);
00759       BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
00760               TRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
00761           .addReg(Src2SubLo).addReg(Src3SubLo);
00762       MBB.erase(MI);
00763       MRI.clearKillFlags(Src1SubHi);
00764       MRI.clearKillFlags(Src1SubLo);
00765       MRI.clearKillFlags(Src2SubHi);
00766       MRI.clearKillFlags(Src2SubLo);
00767       MRI.clearKillFlags(Src3SubHi);
00768       MRI.clearKillFlags(Src3SubLo);
00769       return true;
00770     }
00771     case Hexagon::TCRETURNi:
00772       MI->setDesc(get(Hexagon::J2_jump));
00773       return true;
00774     case Hexagon::TCRETURNr:
00775       MI->setDesc(get(Hexagon::J2_jumpr));
00776       return true;
00777   }
00778 
00779   return false;
00780 }
00781 
00782 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(
00783     MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
00784     MachineBasicBlock::iterator InsertPt, int FI) const {
00785   // Hexagon_TODO: Implement.
00786   return nullptr;
00787 }
00788 
00789 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
00790 
00791   MachineRegisterInfo &RegInfo = MF->getRegInfo();
00792   const TargetRegisterClass *TRC;
00793   if (VT == MVT::i1) {
00794     TRC = &Hexagon::PredRegsRegClass;
00795   } else if (VT == MVT::i32 || VT == MVT::f32) {
00796     TRC = &Hexagon::IntRegsRegClass;
00797   } else if (VT == MVT::i64 || VT == MVT::f64) {
00798     TRC = &Hexagon::DoubleRegsRegClass;
00799   } else {
00800     llvm_unreachable("Cannot handle this register class");
00801   }
00802 
00803   unsigned NewReg = RegInfo.createVirtualRegister(TRC);
00804   return NewReg;
00805 }
00806 
00807 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
00808   const MCInstrDesc &MID = MI->getDesc();
00809   const uint64_t F = MID.TSFlags;
00810   if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
00811     return true;
00812 
00813   // TODO: This is largely obsolete now. Will need to be removed
00814   // in consecutive patches.
00815   switch(MI->getOpcode()) {
00816     // TFR_FI Remains a special case.
00817     case Hexagon::TFR_FI:
00818       return true;
00819     default:
00820       return false;
00821   }
00822   return  false;
00823 }
00824 
00825 // This returns true in two cases:
00826 // - The OP code itself indicates that this is an extended instruction.
00827 // - One of MOs has been marked with HMOTF_ConstExtended flag.
00828 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
00829   // First check if this is permanently extended op code.
00830   const uint64_t F = MI->getDesc().TSFlags;
00831   if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
00832     return true;
00833   // Use MO operand flags to determine if one of MI's operands
00834   // has HMOTF_ConstExtended flag set.
00835   for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
00836        E = MI->operands_end(); I != E; ++I) {
00837     if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
00838       return true;
00839   }
00840   return  false;
00841 }
00842 
00843 bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const {
00844   return MI->getDesc().isBranch();
00845 }
00846 
00847 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
00848   if (isNewValueJump(MI))
00849     return true;
00850 
00851   if (isNewValueStore(MI))
00852     return true;
00853 
00854   return false;
00855 }
00856 
00857 bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
00858   const uint64_t F = MI->getDesc().TSFlags;
00859   return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
00860 }
00861 
00862 bool HexagonInstrInfo::isNewValue(Opcode_t Opcode) const {
00863   const uint64_t F = get(Opcode).TSFlags;
00864   return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
00865 }
00866 
00867 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
00868   return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
00869 }
00870 
00871 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
00872   bool isPred = MI->getDesc().isPredicable();
00873 
00874   if (!isPred)
00875     return false;
00876 
00877   const int Opc = MI->getOpcode();
00878 
00879   switch(Opc) {
00880   case Hexagon::A2_tfrsi:
00881     return (isOperandExtended(MI, 1) && isConstExtended(MI)) || isInt<12>(MI->getOperand(1).getImm());
00882 
00883   case Hexagon::S2_storerd_io:
00884     return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
00885 
00886   case Hexagon::S2_storeri_io:
00887   case Hexagon::S2_storerinew_io:
00888     return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
00889 
00890   case Hexagon::S2_storerh_io:
00891   case Hexagon::S2_storerhnew_io:
00892     return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
00893 
00894   case Hexagon::S2_storerb_io:
00895   case Hexagon::S2_storerbnew_io:
00896     return isUInt<6>(MI->getOperand(1).getImm());
00897 
00898   case Hexagon::L2_loadrd_io:
00899     return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
00900 
00901   case Hexagon::L2_loadri_io:
00902     return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
00903 
00904   case Hexagon::L2_loadrh_io:
00905   case Hexagon::L2_loadruh_io:
00906     return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
00907 
00908   case Hexagon::L2_loadrb_io:
00909   case Hexagon::L2_loadrub_io:
00910     return isUInt<6>(MI->getOperand(2).getImm());
00911 
00912   case Hexagon::L2_loadrd_pi:
00913     return isShiftedInt<4,3>(MI->getOperand(3).getImm());
00914 
00915   case Hexagon::L2_loadri_pi:
00916     return isShiftedInt<4,2>(MI->getOperand(3).getImm());
00917 
00918   case Hexagon::L2_loadrh_pi:
00919   case Hexagon::L2_loadruh_pi:
00920     return isShiftedInt<4,1>(MI->getOperand(3).getImm());
00921 
00922   case Hexagon::L2_loadrb_pi:
00923   case Hexagon::L2_loadrub_pi:
00924     return isInt<4>(MI->getOperand(3).getImm());
00925 
00926   case Hexagon::S4_storeirb_io:
00927   case Hexagon::S4_storeirh_io:
00928   case Hexagon::S4_storeiri_io:
00929     return (isUInt<6>(MI->getOperand(1).getImm()) &&
00930             isInt<6>(MI->getOperand(2).getImm()));
00931 
00932   case Hexagon::A2_addi:
00933     return isInt<8>(MI->getOperand(2).getImm());
00934 
00935   case Hexagon::A2_aslh:
00936   case Hexagon::A2_asrh:
00937   case Hexagon::A2_sxtb:
00938   case Hexagon::A2_sxth:
00939   case Hexagon::A2_zxtb:
00940   case Hexagon::A2_zxth:
00941     return true;
00942   }
00943 
00944   return true;
00945 }
00946 
00947 // This function performs the following inversiones:
00948 //
00949 //  cPt    ---> cNotPt
00950 //  cNotPt ---> cPt
00951 //
00952 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
00953   int InvPredOpcode;
00954   InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
00955                                         : Hexagon::getTruePredOpcode(Opc);
00956   if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
00957     return InvPredOpcode;
00958 
00959   switch(Opc) {
00960     default: llvm_unreachable("Unexpected predicated instruction");
00961     case Hexagon::C2_ccombinewt:
00962       return Hexagon::C2_ccombinewf;
00963     case Hexagon::C2_ccombinewf:
00964       return Hexagon::C2_ccombinewt;
00965 
00966       // Dealloc_return.
00967     case Hexagon::L4_return_t:
00968       return Hexagon::L4_return_f;
00969     case Hexagon::L4_return_f:
00970       return Hexagon::L4_return_t;
00971   }
00972 }
00973 
00974 // New Value Store instructions.
00975 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
00976   const uint64_t F = MI->getDesc().TSFlags;
00977 
00978   return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
00979 }
00980 
00981 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
00982   const uint64_t F = get(Opcode).TSFlags;
00983 
00984   return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
00985 }
00986 
00987 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
00988   enum Hexagon::PredSense inPredSense;
00989   inPredSense = invertPredicate ? Hexagon::PredSense_false :
00990                                   Hexagon::PredSense_true;
00991   int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
00992   if (CondOpcode >= 0) // Valid Conditional opcode/instruction
00993     return CondOpcode;
00994 
00995   // This switch case will be removed once all the instructions have been
00996   // modified to use relation maps.
00997   switch(Opc) {
00998   case Hexagon::TFRI_f:
00999     return !invertPredicate ? Hexagon::TFRI_cPt_f :
01000                               Hexagon::TFRI_cNotPt_f;
01001   case Hexagon::A2_combinew:
01002     return !invertPredicate ? Hexagon::C2_ccombinewt :
01003                               Hexagon::C2_ccombinewf;
01004 
01005   // DEALLOC_RETURN.
01006   case Hexagon::L4_return:
01007     return !invertPredicate ? Hexagon::L4_return_t:
01008                               Hexagon::L4_return_f;
01009   }
01010   llvm_unreachable("Unexpected predicable instruction");
01011 }
01012 
01013 
01014 bool HexagonInstrInfo::
01015 PredicateInstruction(MachineInstr *MI,
01016                      ArrayRef<MachineOperand> Cond) const {
01017   if (Cond.empty() || isEndLoopN(Cond[0].getImm())) {
01018     DEBUG(dbgs() << "\nCannot predicate:"; MI->dump(););
01019     return false;
01020   }
01021   int Opc = MI->getOpcode();
01022   assert (isPredicable(MI) && "Expected predicable instruction");
01023   bool invertJump = predOpcodeHasNot(Cond);
01024 
01025   // We have to predicate MI "in place", i.e. after this function returns,
01026   // MI will need to be transformed into a predicated form. To avoid com-
01027   // plicated manipulations with the operands (handling tied operands,
01028   // etc.), build a new temporary instruction, then overwrite MI with it.
01029 
01030   MachineBasicBlock &B = *MI->getParent();
01031   DebugLoc DL = MI->getDebugLoc();
01032   unsigned PredOpc = getCondOpcode(Opc, invertJump);
01033   MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
01034   unsigned NOp = 0, NumOps = MI->getNumOperands();
01035   while (NOp < NumOps) {
01036     MachineOperand &Op = MI->getOperand(NOp);
01037     if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
01038       break;
01039     T.addOperand(Op);
01040     NOp++;
01041   }
01042 
01043   unsigned PredReg, PredRegPos, PredRegFlags;
01044   bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
01045   (void)GotPredReg;
01046   assert(GotPredReg);
01047   T.addReg(PredReg, PredRegFlags);
01048   while (NOp < NumOps)
01049     T.addOperand(MI->getOperand(NOp++));
01050 
01051   MI->setDesc(get(PredOpc));
01052   while (unsigned n = MI->getNumOperands())
01053     MI->RemoveOperand(n-1);
01054   for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
01055     MI->addOperand(T->getOperand(i));
01056 
01057   MachineBasicBlock::instr_iterator TI = &*T;
01058   B.erase(TI);
01059 
01060   MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
01061   MRI.clearKillFlags(PredReg);
01062 
01063   return true;
01064 }
01065 
01066 
01067 bool
01068 HexagonInstrInfo::
01069 isProfitableToIfCvt(MachineBasicBlock &MBB,
01070                     unsigned NumCycles,
01071                     unsigned ExtraPredCycles,
01072                     const BranchProbability &Probability) const {
01073   return true;
01074 }
01075 
01076 
01077 bool
01078 HexagonInstrInfo::
01079 isProfitableToIfCvt(MachineBasicBlock &TMBB,
01080                     unsigned NumTCycles,
01081                     unsigned ExtraTCycles,
01082                     MachineBasicBlock &FMBB,
01083                     unsigned NumFCycles,
01084                     unsigned ExtraFCycles,
01085                     const BranchProbability &Probability) const {
01086   return true;
01087 }
01088 
01089 // Returns true if an instruction is predicated irrespective of the predicate
01090 // sense. For example, all of the following will return true.
01091 // if (p0) R1 = add(R2, R3)
01092 // if (!p0) R1 = add(R2, R3)
01093 // if (p0.new) R1 = add(R2, R3)
01094 // if (!p0.new) R1 = add(R2, R3)
01095 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
01096   const uint64_t F = MI->getDesc().TSFlags;
01097 
01098   return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
01099 }
01100 
01101 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
01102   const uint64_t F = get(Opcode).TSFlags;
01103 
01104   return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
01105 }
01106 
01107 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
01108   const uint64_t F = MI->getDesc().TSFlags;
01109 
01110   assert(isPredicated(MI));
01111   return (!((F >> HexagonII::PredicatedFalsePos) &
01112             HexagonII::PredicatedFalseMask));
01113 }
01114 
01115 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
01116   const uint64_t F = get(Opcode).TSFlags;
01117 
01118   // Make sure that the instruction is predicated.
01119   assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
01120   return (!((F >> HexagonII::PredicatedFalsePos) &
01121             HexagonII::PredicatedFalseMask));
01122 }
01123 
01124 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
01125   const uint64_t F = MI->getDesc().TSFlags;
01126 
01127   assert(isPredicated(MI));
01128   return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
01129 }
01130 
01131 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
01132   const uint64_t F = get(Opcode).TSFlags;
01133 
01134   assert(isPredicated(Opcode));
01135   return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
01136 }
01137 
01138 // Returns true, if a ST insn can be promoted to a new-value store.
01139 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const {
01140   const uint64_t F = MI->getDesc().TSFlags;
01141 
01142   return ((F >> HexagonII::mayNVStorePos) &
01143            HexagonII::mayNVStoreMask);
01144 }
01145 
01146 bool
01147 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
01148                                    std::vector<MachineOperand> &Pred) const {
01149   for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
01150     MachineOperand MO = MI->getOperand(oper);
01151     if (MO.isReg() && MO.isDef()) {
01152       const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
01153       if (RC == &Hexagon::PredRegsRegClass) {
01154         Pred.push_back(MO);
01155         return true;
01156       }
01157     }
01158   }
01159   return false;
01160 }
01161 
01162 
01163 bool
01164 HexagonInstrInfo::
01165 SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
01166                   ArrayRef<MachineOperand> Pred2) const {
01167   // TODO: Fix this
01168   return false;
01169 }
01170 
01171 
01172 //
01173 // We indicate that we want to reverse the branch by
01174 // inserting the reversed branching opcode.
01175 //
01176 bool HexagonInstrInfo::ReverseBranchCondition(
01177     SmallVectorImpl<MachineOperand> &Cond) const {
01178   if (Cond.empty())
01179     return true;
01180   assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
01181   Opcode_t opcode = Cond[0].getImm();
01182   //unsigned temp;
01183   assert(get(opcode).isBranch() && "Should be a branching condition.");
01184   if (isEndLoopN(opcode))
01185     return true;
01186   Opcode_t NewOpcode = getInvertedPredicatedOpcode(opcode);
01187   Cond[0].setImm(NewOpcode);
01188   return false;
01189 }
01190 
01191 
01192 bool HexagonInstrInfo::
01193 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
01194                           const BranchProbability &Probability) const {
01195   return (NumInstrs <= 4);
01196 }
01197 
01198 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
01199   switch (MI->getOpcode()) {
01200   default: return false;
01201   case Hexagon::L4_return:
01202   case Hexagon::L4_return_t:
01203   case Hexagon::L4_return_f:
01204   case Hexagon::L4_return_tnew_pnt:
01205   case Hexagon::L4_return_fnew_pnt:
01206   case Hexagon::L4_return_tnew_pt:
01207   case Hexagon::L4_return_fnew_pt:
01208    return true;
01209   }
01210 }
01211 
01212 
01213 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
01214       bool Extend) const {
01215   // This function is to check whether the "Offset" is in the correct range of
01216   // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
01217   // inserted to calculate the final address. Due to this reason, the function
01218   // assumes that the "Offset" has correct alignment.
01219   // We used to assert if the offset was not properly aligned, however,
01220   // there are cases where a misaligned pointer recast can cause this
01221   // problem, and we need to allow for it. The front end warns of such
01222   // misaligns with respect to load size.
01223 
01224   switch (Opcode) {
01225   case Hexagon::J2_loop0i:
01226   case Hexagon::J2_loop1i:
01227     return isUInt<10>(Offset);
01228   }
01229 
01230   if (Extend)
01231     return true;
01232 
01233   switch (Opcode) {
01234   case Hexagon::L2_loadri_io:
01235   case Hexagon::S2_storeri_io:
01236     return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
01237       (Offset <= Hexagon_MEMW_OFFSET_MAX);
01238 
01239   case Hexagon::L2_loadrd_io:
01240   case Hexagon::S2_storerd_io:
01241     return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
01242       (Offset <= Hexagon_MEMD_OFFSET_MAX);
01243 
01244   case Hexagon::L2_loadrh_io:
01245   case Hexagon::L2_loadruh_io:
01246   case Hexagon::S2_storerh_io:
01247     return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
01248       (Offset <= Hexagon_MEMH_OFFSET_MAX);
01249 
01250   case Hexagon::L2_loadrb_io:
01251   case Hexagon::S2_storerb_io:
01252   case Hexagon::L2_loadrub_io:
01253     return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
01254       (Offset <= Hexagon_MEMB_OFFSET_MAX);
01255 
01256   case Hexagon::A2_addi:
01257     return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
01258       (Offset <= Hexagon_ADDI_OFFSET_MAX);
01259 
01260   case Hexagon::L4_iadd_memopw_io:
01261   case Hexagon::L4_isub_memopw_io:
01262   case Hexagon::L4_add_memopw_io:
01263   case Hexagon::L4_sub_memopw_io:
01264   case Hexagon::L4_and_memopw_io:
01265   case Hexagon::L4_or_memopw_io:
01266     return (0 <= Offset && Offset <= 255);
01267 
01268   case Hexagon::L4_iadd_memoph_io:
01269   case Hexagon::L4_isub_memoph_io:
01270   case Hexagon::L4_add_memoph_io:
01271   case Hexagon::L4_sub_memoph_io:
01272   case Hexagon::L4_and_memoph_io:
01273   case Hexagon::L4_or_memoph_io:
01274     return (0 <= Offset && Offset <= 127);
01275 
01276   case Hexagon::L4_iadd_memopb_io:
01277   case Hexagon::L4_isub_memopb_io:
01278   case Hexagon::L4_add_memopb_io:
01279   case Hexagon::L4_sub_memopb_io:
01280   case Hexagon::L4_and_memopb_io:
01281   case Hexagon::L4_or_memopb_io:
01282     return (0 <= Offset && Offset <= 63);
01283 
01284   // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
01285   // any size. Later pass knows how to handle it.
01286   case Hexagon::STriw_pred:
01287   case Hexagon::LDriw_pred:
01288     return true;
01289 
01290   case Hexagon::TFR_FI:
01291   case Hexagon::TFR_FIA:
01292   case Hexagon::INLINEASM:
01293     return true;
01294   }
01295 
01296   llvm_unreachable("No offset range is defined for this opcode. "
01297                    "Please define it in the above switch statement!");
01298 }
01299 
01300 
01301 //
01302 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
01303 //
01304 bool HexagonInstrInfo::
01305 isValidAutoIncImm(const EVT VT, const int Offset) const {
01306 
01307   if (VT == MVT::i64) {
01308       return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
01309               Offset <= Hexagon_MEMD_AUTOINC_MAX &&
01310               (Offset & 0x7) == 0);
01311   }
01312   if (VT == MVT::i32) {
01313       return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
01314               Offset <= Hexagon_MEMW_AUTOINC_MAX &&
01315               (Offset & 0x3) == 0);
01316   }
01317   if (VT == MVT::i16) {
01318       return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
01319               Offset <= Hexagon_MEMH_AUTOINC_MAX &&
01320               (Offset & 0x1) == 0);
01321   }
01322   if (VT == MVT::i8) {
01323       return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
01324               Offset <= Hexagon_MEMB_AUTOINC_MAX);
01325   }
01326   llvm_unreachable("Not an auto-inc opc!");
01327 }
01328 
01329 
01330 bool HexagonInstrInfo::
01331 isMemOp(const MachineInstr *MI) const {
01332 //  return MI->getDesc().mayLoad() && MI->getDesc().mayStore();
01333 
01334   switch (MI->getOpcode())
01335   {
01336   default: return false;
01337   case Hexagon::L4_iadd_memopw_io:
01338   case Hexagon::L4_isub_memopw_io:
01339   case Hexagon::L4_add_memopw_io:
01340   case Hexagon::L4_sub_memopw_io:
01341   case Hexagon::L4_and_memopw_io:
01342   case Hexagon::L4_or_memopw_io:
01343   case Hexagon::L4_iadd_memoph_io:
01344   case Hexagon::L4_isub_memoph_io:
01345   case Hexagon::L4_add_memoph_io:
01346   case Hexagon::L4_sub_memoph_io:
01347   case Hexagon::L4_and_memoph_io:
01348   case Hexagon::L4_or_memoph_io:
01349   case Hexagon::L4_iadd_memopb_io:
01350   case Hexagon::L4_isub_memopb_io:
01351   case Hexagon::L4_add_memopb_io:
01352   case Hexagon::L4_sub_memopb_io:
01353   case Hexagon::L4_and_memopb_io:
01354   case Hexagon::L4_or_memopb_io:
01355   case Hexagon::L4_ior_memopb_io:
01356   case Hexagon::L4_ior_memoph_io:
01357   case Hexagon::L4_ior_memopw_io:
01358   case Hexagon::L4_iand_memopb_io:
01359   case Hexagon::L4_iand_memoph_io:
01360   case Hexagon::L4_iand_memopw_io:
01361     return true;
01362   }
01363   return false;
01364 }
01365 
01366 
01367 bool HexagonInstrInfo::
01368 isSpillPredRegOp(const MachineInstr *MI) const {
01369   switch (MI->getOpcode()) {
01370     default: return false;
01371     case Hexagon::STriw_pred :
01372     case Hexagon::LDriw_pred :
01373       return true;
01374   }
01375 }
01376 
01377 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
01378   switch (MI->getOpcode()) {
01379     default: return false;
01380     case Hexagon::C2_cmpeq:
01381     case Hexagon::C2_cmpeqi:
01382     case Hexagon::C2_cmpgt:
01383     case Hexagon::C2_cmpgti:
01384     case Hexagon::C2_cmpgtu:
01385     case Hexagon::C2_cmpgtui:
01386       return true;
01387   }
01388 }
01389 
01390 bool HexagonInstrInfo::
01391 isConditionalTransfer (const MachineInstr *MI) const {
01392   switch (MI->getOpcode()) {
01393     default: return false;
01394     case Hexagon::A2_tfrt:
01395     case Hexagon::A2_tfrf:
01396     case Hexagon::C2_cmoveit:
01397     case Hexagon::C2_cmoveif:
01398     case Hexagon::A2_tfrtnew:
01399     case Hexagon::A2_tfrfnew:
01400     case Hexagon::C2_cmovenewit:
01401     case Hexagon::C2_cmovenewif:
01402       return true;
01403   }
01404 }
01405 
01406 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
01407   switch (MI->getOpcode())
01408   {
01409     default: return false;
01410     case Hexagon::A2_paddf:
01411     case Hexagon::A2_paddfnew:
01412     case Hexagon::A2_paddt:
01413     case Hexagon::A2_paddtnew:
01414     case Hexagon::A2_pandf:
01415     case Hexagon::A2_pandfnew:
01416     case Hexagon::A2_pandt:
01417     case Hexagon::A2_pandtnew:
01418     case Hexagon::A4_paslhf:
01419     case Hexagon::A4_paslhfnew:
01420     case Hexagon::A4_paslht:
01421     case Hexagon::A4_paslhtnew:
01422     case Hexagon::A4_pasrhf:
01423     case Hexagon::A4_pasrhfnew:
01424     case Hexagon::A4_pasrht:
01425     case Hexagon::A4_pasrhtnew:
01426     case Hexagon::A2_porf:
01427     case Hexagon::A2_porfnew:
01428     case Hexagon::A2_port:
01429     case Hexagon::A2_portnew:
01430     case Hexagon::A2_psubf:
01431     case Hexagon::A2_psubfnew:
01432     case Hexagon::A2_psubt:
01433     case Hexagon::A2_psubtnew:
01434     case Hexagon::A2_pxorf:
01435     case Hexagon::A2_pxorfnew:
01436     case Hexagon::A2_pxort:
01437     case Hexagon::A2_pxortnew:
01438     case Hexagon::A4_psxthf:
01439     case Hexagon::A4_psxthfnew:
01440     case Hexagon::A4_psxtht:
01441     case Hexagon::A4_psxthtnew:
01442     case Hexagon::A4_psxtbf:
01443     case Hexagon::A4_psxtbfnew:
01444     case Hexagon::A4_psxtbt:
01445     case Hexagon::A4_psxtbtnew:
01446     case Hexagon::A4_pzxtbf:
01447     case Hexagon::A4_pzxtbfnew:
01448     case Hexagon::A4_pzxtbt:
01449     case Hexagon::A4_pzxtbtnew:
01450     case Hexagon::A4_pzxthf:
01451     case Hexagon::A4_pzxthfnew:
01452     case Hexagon::A4_pzxtht:
01453     case Hexagon::A4_pzxthtnew:
01454     case Hexagon::A2_paddit:
01455     case Hexagon::A2_paddif:
01456     case Hexagon::C2_ccombinewt:
01457     case Hexagon::C2_ccombinewf:
01458       return true;
01459   }
01460 }
01461 
01462 bool HexagonInstrInfo::
01463 isConditionalLoad (const MachineInstr* MI) const {
01464   switch (MI->getOpcode())
01465   {
01466     default: return false;
01467     case Hexagon::L2_ploadrdt_io :
01468     case Hexagon::L2_ploadrdf_io:
01469     case Hexagon::L2_ploadrit_io:
01470     case Hexagon::L2_ploadrif_io:
01471     case Hexagon::L2_ploadrht_io:
01472     case Hexagon::L2_ploadrhf_io:
01473     case Hexagon::L2_ploadrbt_io:
01474     case Hexagon::L2_ploadrbf_io:
01475     case Hexagon::L2_ploadruht_io:
01476     case Hexagon::L2_ploadruhf_io:
01477     case Hexagon::L2_ploadrubt_io:
01478     case Hexagon::L2_ploadrubf_io:
01479     case Hexagon::L2_ploadrdt_pi:
01480     case Hexagon::L2_ploadrdf_pi:
01481     case Hexagon::L2_ploadrit_pi:
01482     case Hexagon::L2_ploadrif_pi:
01483     case Hexagon::L2_ploadrht_pi:
01484     case Hexagon::L2_ploadrhf_pi:
01485     case Hexagon::L2_ploadrbt_pi:
01486     case Hexagon::L2_ploadrbf_pi:
01487     case Hexagon::L2_ploadruht_pi:
01488     case Hexagon::L2_ploadruhf_pi:
01489     case Hexagon::L2_ploadrubt_pi:
01490     case Hexagon::L2_ploadrubf_pi:
01491     case Hexagon::L4_ploadrdt_rr:
01492     case Hexagon::L4_ploadrdf_rr:
01493     case Hexagon::L4_ploadrbt_rr:
01494     case Hexagon::L4_ploadrbf_rr:
01495     case Hexagon::L4_ploadrubt_rr:
01496     case Hexagon::L4_ploadrubf_rr:
01497     case Hexagon::L4_ploadrht_rr:
01498     case Hexagon::L4_ploadrhf_rr:
01499     case Hexagon::L4_ploadruht_rr:
01500     case Hexagon::L4_ploadruhf_rr:
01501     case Hexagon::L4_ploadrit_rr:
01502     case Hexagon::L4_ploadrif_rr:
01503       return true;
01504   }
01505 }
01506 
01507 // Returns true if an instruction is a conditional store.
01508 //
01509 // Note: It doesn't include conditional new-value stores as they can't be
01510 // converted to .new predicate.
01511 //
01512 //               p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
01513 //                ^           ^
01514 //               /             \ (not OK. it will cause new-value store to be
01515 //              /               X conditional on p0.new while R2 producer is
01516 //             /                 \ on p0)
01517 //            /                   \.
01518 //     p.new store                 p.old NV store
01519 // [if(p0.new)memw(R0+#0)=R2]    [if(p0)memw(R0+#0)=R2.new]
01520 //            ^                  ^
01521 //             \                /
01522 //              \              /
01523 //               \            /
01524 //                 p.old store
01525 //             [if (p0)memw(R0+#0)=R2]
01526 //
01527 // The above diagram shows the steps involoved in the conversion of a predicated
01528 // store instruction to its .new predicated new-value form.
01529 //
01530 // The following set of instructions further explains the scenario where
01531 // conditional new-value store becomes invalid when promoted to .new predicate
01532 // form.
01533 //
01534 // { 1) if (p0) r0 = add(r1, r2)
01535 //   2) p0 = cmp.eq(r3, #0) }
01536 //
01537 //   3) if (p0) memb(r1+#0) = r0  --> this instruction can't be grouped with
01538 // the first two instructions because in instr 1, r0 is conditional on old value
01539 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
01540 // is not valid for new-value stores.
01541 bool HexagonInstrInfo::
01542 isConditionalStore (const MachineInstr* MI) const {
01543   switch (MI->getOpcode())
01544   {
01545     default: return false;
01546     case Hexagon::S4_storeirbt_io:
01547     case Hexagon::S4_storeirbf_io:
01548     case Hexagon::S4_pstorerbt_rr:
01549     case Hexagon::S4_pstorerbf_rr:
01550     case Hexagon::S2_pstorerbt_io:
01551     case Hexagon::S2_pstorerbf_io:
01552     case Hexagon::S2_pstorerbt_pi:
01553     case Hexagon::S2_pstorerbf_pi:
01554     case Hexagon::S2_pstorerdt_io:
01555     case Hexagon::S2_pstorerdf_io:
01556     case Hexagon::S4_pstorerdt_rr:
01557     case Hexagon::S4_pstorerdf_rr:
01558     case Hexagon::S2_pstorerdt_pi:
01559     case Hexagon::S2_pstorerdf_pi:
01560     case Hexagon::S2_pstorerht_io:
01561     case Hexagon::S2_pstorerhf_io:
01562     case Hexagon::S4_storeirht_io:
01563     case Hexagon::S4_storeirhf_io:
01564     case Hexagon::S4_pstorerht_rr:
01565     case Hexagon::S4_pstorerhf_rr:
01566     case Hexagon::S2_pstorerht_pi:
01567     case Hexagon::S2_pstorerhf_pi:
01568     case Hexagon::S2_pstorerit_io:
01569     case Hexagon::S2_pstorerif_io:
01570     case Hexagon::S4_storeirit_io:
01571     case Hexagon::S4_storeirif_io:
01572     case Hexagon::S4_pstorerit_rr:
01573     case Hexagon::S4_pstorerif_rr:
01574     case Hexagon::S2_pstorerit_pi:
01575     case Hexagon::S2_pstorerif_pi:
01576 
01577     // V4 global address store before promoting to dot new.
01578     case Hexagon::S4_pstorerdt_abs:
01579     case Hexagon::S4_pstorerdf_abs:
01580     case Hexagon::S4_pstorerbt_abs:
01581     case Hexagon::S4_pstorerbf_abs:
01582     case Hexagon::S4_pstorerht_abs:
01583     case Hexagon::S4_pstorerhf_abs:
01584     case Hexagon::S4_pstorerit_abs:
01585     case Hexagon::S4_pstorerif_abs:
01586       return true;
01587 
01588     // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
01589     // from the "Conditional Store" list. Because a predicated new value store
01590     // would NOT be promoted to a double dot new store. See diagram below:
01591     // This function returns yes for those stores that are predicated but not
01592     // yet promoted to predicate dot new instructions.
01593     //
01594     //                          +---------------------+
01595     //                    /-----| if (p0) memw(..)=r0 |---------\~
01596     //                   ||     +---------------------+         ||
01597     //          promote  ||       /\       /\                   ||  promote
01598     //                   ||      /||\     /||\                  ||
01599     //                  \||/    demote     ||                  \||/
01600     //                   \/       ||       ||                   \/
01601     //       +-------------------------+   ||   +-------------------------+
01602     //       | if (p0.new) memw(..)=r0 |   ||   | if (p0) memw(..)=r0.new |
01603     //       +-------------------------+   ||   +-------------------------+
01604     //                        ||           ||         ||
01605     //                        ||         demote      \||/
01606     //                      promote        ||         \/ NOT possible
01607     //                        ||           ||         /\~
01608     //                       \||/          ||        /||\~
01609     //                        \/           ||         ||
01610     //                      +-----------------------------+
01611     //                      | if (p0.new) memw(..)=r0.new |
01612     //                      +-----------------------------+
01613     //                           Double Dot New Store
01614     //
01615   }
01616 }
01617 
01618 
01619 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
01620   if (isNewValue(MI) && isBranch(MI))
01621     return true;
01622   return false;
01623 }
01624 
01625 bool HexagonInstrInfo::isNewValueJump(Opcode_t Opcode) const {
01626   return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
01627 }
01628 
01629 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
01630   return (getAddrMode(MI) == HexagonII::PostInc);
01631 }
01632 
01633 // Returns true, if any one of the operands is a dot new
01634 // insn, whether it is predicated dot new or register dot new.
01635 bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
01636   return (isNewValueInst(MI) ||
01637      (isPredicated(MI) && isPredicatedNew(MI)));
01638 }
01639 
01640 // Returns the most basic instruction for the .new predicated instructions and
01641 // new-value stores.
01642 // For example, all of the following instructions will be converted back to the
01643 // same instruction:
01644 // 1) if (p0.new) memw(R0+#0) = R1.new  --->
01645 // 2) if (p0) memw(R0+#0)= R1.new      -------> if (p0) memw(R0+#0) = R1
01646 // 3) if (p0.new) memw(R0+#0) = R1      --->
01647 //
01648 
01649 int HexagonInstrInfo::GetDotOldOp(const int opc) const {
01650   int NewOp = opc;
01651   if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
01652     NewOp = Hexagon::getPredOldOpcode(NewOp);
01653     assert(NewOp >= 0 &&
01654            "Couldn't change predicate new instruction to its old form.");
01655   }
01656 
01657   if (isNewValueStore(NewOp)) { // Convert into non-new-value format
01658     NewOp = Hexagon::getNonNVStore(NewOp);
01659     assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
01660   }
01661   return NewOp;
01662 }
01663 
01664 // Return the new value instruction for a given store.
01665 int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const {
01666   int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
01667   if (NVOpcode >= 0) // Valid new-value store instruction.
01668     return NVOpcode;
01669 
01670   switch (MI->getOpcode()) {
01671   default: llvm_unreachable("Unknown .new type");
01672   case Hexagon::S4_storerb_ur:
01673     return Hexagon::S4_storerbnew_ur;
01674 
01675   case Hexagon::S4_storerh_ur:
01676     return Hexagon::S4_storerhnew_ur;
01677 
01678   case Hexagon::S4_storeri_ur:
01679     return Hexagon::S4_storerinew_ur;
01680 
01681   case Hexagon::S2_storerb_pci:
01682     return Hexagon::S2_storerb_pci;
01683 
01684   case Hexagon::S2_storeri_pci:
01685     return Hexagon::S2_storeri_pci;
01686 
01687   case Hexagon::S2_storerh_pci:
01688     return Hexagon::S2_storerh_pci;
01689 
01690   case Hexagon::S2_storerd_pci:
01691     return Hexagon::S2_storerd_pci;
01692 
01693   case Hexagon::S2_storerf_pci:
01694     return Hexagon::S2_storerf_pci;
01695   }
01696   return 0;
01697 }
01698 
01699 // Return .new predicate version for an instruction.
01700 int HexagonInstrInfo::GetDotNewPredOp(MachineInstr *MI,
01701                                       const MachineBranchProbabilityInfo
01702                                       *MBPI) const {
01703 
01704   int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
01705   if (NewOpcode >= 0) // Valid predicate new instruction
01706     return NewOpcode;
01707 
01708   switch (MI->getOpcode()) {
01709   default: llvm_unreachable("Unknown .new type");
01710   // Condtional Jumps
01711   case Hexagon::J2_jumpt:
01712   case Hexagon::J2_jumpf:
01713     return getDotNewPredJumpOp(MI, MBPI);
01714 
01715   case Hexagon::J2_jumprt:
01716     return Hexagon::J2_jumptnewpt;
01717 
01718   case Hexagon::J2_jumprf:
01719     return Hexagon::J2_jumprfnewpt;
01720 
01721   case Hexagon::JMPrett:
01722     return Hexagon::J2_jumprtnewpt;
01723 
01724   case Hexagon::JMPretf:
01725     return Hexagon::J2_jumprfnewpt;
01726 
01727 
01728   // Conditional combine
01729   case Hexagon::C2_ccombinewt:
01730     return Hexagon::C2_ccombinewnewt;
01731   case Hexagon::C2_ccombinewf:
01732     return Hexagon::C2_ccombinewnewf;
01733   }
01734 }
01735 
01736 
01737 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
01738   const uint64_t F = MI->getDesc().TSFlags;
01739 
01740   return((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
01741 }
01742 
01743 /// immediateExtend - Changes the instruction in place to one using an immediate
01744 /// extender.
01745 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
01746   assert((isExtendable(MI)||isConstExtended(MI)) &&
01747                                "Instruction must be extendable");
01748   // Find which operand is extendable.
01749   short ExtOpNum = getCExtOpNum(MI);
01750   MachineOperand &MO = MI->getOperand(ExtOpNum);
01751   // This needs to be something we understand.
01752   assert((MO.isMBB() || MO.isImm()) &&
01753          "Branch with unknown extendable field type");
01754   // Mark given operand as extended.
01755   MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
01756 }
01757 
01758 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
01759     const TargetSubtargetInfo &STI) const {
01760   const InstrItineraryData *II = STI.getInstrItineraryData();
01761   return static_cast<const HexagonSubtarget &>(STI).createDFAPacketizer(II);
01762 }
01763 
01764 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
01765                                             const MachineBasicBlock *MBB,
01766                                             const MachineFunction &MF) const {
01767   // Debug info is never a scheduling boundary. It's necessary to be explicit
01768   // due to the special treatment of IT instructions below, otherwise a
01769   // dbg_value followed by an IT will result in the IT instruction being
01770   // considered a scheduling hazard, which is wrong. It should be the actual
01771   // instruction preceding the dbg_value instruction(s), just like it is
01772   // when debug info is not present.
01773   if (MI->isDebugValue())
01774     return false;
01775 
01776   // Terminators and labels can't be scheduled around.
01777   if (MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm())
01778     return true;
01779 
01780   return false;
01781 }
01782 
01783 bool HexagonInstrInfo::isConstExtended(const MachineInstr *MI) const {
01784   const uint64_t F = MI->getDesc().TSFlags;
01785   unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
01786   if (isExtended) // Instruction must be extended.
01787     return true;
01788 
01789   unsigned isExtendable =
01790     (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
01791   if (!isExtendable)
01792     return false;
01793 
01794   short ExtOpNum = getCExtOpNum(MI);
01795   const MachineOperand &MO = MI->getOperand(ExtOpNum);
01796   // Use MO operand flags to determine if MO
01797   // has the HMOTF_ConstExtended flag set.
01798   if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
01799     return true;
01800   // If this is a Machine BB address we are talking about, and it is
01801   // not marked as extended, say so.
01802   if (MO.isMBB())
01803     return false;
01804 
01805   // We could be using an instruction with an extendable immediate and shoehorn
01806   // a global address into it. If it is a global address it will be constant
01807   // extended. We do this for COMBINE.
01808   // We currently only handle isGlobal() because it is the only kind of
01809   // object we are going to end up with here for now.
01810   // In the future we probably should add isSymbol(), etc.
01811   if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
01812       MO.isJTI() || MO.isCPI())
01813     return true;
01814 
01815   // If the extendable operand is not 'Immediate' type, the instruction should
01816   // have 'isExtended' flag set.
01817   assert(MO.isImm() && "Extendable operand must be Immediate type");
01818 
01819   int MinValue = getMinValue(MI);
01820   int MaxValue = getMaxValue(MI);
01821   int ImmValue = MO.getImm();
01822 
01823   return (ImmValue < MinValue || ImmValue > MaxValue);
01824 }
01825 
01826 // Return the number of bytes required to encode the instruction.
01827 // Hexagon instructions are fixed length, 4 bytes, unless they
01828 // use a constant extender, which requires another 4 bytes.
01829 // For debug instructions and prolog labels, return 0.
01830 unsigned HexagonInstrInfo::getSize(const MachineInstr *MI) const {
01831 
01832   if (MI->isDebugValue() || MI->isPosition())
01833     return 0;
01834 
01835   unsigned Size = MI->getDesc().getSize();
01836   if (!Size)
01837     // Assume the default insn size in case it cannot be determined
01838     // for whatever reason.
01839     Size = HEXAGON_INSTR_SIZE;
01840 
01841   if (isConstExtended(MI) || isExtended(MI))
01842     Size += HEXAGON_INSTR_SIZE;
01843 
01844   return Size;
01845 }
01846 
01847 // Returns the opcode to use when converting MI, which is a conditional jump,
01848 // into a conditional instruction which uses the .new value of the predicate.
01849 // We also use branch probabilities to add a hint to the jump.
01850 int
01851 HexagonInstrInfo::getDotNewPredJumpOp(MachineInstr *MI,
01852                                   const
01853                                   MachineBranchProbabilityInfo *MBPI) const {
01854 
01855   // We assume that block can have at most two successors.
01856   bool taken = false;
01857   MachineBasicBlock *Src = MI->getParent();
01858   MachineOperand *BrTarget = &MI->getOperand(1);
01859   MachineBasicBlock *Dst = BrTarget->getMBB();
01860 
01861   const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
01862   if (Prediction >= BranchProbability(1,2))
01863     taken = true;
01864 
01865   switch (MI->getOpcode()) {
01866   case Hexagon::J2_jumpt:
01867     return taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
01868   case Hexagon::J2_jumpf:
01869     return taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
01870 
01871   default:
01872     llvm_unreachable("Unexpected jump instruction.");
01873   }
01874 }
01875 // Returns true if a particular operand is extendable for an instruction.
01876 bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
01877                                          unsigned short OperandNum) const {
01878   const uint64_t F = MI->getDesc().TSFlags;
01879 
01880   return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
01881           == OperandNum;
01882 }
01883 
01884 // Returns Operand Index for the constant extended instruction.
01885 unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
01886   const uint64_t F = MI->getDesc().TSFlags;
01887   return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
01888 }
01889 
01890 // Returns the min value that doesn't need to be extended.
01891 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
01892   const uint64_t F = MI->getDesc().TSFlags;
01893   unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
01894                     & HexagonII::ExtentSignedMask;
01895   unsigned bits =  (F >> HexagonII::ExtentBitsPos)
01896                     & HexagonII::ExtentBitsMask;
01897 
01898   if (isSigned) // if value is signed
01899     return -1U << (bits - 1);
01900   else
01901     return 0;
01902 }
01903 
01904 // Returns the max value that doesn't need to be extended.
01905 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
01906   const uint64_t F = MI->getDesc().TSFlags;
01907   unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
01908                     & HexagonII::ExtentSignedMask;
01909   unsigned bits =  (F >> HexagonII::ExtentBitsPos)
01910                     & HexagonII::ExtentBitsMask;
01911 
01912   if (isSigned) // if value is signed
01913     return ~(-1U << (bits - 1));
01914   else
01915     return ~(-1U << bits);
01916 }
01917 
01918 // Returns true if an instruction can be converted into a non-extended
01919 // equivalent instruction.
01920 bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr *MI) const {
01921 
01922   short NonExtOpcode;
01923   // Check if the instruction has a register form that uses register in place
01924   // of the extended operand, if so return that as the non-extended form.
01925   if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
01926     return true;
01927 
01928   if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
01929     // Check addressing mode and retrieve non-ext equivalent instruction.
01930 
01931     switch (getAddrMode(MI)) {
01932     case HexagonII::Absolute :
01933       // Load/store with absolute addressing mode can be converted into
01934       // base+offset mode.
01935       NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode());
01936       break;
01937     case HexagonII::BaseImmOffset :
01938       // Load/store with base+offset addressing mode can be converted into
01939       // base+register offset addressing mode. However left shift operand should
01940       // be set to 0.
01941       NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
01942       break;
01943     default:
01944       return false;
01945     }
01946     if (NonExtOpcode < 0)
01947       return false;
01948     return true;
01949   }
01950   return false;
01951 }
01952 
01953 // Returns opcode of the non-extended equivalent instruction.
01954 short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const {
01955 
01956   // Check if the instruction has a register form that uses register in place
01957   // of the extended operand, if so return that as the non-extended form.
01958   short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
01959     if (NonExtOpcode >= 0)
01960       return NonExtOpcode;
01961 
01962   if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
01963     // Check addressing mode and retrieve non-ext equivalent instruction.
01964     switch (getAddrMode(MI)) {
01965     case HexagonII::Absolute :
01966       return Hexagon::getBasedWithImmOffset(MI->getOpcode());
01967     case HexagonII::BaseImmOffset :
01968       return Hexagon::getBaseWithRegOffset(MI->getOpcode());
01969     default:
01970       return -1;
01971     }
01972   }
01973   return -1;
01974 }
01975 
01976 bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode) const {
01977   return (Opcode == Hexagon::J2_jumpt) ||
01978          (Opcode == Hexagon::J2_jumpf) ||
01979          (Opcode == Hexagon::J2_jumptnewpt) ||
01980          (Opcode == Hexagon::J2_jumpfnewpt) ||
01981          (Opcode == Hexagon::J2_jumpt) ||
01982          (Opcode == Hexagon::J2_jumpf);
01983 }
01984 
01985 bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const {
01986   if (Cond.empty() || !isPredicated(Cond[0].getImm()))
01987     return false;
01988   return !isPredicatedTrue(Cond[0].getImm());
01989 }
01990 
01991 bool HexagonInstrInfo::isEndLoopN(Opcode_t Opcode) const {
01992   return (Opcode == Hexagon::ENDLOOP0 ||
01993           Opcode == Hexagon::ENDLOOP1);
01994 }
01995 
01996 bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
01997                                   unsigned &PredReg, unsigned &PredRegPos,
01998                                   unsigned &PredRegFlags) const {
01999   if (Cond.empty())
02000     return false;
02001   assert(Cond.size() == 2);
02002   if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
02003      DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
02004      return false;
02005   }
02006   PredReg = Cond[1].getReg();
02007   PredRegPos = 1;
02008   // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
02009   PredRegFlags = 0;
02010   if (Cond[1].isImplicit())
02011     PredRegFlags = RegState::Implicit;
02012   if (Cond[1].isUndef())
02013     PredRegFlags |= RegState::Undef;
02014   return true;
02015 }
02016