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HexagonInstrInfo.cpp
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00001 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the Hexagon implementation of the TargetInstrInfo class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "HexagonInstrInfo.h"
00015 #include "Hexagon.h"
00016 #include "HexagonRegisterInfo.h"
00017 #include "HexagonSubtarget.h"
00018 #include "llvm/ADT/STLExtras.h"
00019 #include "llvm/ADT/SmallVector.h"
00020 #include "llvm/CodeGen/DFAPacketizer.h"
00021 #include "llvm/CodeGen/MachineFrameInfo.h"
00022 #include "llvm/CodeGen/MachineInstrBuilder.h"
00023 #include "llvm/CodeGen/MachineMemOperand.h"
00024 #include "llvm/CodeGen/MachineRegisterInfo.h"
00025 #include "llvm/CodeGen/PseudoSourceValue.h"
00026 #include "llvm/Support/Debug.h"
00027 #include "llvm/Support/MathExtras.h"
00028 #include "llvm/Support/raw_ostream.h"
00029 
00030 using namespace llvm;
00031 
00032 #define DEBUG_TYPE "hexagon-instrinfo"
00033 
00034 #define GET_INSTRINFO_CTOR_DTOR
00035 #define GET_INSTRMAP_INFO
00036 #include "HexagonGenInstrInfo.inc"
00037 #include "HexagonGenDFAPacketizer.inc"
00038 
00039 ///
00040 /// Constants for Hexagon instructions.
00041 ///
00042 const int Hexagon_MEMW_OFFSET_MAX = 4095;
00043 const int Hexagon_MEMW_OFFSET_MIN = -4096;
00044 const int Hexagon_MEMD_OFFSET_MAX = 8191;
00045 const int Hexagon_MEMD_OFFSET_MIN = -8192;
00046 const int Hexagon_MEMH_OFFSET_MAX = 2047;
00047 const int Hexagon_MEMH_OFFSET_MIN = -2048;
00048 const int Hexagon_MEMB_OFFSET_MAX = 1023;
00049 const int Hexagon_MEMB_OFFSET_MIN = -1024;
00050 const int Hexagon_ADDI_OFFSET_MAX = 32767;
00051 const int Hexagon_ADDI_OFFSET_MIN = -32768;
00052 const int Hexagon_MEMD_AUTOINC_MAX = 56;
00053 const int Hexagon_MEMD_AUTOINC_MIN = -64;
00054 const int Hexagon_MEMW_AUTOINC_MAX = 28;
00055 const int Hexagon_MEMW_AUTOINC_MIN = -32;
00056 const int Hexagon_MEMH_AUTOINC_MAX = 14;
00057 const int Hexagon_MEMH_AUTOINC_MIN = -16;
00058 const int Hexagon_MEMB_AUTOINC_MAX = 7;
00059 const int Hexagon_MEMB_AUTOINC_MIN = -8;
00060 
00061 // Pin the vtable to this file.
00062 void HexagonInstrInfo::anchor() {}
00063 
00064 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
00065   : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
00066     RI(ST), Subtarget(ST) {
00067 }
00068 
00069 
00070 /// isLoadFromStackSlot - If the specified machine instruction is a direct
00071 /// load from a stack slot, return the virtual or physical register number of
00072 /// the destination along with the FrameIndex of the loaded stack slot.  If
00073 /// not, return 0.  This predicate must return 0 if the instruction has
00074 /// any side effects other than loading from the stack slot.
00075 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
00076                                              int &FrameIndex) const {
00077 
00078 
00079   switch (MI->getOpcode()) {
00080   default: break;
00081   case Hexagon::L2_loadri_io:
00082   case Hexagon::L2_loadrd_io:
00083   case Hexagon::L2_loadrh_io:
00084   case Hexagon::L2_loadrb_io:
00085   case Hexagon::L2_loadrub_io:
00086     if (MI->getOperand(2).isFI() &&
00087         MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
00088       FrameIndex = MI->getOperand(2).getIndex();
00089       return MI->getOperand(0).getReg();
00090     }
00091     break;
00092   }
00093   return 0;
00094 }
00095 
00096 
00097 /// isStoreToStackSlot - If the specified machine instruction is a direct
00098 /// store to a stack slot, return the virtual or physical register number of
00099 /// the source reg along with the FrameIndex of the loaded stack slot.  If
00100 /// not, return 0.  This predicate must return 0 if the instruction has
00101 /// any side effects other than storing to the stack slot.
00102 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
00103                                             int &FrameIndex) const {
00104   switch (MI->getOpcode()) {
00105   default: break;
00106   case Hexagon::S2_storeri_io:
00107   case Hexagon::S2_storerd_io:
00108   case Hexagon::S2_storerh_io:
00109   case Hexagon::S2_storerb_io:
00110     if (MI->getOperand(2).isFI() &&
00111         MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
00112       FrameIndex = MI->getOperand(0).getIndex();
00113       return MI->getOperand(2).getReg();
00114     }
00115     break;
00116   }
00117   return 0;
00118 }
00119 
00120 
00121 unsigned
00122 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
00123                              MachineBasicBlock *FBB,
00124                              const SmallVectorImpl<MachineOperand> &Cond,
00125                              DebugLoc DL) const{
00126 
00127     int BOpc   = Hexagon::J2_jump;
00128     int BccOpc = Hexagon::J2_jumpt;
00129 
00130     assert(TBB && "InsertBranch must not be told to insert a fallthrough");
00131 
00132     int regPos = 0;
00133     // Check if ReverseBranchCondition has asked to reverse this branch
00134     // If we want to reverse the branch an odd number of times, we want
00135     // JMP_f.
00136     if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
00137       BccOpc = Hexagon::J2_jumpf;
00138       regPos = 1;
00139     }
00140 
00141     if (!FBB) {
00142       if (Cond.empty()) {
00143         // Due to a bug in TailMerging/CFG Optimization, we need to add a
00144         // special case handling of a predicated jump followed by an
00145         // unconditional jump. If not, Tail Merging and CFG Optimization go
00146         // into an infinite loop.
00147         MachineBasicBlock *NewTBB, *NewFBB;
00148         SmallVector<MachineOperand, 4> Cond;
00149         MachineInstr *Term = MBB.getFirstTerminator();
00150         if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
00151                                                  false)) {
00152           MachineBasicBlock *NextBB =
00153             std::next(MachineFunction::iterator(&MBB));
00154           if (NewTBB == NextBB) {
00155             ReverseBranchCondition(Cond);
00156             RemoveBranch(MBB);
00157             return InsertBranch(MBB, TBB, nullptr, Cond, DL);
00158           }
00159         }
00160         BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
00161       } else {
00162         BuildMI(&MBB, DL,
00163                 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
00164       }
00165       return 1;
00166     }
00167 
00168     BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
00169     BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
00170 
00171     return 2;
00172 }
00173 
00174 
00175 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
00176                                      MachineBasicBlock *&TBB,
00177                                  MachineBasicBlock *&FBB,
00178                                  SmallVectorImpl<MachineOperand> &Cond,
00179                                  bool AllowModify) const {
00180   TBB = nullptr;
00181   FBB = nullptr;
00182 
00183   // If the block has no terminators, it just falls into the block after it.
00184   MachineBasicBlock::instr_iterator I = MBB.instr_end();
00185   if (I == MBB.instr_begin())
00186     return false;
00187 
00188   // A basic block may looks like this:
00189   //
00190   //  [   insn
00191   //     EH_LABEL
00192   //      insn
00193   //      insn
00194   //      insn
00195   //     EH_LABEL
00196   //      insn     ]
00197   //
00198   // It has two succs but does not have a terminator
00199   // Don't know how to handle it.
00200   do {
00201     --I;
00202     if (I->isEHLabel())
00203       return true;
00204   } while (I != MBB.instr_begin());
00205 
00206   I = MBB.instr_end();
00207   --I;
00208 
00209   while (I->isDebugValue()) {
00210     if (I == MBB.instr_begin())
00211       return false;
00212     --I;
00213   }
00214 
00215   // Delete the JMP if it's equivalent to a fall-through.
00216   if (AllowModify && I->getOpcode() == Hexagon::J2_jump &&
00217       MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
00218     DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
00219     I->eraseFromParent();
00220     I = MBB.instr_end();
00221     if (I == MBB.instr_begin())
00222       return false;
00223     --I;
00224   }
00225   if (!isUnpredicatedTerminator(I))
00226     return false;
00227 
00228   // Get the last instruction in the block.
00229   MachineInstr *LastInst = I;
00230   MachineInstr *SecondLastInst = nullptr;
00231   // Find one more terminator if present.
00232   do {
00233     if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(I)) {
00234       if (!SecondLastInst)
00235         SecondLastInst = I;
00236       else
00237         // This is a third branch.
00238         return true;
00239     }
00240     if (I == MBB.instr_begin())
00241       break;
00242     --I;
00243   } while(I);
00244 
00245   int LastOpcode = LastInst->getOpcode();
00246 
00247   bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
00248   bool LastOpcodeHasNot = PredOpcodeHasNot(LastOpcode);
00249 
00250   // If there is only one terminator instruction, process it.
00251   if (LastInst && !SecondLastInst) {
00252     if (LastOpcode == Hexagon::J2_jump) {
00253       TBB = LastInst->getOperand(0).getMBB();
00254       return false;
00255     }
00256     if (LastOpcode == Hexagon::ENDLOOP0) {
00257       TBB = LastInst->getOperand(0).getMBB();
00258       Cond.push_back(LastInst->getOperand(0));
00259       return false;
00260     }
00261     if (LastOpcodeHasJMP_c) {
00262       TBB = LastInst->getOperand(1).getMBB();
00263       if (LastOpcodeHasNot) {
00264         Cond.push_back(MachineOperand::CreateImm(0));
00265       }
00266       Cond.push_back(LastInst->getOperand(0));
00267       return false;
00268     }
00269     // Otherwise, don't know what this is.
00270     return true;
00271   }
00272 
00273   int SecLastOpcode = SecondLastInst->getOpcode();
00274 
00275   bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
00276   bool SecLastOpcodeHasNot = PredOpcodeHasNot(SecLastOpcode);
00277   if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
00278     TBB =  SecondLastInst->getOperand(1).getMBB();
00279     if (SecLastOpcodeHasNot)
00280       Cond.push_back(MachineOperand::CreateImm(0));
00281     Cond.push_back(SecondLastInst->getOperand(0));
00282     FBB = LastInst->getOperand(0).getMBB();
00283     return false;
00284   }
00285 
00286   // If the block ends with two Hexagon:JMPs, handle it.  The second one is not
00287   // executed, so remove it.
00288   if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
00289     TBB = SecondLastInst->getOperand(0).getMBB();
00290     I = LastInst;
00291     if (AllowModify)
00292       I->eraseFromParent();
00293     return false;
00294   }
00295 
00296   // If the block ends with an ENDLOOP, and JMP, handle it.
00297   if (SecLastOpcode == Hexagon::ENDLOOP0 &&
00298       LastOpcode == Hexagon::J2_jump) {
00299     TBB = SecondLastInst->getOperand(0).getMBB();
00300     Cond.push_back(SecondLastInst->getOperand(0));
00301     FBB = LastInst->getOperand(0).getMBB();
00302     return false;
00303   }
00304 
00305   // Otherwise, can't handle this.
00306   return true;
00307 }
00308 
00309 
00310 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
00311   int BOpc   = Hexagon::J2_jump;
00312   int BccOpc = Hexagon::J2_jumpt;
00313   int BccOpcNot = Hexagon::J2_jumpf;
00314 
00315   MachineBasicBlock::iterator I = MBB.end();
00316   if (I == MBB.begin()) return 0;
00317   --I;
00318   if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
00319       I->getOpcode() != BccOpcNot)
00320     return 0;
00321 
00322   // Remove the branch.
00323   I->eraseFromParent();
00324 
00325   I = MBB.end();
00326 
00327   if (I == MBB.begin()) return 1;
00328   --I;
00329   if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
00330     return 1;
00331 
00332   // Remove the branch.
00333   I->eraseFromParent();
00334   return 2;
00335 }
00336 
00337 
00338 /// \brief For a comparison instruction, return the source registers in
00339 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
00340 /// compares against in CmpValue. Return true if the comparison instruction
00341 /// can be analyzed.
00342 bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
00343                                       unsigned &SrcReg, unsigned &SrcReg2,
00344                                       int &Mask, int &Value) const {
00345   unsigned Opc = MI->getOpcode();
00346 
00347   // Set mask and the first source register.
00348   switch (Opc) {
00349     case Hexagon::C2_cmpeqp:
00350     case Hexagon::C2_cmpeqi:
00351     case Hexagon::C2_cmpeq:
00352     case Hexagon::C2_cmpgtp:
00353     case Hexagon::C2_cmpgtup:
00354     case Hexagon::C2_cmpgtui:
00355     case Hexagon::C2_cmpgtu:
00356     case Hexagon::C2_cmpgti:
00357     case Hexagon::C2_cmpgt:
00358       SrcReg = MI->getOperand(1).getReg();
00359       Mask = ~0;
00360       break;
00361     case Hexagon::A4_cmpbeqi:
00362     case Hexagon::A4_cmpbeq:
00363     case Hexagon::A4_cmpbgtui:
00364     case Hexagon::A4_cmpbgtu:
00365     case Hexagon::A4_cmpbgt:
00366       SrcReg = MI->getOperand(1).getReg();
00367       Mask = 0xFF;
00368       break;
00369     case Hexagon::A4_cmpheqi:
00370     case Hexagon::A4_cmpheq:
00371     case Hexagon::A4_cmphgtui:
00372     case Hexagon::A4_cmphgtu:
00373     case Hexagon::A4_cmphgt:
00374       SrcReg = MI->getOperand(1).getReg();
00375       Mask = 0xFFFF;
00376       break;
00377   }
00378 
00379   // Set the value/second source register.
00380   switch (Opc) {
00381     case Hexagon::C2_cmpeqp:
00382     case Hexagon::C2_cmpeq:
00383     case Hexagon::C2_cmpgtp:
00384     case Hexagon::C2_cmpgtup:
00385     case Hexagon::C2_cmpgtu:
00386     case Hexagon::C2_cmpgt:
00387     case Hexagon::A4_cmpbeq:
00388     case Hexagon::A4_cmpbgtu:
00389     case Hexagon::A4_cmpbgt:
00390     case Hexagon::A4_cmpheq:
00391     case Hexagon::A4_cmphgtu:
00392     case Hexagon::A4_cmphgt:
00393       SrcReg2 = MI->getOperand(2).getReg();
00394       return true;
00395 
00396     case Hexagon::C2_cmpeqi:
00397     case Hexagon::C2_cmpgtui:
00398     case Hexagon::C2_cmpgti:
00399     case Hexagon::A4_cmpbeqi:
00400     case Hexagon::A4_cmpbgtui:
00401     case Hexagon::A4_cmpheqi:
00402     case Hexagon::A4_cmphgtui:
00403       SrcReg2 = 0;
00404       Value = MI->getOperand(2).getImm();
00405       return true;
00406   }
00407 
00408   return false;
00409 }
00410 
00411 
00412 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
00413                                  MachineBasicBlock::iterator I, DebugLoc DL,
00414                                  unsigned DestReg, unsigned SrcReg,
00415                                  bool KillSrc) const {
00416   if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
00417     BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg).addReg(SrcReg);
00418     return;
00419   }
00420   if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
00421     BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg).addReg(SrcReg);
00422     return;
00423   }
00424   if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
00425     // Map Pd = Ps to Pd = or(Ps, Ps).
00426     BuildMI(MBB, I, DL, get(Hexagon::C2_or),
00427             DestReg).addReg(SrcReg).addReg(SrcReg);
00428     return;
00429   }
00430   if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
00431       Hexagon::IntRegsRegClass.contains(SrcReg)) {
00432     // We can have an overlap between single and double reg: r1:0 = r0.
00433     if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
00434         // r1:0 = r0
00435         BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
00436                 Hexagon::subreg_hireg))).addImm(0);
00437     } else {
00438         // r1:0 = r1 or no overlap.
00439         BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), (RI.getSubReg(DestReg,
00440                 Hexagon::subreg_loreg))).addReg(SrcReg);
00441         BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
00442                 Hexagon::subreg_hireg))).addImm(0);
00443     }
00444     return;
00445   }
00446   if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
00447       Hexagon::IntRegsRegClass.contains(SrcReg)) {
00448     BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg).addReg(SrcReg);
00449     return;
00450   }
00451   if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
00452       Hexagon::IntRegsRegClass.contains(DestReg)) {
00453     BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg).
00454       addReg(SrcReg, getKillRegState(KillSrc));
00455     return;
00456   }
00457   if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
00458       Hexagon::PredRegsRegClass.contains(DestReg)) {
00459     BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg).
00460       addReg(SrcReg, getKillRegState(KillSrc));
00461     return;
00462   }
00463 
00464   llvm_unreachable("Unimplemented");
00465 }
00466 
00467 
00468 void HexagonInstrInfo::
00469 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
00470                     unsigned SrcReg, bool isKill, int FI,
00471                     const TargetRegisterClass *RC,
00472                     const TargetRegisterInfo *TRI) const {
00473 
00474   DebugLoc DL = MBB.findDebugLoc(I);
00475   MachineFunction &MF = *MBB.getParent();
00476   MachineFrameInfo &MFI = *MF.getFrameInfo();
00477   unsigned Align = MFI.getObjectAlignment(FI);
00478 
00479   MachineMemOperand *MMO =
00480       MF.getMachineMemOperand(
00481                       MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
00482                       MachineMemOperand::MOStore,
00483                       MFI.getObjectSize(FI),
00484                       Align);
00485 
00486   if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
00487     BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
00488           .addFrameIndex(FI).addImm(0)
00489           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00490   } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
00491     BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
00492           .addFrameIndex(FI).addImm(0)
00493           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00494   } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
00495     BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
00496           .addFrameIndex(FI).addImm(0)
00497           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00498   } else {
00499     llvm_unreachable("Unimplemented");
00500   }
00501 }
00502 
00503 
00504 void HexagonInstrInfo::storeRegToAddr(
00505                                  MachineFunction &MF, unsigned SrcReg,
00506                                  bool isKill,
00507                                  SmallVectorImpl<MachineOperand> &Addr,
00508                                  const TargetRegisterClass *RC,
00509                                  SmallVectorImpl<MachineInstr*> &NewMIs) const
00510 {
00511   llvm_unreachable("Unimplemented");
00512 }
00513 
00514 
00515 void HexagonInstrInfo::
00516 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
00517                      unsigned DestReg, int FI,
00518                      const TargetRegisterClass *RC,
00519                      const TargetRegisterInfo *TRI) const {
00520   DebugLoc DL = MBB.findDebugLoc(I);
00521   MachineFunction &MF = *MBB.getParent();
00522   MachineFrameInfo &MFI = *MF.getFrameInfo();
00523   unsigned Align = MFI.getObjectAlignment(FI);
00524 
00525   MachineMemOperand *MMO =
00526       MF.getMachineMemOperand(
00527                       MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
00528                       MachineMemOperand::MOLoad,
00529                       MFI.getObjectSize(FI),
00530                       Align);
00531   if (RC == &Hexagon::IntRegsRegClass) {
00532     BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
00533           .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00534   } else if (RC == &Hexagon::DoubleRegsRegClass) {
00535     BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
00536           .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00537   } else if (RC == &Hexagon::PredRegsRegClass) {
00538     BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
00539           .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00540   } else {
00541     llvm_unreachable("Can't store this register to stack slot");
00542   }
00543 }
00544 
00545 
00546 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
00547                                         SmallVectorImpl<MachineOperand> &Addr,
00548                                         const TargetRegisterClass *RC,
00549                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
00550   llvm_unreachable("Unimplemented");
00551 }
00552 
00553 
00554 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
00555                                                     MachineInstr* MI,
00556                                           const SmallVectorImpl<unsigned> &Ops,
00557                                                     int FI) const {
00558   // Hexagon_TODO: Implement.
00559   return nullptr;
00560 }
00561 
00562 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
00563 
00564   MachineRegisterInfo &RegInfo = MF->getRegInfo();
00565   const TargetRegisterClass *TRC;
00566   if (VT == MVT::i1) {
00567     TRC = &Hexagon::PredRegsRegClass;
00568   } else if (VT == MVT::i32 || VT == MVT::f32) {
00569     TRC = &Hexagon::IntRegsRegClass;
00570   } else if (VT == MVT::i64 || VT == MVT::f64) {
00571     TRC = &Hexagon::DoubleRegsRegClass;
00572   } else {
00573     llvm_unreachable("Cannot handle this register class");
00574   }
00575 
00576   unsigned NewReg = RegInfo.createVirtualRegister(TRC);
00577   return NewReg;
00578 }
00579 
00580 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
00581   // Constant extenders are allowed only for V4 and above.
00582   if (!Subtarget.hasV4TOps())
00583     return false;
00584 
00585   const MCInstrDesc &MID = MI->getDesc();
00586   const uint64_t F = MID.TSFlags;
00587   if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
00588     return true;
00589 
00590   // TODO: This is largely obsolete now. Will need to be removed
00591   // in consecutive patches.
00592   switch(MI->getOpcode()) {
00593     // TFR_FI Remains a special case.
00594     case Hexagon::TFR_FI:
00595       return true;
00596     default:
00597       return false;
00598   }
00599   return  false;
00600 }
00601 
00602 // This returns true in two cases:
00603 // - The OP code itself indicates that this is an extended instruction.
00604 // - One of MOs has been marked with HMOTF_ConstExtended flag.
00605 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
00606   // First check if this is permanently extended op code.
00607   const uint64_t F = MI->getDesc().TSFlags;
00608   if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
00609     return true;
00610   // Use MO operand flags to determine if one of MI's operands
00611   // has HMOTF_ConstExtended flag set.
00612   for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
00613        E = MI->operands_end(); I != E; ++I) {
00614     if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
00615       return true;
00616   }
00617   return  false;
00618 }
00619 
00620 bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const {
00621   return MI->getDesc().isBranch();
00622 }
00623 
00624 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
00625   if (isNewValueJump(MI))
00626     return true;
00627 
00628   if (isNewValueStore(MI))
00629     return true;
00630 
00631   return false;
00632 }
00633 
00634 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
00635   return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
00636 }
00637 
00638 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
00639   bool isPred = MI->getDesc().isPredicable();
00640 
00641   if (!isPred)
00642     return false;
00643 
00644   const int Opc = MI->getOpcode();
00645 
00646   switch(Opc) {
00647   case Hexagon::A2_tfrsi:
00648     return isInt<12>(MI->getOperand(1).getImm());
00649 
00650   case Hexagon::S2_storerd_io:
00651     return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
00652 
00653   case Hexagon::S2_storeri_io:
00654   case Hexagon::S2_storerinew_io:
00655     return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
00656 
00657   case Hexagon::S2_storerh_io:
00658   case Hexagon::S2_storerhnew_io:
00659     return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
00660 
00661   case Hexagon::S2_storerb_io:
00662   case Hexagon::S2_storerbnew_io:
00663     return isUInt<6>(MI->getOperand(1).getImm());
00664 
00665   case Hexagon::L2_loadrd_io:
00666     return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
00667 
00668   case Hexagon::L2_loadri_io:
00669     return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
00670 
00671   case Hexagon::L2_loadrh_io:
00672   case Hexagon::L2_loadruh_io:
00673     return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
00674 
00675   case Hexagon::L2_loadrb_io:
00676   case Hexagon::L2_loadrub_io:
00677     return isUInt<6>(MI->getOperand(2).getImm());
00678 
00679   case Hexagon::L2_loadrd_pi:
00680     return isShiftedInt<4,3>(MI->getOperand(3).getImm());
00681 
00682   case Hexagon::L2_loadri_pi:
00683     return isShiftedInt<4,2>(MI->getOperand(3).getImm());
00684 
00685   case Hexagon::L2_loadrh_pi:
00686   case Hexagon::L2_loadruh_pi:
00687     return isShiftedInt<4,1>(MI->getOperand(3).getImm());
00688 
00689   case Hexagon::L2_loadrb_pi:
00690   case Hexagon::L2_loadrub_pi:
00691     return isInt<4>(MI->getOperand(3).getImm());
00692 
00693   case Hexagon::S4_storeirb_io:
00694   case Hexagon::S4_storeirh_io:
00695   case Hexagon::S4_storeiri_io:
00696     return (isUInt<6>(MI->getOperand(1).getImm()) &&
00697             isInt<6>(MI->getOperand(2).getImm()));
00698 
00699   case Hexagon::ADD_ri:
00700     return isInt<8>(MI->getOperand(2).getImm());
00701 
00702   case Hexagon::A2_aslh:
00703   case Hexagon::A2_asrh:
00704   case Hexagon::A2_sxtb:
00705   case Hexagon::A2_sxth:
00706   case Hexagon::A2_zxtb:
00707   case Hexagon::A2_zxth:
00708     return Subtarget.hasV4TOps();
00709   }
00710 
00711   return true;
00712 }
00713 
00714 // This function performs the following inversiones:
00715 //
00716 //  cPt    ---> cNotPt
00717 //  cNotPt ---> cPt
00718 //
00719 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
00720   int InvPredOpcode;
00721   InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
00722                                         : Hexagon::getTruePredOpcode(Opc);
00723   if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
00724     return InvPredOpcode;
00725 
00726   switch(Opc) {
00727     default: llvm_unreachable("Unexpected predicated instruction");
00728     case Hexagon::C2_ccombinewt:
00729       return Hexagon::C2_ccombinewf;
00730     case Hexagon::C2_ccombinewf:
00731       return Hexagon::C2_ccombinewt;
00732 
00733       // Dealloc_return.
00734     case Hexagon::L4_return_t:
00735       return Hexagon::L4_return_f;
00736     case Hexagon::L4_return_f:
00737       return Hexagon::L4_return_t;
00738   }
00739 }
00740 
00741 // New Value Store instructions.
00742 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
00743   const uint64_t F = MI->getDesc().TSFlags;
00744 
00745   return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
00746 }
00747 
00748 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
00749   const uint64_t F = get(Opcode).TSFlags;
00750 
00751   return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
00752 }
00753 
00754 int HexagonInstrInfo::
00755 getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
00756   enum Hexagon::PredSense inPredSense;
00757   inPredSense = invertPredicate ? Hexagon::PredSense_false :
00758                                   Hexagon::PredSense_true;
00759   int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
00760   if (CondOpcode >= 0) // Valid Conditional opcode/instruction
00761     return CondOpcode;
00762 
00763   // This switch case will be removed once all the instructions have been
00764   // modified to use relation maps.
00765   switch(Opc) {
00766   case Hexagon::TFRI_f:
00767     return !invertPredicate ? Hexagon::TFRI_cPt_f :
00768                               Hexagon::TFRI_cNotPt_f;
00769   case Hexagon::A2_combinew:
00770     return !invertPredicate ? Hexagon::C2_ccombinewt :
00771                               Hexagon::C2_ccombinewf;
00772 
00773   // DEALLOC_RETURN.
00774   case Hexagon::L4_return:
00775     return !invertPredicate ? Hexagon::L4_return_t:
00776                               Hexagon::L4_return_f;
00777   }
00778   llvm_unreachable("Unexpected predicable instruction");
00779 }
00780 
00781 
00782 bool HexagonInstrInfo::
00783 PredicateInstruction(MachineInstr *MI,
00784                      const SmallVectorImpl<MachineOperand> &Cond) const {
00785   int Opc = MI->getOpcode();
00786   assert (isPredicable(MI) && "Expected predicable instruction");
00787   bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
00788                      (Cond[0].getImm() == 0));
00789 
00790   // This will change MI's opcode to its predicate version.
00791   // However, its operand list is still the old one, i.e. the
00792   // non-predicate one.
00793   MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
00794 
00795   int oper = -1;
00796   unsigned int GAIdx = 0;
00797 
00798   // Indicates whether the current MI has a GlobalAddress operand
00799   bool hasGAOpnd = false;
00800   std::vector<MachineOperand> tmpOpnds;
00801 
00802   // Indicates whether we need to shift operands to right.
00803   bool needShift = true;
00804 
00805   // The predicate is ALWAYS the FIRST input operand !!!
00806   if (MI->getNumOperands() == 0) {
00807     // The non-predicate version of MI does not take any operands,
00808     // i.e. no outs and no ins. In this condition, the predicate
00809     // operand will be directly placed at Operands[0]. No operand
00810     // shift is needed.
00811     // Example: BARRIER
00812     needShift = false;
00813     oper = -1;
00814   }
00815   else if (   MI->getOperand(MI->getNumOperands()-1).isReg()
00816            && MI->getOperand(MI->getNumOperands()-1).isDef()
00817            && !MI->getOperand(MI->getNumOperands()-1).isImplicit()) {
00818     // The non-predicate version of MI does not have any input operands.
00819     // In this condition, we extend the length of Operands[] by one and
00820     // copy the original last operand to the newly allocated slot.
00821     // At this moment, it is just a place holder. Later, we will put
00822     // predicate operand directly into it. No operand shift is needed.
00823     // Example: r0=BARRIER (this is a faked insn used here for illustration)
00824     MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
00825     needShift = false;
00826     oper = MI->getNumOperands() - 2;
00827   }
00828   else {
00829     // We need to right shift all input operands by one. Duplicate the
00830     // last operand into the newly allocated slot.
00831     MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
00832   }
00833 
00834   if (needShift)
00835   {
00836     // Operands[ MI->getNumOperands() - 2 ] has been copied into
00837     // Operands[ MI->getNumOperands() - 1 ], so we start from
00838     // Operands[ MI->getNumOperands() - 3 ].
00839     // oper is a signed int.
00840     // It is ok if "MI->getNumOperands()-3" is -3, -2, or -1.
00841     for (oper = MI->getNumOperands() - 3; oper >= 0; --oper)
00842     {
00843       MachineOperand &MO = MI->getOperand(oper);
00844 
00845       // Opnd[0] Opnd[1] Opnd[2] Opnd[3] Opnd[4]   Opnd[5]   Opnd[6]   Opnd[7]
00846       // <Def0>  <Def1>  <Use0>  <Use1>  <ImpDef0> <ImpDef1> <ImpUse0> <ImpUse1>
00847       //               /\~
00848       //              /||\~
00849       //               ||
00850       //        Predicate Operand here
00851       if (MO.isReg() && !MO.isUse() && !MO.isImplicit()) {
00852         break;
00853       }
00854       if (MO.isReg()) {
00855         MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
00856                                                 MO.isImplicit(), MO.isKill(),
00857                                                 MO.isDead(), MO.isUndef(),
00858                                                 MO.isDebug());
00859       }
00860       else if (MO.isImm()) {
00861         MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
00862       }
00863       else if (MO.isGlobal()) {
00864         // MI can not have more than one GlobalAddress operand.
00865         assert(hasGAOpnd == false && "MI can only have one GlobalAddress opnd");
00866 
00867         // There is no member function called "ChangeToGlobalAddress" in the
00868         // MachineOperand class (not like "ChangeToRegister" and
00869         // "ChangeToImmediate"). So we have to remove them from Operands[] list
00870         // first, and then add them back after we have inserted the predicate
00871         // operand. tmpOpnds[] is to remember these operands before we remove
00872         // them.
00873         tmpOpnds.push_back(MO);
00874 
00875         // Operands[oper] is a GlobalAddress operand;
00876         // Operands[oper+1] has been copied into Operands[oper+2];
00877         hasGAOpnd = true;
00878         GAIdx = oper;
00879         continue;
00880       }
00881       else {
00882         llvm_unreachable("Unexpected operand type");
00883       }
00884     }
00885   }
00886 
00887   int regPos = invertJump ? 1 : 0;
00888   MachineOperand PredMO = Cond[regPos];
00889 
00890   // [oper] now points to the last explicit Def. Predicate operand must be
00891   // located at [oper+1]. See diagram above.
00892   // This assumes that the predicate is always the first operand,
00893   // i.e. Operands[0+numResults], in the set of inputs
00894   // It is better to have an assert here to check this. But I don't know how
00895   // to write this assert because findFirstPredOperandIdx() would return -1
00896   if (oper < -1) oper = -1;
00897 
00898   MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
00899                                           PredMO.isImplicit(), false,
00900                                           PredMO.isDead(), PredMO.isUndef(),
00901                                           PredMO.isDebug());
00902 
00903   MachineRegisterInfo &RegInfo = MI->getParent()->getParent()->getRegInfo();
00904   RegInfo.clearKillFlags(PredMO.getReg());
00905 
00906   if (hasGAOpnd)
00907   {
00908     unsigned int i;
00909 
00910     // Operands[GAIdx] is the original GlobalAddress operand, which is
00911     // already copied into tmpOpnds[0].
00912     // Operands[GAIdx] now stores a copy of Operands[GAIdx-1]
00913     // Operands[GAIdx+1] has already been copied into Operands[GAIdx+2],
00914     // so we start from [GAIdx+2]
00915     for (i = GAIdx + 2; i < MI->getNumOperands(); ++i)
00916       tmpOpnds.push_back(MI->getOperand(i));
00917 
00918     // Remove all operands in range [ (GAIdx+1) ... (MI->getNumOperands()-1) ]
00919     // It is very important that we always remove from the end of Operands[]
00920     // MI->getNumOperands() is at least 2 if program goes to here.
00921     for (i = MI->getNumOperands() - 1; i > GAIdx; --i)
00922       MI->RemoveOperand(i);
00923 
00924     for (i = 0; i < tmpOpnds.size(); ++i)
00925       MI->addOperand(tmpOpnds[i]);
00926   }
00927 
00928   return true;
00929 }
00930 
00931 
00932 bool
00933 HexagonInstrInfo::
00934 isProfitableToIfCvt(MachineBasicBlock &MBB,
00935                     unsigned NumCycles,
00936                     unsigned ExtraPredCycles,
00937                     const BranchProbability &Probability) const {
00938   return true;
00939 }
00940 
00941 
00942 bool
00943 HexagonInstrInfo::
00944 isProfitableToIfCvt(MachineBasicBlock &TMBB,
00945                     unsigned NumTCycles,
00946                     unsigned ExtraTCycles,
00947                     MachineBasicBlock &FMBB,
00948                     unsigned NumFCycles,
00949                     unsigned ExtraFCycles,
00950                     const BranchProbability &Probability) const {
00951   return true;
00952 }
00953 
00954 // Returns true if an instruction is predicated irrespective of the predicate
00955 // sense. For example, all of the following will return true.
00956 // if (p0) R1 = add(R2, R3)
00957 // if (!p0) R1 = add(R2, R3)
00958 // if (p0.new) R1 = add(R2, R3)
00959 // if (!p0.new) R1 = add(R2, R3)
00960 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
00961   const uint64_t F = MI->getDesc().TSFlags;
00962 
00963   return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
00964 }
00965 
00966 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
00967   const uint64_t F = get(Opcode).TSFlags;
00968 
00969   return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
00970 }
00971 
00972 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
00973   const uint64_t F = MI->getDesc().TSFlags;
00974 
00975   assert(isPredicated(MI));
00976   return (!((F >> HexagonII::PredicatedFalsePos) &
00977             HexagonII::PredicatedFalseMask));
00978 }
00979 
00980 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
00981   const uint64_t F = get(Opcode).TSFlags;
00982 
00983   // Make sure that the instruction is predicated.
00984   assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
00985   return (!((F >> HexagonII::PredicatedFalsePos) &
00986             HexagonII::PredicatedFalseMask));
00987 }
00988 
00989 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
00990   const uint64_t F = MI->getDesc().TSFlags;
00991 
00992   assert(isPredicated(MI));
00993   return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
00994 }
00995 
00996 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
00997   const uint64_t F = get(Opcode).TSFlags;
00998 
00999   assert(isPredicated(Opcode));
01000   return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
01001 }
01002 
01003 // Returns true, if a ST insn can be promoted to a new-value store.
01004 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const {
01005   const HexagonRegisterInfo& QRI = getRegisterInfo();
01006   const uint64_t F = MI->getDesc().TSFlags;
01007 
01008   return ((F >> HexagonII::mayNVStorePos) &
01009            HexagonII::mayNVStoreMask &
01010            QRI.Subtarget.hasV4TOps());
01011 }
01012 
01013 bool
01014 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
01015                                    std::vector<MachineOperand> &Pred) const {
01016   for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
01017     MachineOperand MO = MI->getOperand(oper);
01018     if (MO.isReg() && MO.isDef()) {
01019       const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
01020       if (RC == &Hexagon::PredRegsRegClass) {
01021         Pred.push_back(MO);
01022         return true;
01023       }
01024     }
01025   }
01026   return false;
01027 }
01028 
01029 
01030 bool
01031 HexagonInstrInfo::
01032 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
01033                   const SmallVectorImpl<MachineOperand> &Pred2) const {
01034   // TODO: Fix this
01035   return false;
01036 }
01037 
01038 
01039 //
01040 // We indicate that we want to reverse the branch by
01041 // inserting a 0 at the beginning of the Cond vector.
01042 //
01043 bool HexagonInstrInfo::
01044 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
01045   if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
01046     Cond.erase(Cond.begin());
01047   } else {
01048     Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
01049   }
01050   return false;
01051 }
01052 
01053 
01054 bool HexagonInstrInfo::
01055 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
01056                           const BranchProbability &Probability) const {
01057   return (NumInstrs <= 4);
01058 }
01059 
01060 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
01061   switch (MI->getOpcode()) {
01062   default: return false;
01063   case Hexagon::L4_return:
01064   case Hexagon::L4_return_t:
01065   case Hexagon::L4_return_f:
01066   case Hexagon::L4_return_tnew_pnt:
01067   case Hexagon::L4_return_fnew_pnt:
01068   case Hexagon::L4_return_tnew_pt:
01069   case Hexagon::L4_return_fnew_pt:
01070    return true;
01071   }
01072 }
01073 
01074 
01075 bool HexagonInstrInfo::
01076 isValidOffset(const int Opcode, const int Offset) const {
01077   // This function is to check whether the "Offset" is in the correct range of
01078   // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
01079   // inserted to calculate the final address. Due to this reason, the function
01080   // assumes that the "Offset" has correct alignment.
01081   // We used to assert if the offset was not properly aligned, however,
01082   // there are cases where a misaligned pointer recast can cause this
01083   // problem, and we need to allow for it. The front end warns of such
01084   // misaligns with respect to load size.
01085 
01086   switch(Opcode) {
01087 
01088   case Hexagon::L2_loadri_io:
01089   case Hexagon::S2_storeri_io:
01090     return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
01091       (Offset <= Hexagon_MEMW_OFFSET_MAX);
01092 
01093   case Hexagon::L2_loadrd_io:
01094   case Hexagon::S2_storerd_io:
01095     return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
01096       (Offset <= Hexagon_MEMD_OFFSET_MAX);
01097 
01098   case Hexagon::L2_loadrh_io:
01099   case Hexagon::L2_loadruh_io:
01100   case Hexagon::S2_storerh_io:
01101     return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
01102       (Offset <= Hexagon_MEMH_OFFSET_MAX);
01103 
01104   case Hexagon::L2_loadrb_io:
01105   case Hexagon::S2_storerb_io:
01106   case Hexagon::L2_loadrub_io:
01107     return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
01108       (Offset <= Hexagon_MEMB_OFFSET_MAX);
01109 
01110   case Hexagon::ADD_ri:
01111   case Hexagon::TFR_FI:
01112     return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
01113       (Offset <= Hexagon_ADDI_OFFSET_MAX);
01114 
01115   case Hexagon::L4_iadd_memopw_io:
01116   case Hexagon::L4_isub_memopw_io:
01117   case Hexagon::L4_add_memopw_io:
01118   case Hexagon::L4_sub_memopw_io:
01119   case Hexagon::L4_and_memopw_io:
01120   case Hexagon::L4_or_memopw_io:
01121     return (0 <= Offset && Offset <= 255);
01122 
01123   case Hexagon::L4_iadd_memoph_io:
01124   case Hexagon::L4_isub_memoph_io:
01125   case Hexagon::L4_add_memoph_io:
01126   case Hexagon::L4_sub_memoph_io:
01127   case Hexagon::L4_and_memoph_io:
01128   case Hexagon::L4_or_memoph_io:
01129     return (0 <= Offset && Offset <= 127);
01130 
01131   case Hexagon::L4_iadd_memopb_io:
01132   case Hexagon::L4_isub_memopb_io:
01133   case Hexagon::L4_add_memopb_io:
01134   case Hexagon::L4_sub_memopb_io:
01135   case Hexagon::L4_and_memopb_io:
01136   case Hexagon::L4_or_memopb_io:
01137     return (0 <= Offset && Offset <= 63);
01138 
01139   // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
01140   // any size. Later pass knows how to handle it.
01141   case Hexagon::STriw_pred:
01142   case Hexagon::LDriw_pred:
01143     return true;
01144 
01145   case Hexagon::J2_loop0i:
01146     return isUInt<10>(Offset);
01147 
01148   // INLINEASM is very special.
01149   case Hexagon::INLINEASM:
01150     return true;
01151   }
01152 
01153   llvm_unreachable("No offset range is defined for this opcode. "
01154                    "Please define it in the above switch statement!");
01155 }
01156 
01157 
01158 //
01159 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
01160 //
01161 bool HexagonInstrInfo::
01162 isValidAutoIncImm(const EVT VT, const int Offset) const {
01163 
01164   if (VT == MVT::i64) {
01165       return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
01166               Offset <= Hexagon_MEMD_AUTOINC_MAX &&
01167               (Offset & 0x7) == 0);
01168   }
01169   if (VT == MVT::i32) {
01170       return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
01171               Offset <= Hexagon_MEMW_AUTOINC_MAX &&
01172               (Offset & 0x3) == 0);
01173   }
01174   if (VT == MVT::i16) {
01175       return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
01176               Offset <= Hexagon_MEMH_AUTOINC_MAX &&
01177               (Offset & 0x1) == 0);
01178   }
01179   if (VT == MVT::i8) {
01180       return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
01181               Offset <= Hexagon_MEMB_AUTOINC_MAX);
01182   }
01183   llvm_unreachable("Not an auto-inc opc!");
01184 }
01185 
01186 
01187 bool HexagonInstrInfo::
01188 isMemOp(const MachineInstr *MI) const {
01189 //  return MI->getDesc().mayLoad() && MI->getDesc().mayStore();
01190 
01191   switch (MI->getOpcode())
01192   {
01193   default: return false;
01194   case Hexagon::L4_iadd_memopw_io:
01195   case Hexagon::L4_isub_memopw_io:
01196   case Hexagon::L4_add_memopw_io:
01197   case Hexagon::L4_sub_memopw_io:
01198   case Hexagon::L4_and_memopw_io:
01199   case Hexagon::L4_or_memopw_io:
01200   case Hexagon::L4_iadd_memoph_io:
01201   case Hexagon::L4_isub_memoph_io:
01202   case Hexagon::L4_add_memoph_io:
01203   case Hexagon::L4_sub_memoph_io:
01204   case Hexagon::L4_and_memoph_io:
01205   case Hexagon::L4_or_memoph_io:
01206   case Hexagon::L4_iadd_memopb_io:
01207   case Hexagon::L4_isub_memopb_io:
01208   case Hexagon::L4_add_memopb_io:
01209   case Hexagon::L4_sub_memopb_io:
01210   case Hexagon::L4_and_memopb_io:
01211   case Hexagon::L4_or_memopb_io:
01212   case Hexagon::L4_ior_memopb_io:
01213   case Hexagon::L4_ior_memoph_io:
01214   case Hexagon::L4_ior_memopw_io:
01215   case Hexagon::L4_iand_memopb_io:
01216   case Hexagon::L4_iand_memoph_io:
01217   case Hexagon::L4_iand_memopw_io:
01218     return true;
01219   }
01220   return false;
01221 }
01222 
01223 
01224 bool HexagonInstrInfo::
01225 isSpillPredRegOp(const MachineInstr *MI) const {
01226   switch (MI->getOpcode()) {
01227     default: return false;
01228     case Hexagon::STriw_pred :
01229     case Hexagon::LDriw_pred :
01230       return true;
01231   }
01232 }
01233 
01234 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
01235   switch (MI->getOpcode()) {
01236     default: return false;
01237     case Hexagon::C2_cmpeq:
01238     case Hexagon::C2_cmpeqi:
01239     case Hexagon::C2_cmpgt:
01240     case Hexagon::C2_cmpgti:
01241     case Hexagon::C2_cmpgtu:
01242     case Hexagon::C2_cmpgtui:
01243       return true;
01244   }
01245 }
01246 
01247 bool HexagonInstrInfo::
01248 isConditionalTransfer (const MachineInstr *MI) const {
01249   switch (MI->getOpcode()) {
01250     default: return false;
01251     case Hexagon::A2_tfrt:
01252     case Hexagon::A2_tfrf:
01253     case Hexagon::C2_cmoveit:
01254     case Hexagon::C2_cmoveif:
01255     case Hexagon::A2_tfrtnew:
01256     case Hexagon::A2_tfrfnew:
01257     case Hexagon::C2_cmovenewit:
01258     case Hexagon::C2_cmovenewif:
01259       return true;
01260   }
01261 }
01262 
01263 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
01264   switch (MI->getOpcode())
01265   {
01266     default: return false;
01267     case Hexagon::A2_paddf:
01268     case Hexagon::A2_paddfnew:
01269     case Hexagon::A2_paddt:
01270     case Hexagon::A2_paddtnew:
01271     case Hexagon::A2_pandf:
01272     case Hexagon::A2_pandfnew:
01273     case Hexagon::A2_pandt:
01274     case Hexagon::A2_pandtnew:
01275     case Hexagon::A4_paslhf:
01276     case Hexagon::A4_paslhfnew:
01277     case Hexagon::A4_paslht:
01278     case Hexagon::A4_paslhtnew:
01279     case Hexagon::A4_pasrhf:
01280     case Hexagon::A4_pasrhfnew:
01281     case Hexagon::A4_pasrht:
01282     case Hexagon::A4_pasrhtnew:
01283     case Hexagon::A2_porf:
01284     case Hexagon::A2_porfnew:
01285     case Hexagon::A2_port:
01286     case Hexagon::A2_portnew:
01287     case Hexagon::A2_psubf:
01288     case Hexagon::A2_psubfnew:
01289     case Hexagon::A2_psubt:
01290     case Hexagon::A2_psubtnew:
01291     case Hexagon::A2_pxorf:
01292     case Hexagon::A2_pxorfnew:
01293     case Hexagon::A2_pxort:
01294     case Hexagon::A2_pxortnew:
01295     case Hexagon::A4_psxthf:
01296     case Hexagon::A4_psxthfnew:
01297     case Hexagon::A4_psxtht:
01298     case Hexagon::A4_psxthtnew:
01299     case Hexagon::A4_psxtbf:
01300     case Hexagon::A4_psxtbfnew:
01301     case Hexagon::A4_psxtbt:
01302     case Hexagon::A4_psxtbtnew:
01303     case Hexagon::A4_pzxtbf:
01304     case Hexagon::A4_pzxtbfnew:
01305     case Hexagon::A4_pzxtbt:
01306     case Hexagon::A4_pzxtbtnew:
01307     case Hexagon::A4_pzxthf:
01308     case Hexagon::A4_pzxthfnew:
01309     case Hexagon::A4_pzxtht:
01310     case Hexagon::A4_pzxthtnew:
01311     case Hexagon::ADD_ri_cPt:
01312     case Hexagon::ADD_ri_cNotPt:
01313     case Hexagon::C2_ccombinewt:
01314     case Hexagon::C2_ccombinewf:
01315       return true;
01316   }
01317 }
01318 
01319 bool HexagonInstrInfo::
01320 isConditionalLoad (const MachineInstr* MI) const {
01321   const HexagonRegisterInfo& QRI = getRegisterInfo();
01322   switch (MI->getOpcode())
01323   {
01324     default: return false;
01325     case Hexagon::L2_ploadrdt_io :
01326     case Hexagon::L2_ploadrdf_io:
01327     case Hexagon::L2_ploadrit_io:
01328     case Hexagon::L2_ploadrif_io:
01329     case Hexagon::L2_ploadrht_io:
01330     case Hexagon::L2_ploadrhf_io:
01331     case Hexagon::L2_ploadrbt_io:
01332     case Hexagon::L2_ploadrbf_io:
01333     case Hexagon::L2_ploadruht_io:
01334     case Hexagon::L2_ploadruhf_io:
01335     case Hexagon::L2_ploadrubt_io:
01336     case Hexagon::L2_ploadrubf_io:
01337       return true;
01338     case Hexagon::L2_ploadrdt_pi:
01339     case Hexagon::L2_ploadrdf_pi:
01340     case Hexagon::L2_ploadrit_pi:
01341     case Hexagon::L2_ploadrif_pi:
01342     case Hexagon::L2_ploadrht_pi:
01343     case Hexagon::L2_ploadrhf_pi:
01344     case Hexagon::L2_ploadrbt_pi:
01345     case Hexagon::L2_ploadrbf_pi:
01346     case Hexagon::L2_ploadruht_pi:
01347     case Hexagon::L2_ploadruhf_pi:
01348     case Hexagon::L2_ploadrubt_pi:
01349     case Hexagon::L2_ploadrubf_pi:
01350       return QRI.Subtarget.hasV4TOps();
01351     case Hexagon::L4_ploadrdt_rr:
01352     case Hexagon::L4_ploadrdf_rr:
01353     case Hexagon::L4_ploadrbt_rr:
01354     case Hexagon::L4_ploadrbf_rr:
01355     case Hexagon::L4_ploadrubt_rr:
01356     case Hexagon::L4_ploadrubf_rr:
01357     case Hexagon::L4_ploadrht_rr:
01358     case Hexagon::L4_ploadrhf_rr:
01359     case Hexagon::L4_ploadruht_rr:
01360     case Hexagon::L4_ploadruhf_rr:
01361     case Hexagon::L4_ploadrit_rr:
01362     case Hexagon::L4_ploadrif_rr:
01363       return QRI.Subtarget.hasV4TOps();
01364   }
01365 }
01366 
01367 // Returns true if an instruction is a conditional store.
01368 //
01369 // Note: It doesn't include conditional new-value stores as they can't be
01370 // converted to .new predicate.
01371 //
01372 //               p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
01373 //                ^           ^
01374 //               /             \ (not OK. it will cause new-value store to be
01375 //              /               X conditional on p0.new while R2 producer is
01376 //             /                 \ on p0)
01377 //            /                   \.
01378 //     p.new store                 p.old NV store
01379 // [if(p0.new)memw(R0+#0)=R2]    [if(p0)memw(R0+#0)=R2.new]
01380 //            ^                  ^
01381 //             \                /
01382 //              \              /
01383 //               \            /
01384 //                 p.old store
01385 //             [if (p0)memw(R0+#0)=R2]
01386 //
01387 // The above diagram shows the steps involoved in the conversion of a predicated
01388 // store instruction to its .new predicated new-value form.
01389 //
01390 // The following set of instructions further explains the scenario where
01391 // conditional new-value store becomes invalid when promoted to .new predicate
01392 // form.
01393 //
01394 // { 1) if (p0) r0 = add(r1, r2)
01395 //   2) p0 = cmp.eq(r3, #0) }
01396 //
01397 //   3) if (p0) memb(r1+#0) = r0  --> this instruction can't be grouped with
01398 // the first two instructions because in instr 1, r0 is conditional on old value
01399 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
01400 // is not valid for new-value stores.
01401 bool HexagonInstrInfo::
01402 isConditionalStore (const MachineInstr* MI) const {
01403   const HexagonRegisterInfo& QRI = getRegisterInfo();
01404   switch (MI->getOpcode())
01405   {
01406     default: return false;
01407     case Hexagon::S4_storeirbt_io:
01408     case Hexagon::S4_storeirbf_io:
01409     case Hexagon::S4_pstorerbt_rr:
01410     case Hexagon::S4_pstorerbf_rr:
01411     case Hexagon::S2_pstorerbt_io:
01412     case Hexagon::S2_pstorerbf_io:
01413     case Hexagon::S2_pstorerbt_pi:
01414     case Hexagon::S2_pstorerbf_pi:
01415     case Hexagon::S2_pstorerdt_io:
01416     case Hexagon::S2_pstorerdf_io:
01417     case Hexagon::S4_pstorerdt_rr:
01418     case Hexagon::S4_pstorerdf_rr:
01419     case Hexagon::S2_pstorerdt_pi:
01420     case Hexagon::S2_pstorerdf_pi:
01421     case Hexagon::S2_pstorerht_io:
01422     case Hexagon::S2_pstorerhf_io:
01423     case Hexagon::S4_storeirht_io:
01424     case Hexagon::S4_storeirhf_io:
01425     case Hexagon::S4_pstorerht_rr:
01426     case Hexagon::S4_pstorerhf_rr:
01427     case Hexagon::S2_pstorerht_pi:
01428     case Hexagon::S2_pstorerhf_pi:
01429     case Hexagon::S2_pstorerit_io:
01430     case Hexagon::S2_pstorerif_io:
01431     case Hexagon::S4_storeirit_io:
01432     case Hexagon::S4_storeirif_io:
01433     case Hexagon::S4_pstorerit_rr:
01434     case Hexagon::S4_pstorerif_rr:
01435     case Hexagon::S2_pstorerit_pi:
01436     case Hexagon::S2_pstorerif_pi:
01437       return QRI.Subtarget.hasV4TOps();
01438 
01439     // V4 global address store before promoting to dot new.
01440     case Hexagon::S4_pstorerdt_abs:
01441     case Hexagon::S4_pstorerdf_abs:
01442     case Hexagon::S4_pstorerbt_abs:
01443     case Hexagon::S4_pstorerbf_abs:
01444     case Hexagon::S4_pstorerht_abs:
01445     case Hexagon::S4_pstorerhf_abs:
01446     case Hexagon::S4_pstorerit_abs:
01447     case Hexagon::S4_pstorerif_abs:
01448       return QRI.Subtarget.hasV4TOps();
01449 
01450     // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
01451     // from the "Conditional Store" list. Because a predicated new value store
01452     // would NOT be promoted to a double dot new store. See diagram below:
01453     // This function returns yes for those stores that are predicated but not
01454     // yet promoted to predicate dot new instructions.
01455     //
01456     //                          +---------------------+
01457     //                    /-----| if (p0) memw(..)=r0 |---------\~
01458     //                   ||     +---------------------+         ||
01459     //          promote  ||       /\       /\                   ||  promote
01460     //                   ||      /||\     /||\                  ||
01461     //                  \||/    demote     ||                  \||/
01462     //                   \/       ||       ||                   \/
01463     //       +-------------------------+   ||   +-------------------------+
01464     //       | if (p0.new) memw(..)=r0 |   ||   | if (p0) memw(..)=r0.new |
01465     //       +-------------------------+   ||   +-------------------------+
01466     //                        ||           ||         ||
01467     //                        ||         demote      \||/
01468     //                      promote        ||         \/ NOT possible
01469     //                        ||           ||         /\~
01470     //                       \||/          ||        /||\~
01471     //                        \/           ||         ||
01472     //                      +-----------------------------+
01473     //                      | if (p0.new) memw(..)=r0.new |
01474     //                      +-----------------------------+
01475     //                           Double Dot New Store
01476     //
01477   }
01478 }
01479 
01480 
01481 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
01482   if (isNewValue(MI) && isBranch(MI))
01483     return true;
01484   return false;
01485 }
01486 
01487 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
01488   return (getAddrMode(MI) == HexagonII::PostInc);
01489 }
01490 
01491 bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
01492   const uint64_t F = MI->getDesc().TSFlags;
01493   return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
01494 }
01495 
01496 // Returns true, if any one of the operands is a dot new
01497 // insn, whether it is predicated dot new or register dot new.
01498 bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
01499   return (isNewValueInst(MI) ||
01500      (isPredicated(MI) && isPredicatedNew(MI)));
01501 }
01502 
01503 // Returns the most basic instruction for the .new predicated instructions and
01504 // new-value stores.
01505 // For example, all of the following instructions will be converted back to the
01506 // same instruction:
01507 // 1) if (p0.new) memw(R0+#0) = R1.new  --->
01508 // 2) if (p0) memw(R0+#0)= R1.new      -------> if (p0) memw(R0+#0) = R1
01509 // 3) if (p0.new) memw(R0+#0) = R1      --->
01510 //
01511 
01512 int HexagonInstrInfo::GetDotOldOp(const int opc) const {
01513   int NewOp = opc;
01514   if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
01515     NewOp = Hexagon::getPredOldOpcode(NewOp);
01516     assert(NewOp >= 0 &&
01517            "Couldn't change predicate new instruction to its old form.");
01518   }
01519 
01520   if (isNewValueStore(NewOp)) { // Convert into non-new-value format
01521     NewOp = Hexagon::getNonNVStore(NewOp);
01522     assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
01523   }
01524   return NewOp;
01525 }
01526 
01527 // Return the new value instruction for a given store.
01528 int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const {
01529   int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
01530   if (NVOpcode >= 0) // Valid new-value store instruction.
01531     return NVOpcode;
01532 
01533   switch (MI->getOpcode()) {
01534   default: llvm_unreachable("Unknown .new type");
01535   // store new value byte
01536   case Hexagon::STrib_shl_V4:
01537     return Hexagon::STrib_shl_nv_V4;
01538 
01539   case Hexagon::STrih_shl_V4:
01540     return Hexagon::STrih_shl_nv_V4;
01541 
01542   case Hexagon::STriw_shl_V4:
01543     return Hexagon::STriw_shl_nv_V4;
01544 
01545   }
01546   return 0;
01547 }
01548 
01549 // Return .new predicate version for an instruction.
01550 int HexagonInstrInfo::GetDotNewPredOp(MachineInstr *MI,
01551                                       const MachineBranchProbabilityInfo
01552                                       *MBPI) const {
01553 
01554   int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
01555   if (NewOpcode >= 0) // Valid predicate new instruction
01556     return NewOpcode;
01557 
01558   switch (MI->getOpcode()) {
01559   default: llvm_unreachable("Unknown .new type");
01560   // Condtional Jumps
01561   case Hexagon::J2_jumpt:
01562   case Hexagon::J2_jumpf:
01563     return getDotNewPredJumpOp(MI, MBPI);
01564 
01565   case Hexagon::J2_jumprt:
01566     return Hexagon::J2_jumptnewpt;
01567 
01568   case Hexagon::J2_jumprf:
01569     return Hexagon::J2_jumprfnewpt;
01570 
01571   case Hexagon::JMPrett:
01572     return Hexagon::J2_jumprtnewpt;
01573 
01574   case Hexagon::JMPretf:
01575     return Hexagon::J2_jumprfnewpt;
01576 
01577 
01578   // Conditional combine
01579   case Hexagon::C2_ccombinewt:
01580     return Hexagon::C2_ccombinewnewt;
01581   case Hexagon::C2_ccombinewf:
01582     return Hexagon::C2_ccombinewnewf;
01583   }
01584 }
01585 
01586 
01587 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
01588   const uint64_t F = MI->getDesc().TSFlags;
01589 
01590   return((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
01591 }
01592 
01593 /// immediateExtend - Changes the instruction in place to one using an immediate
01594 /// extender.
01595 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
01596   assert((isExtendable(MI)||isConstExtended(MI)) &&
01597                                "Instruction must be extendable");
01598   // Find which operand is extendable.
01599   short ExtOpNum = getCExtOpNum(MI);
01600   MachineOperand &MO = MI->getOperand(ExtOpNum);
01601   // This needs to be something we understand.
01602   assert((MO.isMBB() || MO.isImm()) &&
01603          "Branch with unknown extendable field type");
01604   // Mark given operand as extended.
01605   MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
01606 }
01607 
01608 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
01609     const TargetSubtargetInfo &STI) const {
01610   const InstrItineraryData *II = STI.getInstrItineraryData();
01611   return static_cast<const HexagonSubtarget &>(STI).createDFAPacketizer(II);
01612 }
01613 
01614 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
01615                                             const MachineBasicBlock *MBB,
01616                                             const MachineFunction &MF) const {
01617   // Debug info is never a scheduling boundary. It's necessary to be explicit
01618   // due to the special treatment of IT instructions below, otherwise a
01619   // dbg_value followed by an IT will result in the IT instruction being
01620   // considered a scheduling hazard, which is wrong. It should be the actual
01621   // instruction preceding the dbg_value instruction(s), just like it is
01622   // when debug info is not present.
01623   if (MI->isDebugValue())
01624     return false;
01625 
01626   // Terminators and labels can't be scheduled around.
01627   if (MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm())
01628     return true;
01629 
01630   return false;
01631 }
01632 
01633 bool HexagonInstrInfo::isConstExtended(MachineInstr *MI) const {
01634 
01635   // Constant extenders are allowed only for V4 and above.
01636   if (!Subtarget.hasV4TOps())
01637     return false;
01638 
01639   const uint64_t F = MI->getDesc().TSFlags;
01640   unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
01641   if (isExtended) // Instruction must be extended.
01642     return true;
01643 
01644   unsigned isExtendable = (F >> HexagonII::ExtendablePos)
01645                           & HexagonII::ExtendableMask;
01646   if (!isExtendable)
01647     return false;
01648 
01649   short ExtOpNum = getCExtOpNum(MI);
01650   const MachineOperand &MO = MI->getOperand(ExtOpNum);
01651   // Use MO operand flags to determine if MO
01652   // has the HMOTF_ConstExtended flag set.
01653   if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
01654     return true;
01655   // If this is a Machine BB address we are talking about, and it is
01656   // not marked as extended, say so.
01657   if (MO.isMBB())
01658     return false;
01659 
01660   // We could be using an instruction with an extendable immediate and shoehorn
01661   // a global address into it. If it is a global address it will be constant
01662   // extended. We do this for COMBINE.
01663   // We currently only handle isGlobal() because it is the only kind of
01664   // object we are going to end up with here for now.
01665   // In the future we probably should add isSymbol(), etc.
01666   if (MO.isGlobal() || MO.isSymbol())
01667     return true;
01668 
01669   // If the extendable operand is not 'Immediate' type, the instruction should
01670   // have 'isExtended' flag set.
01671   assert(MO.isImm() && "Extendable operand must be Immediate type");
01672 
01673   int MinValue = getMinValue(MI);
01674   int MaxValue = getMaxValue(MI);
01675   int ImmValue = MO.getImm();
01676 
01677   return (ImmValue < MinValue || ImmValue > MaxValue);
01678 }
01679 
01680 // Returns the opcode to use when converting MI, which is a conditional jump,
01681 // into a conditional instruction which uses the .new value of the predicate.
01682 // We also use branch probabilities to add a hint to the jump.
01683 int
01684 HexagonInstrInfo::getDotNewPredJumpOp(MachineInstr *MI,
01685                                   const
01686                                   MachineBranchProbabilityInfo *MBPI) const {
01687 
01688   // We assume that block can have at most two successors.
01689   bool taken = false;
01690   MachineBasicBlock *Src = MI->getParent();
01691   MachineOperand *BrTarget = &MI->getOperand(1);
01692   MachineBasicBlock *Dst = BrTarget->getMBB();
01693 
01694   const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
01695   if (Prediction >= BranchProbability(1,2))
01696     taken = true;
01697 
01698   switch (MI->getOpcode()) {
01699   case Hexagon::J2_jumpt:
01700     return taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
01701   case Hexagon::J2_jumpf:
01702     return taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
01703 
01704   default:
01705     llvm_unreachable("Unexpected jump instruction.");
01706   }
01707 }
01708 // Returns true if a particular operand is extendable for an instruction.
01709 bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
01710                                          unsigned short OperandNum) const {
01711   // Constant extenders are allowed only for V4 and above.
01712   if (!Subtarget.hasV4TOps())
01713     return false;
01714 
01715   const uint64_t F = MI->getDesc().TSFlags;
01716 
01717   return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
01718           == OperandNum;
01719 }
01720 
01721 // Returns Operand Index for the constant extended instruction.
01722 unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
01723   const uint64_t F = MI->getDesc().TSFlags;
01724   return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
01725 }
01726 
01727 // Returns the min value that doesn't need to be extended.
01728 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
01729   const uint64_t F = MI->getDesc().TSFlags;
01730   unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
01731                     & HexagonII::ExtentSignedMask;
01732   unsigned bits =  (F >> HexagonII::ExtentBitsPos)
01733                     & HexagonII::ExtentBitsMask;
01734 
01735   if (isSigned) // if value is signed
01736     return -1U << (bits - 1);
01737   else
01738     return 0;
01739 }
01740 
01741 // Returns the max value that doesn't need to be extended.
01742 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
01743   const uint64_t F = MI->getDesc().TSFlags;
01744   unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
01745                     & HexagonII::ExtentSignedMask;
01746   unsigned bits =  (F >> HexagonII::ExtentBitsPos)
01747                     & HexagonII::ExtentBitsMask;
01748 
01749   if (isSigned) // if value is signed
01750     return ~(-1U << (bits - 1));
01751   else
01752     return ~(-1U << bits);
01753 }
01754 
01755 // Returns true if an instruction can be converted into a non-extended
01756 // equivalent instruction.
01757 bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr *MI) const {
01758 
01759   short NonExtOpcode;
01760   // Check if the instruction has a register form that uses register in place
01761   // of the extended operand, if so return that as the non-extended form.
01762   if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
01763     return true;
01764 
01765   if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
01766     // Check addressing mode and retrieve non-ext equivalent instruction.
01767 
01768     switch (getAddrMode(MI)) {
01769     case HexagonII::Absolute :
01770       // Load/store with absolute addressing mode can be converted into
01771       // base+offset mode.
01772       NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode());
01773       break;
01774     case HexagonII::BaseImmOffset :
01775       // Load/store with base+offset addressing mode can be converted into
01776       // base+register offset addressing mode. However left shift operand should
01777       // be set to 0.
01778       NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
01779       break;
01780     default:
01781       return false;
01782     }
01783     if (NonExtOpcode < 0)
01784       return false;
01785     return true;
01786   }
01787   return false;
01788 }
01789 
01790 // Returns opcode of the non-extended equivalent instruction.
01791 short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const {
01792 
01793   // Check if the instruction has a register form that uses register in place
01794   // of the extended operand, if so return that as the non-extended form.
01795   short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
01796     if (NonExtOpcode >= 0)
01797       return NonExtOpcode;
01798 
01799   if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
01800     // Check addressing mode and retrieve non-ext equivalent instruction.
01801     switch (getAddrMode(MI)) {
01802     case HexagonII::Absolute :
01803       return Hexagon::getBasedWithImmOffset(MI->getOpcode());
01804     case HexagonII::BaseImmOffset :
01805       return Hexagon::getBaseWithRegOffset(MI->getOpcode());
01806     default:
01807       return -1;
01808     }
01809   }
01810   return -1;
01811 }
01812 
01813 bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode) const {
01814   return (Opcode == Hexagon::J2_jumpt) ||
01815          (Opcode == Hexagon::J2_jumpf) ||
01816          (Opcode == Hexagon::J2_jumptnewpt) ||
01817          (Opcode == Hexagon::J2_jumpfnewpt) ||
01818          (Opcode == Hexagon::J2_jumpt) ||
01819          (Opcode == Hexagon::J2_jumpf);
01820 }
01821 
01822 bool HexagonInstrInfo::PredOpcodeHasNot(Opcode_t Opcode) const {
01823   return (Opcode == Hexagon::J2_jumpf) ||
01824          (Opcode == Hexagon::J2_jumpfnewpt) ||
01825          (Opcode == Hexagon::J2_jumpfnew);
01826 }