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HexagonInstrInfo.cpp
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00001 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the Hexagon implementation of the TargetInstrInfo class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "HexagonInstrInfo.h"
00015 #include "Hexagon.h"
00016 #include "HexagonRegisterInfo.h"
00017 #include "HexagonSubtarget.h"
00018 #include "llvm/ADT/STLExtras.h"
00019 #include "llvm/ADT/SmallVector.h"
00020 #include "llvm/CodeGen/DFAPacketizer.h"
00021 #include "llvm/CodeGen/MachineFrameInfo.h"
00022 #include "llvm/CodeGen/MachineInstrBuilder.h"
00023 #include "llvm/CodeGen/MachineMemOperand.h"
00024 #include "llvm/CodeGen/MachineRegisterInfo.h"
00025 #include "llvm/CodeGen/PseudoSourceValue.h"
00026 #include "llvm/Support/Debug.h"
00027 #include "llvm/Support/MathExtras.h"
00028 #include "llvm/Support/raw_ostream.h"
00029 
00030 using namespace llvm;
00031 
00032 #define DEBUG_TYPE "hexagon-instrinfo"
00033 
00034 #define GET_INSTRINFO_CTOR_DTOR
00035 #define GET_INSTRMAP_INFO
00036 #include "HexagonGenInstrInfo.inc"
00037 #include "HexagonGenDFAPacketizer.inc"
00038 
00039 ///
00040 /// Constants for Hexagon instructions.
00041 ///
00042 const int Hexagon_MEMW_OFFSET_MAX = 4095;
00043 const int Hexagon_MEMW_OFFSET_MIN = -4096;
00044 const int Hexagon_MEMD_OFFSET_MAX = 8191;
00045 const int Hexagon_MEMD_OFFSET_MIN = -8192;
00046 const int Hexagon_MEMH_OFFSET_MAX = 2047;
00047 const int Hexagon_MEMH_OFFSET_MIN = -2048;
00048 const int Hexagon_MEMB_OFFSET_MAX = 1023;
00049 const int Hexagon_MEMB_OFFSET_MIN = -1024;
00050 const int Hexagon_ADDI_OFFSET_MAX = 32767;
00051 const int Hexagon_ADDI_OFFSET_MIN = -32768;
00052 const int Hexagon_MEMD_AUTOINC_MAX = 56;
00053 const int Hexagon_MEMD_AUTOINC_MIN = -64;
00054 const int Hexagon_MEMW_AUTOINC_MAX = 28;
00055 const int Hexagon_MEMW_AUTOINC_MIN = -32;
00056 const int Hexagon_MEMH_AUTOINC_MAX = 14;
00057 const int Hexagon_MEMH_AUTOINC_MIN = -16;
00058 const int Hexagon_MEMB_AUTOINC_MAX = 7;
00059 const int Hexagon_MEMB_AUTOINC_MIN = -8;
00060 
00061 // Pin the vtable to this file.
00062 void HexagonInstrInfo::anchor() {}
00063 
00064 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
00065   : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
00066     RI(ST), Subtarget(ST) {
00067 }
00068 
00069 
00070 /// isLoadFromStackSlot - If the specified machine instruction is a direct
00071 /// load from a stack slot, return the virtual or physical register number of
00072 /// the destination along with the FrameIndex of the loaded stack slot.  If
00073 /// not, return 0.  This predicate must return 0 if the instruction has
00074 /// any side effects other than loading from the stack slot.
00075 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
00076                                              int &FrameIndex) const {
00077 
00078 
00079   switch (MI->getOpcode()) {
00080   default: break;
00081   case Hexagon::LDriw:
00082   case Hexagon::LDrid:
00083   case Hexagon::LDrih:
00084   case Hexagon::LDrib:
00085   case Hexagon::LDriub:
00086     if (MI->getOperand(2).isFI() &&
00087         MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
00088       FrameIndex = MI->getOperand(2).getIndex();
00089       return MI->getOperand(0).getReg();
00090     }
00091     break;
00092   }
00093   return 0;
00094 }
00095 
00096 
00097 /// isStoreToStackSlot - If the specified machine instruction is a direct
00098 /// store to a stack slot, return the virtual or physical register number of
00099 /// the source reg along with the FrameIndex of the loaded stack slot.  If
00100 /// not, return 0.  This predicate must return 0 if the instruction has
00101 /// any side effects other than storing to the stack slot.
00102 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
00103                                             int &FrameIndex) const {
00104   switch (MI->getOpcode()) {
00105   default: break;
00106   case Hexagon::STriw:
00107   case Hexagon::STrid:
00108   case Hexagon::STrih:
00109   case Hexagon::STrib:
00110     if (MI->getOperand(2).isFI() &&
00111         MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
00112       FrameIndex = MI->getOperand(0).getIndex();
00113       return MI->getOperand(2).getReg();
00114     }
00115     break;
00116   }
00117   return 0;
00118 }
00119 
00120 
00121 unsigned
00122 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
00123                              MachineBasicBlock *FBB,
00124                              const SmallVectorImpl<MachineOperand> &Cond,
00125                              DebugLoc DL) const{
00126 
00127     int BOpc   = Hexagon::JMP;
00128     int BccOpc = Hexagon::JMP_t;
00129 
00130     assert(TBB && "InsertBranch must not be told to insert a fallthrough");
00131 
00132     int regPos = 0;
00133     // Check if ReverseBranchCondition has asked to reverse this branch
00134     // If we want to reverse the branch an odd number of times, we want
00135     // JMP_f.
00136     if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
00137       BccOpc = Hexagon::JMP_f;
00138       regPos = 1;
00139     }
00140 
00141     if (!FBB) {
00142       if (Cond.empty()) {
00143         // Due to a bug in TailMerging/CFG Optimization, we need to add a
00144         // special case handling of a predicated jump followed by an
00145         // unconditional jump. If not, Tail Merging and CFG Optimization go
00146         // into an infinite loop.
00147         MachineBasicBlock *NewTBB, *NewFBB;
00148         SmallVector<MachineOperand, 4> Cond;
00149         MachineInstr *Term = MBB.getFirstTerminator();
00150         if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
00151                                                  false)) {
00152           MachineBasicBlock *NextBB =
00153             std::next(MachineFunction::iterator(&MBB));
00154           if (NewTBB == NextBB) {
00155             ReverseBranchCondition(Cond);
00156             RemoveBranch(MBB);
00157             return InsertBranch(MBB, TBB, nullptr, Cond, DL);
00158           }
00159         }
00160         BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
00161       } else {
00162         BuildMI(&MBB, DL,
00163                 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
00164       }
00165       return 1;
00166     }
00167 
00168     BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
00169     BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
00170 
00171     return 2;
00172 }
00173 
00174 
00175 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
00176                                      MachineBasicBlock *&TBB,
00177                                  MachineBasicBlock *&FBB,
00178                                  SmallVectorImpl<MachineOperand> &Cond,
00179                                  bool AllowModify) const {
00180   TBB = nullptr;
00181   FBB = nullptr;
00182 
00183   // If the block has no terminators, it just falls into the block after it.
00184   MachineBasicBlock::instr_iterator I = MBB.instr_end();
00185   if (I == MBB.instr_begin())
00186     return false;
00187 
00188   // A basic block may looks like this:
00189   //
00190   //  [   insn
00191   //     EH_LABEL
00192   //      insn
00193   //      insn
00194   //      insn
00195   //     EH_LABEL
00196   //      insn     ]
00197   //
00198   // It has two succs but does not have a terminator
00199   // Don't know how to handle it.
00200   do {
00201     --I;
00202     if (I->isEHLabel())
00203       return true;
00204   } while (I != MBB.instr_begin());
00205 
00206   I = MBB.instr_end();
00207   --I;
00208 
00209   while (I->isDebugValue()) {
00210     if (I == MBB.instr_begin())
00211       return false;
00212     --I;
00213   }
00214 
00215   // Delete the JMP if it's equivalent to a fall-through.
00216   if (AllowModify && I->getOpcode() == Hexagon::JMP &&
00217       MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
00218     DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
00219     I->eraseFromParent();
00220     I = MBB.instr_end();
00221     if (I == MBB.instr_begin())
00222       return false;
00223     --I;
00224   }
00225   if (!isUnpredicatedTerminator(I))
00226     return false;
00227 
00228   // Get the last instruction in the block.
00229   MachineInstr *LastInst = I;
00230   MachineInstr *SecondLastInst = nullptr;
00231   // Find one more terminator if present.
00232   do {
00233     if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(I)) {
00234       if (!SecondLastInst)
00235         SecondLastInst = I;
00236       else
00237         // This is a third branch.
00238         return true;
00239     }
00240     if (I == MBB.instr_begin())
00241       break;
00242     --I;
00243   } while(I);
00244 
00245   int LastOpcode = LastInst->getOpcode();
00246 
00247   bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
00248   bool LastOpcodeHasNot = PredOpcodeHasNot(LastOpcode);
00249 
00250   // If there is only one terminator instruction, process it.
00251   if (LastInst && !SecondLastInst) {
00252     if (LastOpcode == Hexagon::JMP) {
00253       TBB = LastInst->getOperand(0).getMBB();
00254       return false;
00255     }
00256     if (LastOpcode == Hexagon::ENDLOOP0) {
00257       TBB = LastInst->getOperand(0).getMBB();
00258       Cond.push_back(LastInst->getOperand(0));
00259       return false;
00260     }
00261     if (LastOpcodeHasJMP_c) {
00262       TBB = LastInst->getOperand(1).getMBB();
00263       if (LastOpcodeHasNot) {
00264         Cond.push_back(MachineOperand::CreateImm(0));
00265       }
00266       Cond.push_back(LastInst->getOperand(0));
00267       return false;
00268     }
00269     // Otherwise, don't know what this is.
00270     return true;
00271   }
00272 
00273   int SecLastOpcode = SecondLastInst->getOpcode();
00274 
00275   bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
00276   bool SecLastOpcodeHasNot = PredOpcodeHasNot(SecLastOpcode);
00277   if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::JMP)) {
00278     TBB =  SecondLastInst->getOperand(1).getMBB();
00279     if (SecLastOpcodeHasNot)
00280       Cond.push_back(MachineOperand::CreateImm(0));
00281     Cond.push_back(SecondLastInst->getOperand(0));
00282     FBB = LastInst->getOperand(0).getMBB();
00283     return false;
00284   }
00285 
00286   // If the block ends with two Hexagon:JMPs, handle it.  The second one is not
00287   // executed, so remove it.
00288   if (SecLastOpcode == Hexagon::JMP && LastOpcode == Hexagon::JMP) {
00289     TBB = SecondLastInst->getOperand(0).getMBB();
00290     I = LastInst;
00291     if (AllowModify)
00292       I->eraseFromParent();
00293     return false;
00294   }
00295 
00296   // If the block ends with an ENDLOOP, and JMP, handle it.
00297   if (SecLastOpcode == Hexagon::ENDLOOP0 &&
00298       LastOpcode == Hexagon::JMP) {
00299     TBB = SecondLastInst->getOperand(0).getMBB();
00300     Cond.push_back(SecondLastInst->getOperand(0));
00301     FBB = LastInst->getOperand(0).getMBB();
00302     return false;
00303   }
00304 
00305   // Otherwise, can't handle this.
00306   return true;
00307 }
00308 
00309 
00310 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
00311   int BOpc   = Hexagon::JMP;
00312   int BccOpc = Hexagon::JMP_t;
00313   int BccOpcNot = Hexagon::JMP_f;
00314 
00315   MachineBasicBlock::iterator I = MBB.end();
00316   if (I == MBB.begin()) return 0;
00317   --I;
00318   if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
00319       I->getOpcode() != BccOpcNot)
00320     return 0;
00321 
00322   // Remove the branch.
00323   I->eraseFromParent();
00324 
00325   I = MBB.end();
00326 
00327   if (I == MBB.begin()) return 1;
00328   --I;
00329   if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
00330     return 1;
00331 
00332   // Remove the branch.
00333   I->eraseFromParent();
00334   return 2;
00335 }
00336 
00337 
00338 /// \brief For a comparison instruction, return the source registers in
00339 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
00340 /// compares against in CmpValue. Return true if the comparison instruction
00341 /// can be analyzed.
00342 bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
00343                                       unsigned &SrcReg, unsigned &SrcReg2,
00344                                       int &Mask, int &Value) const {
00345   unsigned Opc = MI->getOpcode();
00346 
00347   // Set mask and the first source register.
00348   switch (Opc) {
00349     case Hexagon::CMPEHexagon4rr:
00350     case Hexagon::CMPEQri:
00351     case Hexagon::CMPEQrr:
00352     case Hexagon::CMPGT64rr:
00353     case Hexagon::CMPGTU64rr:
00354     case Hexagon::CMPGTUri:
00355     case Hexagon::CMPGTUrr:
00356     case Hexagon::CMPGTri:
00357     case Hexagon::CMPGTrr:
00358       SrcReg = MI->getOperand(1).getReg();
00359       Mask = ~0;
00360       break;
00361     case Hexagon::CMPbEQri_V4:
00362     case Hexagon::CMPbEQrr_sbsb_V4:
00363     case Hexagon::CMPbEQrr_ubub_V4:
00364     case Hexagon::CMPbGTUri_V4:
00365     case Hexagon::CMPbGTUrr_V4:
00366     case Hexagon::CMPbGTrr_V4:
00367       SrcReg = MI->getOperand(1).getReg();
00368       Mask = 0xFF;
00369       break;
00370     case Hexagon::CMPhEQri_V4:
00371     case Hexagon::CMPhEQrr_shl_V4:
00372     case Hexagon::CMPhEQrr_xor_V4:
00373     case Hexagon::CMPhGTUri_V4:
00374     case Hexagon::CMPhGTUrr_V4:
00375     case Hexagon::CMPhGTrr_shl_V4:
00376       SrcReg = MI->getOperand(1).getReg();
00377       Mask = 0xFFFF;
00378       break;
00379   }
00380 
00381   // Set the value/second source register.
00382   switch (Opc) {
00383     case Hexagon::CMPEHexagon4rr:
00384     case Hexagon::CMPEQrr:
00385     case Hexagon::CMPGT64rr:
00386     case Hexagon::CMPGTU64rr:
00387     case Hexagon::CMPGTUrr:
00388     case Hexagon::CMPGTrr:
00389     case Hexagon::CMPbEQrr_sbsb_V4:
00390     case Hexagon::CMPbEQrr_ubub_V4:
00391     case Hexagon::CMPbGTUrr_V4:
00392     case Hexagon::CMPbGTrr_V4:
00393     case Hexagon::CMPhEQrr_shl_V4:
00394     case Hexagon::CMPhEQrr_xor_V4:
00395     case Hexagon::CMPhGTUrr_V4:
00396     case Hexagon::CMPhGTrr_shl_V4:
00397       SrcReg2 = MI->getOperand(2).getReg();
00398       return true;
00399 
00400     case Hexagon::CMPEQri:
00401     case Hexagon::CMPGTUri:
00402     case Hexagon::CMPGTri:
00403     case Hexagon::CMPbEQri_V4:
00404     case Hexagon::CMPbGTUri_V4:
00405     case Hexagon::CMPhEQri_V4:
00406     case Hexagon::CMPhGTUri_V4:
00407       SrcReg2 = 0;
00408       Value = MI->getOperand(2).getImm();
00409       return true;
00410   }
00411 
00412   return false;
00413 }
00414 
00415 
00416 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
00417                                  MachineBasicBlock::iterator I, DebugLoc DL,
00418                                  unsigned DestReg, unsigned SrcReg,
00419                                  bool KillSrc) const {
00420   if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
00421     BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
00422     return;
00423   }
00424   if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
00425     BuildMI(MBB, I, DL, get(Hexagon::TFR64), DestReg).addReg(SrcReg);
00426     return;
00427   }
00428   if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
00429     // Map Pd = Ps to Pd = or(Ps, Ps).
00430     BuildMI(MBB, I, DL, get(Hexagon::OR_pp),
00431             DestReg).addReg(SrcReg).addReg(SrcReg);
00432     return;
00433   }
00434   if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
00435       Hexagon::IntRegsRegClass.contains(SrcReg)) {
00436     // We can have an overlap between single and double reg: r1:0 = r0.
00437     if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
00438         // r1:0 = r0
00439         BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
00440                 Hexagon::subreg_hireg))).addImm(0);
00441     } else {
00442         // r1:0 = r1 or no overlap.
00443         BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg,
00444                 Hexagon::subreg_loreg))).addReg(SrcReg);
00445         BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
00446                 Hexagon::subreg_hireg))).addImm(0);
00447     }
00448     return;
00449   }
00450   if (Hexagon::CRRegsRegClass.contains(DestReg) &&
00451       Hexagon::IntRegsRegClass.contains(SrcReg)) {
00452     BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
00453     return;
00454   }
00455   if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
00456       Hexagon::IntRegsRegClass.contains(DestReg)) {
00457     BuildMI(MBB, I, DL, get(Hexagon::TFR_RsPd), DestReg).
00458       addReg(SrcReg, getKillRegState(KillSrc));
00459     return;
00460   }
00461   if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
00462       Hexagon::PredRegsRegClass.contains(DestReg)) {
00463     BuildMI(MBB, I, DL, get(Hexagon::TFR_PdRs), DestReg).
00464       addReg(SrcReg, getKillRegState(KillSrc));
00465     return;
00466   }
00467 
00468   llvm_unreachable("Unimplemented");
00469 }
00470 
00471 
00472 void HexagonInstrInfo::
00473 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
00474                     unsigned SrcReg, bool isKill, int FI,
00475                     const TargetRegisterClass *RC,
00476                     const TargetRegisterInfo *TRI) const {
00477 
00478   DebugLoc DL = MBB.findDebugLoc(I);
00479   MachineFunction &MF = *MBB.getParent();
00480   MachineFrameInfo &MFI = *MF.getFrameInfo();
00481   unsigned Align = MFI.getObjectAlignment(FI);
00482 
00483   MachineMemOperand *MMO =
00484       MF.getMachineMemOperand(
00485                       MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
00486                       MachineMemOperand::MOStore,
00487                       MFI.getObjectSize(FI),
00488                       Align);
00489 
00490   if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
00491     BuildMI(MBB, I, DL, get(Hexagon::STriw))
00492           .addFrameIndex(FI).addImm(0)
00493           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00494   } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
00495     BuildMI(MBB, I, DL, get(Hexagon::STrid))
00496           .addFrameIndex(FI).addImm(0)
00497           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00498   } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
00499     BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
00500           .addFrameIndex(FI).addImm(0)
00501           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00502   } else {
00503     llvm_unreachable("Unimplemented");
00504   }
00505 }
00506 
00507 
00508 void HexagonInstrInfo::storeRegToAddr(
00509                                  MachineFunction &MF, unsigned SrcReg,
00510                                  bool isKill,
00511                                  SmallVectorImpl<MachineOperand> &Addr,
00512                                  const TargetRegisterClass *RC,
00513                                  SmallVectorImpl<MachineInstr*> &NewMIs) const
00514 {
00515   llvm_unreachable("Unimplemented");
00516 }
00517 
00518 
00519 void HexagonInstrInfo::
00520 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
00521                      unsigned DestReg, int FI,
00522                      const TargetRegisterClass *RC,
00523                      const TargetRegisterInfo *TRI) const {
00524   DebugLoc DL = MBB.findDebugLoc(I);
00525   MachineFunction &MF = *MBB.getParent();
00526   MachineFrameInfo &MFI = *MF.getFrameInfo();
00527   unsigned Align = MFI.getObjectAlignment(FI);
00528 
00529   MachineMemOperand *MMO =
00530       MF.getMachineMemOperand(
00531                       MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
00532                       MachineMemOperand::MOLoad,
00533                       MFI.getObjectSize(FI),
00534                       Align);
00535   if (RC == &Hexagon::IntRegsRegClass) {
00536     BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg)
00537           .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00538   } else if (RC == &Hexagon::DoubleRegsRegClass) {
00539     BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
00540           .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00541   } else if (RC == &Hexagon::PredRegsRegClass) {
00542     BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
00543           .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00544   } else {
00545     llvm_unreachable("Can't store this register to stack slot");
00546   }
00547 }
00548 
00549 
00550 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
00551                                         SmallVectorImpl<MachineOperand> &Addr,
00552                                         const TargetRegisterClass *RC,
00553                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
00554   llvm_unreachable("Unimplemented");
00555 }
00556 
00557 
00558 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
00559                                                     MachineInstr* MI,
00560                                           const SmallVectorImpl<unsigned> &Ops,
00561                                                     int FI) const {
00562   // Hexagon_TODO: Implement.
00563   return nullptr;
00564 }
00565 
00566 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
00567 
00568   MachineRegisterInfo &RegInfo = MF->getRegInfo();
00569   const TargetRegisterClass *TRC;
00570   if (VT == MVT::i1) {
00571     TRC = &Hexagon::PredRegsRegClass;
00572   } else if (VT == MVT::i32 || VT == MVT::f32) {
00573     TRC = &Hexagon::IntRegsRegClass;
00574   } else if (VT == MVT::i64 || VT == MVT::f64) {
00575     TRC = &Hexagon::DoubleRegsRegClass;
00576   } else {
00577     llvm_unreachable("Cannot handle this register class");
00578   }
00579 
00580   unsigned NewReg = RegInfo.createVirtualRegister(TRC);
00581   return NewReg;
00582 }
00583 
00584 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
00585   // Constant extenders are allowed only for V4 and above.
00586   if (!Subtarget.hasV4TOps())
00587     return false;
00588 
00589   const MCInstrDesc &MID = MI->getDesc();
00590   const uint64_t F = MID.TSFlags;
00591   if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
00592     return true;
00593 
00594   // TODO: This is largely obsolete now. Will need to be removed
00595   // in consecutive patches.
00596   switch(MI->getOpcode()) {
00597     // TFR_FI Remains a special case.
00598     case Hexagon::TFR_FI:
00599       return true;
00600     default:
00601       return false;
00602   }
00603   return  false;
00604 }
00605 
00606 // This returns true in two cases:
00607 // - The OP code itself indicates that this is an extended instruction.
00608 // - One of MOs has been marked with HMOTF_ConstExtended flag.
00609 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
00610   // First check if this is permanently extended op code.
00611   const uint64_t F = MI->getDesc().TSFlags;
00612   if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
00613     return true;
00614   // Use MO operand flags to determine if one of MI's operands
00615   // has HMOTF_ConstExtended flag set.
00616   for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
00617        E = MI->operands_end(); I != E; ++I) {
00618     if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
00619       return true;
00620   }
00621   return  false;
00622 }
00623 
00624 bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const {
00625   return MI->getDesc().isBranch();
00626 }
00627 
00628 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
00629   if (isNewValueJump(MI))
00630     return true;
00631 
00632   if (isNewValueStore(MI))
00633     return true;
00634 
00635   return false;
00636 }
00637 
00638 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
00639   return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
00640 }
00641 
00642 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
00643   bool isPred = MI->getDesc().isPredicable();
00644 
00645   if (!isPred)
00646     return false;
00647 
00648   const int Opc = MI->getOpcode();
00649 
00650   switch(Opc) {
00651   case Hexagon::TFRI:
00652     return isInt<12>(MI->getOperand(1).getImm());
00653 
00654   case Hexagon::STrid:
00655   case Hexagon::STrid_indexed:
00656     return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
00657 
00658   case Hexagon::STriw:
00659   case Hexagon::STriw_indexed:
00660   case Hexagon::STriw_nv_V4:
00661     return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
00662 
00663   case Hexagon::STrih:
00664   case Hexagon::STrih_indexed:
00665   case Hexagon::STrih_nv_V4:
00666     return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
00667 
00668   case Hexagon::STrib:
00669   case Hexagon::STrib_indexed:
00670   case Hexagon::STrib_nv_V4:
00671     return isUInt<6>(MI->getOperand(1).getImm());
00672 
00673   case Hexagon::LDrid:
00674   case Hexagon::LDrid_indexed:
00675     return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
00676 
00677   case Hexagon::LDriw:
00678   case Hexagon::LDriw_indexed:
00679     return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
00680 
00681   case Hexagon::LDrih:
00682   case Hexagon::LDriuh:
00683   case Hexagon::LDrih_indexed:
00684   case Hexagon::LDriuh_indexed:
00685     return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
00686 
00687   case Hexagon::LDrib:
00688   case Hexagon::LDriub:
00689   case Hexagon::LDrib_indexed:
00690   case Hexagon::LDriub_indexed:
00691     return isUInt<6>(MI->getOperand(2).getImm());
00692 
00693   case Hexagon::POST_LDrid:
00694     return isShiftedInt<4,3>(MI->getOperand(3).getImm());
00695 
00696   case Hexagon::POST_LDriw:
00697     return isShiftedInt<4,2>(MI->getOperand(3).getImm());
00698 
00699   case Hexagon::POST_LDrih:
00700   case Hexagon::POST_LDriuh:
00701     return isShiftedInt<4,1>(MI->getOperand(3).getImm());
00702 
00703   case Hexagon::POST_LDrib:
00704   case Hexagon::POST_LDriub:
00705     return isInt<4>(MI->getOperand(3).getImm());
00706 
00707   case Hexagon::STrib_imm_V4:
00708   case Hexagon::STrih_imm_V4:
00709   case Hexagon::STriw_imm_V4:
00710     return (isUInt<6>(MI->getOperand(1).getImm()) &&
00711             isInt<6>(MI->getOperand(2).getImm()));
00712 
00713   case Hexagon::ADD_ri:
00714     return isInt<8>(MI->getOperand(2).getImm());
00715 
00716   case Hexagon::ASLH:
00717   case Hexagon::ASRH:
00718   case Hexagon::A2_sxtb:
00719   case Hexagon::A2_sxth:
00720   case Hexagon::ZXTB:
00721   case Hexagon::ZXTH:
00722     return Subtarget.hasV4TOps();
00723   }
00724 
00725   return true;
00726 }
00727 
00728 // This function performs the following inversiones:
00729 //
00730 //  cPt    ---> cNotPt
00731 //  cNotPt ---> cPt
00732 //
00733 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
00734   int InvPredOpcode;
00735   InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
00736                                         : Hexagon::getTruePredOpcode(Opc);
00737   if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
00738     return InvPredOpcode;
00739 
00740   switch(Opc) {
00741     default: llvm_unreachable("Unexpected predicated instruction");
00742     case Hexagon::COMBINE_rr_cPt:
00743       return Hexagon::COMBINE_rr_cNotPt;
00744     case Hexagon::COMBINE_rr_cNotPt:
00745       return Hexagon::COMBINE_rr_cPt;
00746 
00747       // Dealloc_return.
00748     case Hexagon::DEALLOC_RET_cPt_V4:
00749       return Hexagon::DEALLOC_RET_cNotPt_V4;
00750     case Hexagon::DEALLOC_RET_cNotPt_V4:
00751       return Hexagon::DEALLOC_RET_cPt_V4;
00752   }
00753 }
00754 
00755 // New Value Store instructions.
00756 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
00757   const uint64_t F = MI->getDesc().TSFlags;
00758 
00759   return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
00760 }
00761 
00762 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
00763   const uint64_t F = get(Opcode).TSFlags;
00764 
00765   return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
00766 }
00767 
00768 int HexagonInstrInfo::
00769 getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
00770   enum Hexagon::PredSense inPredSense;
00771   inPredSense = invertPredicate ? Hexagon::PredSense_false :
00772                                   Hexagon::PredSense_true;
00773   int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
00774   if (CondOpcode >= 0) // Valid Conditional opcode/instruction
00775     return CondOpcode;
00776 
00777   // This switch case will be removed once all the instructions have been
00778   // modified to use relation maps.
00779   switch(Opc) {
00780   case Hexagon::TFRI_f:
00781     return !invertPredicate ? Hexagon::TFRI_cPt_f :
00782                               Hexagon::TFRI_cNotPt_f;
00783   case Hexagon::COMBINE_rr:
00784     return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
00785                               Hexagon::COMBINE_rr_cNotPt;
00786 
00787   // Word.
00788   case Hexagon::STriw_f:
00789     return !invertPredicate ? Hexagon::STriw_cPt :
00790                               Hexagon::STriw_cNotPt;
00791   case Hexagon::STriw_indexed_f:
00792     return !invertPredicate ? Hexagon::STriw_indexed_cPt :
00793                               Hexagon::STriw_indexed_cNotPt;
00794 
00795   // DEALLOC_RETURN.
00796   case Hexagon::DEALLOC_RET_V4:
00797     return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
00798                               Hexagon::DEALLOC_RET_cNotPt_V4;
00799   }
00800   llvm_unreachable("Unexpected predicable instruction");
00801 }
00802 
00803 
00804 bool HexagonInstrInfo::
00805 PredicateInstruction(MachineInstr *MI,
00806                      const SmallVectorImpl<MachineOperand> &Cond) const {
00807   int Opc = MI->getOpcode();
00808   assert (isPredicable(MI) && "Expected predicable instruction");
00809   bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
00810                      (Cond[0].getImm() == 0));
00811 
00812   // This will change MI's opcode to its predicate version.
00813   // However, its operand list is still the old one, i.e. the
00814   // non-predicate one.
00815   MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
00816 
00817   int oper = -1;
00818   unsigned int GAIdx = 0;
00819 
00820   // Indicates whether the current MI has a GlobalAddress operand
00821   bool hasGAOpnd = false;
00822   std::vector<MachineOperand> tmpOpnds;
00823 
00824   // Indicates whether we need to shift operands to right.
00825   bool needShift = true;
00826 
00827   // The predicate is ALWAYS the FIRST input operand !!!
00828   if (MI->getNumOperands() == 0) {
00829     // The non-predicate version of MI does not take any operands,
00830     // i.e. no outs and no ins. In this condition, the predicate
00831     // operand will be directly placed at Operands[0]. No operand
00832     // shift is needed.
00833     // Example: BARRIER
00834     needShift = false;
00835     oper = -1;
00836   }
00837   else if (   MI->getOperand(MI->getNumOperands()-1).isReg()
00838            && MI->getOperand(MI->getNumOperands()-1).isDef()
00839            && !MI->getOperand(MI->getNumOperands()-1).isImplicit()) {
00840     // The non-predicate version of MI does not have any input operands.
00841     // In this condition, we extend the length of Operands[] by one and
00842     // copy the original last operand to the newly allocated slot.
00843     // At this moment, it is just a place holder. Later, we will put
00844     // predicate operand directly into it. No operand shift is needed.
00845     // Example: r0=BARRIER (this is a faked insn used here for illustration)
00846     MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
00847     needShift = false;
00848     oper = MI->getNumOperands() - 2;
00849   }
00850   else {
00851     // We need to right shift all input operands by one. Duplicate the
00852     // last operand into the newly allocated slot.
00853     MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
00854   }
00855 
00856   if (needShift)
00857   {
00858     // Operands[ MI->getNumOperands() - 2 ] has been copied into
00859     // Operands[ MI->getNumOperands() - 1 ], so we start from
00860     // Operands[ MI->getNumOperands() - 3 ].
00861     // oper is a signed int.
00862     // It is ok if "MI->getNumOperands()-3" is -3, -2, or -1.
00863     for (oper = MI->getNumOperands() - 3; oper >= 0; --oper)
00864     {
00865       MachineOperand &MO = MI->getOperand(oper);
00866 
00867       // Opnd[0] Opnd[1] Opnd[2] Opnd[3] Opnd[4]   Opnd[5]   Opnd[6]   Opnd[7]
00868       // <Def0>  <Def1>  <Use0>  <Use1>  <ImpDef0> <ImpDef1> <ImpUse0> <ImpUse1>
00869       //               /\~
00870       //              /||\~
00871       //               ||
00872       //        Predicate Operand here
00873       if (MO.isReg() && !MO.isUse() && !MO.isImplicit()) {
00874         break;
00875       }
00876       if (MO.isReg()) {
00877         MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
00878                                                 MO.isImplicit(), MO.isKill(),
00879                                                 MO.isDead(), MO.isUndef(),
00880                                                 MO.isDebug());
00881       }
00882       else if (MO.isImm()) {
00883         MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
00884       }
00885       else if (MO.isGlobal()) {
00886         // MI can not have more than one GlobalAddress operand.
00887         assert(hasGAOpnd == false && "MI can only have one GlobalAddress opnd");
00888 
00889         // There is no member function called "ChangeToGlobalAddress" in the
00890         // MachineOperand class (not like "ChangeToRegister" and
00891         // "ChangeToImmediate"). So we have to remove them from Operands[] list
00892         // first, and then add them back after we have inserted the predicate
00893         // operand. tmpOpnds[] is to remember these operands before we remove
00894         // them.
00895         tmpOpnds.push_back(MO);
00896 
00897         // Operands[oper] is a GlobalAddress operand;
00898         // Operands[oper+1] has been copied into Operands[oper+2];
00899         hasGAOpnd = true;
00900         GAIdx = oper;
00901         continue;
00902       }
00903       else {
00904         assert(false && "Unexpected operand type");
00905       }
00906     }
00907   }
00908 
00909   int regPos = invertJump ? 1 : 0;
00910   MachineOperand PredMO = Cond[regPos];
00911 
00912   // [oper] now points to the last explicit Def. Predicate operand must be
00913   // located at [oper+1]. See diagram above.
00914   // This assumes that the predicate is always the first operand,
00915   // i.e. Operands[0+numResults], in the set of inputs
00916   // It is better to have an assert here to check this. But I don't know how
00917   // to write this assert because findFirstPredOperandIdx() would return -1
00918   if (oper < -1) oper = -1;
00919 
00920   MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
00921                                           PredMO.isImplicit(), false,
00922                                           PredMO.isDead(), PredMO.isUndef(),
00923                                           PredMO.isDebug());
00924 
00925   MachineRegisterInfo &RegInfo = MI->getParent()->getParent()->getRegInfo();
00926   RegInfo.clearKillFlags(PredMO.getReg());
00927 
00928   if (hasGAOpnd)
00929   {
00930     unsigned int i;
00931 
00932     // Operands[GAIdx] is the original GlobalAddress operand, which is
00933     // already copied into tmpOpnds[0].
00934     // Operands[GAIdx] now stores a copy of Operands[GAIdx-1]
00935     // Operands[GAIdx+1] has already been copied into Operands[GAIdx+2],
00936     // so we start from [GAIdx+2]
00937     for (i = GAIdx + 2; i < MI->getNumOperands(); ++i)
00938       tmpOpnds.push_back(MI->getOperand(i));
00939 
00940     // Remove all operands in range [ (GAIdx+1) ... (MI->getNumOperands()-1) ]
00941     // It is very important that we always remove from the end of Operands[]
00942     // MI->getNumOperands() is at least 2 if program goes to here.
00943     for (i = MI->getNumOperands() - 1; i > GAIdx; --i)
00944       MI->RemoveOperand(i);
00945 
00946     for (i = 0; i < tmpOpnds.size(); ++i)
00947       MI->addOperand(tmpOpnds[i]);
00948   }
00949 
00950   return true;
00951 }
00952 
00953 
00954 bool
00955 HexagonInstrInfo::
00956 isProfitableToIfCvt(MachineBasicBlock &MBB,
00957                     unsigned NumCycles,
00958                     unsigned ExtraPredCycles,
00959                     const BranchProbability &Probability) const {
00960   return true;
00961 }
00962 
00963 
00964 bool
00965 HexagonInstrInfo::
00966 isProfitableToIfCvt(MachineBasicBlock &TMBB,
00967                     unsigned NumTCycles,
00968                     unsigned ExtraTCycles,
00969                     MachineBasicBlock &FMBB,
00970                     unsigned NumFCycles,
00971                     unsigned ExtraFCycles,
00972                     const BranchProbability &Probability) const {
00973   return true;
00974 }
00975 
00976 // Returns true if an instruction is predicated irrespective of the predicate
00977 // sense. For example, all of the following will return true.
00978 // if (p0) R1 = add(R2, R3)
00979 // if (!p0) R1 = add(R2, R3)
00980 // if (p0.new) R1 = add(R2, R3)
00981 // if (!p0.new) R1 = add(R2, R3)
00982 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
00983   const uint64_t F = MI->getDesc().TSFlags;
00984 
00985   return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
00986 }
00987 
00988 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
00989   const uint64_t F = get(Opcode).TSFlags;
00990 
00991   return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
00992 }
00993 
00994 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
00995   const uint64_t F = MI->getDesc().TSFlags;
00996 
00997   assert(isPredicated(MI));
00998   return (!((F >> HexagonII::PredicatedFalsePos) &
00999             HexagonII::PredicatedFalseMask));
01000 }
01001 
01002 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
01003   const uint64_t F = get(Opcode).TSFlags;
01004 
01005   // Make sure that the instruction is predicated.
01006   assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
01007   return (!((F >> HexagonII::PredicatedFalsePos) &
01008             HexagonII::PredicatedFalseMask));
01009 }
01010 
01011 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
01012   const uint64_t F = MI->getDesc().TSFlags;
01013 
01014   assert(isPredicated(MI));
01015   return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
01016 }
01017 
01018 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
01019   const uint64_t F = get(Opcode).TSFlags;
01020 
01021   assert(isPredicated(Opcode));
01022   return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
01023 }
01024 
01025 // Returns true, if a ST insn can be promoted to a new-value store.
01026 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const {
01027   const HexagonRegisterInfo& QRI = getRegisterInfo();
01028   const uint64_t F = MI->getDesc().TSFlags;
01029 
01030   return ((F >> HexagonII::mayNVStorePos) &
01031            HexagonII::mayNVStoreMask &
01032            QRI.Subtarget.hasV4TOps());
01033 }
01034 
01035 bool
01036 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
01037                                    std::vector<MachineOperand> &Pred) const {
01038   for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
01039     MachineOperand MO = MI->getOperand(oper);
01040     if (MO.isReg() && MO.isDef()) {
01041       const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
01042       if (RC == &Hexagon::PredRegsRegClass) {
01043         Pred.push_back(MO);
01044         return true;
01045       }
01046     }
01047   }
01048   return false;
01049 }
01050 
01051 
01052 bool
01053 HexagonInstrInfo::
01054 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
01055                   const SmallVectorImpl<MachineOperand> &Pred2) const {
01056   // TODO: Fix this
01057   return false;
01058 }
01059 
01060 
01061 //
01062 // We indicate that we want to reverse the branch by
01063 // inserting a 0 at the beginning of the Cond vector.
01064 //
01065 bool HexagonInstrInfo::
01066 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
01067   if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
01068     Cond.erase(Cond.begin());
01069   } else {
01070     Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
01071   }
01072   return false;
01073 }
01074 
01075 
01076 bool HexagonInstrInfo::
01077 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
01078                           const BranchProbability &Probability) const {
01079   return (NumInstrs <= 4);
01080 }
01081 
01082 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
01083   switch (MI->getOpcode()) {
01084   default: return false;
01085   case Hexagon::DEALLOC_RET_V4 :
01086   case Hexagon::DEALLOC_RET_cPt_V4 :
01087   case Hexagon::DEALLOC_RET_cNotPt_V4 :
01088   case Hexagon::DEALLOC_RET_cdnPnt_V4 :
01089   case Hexagon::DEALLOC_RET_cNotdnPnt_V4 :
01090   case Hexagon::DEALLOC_RET_cdnPt_V4 :
01091   case Hexagon::DEALLOC_RET_cNotdnPt_V4 :
01092    return true;
01093   }
01094 }
01095 
01096 
01097 bool HexagonInstrInfo::
01098 isValidOffset(const int Opcode, const int Offset) const {
01099   // This function is to check whether the "Offset" is in the correct range of
01100   // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
01101   // inserted to calculate the final address. Due to this reason, the function
01102   // assumes that the "Offset" has correct alignment.
01103   // We used to assert if the offset was not properly aligned, however,
01104   // there are cases where a misaligned pointer recast can cause this
01105   // problem, and we need to allow for it. The front end warns of such
01106   // misaligns with respect to load size.
01107 
01108   switch(Opcode) {
01109 
01110   case Hexagon::LDriw:
01111   case Hexagon::LDriw_indexed:
01112   case Hexagon::LDriw_f:
01113   case Hexagon::STriw_indexed:
01114   case Hexagon::STriw:
01115   case Hexagon::STriw_f:
01116     return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
01117       (Offset <= Hexagon_MEMW_OFFSET_MAX);
01118 
01119   case Hexagon::LDrid:
01120   case Hexagon::LDrid_indexed:
01121   case Hexagon::LDrid_f:
01122   case Hexagon::STrid:
01123   case Hexagon::STrid_indexed:
01124   case Hexagon::STrid_f:
01125     return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
01126       (Offset <= Hexagon_MEMD_OFFSET_MAX);
01127 
01128   case Hexagon::LDrih:
01129   case Hexagon::LDriuh:
01130   case Hexagon::STrih:
01131     return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
01132       (Offset <= Hexagon_MEMH_OFFSET_MAX);
01133 
01134   case Hexagon::LDrib:
01135   case Hexagon::STrib:
01136   case Hexagon::LDriub:
01137     return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
01138       (Offset <= Hexagon_MEMB_OFFSET_MAX);
01139 
01140   case Hexagon::ADD_ri:
01141   case Hexagon::TFR_FI:
01142     return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
01143       (Offset <= Hexagon_ADDI_OFFSET_MAX);
01144 
01145   case Hexagon::MemOPw_ADDi_V4 :
01146   case Hexagon::MemOPw_SUBi_V4 :
01147   case Hexagon::MemOPw_ADDr_V4 :
01148   case Hexagon::MemOPw_SUBr_V4 :
01149   case Hexagon::MemOPw_ANDr_V4 :
01150   case Hexagon::MemOPw_ORr_V4 :
01151     return (0 <= Offset && Offset <= 255);
01152 
01153   case Hexagon::MemOPh_ADDi_V4 :
01154   case Hexagon::MemOPh_SUBi_V4 :
01155   case Hexagon::MemOPh_ADDr_V4 :
01156   case Hexagon::MemOPh_SUBr_V4 :
01157   case Hexagon::MemOPh_ANDr_V4 :
01158   case Hexagon::MemOPh_ORr_V4 :
01159     return (0 <= Offset && Offset <= 127);
01160 
01161   case Hexagon::MemOPb_ADDi_V4 :
01162   case Hexagon::MemOPb_SUBi_V4 :
01163   case Hexagon::MemOPb_ADDr_V4 :
01164   case Hexagon::MemOPb_SUBr_V4 :
01165   case Hexagon::MemOPb_ANDr_V4 :
01166   case Hexagon::MemOPb_ORr_V4 :
01167     return (0 <= Offset && Offset <= 63);
01168 
01169   // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
01170   // any size. Later pass knows how to handle it.
01171   case Hexagon::STriw_pred:
01172   case Hexagon::LDriw_pred:
01173     return true;
01174 
01175   case Hexagon::LOOP0_i:
01176     return isUInt<10>(Offset);
01177 
01178   // INLINEASM is very special.
01179   case Hexagon::INLINEASM:
01180     return true;
01181   }
01182 
01183   llvm_unreachable("No offset range is defined for this opcode. "
01184                    "Please define it in the above switch statement!");
01185 }
01186 
01187 
01188 //
01189 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
01190 //
01191 bool HexagonInstrInfo::
01192 isValidAutoIncImm(const EVT VT, const int Offset) const {
01193 
01194   if (VT == MVT::i64) {
01195       return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
01196               Offset <= Hexagon_MEMD_AUTOINC_MAX &&
01197               (Offset & 0x7) == 0);
01198   }
01199   if (VT == MVT::i32) {
01200       return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
01201               Offset <= Hexagon_MEMW_AUTOINC_MAX &&
01202               (Offset & 0x3) == 0);
01203   }
01204   if (VT == MVT::i16) {
01205       return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
01206               Offset <= Hexagon_MEMH_AUTOINC_MAX &&
01207               (Offset & 0x1) == 0);
01208   }
01209   if (VT == MVT::i8) {
01210       return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
01211               Offset <= Hexagon_MEMB_AUTOINC_MAX);
01212   }
01213   llvm_unreachable("Not an auto-inc opc!");
01214 }
01215 
01216 
01217 bool HexagonInstrInfo::
01218 isMemOp(const MachineInstr *MI) const {
01219 //  return MI->getDesc().mayLoad() && MI->getDesc().mayStore();
01220 
01221   switch (MI->getOpcode())
01222   {
01223     default: return false;
01224     case Hexagon::MemOPw_ADDi_V4 :
01225     case Hexagon::MemOPw_SUBi_V4 :
01226     case Hexagon::MemOPw_ADDr_V4 :
01227     case Hexagon::MemOPw_SUBr_V4 :
01228     case Hexagon::MemOPw_ANDr_V4 :
01229     case Hexagon::MemOPw_ORr_V4 :
01230     case Hexagon::MemOPh_ADDi_V4 :
01231     case Hexagon::MemOPh_SUBi_V4 :
01232     case Hexagon::MemOPh_ADDr_V4 :
01233     case Hexagon::MemOPh_SUBr_V4 :
01234     case Hexagon::MemOPh_ANDr_V4 :
01235     case Hexagon::MemOPh_ORr_V4 :
01236     case Hexagon::MemOPb_ADDi_V4 :
01237     case Hexagon::MemOPb_SUBi_V4 :
01238     case Hexagon::MemOPb_ADDr_V4 :
01239     case Hexagon::MemOPb_SUBr_V4 :
01240     case Hexagon::MemOPb_ANDr_V4 :
01241     case Hexagon::MemOPb_ORr_V4 :
01242     case Hexagon::MemOPb_SETBITi_V4:
01243     case Hexagon::MemOPh_SETBITi_V4:
01244     case Hexagon::MemOPw_SETBITi_V4:
01245     case Hexagon::MemOPb_CLRBITi_V4:
01246     case Hexagon::MemOPh_CLRBITi_V4:
01247     case Hexagon::MemOPw_CLRBITi_V4:
01248     return true;
01249   }
01250   return false;
01251 }
01252 
01253 
01254 bool HexagonInstrInfo::
01255 isSpillPredRegOp(const MachineInstr *MI) const {
01256   switch (MI->getOpcode()) {
01257     default: return false;
01258     case Hexagon::STriw_pred :
01259     case Hexagon::LDriw_pred :
01260       return true;
01261   }
01262 }
01263 
01264 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
01265   switch (MI->getOpcode()) {
01266     default: return false;
01267     case Hexagon::CMPEQrr:
01268     case Hexagon::CMPEQri:
01269     case Hexagon::CMPGTrr:
01270     case Hexagon::CMPGTri:
01271     case Hexagon::CMPGTUrr:
01272     case Hexagon::CMPGTUri:
01273       return true;
01274   }
01275 }
01276 
01277 bool HexagonInstrInfo::
01278 isConditionalTransfer (const MachineInstr *MI) const {
01279   switch (MI->getOpcode()) {
01280     default: return false;
01281     case Hexagon::TFR_cPt:
01282     case Hexagon::TFR_cNotPt:
01283     case Hexagon::TFRI_cPt:
01284     case Hexagon::TFRI_cNotPt:
01285     case Hexagon::TFR_cdnPt:
01286     case Hexagon::TFR_cdnNotPt:
01287     case Hexagon::TFRI_cdnPt:
01288     case Hexagon::TFRI_cdnNotPt:
01289       return true;
01290   }
01291 }
01292 
01293 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
01294   const HexagonRegisterInfo& QRI = getRegisterInfo();
01295   switch (MI->getOpcode())
01296   {
01297     default: return false;
01298     case Hexagon::A2_paddf:
01299     case Hexagon::A2_paddfnew:
01300     case Hexagon::A2_paddt:
01301     case Hexagon::A2_paddtnew:
01302     case Hexagon::A2_pandf:
01303     case Hexagon::A2_pandfnew:
01304     case Hexagon::A2_pandt:
01305     case Hexagon::A2_pandtnew:
01306     case Hexagon::A2_porf:
01307     case Hexagon::A2_porfnew:
01308     case Hexagon::A2_port:
01309     case Hexagon::A2_portnew:
01310     case Hexagon::A2_psubf:
01311     case Hexagon::A2_psubfnew:
01312     case Hexagon::A2_psubt:
01313     case Hexagon::A2_psubtnew:
01314     case Hexagon::A2_pxorf:
01315     case Hexagon::A2_pxorfnew:
01316     case Hexagon::A2_pxort:
01317     case Hexagon::A2_pxortnew:
01318     case Hexagon::A4_psxthf:
01319     case Hexagon::A4_psxthfnew:
01320     case Hexagon::A4_psxtht:
01321     case Hexagon::A4_psxthtnew:
01322     case Hexagon::A4_psxtbf:
01323     case Hexagon::A4_psxtbfnew:
01324     case Hexagon::A4_psxtbt:
01325     case Hexagon::A4_psxtbtnew:
01326     case Hexagon::ADD_ri_cPt:
01327     case Hexagon::ADD_ri_cNotPt:
01328     case Hexagon::COMBINE_rr_cPt:
01329     case Hexagon::COMBINE_rr_cNotPt:
01330       return true;
01331     case Hexagon::ASLH_cPt_V4:
01332     case Hexagon::ASLH_cNotPt_V4:
01333     case Hexagon::ASRH_cPt_V4:
01334     case Hexagon::ASRH_cNotPt_V4:
01335     case Hexagon::ZXTB_cPt_V4:
01336     case Hexagon::ZXTB_cNotPt_V4:
01337     case Hexagon::ZXTH_cPt_V4:
01338     case Hexagon::ZXTH_cNotPt_V4:
01339       return QRI.Subtarget.hasV4TOps();
01340   }
01341 }
01342 
01343 bool HexagonInstrInfo::
01344 isConditionalLoad (const MachineInstr* MI) const {
01345   const HexagonRegisterInfo& QRI = getRegisterInfo();
01346   switch (MI->getOpcode())
01347   {
01348     default: return false;
01349     case Hexagon::LDrid_cPt :
01350     case Hexagon::LDrid_cNotPt :
01351     case Hexagon::LDrid_indexed_cPt :
01352     case Hexagon::LDrid_indexed_cNotPt :
01353     case Hexagon::LDriw_cPt :
01354     case Hexagon::LDriw_cNotPt :
01355     case Hexagon::LDriw_indexed_cPt :
01356     case Hexagon::LDriw_indexed_cNotPt :
01357     case Hexagon::LDrih_cPt :
01358     case Hexagon::LDrih_cNotPt :
01359     case Hexagon::LDrih_indexed_cPt :
01360     case Hexagon::LDrih_indexed_cNotPt :
01361     case Hexagon::LDrib_cPt :
01362     case Hexagon::LDrib_cNotPt :
01363     case Hexagon::LDrib_indexed_cPt :
01364     case Hexagon::LDrib_indexed_cNotPt :
01365     case Hexagon::LDriuh_cPt :
01366     case Hexagon::LDriuh_cNotPt :
01367     case Hexagon::LDriuh_indexed_cPt :
01368     case Hexagon::LDriuh_indexed_cNotPt :
01369     case Hexagon::LDriub_cPt :
01370     case Hexagon::LDriub_cNotPt :
01371     case Hexagon::LDriub_indexed_cPt :
01372     case Hexagon::LDriub_indexed_cNotPt :
01373       return true;
01374     case Hexagon::POST_LDrid_cPt :
01375     case Hexagon::POST_LDrid_cNotPt :
01376     case Hexagon::POST_LDriw_cPt :
01377     case Hexagon::POST_LDriw_cNotPt :
01378     case Hexagon::POST_LDrih_cPt :
01379     case Hexagon::POST_LDrih_cNotPt :
01380     case Hexagon::POST_LDrib_cPt :
01381     case Hexagon::POST_LDrib_cNotPt :
01382     case Hexagon::POST_LDriuh_cPt :
01383     case Hexagon::POST_LDriuh_cNotPt :
01384     case Hexagon::POST_LDriub_cPt :
01385     case Hexagon::POST_LDriub_cNotPt :
01386       return QRI.Subtarget.hasV4TOps();
01387     case Hexagon::LDrid_indexed_shl_cPt_V4 :
01388     case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
01389     case Hexagon::LDrib_indexed_shl_cPt_V4 :
01390     case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
01391     case Hexagon::LDriub_indexed_shl_cPt_V4 :
01392     case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
01393     case Hexagon::LDrih_indexed_shl_cPt_V4 :
01394     case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
01395     case Hexagon::LDriuh_indexed_shl_cPt_V4 :
01396     case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
01397     case Hexagon::LDriw_indexed_shl_cPt_V4 :
01398     case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
01399       return QRI.Subtarget.hasV4TOps();
01400   }
01401 }
01402 
01403 // Returns true if an instruction is a conditional store.
01404 //
01405 // Note: It doesn't include conditional new-value stores as they can't be
01406 // converted to .new predicate.
01407 //
01408 //               p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
01409 //                ^           ^
01410 //               /             \ (not OK. it will cause new-value store to be
01411 //              /               X conditional on p0.new while R2 producer is
01412 //             /                 \ on p0)
01413 //            /                   \.
01414 //     p.new store                 p.old NV store
01415 // [if(p0.new)memw(R0+#0)=R2]    [if(p0)memw(R0+#0)=R2.new]
01416 //            ^                  ^
01417 //             \                /
01418 //              \              /
01419 //               \            /
01420 //                 p.old store
01421 //             [if (p0)memw(R0+#0)=R2]
01422 //
01423 // The above diagram shows the steps involoved in the conversion of a predicated
01424 // store instruction to its .new predicated new-value form.
01425 //
01426 // The following set of instructions further explains the scenario where
01427 // conditional new-value store becomes invalid when promoted to .new predicate
01428 // form.
01429 //
01430 // { 1) if (p0) r0 = add(r1, r2)
01431 //   2) p0 = cmp.eq(r3, #0) }
01432 //
01433 //   3) if (p0) memb(r1+#0) = r0  --> this instruction can't be grouped with
01434 // the first two instructions because in instr 1, r0 is conditional on old value
01435 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
01436 // is not valid for new-value stores.
01437 bool HexagonInstrInfo::
01438 isConditionalStore (const MachineInstr* MI) const {
01439   const HexagonRegisterInfo& QRI = getRegisterInfo();
01440   switch (MI->getOpcode())
01441   {
01442     default: return false;
01443     case Hexagon::STrib_imm_cPt_V4 :
01444     case Hexagon::STrib_imm_cNotPt_V4 :
01445     case Hexagon::STrib_indexed_shl_cPt_V4 :
01446     case Hexagon::STrib_indexed_shl_cNotPt_V4 :
01447     case Hexagon::STrib_cPt :
01448     case Hexagon::STrib_cNotPt :
01449     case Hexagon::POST_STbri_cPt :
01450     case Hexagon::POST_STbri_cNotPt :
01451     case Hexagon::STrid_indexed_cPt :
01452     case Hexagon::STrid_indexed_cNotPt :
01453     case Hexagon::STrid_indexed_shl_cPt_V4 :
01454     case Hexagon::POST_STdri_cPt :
01455     case Hexagon::POST_STdri_cNotPt :
01456     case Hexagon::STrih_cPt :
01457     case Hexagon::STrih_cNotPt :
01458     case Hexagon::STrih_indexed_cPt :
01459     case Hexagon::STrih_indexed_cNotPt :
01460     case Hexagon::STrih_imm_cPt_V4 :
01461     case Hexagon::STrih_imm_cNotPt_V4 :
01462     case Hexagon::STrih_indexed_shl_cPt_V4 :
01463     case Hexagon::STrih_indexed_shl_cNotPt_V4 :
01464     case Hexagon::POST_SThri_cPt :
01465     case Hexagon::POST_SThri_cNotPt :
01466     case Hexagon::STriw_cPt :
01467     case Hexagon::STriw_cNotPt :
01468     case Hexagon::STriw_indexed_cPt :
01469     case Hexagon::STriw_indexed_cNotPt :
01470     case Hexagon::STriw_imm_cPt_V4 :
01471     case Hexagon::STriw_imm_cNotPt_V4 :
01472     case Hexagon::STriw_indexed_shl_cPt_V4 :
01473     case Hexagon::STriw_indexed_shl_cNotPt_V4 :
01474     case Hexagon::POST_STwri_cPt :
01475     case Hexagon::POST_STwri_cNotPt :
01476       return QRI.Subtarget.hasV4TOps();
01477 
01478     // V4 global address store before promoting to dot new.
01479     case Hexagon::STd_GP_cPt_V4 :
01480     case Hexagon::STd_GP_cNotPt_V4 :
01481     case Hexagon::STb_GP_cPt_V4 :
01482     case Hexagon::STb_GP_cNotPt_V4 :
01483     case Hexagon::STh_GP_cPt_V4 :
01484     case Hexagon::STh_GP_cNotPt_V4 :
01485     case Hexagon::STw_GP_cPt_V4 :
01486     case Hexagon::STw_GP_cNotPt_V4 :
01487       return QRI.Subtarget.hasV4TOps();
01488 
01489     // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
01490     // from the "Conditional Store" list. Because a predicated new value store
01491     // would NOT be promoted to a double dot new store. See diagram below:
01492     // This function returns yes for those stores that are predicated but not
01493     // yet promoted to predicate dot new instructions.
01494     //
01495     //                          +---------------------+
01496     //                    /-----| if (p0) memw(..)=r0 |---------\~
01497     //                   ||     +---------------------+         ||
01498     //          promote  ||       /\       /\                   ||  promote
01499     //                   ||      /||\     /||\                  ||
01500     //                  \||/    demote     ||                  \||/
01501     //                   \/       ||       ||                   \/
01502     //       +-------------------------+   ||   +-------------------------+
01503     //       | if (p0.new) memw(..)=r0 |   ||   | if (p0) memw(..)=r0.new |
01504     //       +-------------------------+   ||   +-------------------------+
01505     //                        ||           ||         ||
01506     //                        ||         demote      \||/
01507     //                      promote        ||         \/ NOT possible
01508     //                        ||           ||         /\~
01509     //                       \||/          ||        /||\~
01510     //                        \/           ||         ||
01511     //                      +-----------------------------+
01512     //                      | if (p0.new) memw(..)=r0.new |
01513     //                      +-----------------------------+
01514     //                           Double Dot New Store
01515     //
01516   }
01517 }
01518 
01519 
01520 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
01521   if (isNewValue(MI) && isBranch(MI))
01522     return true;
01523   return false;
01524 }
01525 
01526 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
01527   return (getAddrMode(MI) == HexagonII::PostInc);
01528 }
01529 
01530 bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
01531   const uint64_t F = MI->getDesc().TSFlags;
01532   return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
01533 }
01534 
01535 // Returns true, if any one of the operands is a dot new
01536 // insn, whether it is predicated dot new or register dot new.
01537 bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
01538   return (isNewValueInst(MI) ||
01539      (isPredicated(MI) && isPredicatedNew(MI)));
01540 }
01541 
01542 // Returns the most basic instruction for the .new predicated instructions and
01543 // new-value stores.
01544 // For example, all of the following instructions will be converted back to the
01545 // same instruction:
01546 // 1) if (p0.new) memw(R0+#0) = R1.new  --->
01547 // 2) if (p0) memw(R0+#0)= R1.new      -------> if (p0) memw(R0+#0) = R1
01548 // 3) if (p0.new) memw(R0+#0) = R1      --->
01549 //
01550 
01551 int HexagonInstrInfo::GetDotOldOp(const int opc) const {
01552   int NewOp = opc;
01553   if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
01554     NewOp = Hexagon::getPredOldOpcode(NewOp);
01555     assert(NewOp >= 0 &&
01556            "Couldn't change predicate new instruction to its old form.");
01557   }
01558 
01559   if (isNewValueStore(NewOp)) { // Convert into non-new-value format
01560     NewOp = Hexagon::getNonNVStore(NewOp);
01561     assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
01562   }
01563   return NewOp;
01564 }
01565 
01566 // Return the new value instruction for a given store.
01567 int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const {
01568   int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
01569   if (NVOpcode >= 0) // Valid new-value store instruction.
01570     return NVOpcode;
01571 
01572   switch (MI->getOpcode()) {
01573   default: llvm_unreachable("Unknown .new type");
01574   // store new value byte
01575   case Hexagon::STrib_shl_V4:
01576     return Hexagon::STrib_shl_nv_V4;
01577 
01578   case Hexagon::STrih_shl_V4:
01579     return Hexagon::STrih_shl_nv_V4;
01580 
01581   case Hexagon::STriw_f:
01582     return Hexagon::STriw_nv_V4;
01583 
01584   case Hexagon::STriw_indexed_f:
01585     return Hexagon::STriw_indexed_nv_V4;
01586 
01587   case Hexagon::STriw_shl_V4:
01588     return Hexagon::STriw_shl_nv_V4;
01589 
01590   }
01591   return 0;
01592 }
01593 
01594 // Return .new predicate version for an instruction.
01595 int HexagonInstrInfo::GetDotNewPredOp(MachineInstr *MI,
01596                                       const MachineBranchProbabilityInfo
01597                                       *MBPI) const {
01598 
01599   int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
01600   if (NewOpcode >= 0) // Valid predicate new instruction
01601     return NewOpcode;
01602 
01603   switch (MI->getOpcode()) {
01604   default: llvm_unreachable("Unknown .new type");
01605   // Condtional Jumps
01606   case Hexagon::JMP_t:
01607   case Hexagon::JMP_f:
01608     return getDotNewPredJumpOp(MI, MBPI);
01609 
01610   case Hexagon::JMPR_t:
01611     return Hexagon::JMPR_tnew_tV3;
01612 
01613   case Hexagon::JMPR_f:
01614     return Hexagon::JMPR_fnew_tV3;
01615 
01616   case Hexagon::JMPret_t:
01617     return Hexagon::JMPret_tnew_tV3;
01618 
01619   case Hexagon::JMPret_f:
01620     return Hexagon::JMPret_fnew_tV3;
01621 
01622 
01623   // Conditional combine
01624   case Hexagon::COMBINE_rr_cPt :
01625     return Hexagon::COMBINE_rr_cdnPt;
01626   case Hexagon::COMBINE_rr_cNotPt :
01627     return Hexagon::COMBINE_rr_cdnNotPt;
01628   }
01629 }
01630 
01631 
01632 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
01633   const uint64_t F = MI->getDesc().TSFlags;
01634 
01635   return((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
01636 }
01637 
01638 /// immediateExtend - Changes the instruction in place to one using an immediate
01639 /// extender.
01640 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
01641   assert((isExtendable(MI)||isConstExtended(MI)) &&
01642                                "Instruction must be extendable");
01643   // Find which operand is extendable.
01644   short ExtOpNum = getCExtOpNum(MI);
01645   MachineOperand &MO = MI->getOperand(ExtOpNum);
01646   // This needs to be something we understand.
01647   assert((MO.isMBB() || MO.isImm()) &&
01648          "Branch with unknown extendable field type");
01649   // Mark given operand as extended.
01650   MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
01651 }
01652 
01653 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
01654     const TargetSubtargetInfo &STI) const {
01655   const InstrItineraryData *II = STI.getInstrItineraryData();
01656   return static_cast<const HexagonSubtarget &>(STI).createDFAPacketizer(II);
01657 }
01658 
01659 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
01660                                             const MachineBasicBlock *MBB,
01661                                             const MachineFunction &MF) const {
01662   // Debug info is never a scheduling boundary. It's necessary to be explicit
01663   // due to the special treatment of IT instructions below, otherwise a
01664   // dbg_value followed by an IT will result in the IT instruction being
01665   // considered a scheduling hazard, which is wrong. It should be the actual
01666   // instruction preceding the dbg_value instruction(s), just like it is
01667   // when debug info is not present.
01668   if (MI->isDebugValue())
01669     return false;
01670 
01671   // Terminators and labels can't be scheduled around.
01672   if (MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm())
01673     return true;
01674 
01675   return false;
01676 }
01677 
01678 bool HexagonInstrInfo::isConstExtended(MachineInstr *MI) const {
01679 
01680   // Constant extenders are allowed only for V4 and above.
01681   if (!Subtarget.hasV4TOps())
01682     return false;
01683 
01684   const uint64_t F = MI->getDesc().TSFlags;
01685   unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
01686   if (isExtended) // Instruction must be extended.
01687     return true;
01688 
01689   unsigned isExtendable = (F >> HexagonII::ExtendablePos)
01690                           & HexagonII::ExtendableMask;
01691   if (!isExtendable)
01692     return false;
01693 
01694   short ExtOpNum = getCExtOpNum(MI);
01695   const MachineOperand &MO = MI->getOperand(ExtOpNum);
01696   // Use MO operand flags to determine if MO
01697   // has the HMOTF_ConstExtended flag set.
01698   if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
01699     return true;
01700   // If this is a Machine BB address we are talking about, and it is
01701   // not marked as extended, say so.
01702   if (MO.isMBB())
01703     return false;
01704 
01705   // We could be using an instruction with an extendable immediate and shoehorn
01706   // a global address into it. If it is a global address it will be constant
01707   // extended. We do this for COMBINE.
01708   // We currently only handle isGlobal() because it is the only kind of
01709   // object we are going to end up with here for now.
01710   // In the future we probably should add isSymbol(), etc.
01711   if (MO.isGlobal() || MO.isSymbol())
01712     return true;
01713 
01714   // If the extendable operand is not 'Immediate' type, the instruction should
01715   // have 'isExtended' flag set.
01716   assert(MO.isImm() && "Extendable operand must be Immediate type");
01717 
01718   int MinValue = getMinValue(MI);
01719   int MaxValue = getMaxValue(MI);
01720   int ImmValue = MO.getImm();
01721 
01722   return (ImmValue < MinValue || ImmValue > MaxValue);
01723 }
01724 
01725 // Returns the opcode to use when converting MI, which is a conditional jump,
01726 // into a conditional instruction which uses the .new value of the predicate.
01727 // We also use branch probabilities to add a hint to the jump.
01728 int
01729 HexagonInstrInfo::getDotNewPredJumpOp(MachineInstr *MI,
01730                                   const
01731                                   MachineBranchProbabilityInfo *MBPI) const {
01732 
01733   // We assume that block can have at most two successors.
01734   bool taken = false;
01735   MachineBasicBlock *Src = MI->getParent();
01736   MachineOperand *BrTarget = &MI->getOperand(1);
01737   MachineBasicBlock *Dst = BrTarget->getMBB();
01738 
01739   const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
01740   if (Prediction >= BranchProbability(1,2))
01741     taken = true;
01742 
01743   switch (MI->getOpcode()) {
01744   case Hexagon::JMP_t:
01745     return taken ? Hexagon::JMP_tnew_t : Hexagon::JMP_tnew_nt;
01746   case Hexagon::JMP_f:
01747     return taken ? Hexagon::JMP_fnew_t : Hexagon::JMP_fnew_nt;
01748 
01749   default:
01750     llvm_unreachable("Unexpected jump instruction.");
01751   }
01752 }
01753 // Returns true if a particular operand is extendable for an instruction.
01754 bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
01755                                          unsigned short OperandNum) const {
01756   // Constant extenders are allowed only for V4 and above.
01757   if (!Subtarget.hasV4TOps())
01758     return false;
01759 
01760   const uint64_t F = MI->getDesc().TSFlags;
01761 
01762   return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
01763           == OperandNum;
01764 }
01765 
01766 // Returns Operand Index for the constant extended instruction.
01767 unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
01768   const uint64_t F = MI->getDesc().TSFlags;
01769   return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
01770 }
01771 
01772 // Returns the min value that doesn't need to be extended.
01773 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
01774   const uint64_t F = MI->getDesc().TSFlags;
01775   unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
01776                     & HexagonII::ExtentSignedMask;
01777   unsigned bits =  (F >> HexagonII::ExtentBitsPos)
01778                     & HexagonII::ExtentBitsMask;
01779 
01780   if (isSigned) // if value is signed
01781     return -1U << (bits - 1);
01782   else
01783     return 0;
01784 }
01785 
01786 // Returns the max value that doesn't need to be extended.
01787 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
01788   const uint64_t F = MI->getDesc().TSFlags;
01789   unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
01790                     & HexagonII::ExtentSignedMask;
01791   unsigned bits =  (F >> HexagonII::ExtentBitsPos)
01792                     & HexagonII::ExtentBitsMask;
01793 
01794   if (isSigned) // if value is signed
01795     return ~(-1U << (bits - 1));
01796   else
01797     return ~(-1U << bits);
01798 }
01799 
01800 // Returns true if an instruction can be converted into a non-extended
01801 // equivalent instruction.
01802 bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr *MI) const {
01803 
01804   short NonExtOpcode;
01805   // Check if the instruction has a register form that uses register in place
01806   // of the extended operand, if so return that as the non-extended form.
01807   if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
01808     return true;
01809 
01810   if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
01811     // Check addressing mode and retrieve non-ext equivalent instruction.
01812 
01813     switch (getAddrMode(MI)) {
01814     case HexagonII::Absolute :
01815       // Load/store with absolute addressing mode can be converted into
01816       // base+offset mode.
01817       NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode());
01818       break;
01819     case HexagonII::BaseImmOffset :
01820       // Load/store with base+offset addressing mode can be converted into
01821       // base+register offset addressing mode. However left shift operand should
01822       // be set to 0.
01823       NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
01824       break;
01825     default:
01826       return false;
01827     }
01828     if (NonExtOpcode < 0)
01829       return false;
01830     return true;
01831   }
01832   return false;
01833 }
01834 
01835 // Returns opcode of the non-extended equivalent instruction.
01836 short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const {
01837 
01838   // Check if the instruction has a register form that uses register in place
01839   // of the extended operand, if so return that as the non-extended form.
01840   short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
01841     if (NonExtOpcode >= 0)
01842       return NonExtOpcode;
01843 
01844   if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
01845     // Check addressing mode and retrieve non-ext equivalent instruction.
01846     switch (getAddrMode(MI)) {
01847     case HexagonII::Absolute :
01848       return Hexagon::getBasedWithImmOffset(MI->getOpcode());
01849     case HexagonII::BaseImmOffset :
01850       return Hexagon::getBaseWithRegOffset(MI->getOpcode());
01851     default:
01852       return -1;
01853     }
01854   }
01855   return -1;
01856 }
01857 
01858 bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode) const {
01859   return (Opcode == Hexagon::JMP_t) ||
01860          (Opcode == Hexagon::JMP_f) ||
01861          (Opcode == Hexagon::JMP_tnew_t) ||
01862          (Opcode == Hexagon::JMP_fnew_t) ||
01863          (Opcode == Hexagon::JMP_tnew_nt) ||
01864          (Opcode == Hexagon::JMP_fnew_nt);
01865 }
01866 
01867 bool HexagonInstrInfo::PredOpcodeHasNot(Opcode_t Opcode) const {
01868   return (Opcode == Hexagon::JMP_f) ||
01869          (Opcode == Hexagon::JMP_fnew_t) ||
01870          (Opcode == Hexagon::JMP_fnew_nt);
01871 }