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HexagonInstrInfo.cpp
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00001 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the Hexagon implementation of the TargetInstrInfo class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "HexagonInstrInfo.h"
00015 #include "Hexagon.h"
00016 #include "HexagonRegisterInfo.h"
00017 #include "HexagonSubtarget.h"
00018 #include "llvm/ADT/STLExtras.h"
00019 #include "llvm/ADT/SmallVector.h"
00020 #include "llvm/CodeGen/DFAPacketizer.h"
00021 #include "llvm/CodeGen/MachineFrameInfo.h"
00022 #include "llvm/CodeGen/MachineInstrBuilder.h"
00023 #include "llvm/CodeGen/MachineMemOperand.h"
00024 #include "llvm/CodeGen/MachineRegisterInfo.h"
00025 #include "llvm/CodeGen/PseudoSourceValue.h"
00026 #include "llvm/Support/Debug.h"
00027 #include "llvm/Support/MathExtras.h"
00028 #include "llvm/Support/raw_ostream.h"
00029 #define GET_INSTRINFO_CTOR_DTOR
00030 #define GET_INSTRMAP_INFO
00031 #include "HexagonGenInstrInfo.inc"
00032 #include "HexagonGenDFAPacketizer.inc"
00033 
00034 using namespace llvm;
00035 
00036 ///
00037 /// Constants for Hexagon instructions.
00038 ///
00039 const int Hexagon_MEMW_OFFSET_MAX = 4095;
00040 const int Hexagon_MEMW_OFFSET_MIN = -4096;
00041 const int Hexagon_MEMD_OFFSET_MAX = 8191;
00042 const int Hexagon_MEMD_OFFSET_MIN = -8192;
00043 const int Hexagon_MEMH_OFFSET_MAX = 2047;
00044 const int Hexagon_MEMH_OFFSET_MIN = -2048;
00045 const int Hexagon_MEMB_OFFSET_MAX = 1023;
00046 const int Hexagon_MEMB_OFFSET_MIN = -1024;
00047 const int Hexagon_ADDI_OFFSET_MAX = 32767;
00048 const int Hexagon_ADDI_OFFSET_MIN = -32768;
00049 const int Hexagon_MEMD_AUTOINC_MAX = 56;
00050 const int Hexagon_MEMD_AUTOINC_MIN = -64;
00051 const int Hexagon_MEMW_AUTOINC_MAX = 28;
00052 const int Hexagon_MEMW_AUTOINC_MIN = -32;
00053 const int Hexagon_MEMH_AUTOINC_MAX = 14;
00054 const int Hexagon_MEMH_AUTOINC_MIN = -16;
00055 const int Hexagon_MEMB_AUTOINC_MAX = 7;
00056 const int Hexagon_MEMB_AUTOINC_MIN = -8;
00057 
00058 // Pin the vtable to this file.
00059 void HexagonInstrInfo::anchor() {}
00060 
00061 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
00062   : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
00063     RI(ST), Subtarget(ST) {
00064 }
00065 
00066 
00067 /// isLoadFromStackSlot - If the specified machine instruction is a direct
00068 /// load from a stack slot, return the virtual or physical register number of
00069 /// the destination along with the FrameIndex of the loaded stack slot.  If
00070 /// not, return 0.  This predicate must return 0 if the instruction has
00071 /// any side effects other than loading from the stack slot.
00072 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
00073                                              int &FrameIndex) const {
00074 
00075 
00076   switch (MI->getOpcode()) {
00077   default: break;
00078   case Hexagon::LDriw:
00079   case Hexagon::LDrid:
00080   case Hexagon::LDrih:
00081   case Hexagon::LDrib:
00082   case Hexagon::LDriub:
00083     if (MI->getOperand(2).isFI() &&
00084         MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
00085       FrameIndex = MI->getOperand(2).getIndex();
00086       return MI->getOperand(0).getReg();
00087     }
00088     break;
00089   }
00090   return 0;
00091 }
00092 
00093 
00094 /// isStoreToStackSlot - If the specified machine instruction is a direct
00095 /// store to a stack slot, return the virtual or physical register number of
00096 /// the source reg along with the FrameIndex of the loaded stack slot.  If
00097 /// not, return 0.  This predicate must return 0 if the instruction has
00098 /// any side effects other than storing to the stack slot.
00099 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
00100                                             int &FrameIndex) const {
00101   switch (MI->getOpcode()) {
00102   default: break;
00103   case Hexagon::STriw:
00104   case Hexagon::STrid:
00105   case Hexagon::STrih:
00106   case Hexagon::STrib:
00107     if (MI->getOperand(2).isFI() &&
00108         MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
00109       FrameIndex = MI->getOperand(0).getIndex();
00110       return MI->getOperand(2).getReg();
00111     }
00112     break;
00113   }
00114   return 0;
00115 }
00116 
00117 
00118 unsigned
00119 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
00120                              MachineBasicBlock *FBB,
00121                              const SmallVectorImpl<MachineOperand> &Cond,
00122                              DebugLoc DL) const{
00123 
00124     int BOpc   = Hexagon::JMP;
00125     int BccOpc = Hexagon::JMP_t;
00126 
00127     assert(TBB && "InsertBranch must not be told to insert a fallthrough");
00128 
00129     int regPos = 0;
00130     // Check if ReverseBranchCondition has asked to reverse this branch
00131     // If we want to reverse the branch an odd number of times, we want
00132     // JMP_f.
00133     if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
00134       BccOpc = Hexagon::JMP_f;
00135       regPos = 1;
00136     }
00137 
00138     if (FBB == 0) {
00139       if (Cond.empty()) {
00140         // Due to a bug in TailMerging/CFG Optimization, we need to add a
00141         // special case handling of a predicated jump followed by an
00142         // unconditional jump. If not, Tail Merging and CFG Optimization go
00143         // into an infinite loop.
00144         MachineBasicBlock *NewTBB, *NewFBB;
00145         SmallVector<MachineOperand, 4> Cond;
00146         MachineInstr *Term = MBB.getFirstTerminator();
00147         if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
00148                                                  false)) {
00149           MachineBasicBlock *NextBB =
00150             std::next(MachineFunction::iterator(&MBB));
00151           if (NewTBB == NextBB) {
00152             ReverseBranchCondition(Cond);
00153             RemoveBranch(MBB);
00154             return InsertBranch(MBB, TBB, 0, Cond, DL);
00155           }
00156         }
00157         BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
00158       } else {
00159         BuildMI(&MBB, DL,
00160                 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
00161       }
00162       return 1;
00163     }
00164 
00165     BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
00166     BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
00167 
00168     return 2;
00169 }
00170 
00171 
00172 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
00173                                      MachineBasicBlock *&TBB,
00174                                  MachineBasicBlock *&FBB,
00175                                  SmallVectorImpl<MachineOperand> &Cond,
00176                                  bool AllowModify) const {
00177   TBB = NULL;
00178   FBB = NULL;
00179 
00180   // If the block has no terminators, it just falls into the block after it.
00181   MachineBasicBlock::instr_iterator I = MBB.instr_end();
00182   if (I == MBB.instr_begin())
00183     return false;
00184 
00185   // A basic block may looks like this:
00186   //
00187   //  [   insn
00188   //     EH_LABEL
00189   //      insn
00190   //      insn
00191   //      insn
00192   //     EH_LABEL
00193   //      insn     ]
00194   //
00195   // It has two succs but does not have a terminator
00196   // Don't know how to handle it.
00197   do {
00198     --I;
00199     if (I->isEHLabel())
00200       return true;
00201   } while (I != MBB.instr_begin());
00202 
00203   I = MBB.instr_end();
00204   --I;
00205 
00206   while (I->isDebugValue()) {
00207     if (I == MBB.instr_begin())
00208       return false;
00209     --I;
00210   }
00211 
00212   // Delete the JMP if it's equivalent to a fall-through.
00213   if (AllowModify && I->getOpcode() == Hexagon::JMP &&
00214       MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
00215     DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
00216     I->eraseFromParent();
00217     I = MBB.instr_end();
00218     if (I == MBB.instr_begin())
00219       return false;
00220     --I;
00221   }
00222   if (!isUnpredicatedTerminator(I))
00223     return false;
00224 
00225   // Get the last instruction in the block.
00226   MachineInstr *LastInst = I;
00227   MachineInstr *SecondLastInst = NULL;
00228   // Find one more terminator if present.
00229   do {
00230     if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(I)) {
00231       if (!SecondLastInst)
00232         SecondLastInst = I;
00233       else
00234         // This is a third branch.
00235         return true;
00236     }
00237     if (I == MBB.instr_begin())
00238       break;
00239     --I;
00240   } while(I);
00241 
00242   int LastOpcode = LastInst->getOpcode();
00243 
00244   bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
00245   bool LastOpcodeHasNot = PredOpcodeHasNot(LastOpcode);
00246 
00247   // If there is only one terminator instruction, process it.
00248   if (LastInst && !SecondLastInst) {
00249     if (LastOpcode == Hexagon::JMP) {
00250       TBB = LastInst->getOperand(0).getMBB();
00251       return false;
00252     }
00253     if (LastOpcode == Hexagon::ENDLOOP0) {
00254       TBB = LastInst->getOperand(0).getMBB();
00255       Cond.push_back(LastInst->getOperand(0));
00256       return false;
00257     }
00258     if (LastOpcodeHasJMP_c) {
00259       TBB = LastInst->getOperand(1).getMBB();
00260       if (LastOpcodeHasNot) {
00261         Cond.push_back(MachineOperand::CreateImm(0));
00262       }
00263       Cond.push_back(LastInst->getOperand(0));
00264       return false;
00265     }
00266     // Otherwise, don't know what this is.
00267     return true;
00268   }
00269 
00270   int SecLastOpcode = SecondLastInst->getOpcode();
00271 
00272   bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
00273   bool SecLastOpcodeHasNot = PredOpcodeHasNot(SecLastOpcode);
00274   if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::JMP)) {
00275     TBB =  SecondLastInst->getOperand(1).getMBB();
00276     if (SecLastOpcodeHasNot)
00277       Cond.push_back(MachineOperand::CreateImm(0));
00278     Cond.push_back(SecondLastInst->getOperand(0));
00279     FBB = LastInst->getOperand(0).getMBB();
00280     return false;
00281   }
00282 
00283   // If the block ends with two Hexagon:JMPs, handle it.  The second one is not
00284   // executed, so remove it.
00285   if (SecLastOpcode == Hexagon::JMP && LastOpcode == Hexagon::JMP) {
00286     TBB = SecondLastInst->getOperand(0).getMBB();
00287     I = LastInst;
00288     if (AllowModify)
00289       I->eraseFromParent();
00290     return false;
00291   }
00292 
00293   // If the block ends with an ENDLOOP, and JMP, handle it.
00294   if (SecLastOpcode == Hexagon::ENDLOOP0 &&
00295       LastOpcode == Hexagon::JMP) {
00296     TBB = SecondLastInst->getOperand(0).getMBB();
00297     Cond.push_back(SecondLastInst->getOperand(0));
00298     FBB = LastInst->getOperand(0).getMBB();
00299     return false;
00300   }
00301 
00302   // Otherwise, can't handle this.
00303   return true;
00304 }
00305 
00306 
00307 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
00308   int BOpc   = Hexagon::JMP;
00309   int BccOpc = Hexagon::JMP_t;
00310   int BccOpcNot = Hexagon::JMP_f;
00311 
00312   MachineBasicBlock::iterator I = MBB.end();
00313   if (I == MBB.begin()) return 0;
00314   --I;
00315   if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
00316       I->getOpcode() != BccOpcNot)
00317     return 0;
00318 
00319   // Remove the branch.
00320   I->eraseFromParent();
00321 
00322   I = MBB.end();
00323 
00324   if (I == MBB.begin()) return 1;
00325   --I;
00326   if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
00327     return 1;
00328 
00329   // Remove the branch.
00330   I->eraseFromParent();
00331   return 2;
00332 }
00333 
00334 
00335 /// \brief For a comparison instruction, return the source registers in
00336 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
00337 /// compares against in CmpValue. Return true if the comparison instruction
00338 /// can be analyzed.
00339 bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
00340                                       unsigned &SrcReg, unsigned &SrcReg2,
00341                                       int &Mask, int &Value) const {
00342   unsigned Opc = MI->getOpcode();
00343 
00344   // Set mask and the first source register.
00345   switch (Opc) {
00346     case Hexagon::CMPEHexagon4rr:
00347     case Hexagon::CMPEQri:
00348     case Hexagon::CMPEQrr:
00349     case Hexagon::CMPGT64rr:
00350     case Hexagon::CMPGTU64rr:
00351     case Hexagon::CMPGTUri:
00352     case Hexagon::CMPGTUrr:
00353     case Hexagon::CMPGTri:
00354     case Hexagon::CMPGTrr:
00355       SrcReg = MI->getOperand(1).getReg();
00356       Mask = ~0;
00357       break;
00358     case Hexagon::CMPbEQri_V4:
00359     case Hexagon::CMPbEQrr_sbsb_V4:
00360     case Hexagon::CMPbEQrr_ubub_V4:
00361     case Hexagon::CMPbGTUri_V4:
00362     case Hexagon::CMPbGTUrr_V4:
00363     case Hexagon::CMPbGTrr_V4:
00364       SrcReg = MI->getOperand(1).getReg();
00365       Mask = 0xFF;
00366       break;
00367     case Hexagon::CMPhEQri_V4:
00368     case Hexagon::CMPhEQrr_shl_V4:
00369     case Hexagon::CMPhEQrr_xor_V4:
00370     case Hexagon::CMPhGTUri_V4:
00371     case Hexagon::CMPhGTUrr_V4:
00372     case Hexagon::CMPhGTrr_shl_V4:
00373       SrcReg = MI->getOperand(1).getReg();
00374       Mask = 0xFFFF;
00375       break;
00376   }
00377 
00378   // Set the value/second source register.
00379   switch (Opc) {
00380     case Hexagon::CMPEHexagon4rr:
00381     case Hexagon::CMPEQrr:
00382     case Hexagon::CMPGT64rr:
00383     case Hexagon::CMPGTU64rr:
00384     case Hexagon::CMPGTUrr:
00385     case Hexagon::CMPGTrr:
00386     case Hexagon::CMPbEQrr_sbsb_V4:
00387     case Hexagon::CMPbEQrr_ubub_V4:
00388     case Hexagon::CMPbGTUrr_V4:
00389     case Hexagon::CMPbGTrr_V4:
00390     case Hexagon::CMPhEQrr_shl_V4:
00391     case Hexagon::CMPhEQrr_xor_V4:
00392     case Hexagon::CMPhGTUrr_V4:
00393     case Hexagon::CMPhGTrr_shl_V4:
00394       SrcReg2 = MI->getOperand(2).getReg();
00395       return true;
00396 
00397     case Hexagon::CMPEQri:
00398     case Hexagon::CMPGTUri:
00399     case Hexagon::CMPGTri:
00400     case Hexagon::CMPbEQri_V4:
00401     case Hexagon::CMPbGTUri_V4:
00402     case Hexagon::CMPhEQri_V4:
00403     case Hexagon::CMPhGTUri_V4:
00404       SrcReg2 = 0;
00405       Value = MI->getOperand(2).getImm();
00406       return true;
00407   }
00408 
00409   return false;
00410 }
00411 
00412 
00413 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
00414                                  MachineBasicBlock::iterator I, DebugLoc DL,
00415                                  unsigned DestReg, unsigned SrcReg,
00416                                  bool KillSrc) const {
00417   if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
00418     BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
00419     return;
00420   }
00421   if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
00422     BuildMI(MBB, I, DL, get(Hexagon::TFR64), DestReg).addReg(SrcReg);
00423     return;
00424   }
00425   if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
00426     // Map Pd = Ps to Pd = or(Ps, Ps).
00427     BuildMI(MBB, I, DL, get(Hexagon::OR_pp),
00428             DestReg).addReg(SrcReg).addReg(SrcReg);
00429     return;
00430   }
00431   if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
00432       Hexagon::IntRegsRegClass.contains(SrcReg)) {
00433     // We can have an overlap between single and double reg: r1:0 = r0.
00434     if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
00435         // r1:0 = r0
00436         BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
00437                 Hexagon::subreg_hireg))).addImm(0);
00438     } else {
00439         // r1:0 = r1 or no overlap.
00440         BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg,
00441                 Hexagon::subreg_loreg))).addReg(SrcReg);
00442         BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
00443                 Hexagon::subreg_hireg))).addImm(0);
00444     }
00445     return;
00446   }
00447   if (Hexagon::CRRegsRegClass.contains(DestReg) &&
00448       Hexagon::IntRegsRegClass.contains(SrcReg)) {
00449     BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
00450     return;
00451   }
00452   if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
00453       Hexagon::IntRegsRegClass.contains(DestReg)) {
00454     BuildMI(MBB, I, DL, get(Hexagon::TFR_RsPd), DestReg).
00455       addReg(SrcReg, getKillRegState(KillSrc));
00456     return;
00457   }
00458   if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
00459       Hexagon::PredRegsRegClass.contains(DestReg)) {
00460     BuildMI(MBB, I, DL, get(Hexagon::TFR_PdRs), DestReg).
00461       addReg(SrcReg, getKillRegState(KillSrc));
00462     return;
00463   }
00464 
00465   llvm_unreachable("Unimplemented");
00466 }
00467 
00468 
00469 void HexagonInstrInfo::
00470 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
00471                     unsigned SrcReg, bool isKill, int FI,
00472                     const TargetRegisterClass *RC,
00473                     const TargetRegisterInfo *TRI) const {
00474 
00475   DebugLoc DL = MBB.findDebugLoc(I);
00476   MachineFunction &MF = *MBB.getParent();
00477   MachineFrameInfo &MFI = *MF.getFrameInfo();
00478   unsigned Align = MFI.getObjectAlignment(FI);
00479 
00480   MachineMemOperand *MMO =
00481       MF.getMachineMemOperand(
00482                       MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
00483                       MachineMemOperand::MOStore,
00484                       MFI.getObjectSize(FI),
00485                       Align);
00486 
00487   if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
00488     BuildMI(MBB, I, DL, get(Hexagon::STriw))
00489           .addFrameIndex(FI).addImm(0)
00490           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00491   } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
00492     BuildMI(MBB, I, DL, get(Hexagon::STrid))
00493           .addFrameIndex(FI).addImm(0)
00494           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00495   } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
00496     BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
00497           .addFrameIndex(FI).addImm(0)
00498           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00499   } else {
00500     llvm_unreachable("Unimplemented");
00501   }
00502 }
00503 
00504 
00505 void HexagonInstrInfo::storeRegToAddr(
00506                                  MachineFunction &MF, unsigned SrcReg,
00507                                  bool isKill,
00508                                  SmallVectorImpl<MachineOperand> &Addr,
00509                                  const TargetRegisterClass *RC,
00510                                  SmallVectorImpl<MachineInstr*> &NewMIs) const
00511 {
00512   llvm_unreachable("Unimplemented");
00513 }
00514 
00515 
00516 void HexagonInstrInfo::
00517 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
00518                      unsigned DestReg, int FI,
00519                      const TargetRegisterClass *RC,
00520                      const TargetRegisterInfo *TRI) const {
00521   DebugLoc DL = MBB.findDebugLoc(I);
00522   MachineFunction &MF = *MBB.getParent();
00523   MachineFrameInfo &MFI = *MF.getFrameInfo();
00524   unsigned Align = MFI.getObjectAlignment(FI);
00525 
00526   MachineMemOperand *MMO =
00527       MF.getMachineMemOperand(
00528                       MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
00529                       MachineMemOperand::MOLoad,
00530                       MFI.getObjectSize(FI),
00531                       Align);
00532   if (RC == &Hexagon::IntRegsRegClass) {
00533     BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg)
00534           .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00535   } else if (RC == &Hexagon::DoubleRegsRegClass) {
00536     BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
00537           .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00538   } else if (RC == &Hexagon::PredRegsRegClass) {
00539     BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
00540           .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00541   } else {
00542     llvm_unreachable("Can't store this register to stack slot");
00543   }
00544 }
00545 
00546 
00547 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
00548                                         SmallVectorImpl<MachineOperand> &Addr,
00549                                         const TargetRegisterClass *RC,
00550                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
00551   llvm_unreachable("Unimplemented");
00552 }
00553 
00554 
00555 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
00556                                                     MachineInstr* MI,
00557                                           const SmallVectorImpl<unsigned> &Ops,
00558                                                     int FI) const {
00559   // Hexagon_TODO: Implement.
00560   return(0);
00561 }
00562 
00563 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
00564 
00565   MachineRegisterInfo &RegInfo = MF->getRegInfo();
00566   const TargetRegisterClass *TRC;
00567   if (VT == MVT::i1) {
00568     TRC = &Hexagon::PredRegsRegClass;
00569   } else if (VT == MVT::i32 || VT == MVT::f32) {
00570     TRC = &Hexagon::IntRegsRegClass;
00571   } else if (VT == MVT::i64 || VT == MVT::f64) {
00572     TRC = &Hexagon::DoubleRegsRegClass;
00573   } else {
00574     llvm_unreachable("Cannot handle this register class");
00575   }
00576 
00577   unsigned NewReg = RegInfo.createVirtualRegister(TRC);
00578   return NewReg;
00579 }
00580 
00581 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
00582   // Constant extenders are allowed only for V4 and above.
00583   if (!Subtarget.hasV4TOps())
00584     return false;
00585 
00586   const MCInstrDesc &MID = MI->getDesc();
00587   const uint64_t F = MID.TSFlags;
00588   if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
00589     return true;
00590 
00591   // TODO: This is largely obsolete now. Will need to be removed
00592   // in consecutive patches.
00593   switch(MI->getOpcode()) {
00594     // TFR_FI Remains a special case.
00595     case Hexagon::TFR_FI:
00596       return true;
00597     default:
00598       return false;
00599   }
00600   return  false;
00601 }
00602 
00603 // This returns true in two cases:
00604 // - The OP code itself indicates that this is an extended instruction.
00605 // - One of MOs has been marked with HMOTF_ConstExtended flag.
00606 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
00607   // First check if this is permanently extended op code.
00608   const uint64_t F = MI->getDesc().TSFlags;
00609   if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
00610     return true;
00611   // Use MO operand flags to determine if one of MI's operands
00612   // has HMOTF_ConstExtended flag set.
00613   for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
00614        E = MI->operands_end(); I != E; ++I) {
00615     if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
00616       return true;
00617   }
00618   return  false;
00619 }
00620 
00621 bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const {
00622   return MI->getDesc().isBranch();
00623 }
00624 
00625 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
00626   if (isNewValueJump(MI))
00627     return true;
00628 
00629   if (isNewValueStore(MI))
00630     return true;
00631 
00632   return false;
00633 }
00634 
00635 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
00636   return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
00637 }
00638 
00639 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
00640   bool isPred = MI->getDesc().isPredicable();
00641 
00642   if (!isPred)
00643     return false;
00644 
00645   const int Opc = MI->getOpcode();
00646 
00647   switch(Opc) {
00648   case Hexagon::TFRI:
00649     return isInt<12>(MI->getOperand(1).getImm());
00650 
00651   case Hexagon::STrid:
00652   case Hexagon::STrid_indexed:
00653     return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
00654 
00655   case Hexagon::STriw:
00656   case Hexagon::STriw_indexed:
00657   case Hexagon::STriw_nv_V4:
00658     return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
00659 
00660   case Hexagon::STrih:
00661   case Hexagon::STrih_indexed:
00662   case Hexagon::STrih_nv_V4:
00663     return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
00664 
00665   case Hexagon::STrib:
00666   case Hexagon::STrib_indexed:
00667   case Hexagon::STrib_nv_V4:
00668     return isUInt<6>(MI->getOperand(1).getImm());
00669 
00670   case Hexagon::LDrid:
00671   case Hexagon::LDrid_indexed:
00672     return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
00673 
00674   case Hexagon::LDriw:
00675   case Hexagon::LDriw_indexed:
00676     return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
00677 
00678   case Hexagon::LDrih:
00679   case Hexagon::LDriuh:
00680   case Hexagon::LDrih_indexed:
00681   case Hexagon::LDriuh_indexed:
00682     return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
00683 
00684   case Hexagon::LDrib:
00685   case Hexagon::LDriub:
00686   case Hexagon::LDrib_indexed:
00687   case Hexagon::LDriub_indexed:
00688     return isUInt<6>(MI->getOperand(2).getImm());
00689 
00690   case Hexagon::POST_LDrid:
00691     return isShiftedInt<4,3>(MI->getOperand(3).getImm());
00692 
00693   case Hexagon::POST_LDriw:
00694     return isShiftedInt<4,2>(MI->getOperand(3).getImm());
00695 
00696   case Hexagon::POST_LDrih:
00697   case Hexagon::POST_LDriuh:
00698     return isShiftedInt<4,1>(MI->getOperand(3).getImm());
00699 
00700   case Hexagon::POST_LDrib:
00701   case Hexagon::POST_LDriub:
00702     return isInt<4>(MI->getOperand(3).getImm());
00703 
00704   case Hexagon::STrib_imm_V4:
00705   case Hexagon::STrih_imm_V4:
00706   case Hexagon::STriw_imm_V4:
00707     return (isUInt<6>(MI->getOperand(1).getImm()) &&
00708             isInt<6>(MI->getOperand(2).getImm()));
00709 
00710   case Hexagon::ADD_ri:
00711     return isInt<8>(MI->getOperand(2).getImm());
00712 
00713   case Hexagon::ASLH:
00714   case Hexagon::ASRH:
00715   case Hexagon::SXTB:
00716   case Hexagon::SXTH:
00717   case Hexagon::ZXTB:
00718   case Hexagon::ZXTH:
00719     return Subtarget.hasV4TOps();
00720   }
00721 
00722   return true;
00723 }
00724 
00725 // This function performs the following inversiones:
00726 //
00727 //  cPt    ---> cNotPt
00728 //  cNotPt ---> cPt
00729 //
00730 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
00731   int InvPredOpcode;
00732   InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
00733                                         : Hexagon::getTruePredOpcode(Opc);
00734   if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
00735     return InvPredOpcode;
00736 
00737   switch(Opc) {
00738     default: llvm_unreachable("Unexpected predicated instruction");
00739     case Hexagon::COMBINE_rr_cPt:
00740       return Hexagon::COMBINE_rr_cNotPt;
00741     case Hexagon::COMBINE_rr_cNotPt:
00742       return Hexagon::COMBINE_rr_cPt;
00743 
00744       // Dealloc_return.
00745     case Hexagon::DEALLOC_RET_cPt_V4:
00746       return Hexagon::DEALLOC_RET_cNotPt_V4;
00747     case Hexagon::DEALLOC_RET_cNotPt_V4:
00748       return Hexagon::DEALLOC_RET_cPt_V4;
00749   }
00750 }
00751 
00752 // New Value Store instructions.
00753 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
00754   const uint64_t F = MI->getDesc().TSFlags;
00755 
00756   return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
00757 }
00758 
00759 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
00760   const uint64_t F = get(Opcode).TSFlags;
00761 
00762   return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
00763 }
00764 
00765 int HexagonInstrInfo::
00766 getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
00767   enum Hexagon::PredSense inPredSense;
00768   inPredSense = invertPredicate ? Hexagon::PredSense_false :
00769                                   Hexagon::PredSense_true;
00770   int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
00771   if (CondOpcode >= 0) // Valid Conditional opcode/instruction
00772     return CondOpcode;
00773 
00774   // This switch case will be removed once all the instructions have been
00775   // modified to use relation maps.
00776   switch(Opc) {
00777   case Hexagon::TFRI_f:
00778     return !invertPredicate ? Hexagon::TFRI_cPt_f :
00779                               Hexagon::TFRI_cNotPt_f;
00780   case Hexagon::COMBINE_rr:
00781     return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
00782                               Hexagon::COMBINE_rr_cNotPt;
00783 
00784   // Word.
00785   case Hexagon::STriw_f:
00786     return !invertPredicate ? Hexagon::STriw_cPt :
00787                               Hexagon::STriw_cNotPt;
00788   case Hexagon::STriw_indexed_f:
00789     return !invertPredicate ? Hexagon::STriw_indexed_cPt :
00790                               Hexagon::STriw_indexed_cNotPt;
00791 
00792   // DEALLOC_RETURN.
00793   case Hexagon::DEALLOC_RET_V4:
00794     return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
00795                               Hexagon::DEALLOC_RET_cNotPt_V4;
00796   }
00797   llvm_unreachable("Unexpected predicable instruction");
00798 }
00799 
00800 
00801 bool HexagonInstrInfo::
00802 PredicateInstruction(MachineInstr *MI,
00803                      const SmallVectorImpl<MachineOperand> &Cond) const {
00804   int Opc = MI->getOpcode();
00805   assert (isPredicable(MI) && "Expected predicable instruction");
00806   bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
00807                      (Cond[0].getImm() == 0));
00808 
00809   // This will change MI's opcode to its predicate version.
00810   // However, its operand list is still the old one, i.e. the
00811   // non-predicate one.
00812   MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
00813 
00814   int oper = -1;
00815   unsigned int GAIdx = 0;
00816 
00817   // Indicates whether the current MI has a GlobalAddress operand
00818   bool hasGAOpnd = false;
00819   std::vector<MachineOperand> tmpOpnds;
00820 
00821   // Indicates whether we need to shift operands to right.
00822   bool needShift = true;
00823 
00824   // The predicate is ALWAYS the FIRST input operand !!!
00825   if (MI->getNumOperands() == 0) {
00826     // The non-predicate version of MI does not take any operands,
00827     // i.e. no outs and no ins. In this condition, the predicate
00828     // operand will be directly placed at Operands[0]. No operand
00829     // shift is needed.
00830     // Example: BARRIER
00831     needShift = false;
00832     oper = -1;
00833   }
00834   else if (   MI->getOperand(MI->getNumOperands()-1).isReg()
00835            && MI->getOperand(MI->getNumOperands()-1).isDef()
00836            && !MI->getOperand(MI->getNumOperands()-1).isImplicit()) {
00837     // The non-predicate version of MI does not have any input operands.
00838     // In this condition, we extend the length of Operands[] by one and
00839     // copy the original last operand to the newly allocated slot.
00840     // At this moment, it is just a place holder. Later, we will put
00841     // predicate operand directly into it. No operand shift is needed.
00842     // Example: r0=BARRIER (this is a faked insn used here for illustration)
00843     MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
00844     needShift = false;
00845     oper = MI->getNumOperands() - 2;
00846   }
00847   else {
00848     // We need to right shift all input operands by one. Duplicate the
00849     // last operand into the newly allocated slot.
00850     MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
00851   }
00852 
00853   if (needShift)
00854   {
00855     // Operands[ MI->getNumOperands() - 2 ] has been copied into
00856     // Operands[ MI->getNumOperands() - 1 ], so we start from
00857     // Operands[ MI->getNumOperands() - 3 ].
00858     // oper is a signed int.
00859     // It is ok if "MI->getNumOperands()-3" is -3, -2, or -1.
00860     for (oper = MI->getNumOperands() - 3; oper >= 0; --oper)
00861     {
00862       MachineOperand &MO = MI->getOperand(oper);
00863 
00864       // Opnd[0] Opnd[1] Opnd[2] Opnd[3] Opnd[4]   Opnd[5]   Opnd[6]   Opnd[7]
00865       // <Def0>  <Def1>  <Use0>  <Use1>  <ImpDef0> <ImpDef1> <ImpUse0> <ImpUse1>
00866       //               /\~
00867       //              /||\~
00868       //               ||
00869       //        Predicate Operand here
00870       if (MO.isReg() && !MO.isUse() && !MO.isImplicit()) {
00871         break;
00872       }
00873       if (MO.isReg()) {
00874         MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
00875                                                 MO.isImplicit(), MO.isKill(),
00876                                                 MO.isDead(), MO.isUndef(),
00877                                                 MO.isDebug());
00878       }
00879       else if (MO.isImm()) {
00880         MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
00881       }
00882       else if (MO.isGlobal()) {
00883         // MI can not have more than one GlobalAddress operand.
00884         assert(hasGAOpnd == false && "MI can only have one GlobalAddress opnd");
00885 
00886         // There is no member function called "ChangeToGlobalAddress" in the
00887         // MachineOperand class (not like "ChangeToRegister" and
00888         // "ChangeToImmediate"). So we have to remove them from Operands[] list
00889         // first, and then add them back after we have inserted the predicate
00890         // operand. tmpOpnds[] is to remember these operands before we remove
00891         // them.
00892         tmpOpnds.push_back(MO);
00893 
00894         // Operands[oper] is a GlobalAddress operand;
00895         // Operands[oper+1] has been copied into Operands[oper+2];
00896         hasGAOpnd = true;
00897         GAIdx = oper;
00898         continue;
00899       }
00900       else {
00901         assert(false && "Unexpected operand type");
00902       }
00903     }
00904   }
00905 
00906   int regPos = invertJump ? 1 : 0;
00907   MachineOperand PredMO = Cond[regPos];
00908 
00909   // [oper] now points to the last explicit Def. Predicate operand must be
00910   // located at [oper+1]. See diagram above.
00911   // This assumes that the predicate is always the first operand,
00912   // i.e. Operands[0+numResults], in the set of inputs
00913   // It is better to have an assert here to check this. But I don't know how
00914   // to write this assert because findFirstPredOperandIdx() would return -1
00915   if (oper < -1) oper = -1;
00916 
00917   MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
00918                                           PredMO.isImplicit(), false,
00919                                           PredMO.isDead(), PredMO.isUndef(),
00920                                           PredMO.isDebug());
00921 
00922   MachineRegisterInfo &RegInfo = MI->getParent()->getParent()->getRegInfo();
00923   RegInfo.clearKillFlags(PredMO.getReg());
00924 
00925   if (hasGAOpnd)
00926   {
00927     unsigned int i;
00928 
00929     // Operands[GAIdx] is the original GlobalAddress operand, which is
00930     // already copied into tmpOpnds[0].
00931     // Operands[GAIdx] now stores a copy of Operands[GAIdx-1]
00932     // Operands[GAIdx+1] has already been copied into Operands[GAIdx+2],
00933     // so we start from [GAIdx+2]
00934     for (i = GAIdx + 2; i < MI->getNumOperands(); ++i)
00935       tmpOpnds.push_back(MI->getOperand(i));
00936 
00937     // Remove all operands in range [ (GAIdx+1) ... (MI->getNumOperands()-1) ]
00938     // It is very important that we always remove from the end of Operands[]
00939     // MI->getNumOperands() is at least 2 if program goes to here.
00940     for (i = MI->getNumOperands() - 1; i > GAIdx; --i)
00941       MI->RemoveOperand(i);
00942 
00943     for (i = 0; i < tmpOpnds.size(); ++i)
00944       MI->addOperand(tmpOpnds[i]);
00945   }
00946 
00947   return true;
00948 }
00949 
00950 
00951 bool
00952 HexagonInstrInfo::
00953 isProfitableToIfCvt(MachineBasicBlock &MBB,
00954                     unsigned NumCycles,
00955                     unsigned ExtraPredCycles,
00956                     const BranchProbability &Probability) const {
00957   return true;
00958 }
00959 
00960 
00961 bool
00962 HexagonInstrInfo::
00963 isProfitableToIfCvt(MachineBasicBlock &TMBB,
00964                     unsigned NumTCycles,
00965                     unsigned ExtraTCycles,
00966                     MachineBasicBlock &FMBB,
00967                     unsigned NumFCycles,
00968                     unsigned ExtraFCycles,
00969                     const BranchProbability &Probability) const {
00970   return true;
00971 }
00972 
00973 // Returns true if an instruction is predicated irrespective of the predicate
00974 // sense. For example, all of the following will return true.
00975 // if (p0) R1 = add(R2, R3)
00976 // if (!p0) R1 = add(R2, R3)
00977 // if (p0.new) R1 = add(R2, R3)
00978 // if (!p0.new) R1 = add(R2, R3)
00979 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
00980   const uint64_t F = MI->getDesc().TSFlags;
00981 
00982   return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
00983 }
00984 
00985 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
00986   const uint64_t F = get(Opcode).TSFlags;
00987 
00988   return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
00989 }
00990 
00991 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
00992   const uint64_t F = MI->getDesc().TSFlags;
00993 
00994   assert(isPredicated(MI));
00995   return (!((F >> HexagonII::PredicatedFalsePos) &
00996             HexagonII::PredicatedFalseMask));
00997 }
00998 
00999 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
01000   const uint64_t F = get(Opcode).TSFlags;
01001 
01002   // Make sure that the instruction is predicated.
01003   assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
01004   return (!((F >> HexagonII::PredicatedFalsePos) &
01005             HexagonII::PredicatedFalseMask));
01006 }
01007 
01008 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
01009   const uint64_t F = MI->getDesc().TSFlags;
01010 
01011   assert(isPredicated(MI));
01012   return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
01013 }
01014 
01015 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
01016   const uint64_t F = get(Opcode).TSFlags;
01017 
01018   assert(isPredicated(Opcode));
01019   return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
01020 }
01021 
01022 // Returns true, if a ST insn can be promoted to a new-value store.
01023 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const {
01024   const HexagonRegisterInfo& QRI = getRegisterInfo();
01025   const uint64_t F = MI->getDesc().TSFlags;
01026 
01027   return ((F >> HexagonII::mayNVStorePos) &
01028            HexagonII::mayNVStoreMask &
01029            QRI.Subtarget.hasV4TOps());
01030 }
01031 
01032 bool
01033 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
01034                                    std::vector<MachineOperand> &Pred) const {
01035   for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
01036     MachineOperand MO = MI->getOperand(oper);
01037     if (MO.isReg() && MO.isDef()) {
01038       const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
01039       if (RC == &Hexagon::PredRegsRegClass) {
01040         Pred.push_back(MO);
01041         return true;
01042       }
01043     }
01044   }
01045   return false;
01046 }
01047 
01048 
01049 bool
01050 HexagonInstrInfo::
01051 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
01052                   const SmallVectorImpl<MachineOperand> &Pred2) const {
01053   // TODO: Fix this
01054   return false;
01055 }
01056 
01057 
01058 //
01059 // We indicate that we want to reverse the branch by
01060 // inserting a 0 at the beginning of the Cond vector.
01061 //
01062 bool HexagonInstrInfo::
01063 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
01064   if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
01065     Cond.erase(Cond.begin());
01066   } else {
01067     Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
01068   }
01069   return false;
01070 }
01071 
01072 
01073 bool HexagonInstrInfo::
01074 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
01075                           const BranchProbability &Probability) const {
01076   return (NumInstrs <= 4);
01077 }
01078 
01079 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
01080   switch (MI->getOpcode()) {
01081   default: return false;
01082   case Hexagon::DEALLOC_RET_V4 :
01083   case Hexagon::DEALLOC_RET_cPt_V4 :
01084   case Hexagon::DEALLOC_RET_cNotPt_V4 :
01085   case Hexagon::DEALLOC_RET_cdnPnt_V4 :
01086   case Hexagon::DEALLOC_RET_cNotdnPnt_V4 :
01087   case Hexagon::DEALLOC_RET_cdnPt_V4 :
01088   case Hexagon::DEALLOC_RET_cNotdnPt_V4 :
01089    return true;
01090   }
01091 }
01092 
01093 
01094 bool HexagonInstrInfo::
01095 isValidOffset(const int Opcode, const int Offset) const {
01096   // This function is to check whether the "Offset" is in the correct range of
01097   // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
01098   // inserted to calculate the final address. Due to this reason, the function
01099   // assumes that the "Offset" has correct alignment.
01100   // We used to assert if the offset was not properly aligned, however,
01101   // there are cases where a misaligned pointer recast can cause this
01102   // problem, and we need to allow for it. The front end warns of such
01103   // misaligns with respect to load size.
01104 
01105   switch(Opcode) {
01106 
01107   case Hexagon::LDriw:
01108   case Hexagon::LDriw_indexed:
01109   case Hexagon::LDriw_f:
01110   case Hexagon::STriw_indexed:
01111   case Hexagon::STriw:
01112   case Hexagon::STriw_f:
01113     return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
01114       (Offset <= Hexagon_MEMW_OFFSET_MAX);
01115 
01116   case Hexagon::LDrid:
01117   case Hexagon::LDrid_indexed:
01118   case Hexagon::LDrid_f:
01119   case Hexagon::STrid:
01120   case Hexagon::STrid_indexed:
01121   case Hexagon::STrid_f:
01122     return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
01123       (Offset <= Hexagon_MEMD_OFFSET_MAX);
01124 
01125   case Hexagon::LDrih:
01126   case Hexagon::LDriuh:
01127   case Hexagon::STrih:
01128     return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
01129       (Offset <= Hexagon_MEMH_OFFSET_MAX);
01130 
01131   case Hexagon::LDrib:
01132   case Hexagon::STrib:
01133   case Hexagon::LDriub:
01134     return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
01135       (Offset <= Hexagon_MEMB_OFFSET_MAX);
01136 
01137   case Hexagon::ADD_ri:
01138   case Hexagon::TFR_FI:
01139     return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
01140       (Offset <= Hexagon_ADDI_OFFSET_MAX);
01141 
01142   case Hexagon::MemOPw_ADDi_V4 :
01143   case Hexagon::MemOPw_SUBi_V4 :
01144   case Hexagon::MemOPw_ADDr_V4 :
01145   case Hexagon::MemOPw_SUBr_V4 :
01146   case Hexagon::MemOPw_ANDr_V4 :
01147   case Hexagon::MemOPw_ORr_V4 :
01148     return (0 <= Offset && Offset <= 255);
01149 
01150   case Hexagon::MemOPh_ADDi_V4 :
01151   case Hexagon::MemOPh_SUBi_V4 :
01152   case Hexagon::MemOPh_ADDr_V4 :
01153   case Hexagon::MemOPh_SUBr_V4 :
01154   case Hexagon::MemOPh_ANDr_V4 :
01155   case Hexagon::MemOPh_ORr_V4 :
01156     return (0 <= Offset && Offset <= 127);
01157 
01158   case Hexagon::MemOPb_ADDi_V4 :
01159   case Hexagon::MemOPb_SUBi_V4 :
01160   case Hexagon::MemOPb_ADDr_V4 :
01161   case Hexagon::MemOPb_SUBr_V4 :
01162   case Hexagon::MemOPb_ANDr_V4 :
01163   case Hexagon::MemOPb_ORr_V4 :
01164     return (0 <= Offset && Offset <= 63);
01165 
01166   // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
01167   // any size. Later pass knows how to handle it.
01168   case Hexagon::STriw_pred:
01169   case Hexagon::LDriw_pred:
01170     return true;
01171 
01172   case Hexagon::LOOP0_i:
01173     return isUInt<10>(Offset);
01174 
01175   // INLINEASM is very special.
01176   case Hexagon::INLINEASM:
01177     return true;
01178   }
01179 
01180   llvm_unreachable("No offset range is defined for this opcode. "
01181                    "Please define it in the above switch statement!");
01182 }
01183 
01184 
01185 //
01186 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
01187 //
01188 bool HexagonInstrInfo::
01189 isValidAutoIncImm(const EVT VT, const int Offset) const {
01190 
01191   if (VT == MVT::i64) {
01192       return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
01193               Offset <= Hexagon_MEMD_AUTOINC_MAX &&
01194               (Offset & 0x7) == 0);
01195   }
01196   if (VT == MVT::i32) {
01197       return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
01198               Offset <= Hexagon_MEMW_AUTOINC_MAX &&
01199               (Offset & 0x3) == 0);
01200   }
01201   if (VT == MVT::i16) {
01202       return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
01203               Offset <= Hexagon_MEMH_AUTOINC_MAX &&
01204               (Offset & 0x1) == 0);
01205   }
01206   if (VT == MVT::i8) {
01207       return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
01208               Offset <= Hexagon_MEMB_AUTOINC_MAX);
01209   }
01210   llvm_unreachable("Not an auto-inc opc!");
01211 }
01212 
01213 
01214 bool HexagonInstrInfo::
01215 isMemOp(const MachineInstr *MI) const {
01216 //  return MI->getDesc().mayLoad() && MI->getDesc().mayStore();
01217 
01218   switch (MI->getOpcode())
01219   {
01220     default: return false;
01221     case Hexagon::MemOPw_ADDi_V4 :
01222     case Hexagon::MemOPw_SUBi_V4 :
01223     case Hexagon::MemOPw_ADDr_V4 :
01224     case Hexagon::MemOPw_SUBr_V4 :
01225     case Hexagon::MemOPw_ANDr_V4 :
01226     case Hexagon::MemOPw_ORr_V4 :
01227     case Hexagon::MemOPh_ADDi_V4 :
01228     case Hexagon::MemOPh_SUBi_V4 :
01229     case Hexagon::MemOPh_ADDr_V4 :
01230     case Hexagon::MemOPh_SUBr_V4 :
01231     case Hexagon::MemOPh_ANDr_V4 :
01232     case Hexagon::MemOPh_ORr_V4 :
01233     case Hexagon::MemOPb_ADDi_V4 :
01234     case Hexagon::MemOPb_SUBi_V4 :
01235     case Hexagon::MemOPb_ADDr_V4 :
01236     case Hexagon::MemOPb_SUBr_V4 :
01237     case Hexagon::MemOPb_ANDr_V4 :
01238     case Hexagon::MemOPb_ORr_V4 :
01239     case Hexagon::MemOPb_SETBITi_V4:
01240     case Hexagon::MemOPh_SETBITi_V4:
01241     case Hexagon::MemOPw_SETBITi_V4:
01242     case Hexagon::MemOPb_CLRBITi_V4:
01243     case Hexagon::MemOPh_CLRBITi_V4:
01244     case Hexagon::MemOPw_CLRBITi_V4:
01245     return true;
01246   }
01247   return false;
01248 }
01249 
01250 
01251 bool HexagonInstrInfo::
01252 isSpillPredRegOp(const MachineInstr *MI) const {
01253   switch (MI->getOpcode()) {
01254     default: return false;
01255     case Hexagon::STriw_pred :
01256     case Hexagon::LDriw_pred :
01257       return true;
01258   }
01259 }
01260 
01261 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
01262   switch (MI->getOpcode()) {
01263     default: return false;
01264     case Hexagon::CMPEQrr:
01265     case Hexagon::CMPEQri:
01266     case Hexagon::CMPGTrr:
01267     case Hexagon::CMPGTri:
01268     case Hexagon::CMPGTUrr:
01269     case Hexagon::CMPGTUri:
01270       return true;
01271   }
01272 }
01273 
01274 bool HexagonInstrInfo::
01275 isConditionalTransfer (const MachineInstr *MI) const {
01276   switch (MI->getOpcode()) {
01277     default: return false;
01278     case Hexagon::TFR_cPt:
01279     case Hexagon::TFR_cNotPt:
01280     case Hexagon::TFRI_cPt:
01281     case Hexagon::TFRI_cNotPt:
01282     case Hexagon::TFR_cdnPt:
01283     case Hexagon::TFR_cdnNotPt:
01284     case Hexagon::TFRI_cdnPt:
01285     case Hexagon::TFRI_cdnNotPt:
01286       return true;
01287   }
01288 }
01289 
01290 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
01291   const HexagonRegisterInfo& QRI = getRegisterInfo();
01292   switch (MI->getOpcode())
01293   {
01294     default: return false;
01295     case Hexagon::ADD_ri_cPt:
01296     case Hexagon::ADD_ri_cNotPt:
01297     case Hexagon::ADD_rr_cPt:
01298     case Hexagon::ADD_rr_cNotPt:
01299     case Hexagon::XOR_rr_cPt:
01300     case Hexagon::XOR_rr_cNotPt:
01301     case Hexagon::AND_rr_cPt:
01302     case Hexagon::AND_rr_cNotPt:
01303     case Hexagon::OR_rr_cPt:
01304     case Hexagon::OR_rr_cNotPt:
01305     case Hexagon::SUB_rr_cPt:
01306     case Hexagon::SUB_rr_cNotPt:
01307     case Hexagon::COMBINE_rr_cPt:
01308     case Hexagon::COMBINE_rr_cNotPt:
01309       return true;
01310     case Hexagon::ASLH_cPt_V4:
01311     case Hexagon::ASLH_cNotPt_V4:
01312     case Hexagon::ASRH_cPt_V4:
01313     case Hexagon::ASRH_cNotPt_V4:
01314     case Hexagon::SXTB_cPt_V4:
01315     case Hexagon::SXTB_cNotPt_V4:
01316     case Hexagon::SXTH_cPt_V4:
01317     case Hexagon::SXTH_cNotPt_V4:
01318     case Hexagon::ZXTB_cPt_V4:
01319     case Hexagon::ZXTB_cNotPt_V4:
01320     case Hexagon::ZXTH_cPt_V4:
01321     case Hexagon::ZXTH_cNotPt_V4:
01322       return QRI.Subtarget.hasV4TOps();
01323   }
01324 }
01325 
01326 bool HexagonInstrInfo::
01327 isConditionalLoad (const MachineInstr* MI) const {
01328   const HexagonRegisterInfo& QRI = getRegisterInfo();
01329   switch (MI->getOpcode())
01330   {
01331     default: return false;
01332     case Hexagon::LDrid_cPt :
01333     case Hexagon::LDrid_cNotPt :
01334     case Hexagon::LDrid_indexed_cPt :
01335     case Hexagon::LDrid_indexed_cNotPt :
01336     case Hexagon::LDriw_cPt :
01337     case Hexagon::LDriw_cNotPt :
01338     case Hexagon::LDriw_indexed_cPt :
01339     case Hexagon::LDriw_indexed_cNotPt :
01340     case Hexagon::LDrih_cPt :
01341     case Hexagon::LDrih_cNotPt :
01342     case Hexagon::LDrih_indexed_cPt :
01343     case Hexagon::LDrih_indexed_cNotPt :
01344     case Hexagon::LDrib_cPt :
01345     case Hexagon::LDrib_cNotPt :
01346     case Hexagon::LDrib_indexed_cPt :
01347     case Hexagon::LDrib_indexed_cNotPt :
01348     case Hexagon::LDriuh_cPt :
01349     case Hexagon::LDriuh_cNotPt :
01350     case Hexagon::LDriuh_indexed_cPt :
01351     case Hexagon::LDriuh_indexed_cNotPt :
01352     case Hexagon::LDriub_cPt :
01353     case Hexagon::LDriub_cNotPt :
01354     case Hexagon::LDriub_indexed_cPt :
01355     case Hexagon::LDriub_indexed_cNotPt :
01356       return true;
01357     case Hexagon::POST_LDrid_cPt :
01358     case Hexagon::POST_LDrid_cNotPt :
01359     case Hexagon::POST_LDriw_cPt :
01360     case Hexagon::POST_LDriw_cNotPt :
01361     case Hexagon::POST_LDrih_cPt :
01362     case Hexagon::POST_LDrih_cNotPt :
01363     case Hexagon::POST_LDrib_cPt :
01364     case Hexagon::POST_LDrib_cNotPt :
01365     case Hexagon::POST_LDriuh_cPt :
01366     case Hexagon::POST_LDriuh_cNotPt :
01367     case Hexagon::POST_LDriub_cPt :
01368     case Hexagon::POST_LDriub_cNotPt :
01369       return QRI.Subtarget.hasV4TOps();
01370     case Hexagon::LDrid_indexed_shl_cPt_V4 :
01371     case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
01372     case Hexagon::LDrib_indexed_shl_cPt_V4 :
01373     case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
01374     case Hexagon::LDriub_indexed_shl_cPt_V4 :
01375     case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
01376     case Hexagon::LDrih_indexed_shl_cPt_V4 :
01377     case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
01378     case Hexagon::LDriuh_indexed_shl_cPt_V4 :
01379     case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
01380     case Hexagon::LDriw_indexed_shl_cPt_V4 :
01381     case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
01382       return QRI.Subtarget.hasV4TOps();
01383   }
01384 }
01385 
01386 // Returns true if an instruction is a conditional store.
01387 //
01388 // Note: It doesn't include conditional new-value stores as they can't be
01389 // converted to .new predicate.
01390 //
01391 //               p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
01392 //                ^           ^
01393 //               /             \ (not OK. it will cause new-value store to be
01394 //              /               X conditional on p0.new while R2 producer is
01395 //             /                 \ on p0)
01396 //            /                   \.
01397 //     p.new store                 p.old NV store
01398 // [if(p0.new)memw(R0+#0)=R2]    [if(p0)memw(R0+#0)=R2.new]
01399 //            ^                  ^
01400 //             \                /
01401 //              \              /
01402 //               \            /
01403 //                 p.old store
01404 //             [if (p0)memw(R0+#0)=R2]
01405 //
01406 // The above diagram shows the steps involoved in the conversion of a predicated
01407 // store instruction to its .new predicated new-value form.
01408 //
01409 // The following set of instructions further explains the scenario where
01410 // conditional new-value store becomes invalid when promoted to .new predicate
01411 // form.
01412 //
01413 // { 1) if (p0) r0 = add(r1, r2)
01414 //   2) p0 = cmp.eq(r3, #0) }
01415 //
01416 //   3) if (p0) memb(r1+#0) = r0  --> this instruction can't be grouped with
01417 // the first two instructions because in instr 1, r0 is conditional on old value
01418 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
01419 // is not valid for new-value stores.
01420 bool HexagonInstrInfo::
01421 isConditionalStore (const MachineInstr* MI) const {
01422   const HexagonRegisterInfo& QRI = getRegisterInfo();
01423   switch (MI->getOpcode())
01424   {
01425     default: return false;
01426     case Hexagon::STrib_imm_cPt_V4 :
01427     case Hexagon::STrib_imm_cNotPt_V4 :
01428     case Hexagon::STrib_indexed_shl_cPt_V4 :
01429     case Hexagon::STrib_indexed_shl_cNotPt_V4 :
01430     case Hexagon::STrib_cPt :
01431     case Hexagon::STrib_cNotPt :
01432     case Hexagon::POST_STbri_cPt :
01433     case Hexagon::POST_STbri_cNotPt :
01434     case Hexagon::STrid_indexed_cPt :
01435     case Hexagon::STrid_indexed_cNotPt :
01436     case Hexagon::STrid_indexed_shl_cPt_V4 :
01437     case Hexagon::POST_STdri_cPt :
01438     case Hexagon::POST_STdri_cNotPt :
01439     case Hexagon::STrih_cPt :
01440     case Hexagon::STrih_cNotPt :
01441     case Hexagon::STrih_indexed_cPt :
01442     case Hexagon::STrih_indexed_cNotPt :
01443     case Hexagon::STrih_imm_cPt_V4 :
01444     case Hexagon::STrih_imm_cNotPt_V4 :
01445     case Hexagon::STrih_indexed_shl_cPt_V4 :
01446     case Hexagon::STrih_indexed_shl_cNotPt_V4 :
01447     case Hexagon::POST_SThri_cPt :
01448     case Hexagon::POST_SThri_cNotPt :
01449     case Hexagon::STriw_cPt :
01450     case Hexagon::STriw_cNotPt :
01451     case Hexagon::STriw_indexed_cPt :
01452     case Hexagon::STriw_indexed_cNotPt :
01453     case Hexagon::STriw_imm_cPt_V4 :
01454     case Hexagon::STriw_imm_cNotPt_V4 :
01455     case Hexagon::STriw_indexed_shl_cPt_V4 :
01456     case Hexagon::STriw_indexed_shl_cNotPt_V4 :
01457     case Hexagon::POST_STwri_cPt :
01458     case Hexagon::POST_STwri_cNotPt :
01459       return QRI.Subtarget.hasV4TOps();
01460 
01461     // V4 global address store before promoting to dot new.
01462     case Hexagon::STd_GP_cPt_V4 :
01463     case Hexagon::STd_GP_cNotPt_V4 :
01464     case Hexagon::STb_GP_cPt_V4 :
01465     case Hexagon::STb_GP_cNotPt_V4 :
01466     case Hexagon::STh_GP_cPt_V4 :
01467     case Hexagon::STh_GP_cNotPt_V4 :
01468     case Hexagon::STw_GP_cPt_V4 :
01469     case Hexagon::STw_GP_cNotPt_V4 :
01470       return QRI.Subtarget.hasV4TOps();
01471 
01472     // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
01473     // from the "Conditional Store" list. Because a predicated new value store
01474     // would NOT be promoted to a double dot new store. See diagram below:
01475     // This function returns yes for those stores that are predicated but not
01476     // yet promoted to predicate dot new instructions.
01477     //
01478     //                          +---------------------+
01479     //                    /-----| if (p0) memw(..)=r0 |---------\~
01480     //                   ||     +---------------------+         ||
01481     //          promote  ||       /\       /\                   ||  promote
01482     //                   ||      /||\     /||\                  ||
01483     //                  \||/    demote     ||                  \||/
01484     //                   \/       ||       ||                   \/
01485     //       +-------------------------+   ||   +-------------------------+
01486     //       | if (p0.new) memw(..)=r0 |   ||   | if (p0) memw(..)=r0.new |
01487     //       +-------------------------+   ||   +-------------------------+
01488     //                        ||           ||         ||
01489     //                        ||         demote      \||/
01490     //                      promote        ||         \/ NOT possible
01491     //                        ||           ||         /\~
01492     //                       \||/          ||        /||\~
01493     //                        \/           ||         ||
01494     //                      +-----------------------------+
01495     //                      | if (p0.new) memw(..)=r0.new |
01496     //                      +-----------------------------+
01497     //                           Double Dot New Store
01498     //
01499   }
01500 }
01501 
01502 
01503 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
01504   if (isNewValue(MI) && isBranch(MI))
01505     return true;
01506   return false;
01507 }
01508 
01509 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
01510   return (getAddrMode(MI) == HexagonII::PostInc);
01511 }
01512 
01513 bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
01514   const uint64_t F = MI->getDesc().TSFlags;
01515   return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
01516 }
01517 
01518 // Returns true, if any one of the operands is a dot new
01519 // insn, whether it is predicated dot new or register dot new.
01520 bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
01521   return (isNewValueInst(MI) ||
01522      (isPredicated(MI) && isPredicatedNew(MI)));
01523 }
01524 
01525 // Returns the most basic instruction for the .new predicated instructions and
01526 // new-value stores.
01527 // For example, all of the following instructions will be converted back to the
01528 // same instruction:
01529 // 1) if (p0.new) memw(R0+#0) = R1.new  --->
01530 // 2) if (p0) memw(R0+#0)= R1.new      -------> if (p0) memw(R0+#0) = R1
01531 // 3) if (p0.new) memw(R0+#0) = R1      --->
01532 //
01533 
01534 int HexagonInstrInfo::GetDotOldOp(const int opc) const {
01535   int NewOp = opc;
01536   if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
01537     NewOp = Hexagon::getPredOldOpcode(NewOp);
01538     if (NewOp < 0)
01539       assert(0 && "Couldn't change predicate new instruction to its old form.");
01540   }
01541 
01542   if (isNewValueStore(NewOp)) { // Convert into non-new-value format
01543     NewOp = Hexagon::getNonNVStore(NewOp);
01544     if (NewOp < 0)
01545       assert(0 && "Couldn't change new-value store to its old form.");
01546   }
01547   return NewOp;
01548 }
01549 
01550 // Return the new value instruction for a given store.
01551 int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const {
01552   int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
01553   if (NVOpcode >= 0) // Valid new-value store instruction.
01554     return NVOpcode;
01555 
01556   switch (MI->getOpcode()) {
01557   default: llvm_unreachable("Unknown .new type");
01558   // store new value byte
01559   case Hexagon::STrib_shl_V4:
01560     return Hexagon::STrib_shl_nv_V4;
01561 
01562   case Hexagon::STrih_shl_V4:
01563     return Hexagon::STrih_shl_nv_V4;
01564 
01565   case Hexagon::STriw_f:
01566     return Hexagon::STriw_nv_V4;
01567 
01568   case Hexagon::STriw_indexed_f:
01569     return Hexagon::STriw_indexed_nv_V4;
01570 
01571   case Hexagon::STriw_shl_V4:
01572     return Hexagon::STriw_shl_nv_V4;
01573 
01574   }
01575   return 0;
01576 }
01577 
01578 // Return .new predicate version for an instruction.
01579 int HexagonInstrInfo::GetDotNewPredOp(MachineInstr *MI,
01580                                       const MachineBranchProbabilityInfo
01581                                       *MBPI) const {
01582 
01583   int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
01584   if (NewOpcode >= 0) // Valid predicate new instruction
01585     return NewOpcode;
01586 
01587   switch (MI->getOpcode()) {
01588   default: llvm_unreachable("Unknown .new type");
01589   // Condtional Jumps
01590   case Hexagon::JMP_t:
01591   case Hexagon::JMP_f:
01592     return getDotNewPredJumpOp(MI, MBPI);
01593 
01594   case Hexagon::JMPR_t:
01595     return Hexagon::JMPR_tnew_tV3;
01596 
01597   case Hexagon::JMPR_f:
01598     return Hexagon::JMPR_fnew_tV3;
01599 
01600   case Hexagon::JMPret_t:
01601     return Hexagon::JMPret_tnew_tV3;
01602 
01603   case Hexagon::JMPret_f:
01604     return Hexagon::JMPret_fnew_tV3;
01605 
01606 
01607   // Conditional combine
01608   case Hexagon::COMBINE_rr_cPt :
01609     return Hexagon::COMBINE_rr_cdnPt;
01610   case Hexagon::COMBINE_rr_cNotPt :
01611     return Hexagon::COMBINE_rr_cdnNotPt;
01612   }
01613 }
01614 
01615 
01616 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
01617   const uint64_t F = MI->getDesc().TSFlags;
01618 
01619   return((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
01620 }
01621 
01622 /// immediateExtend - Changes the instruction in place to one using an immediate
01623 /// extender.
01624 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
01625   assert((isExtendable(MI)||isConstExtended(MI)) &&
01626                                "Instruction must be extendable");
01627   // Find which operand is extendable.
01628   short ExtOpNum = getCExtOpNum(MI);
01629   MachineOperand &MO = MI->getOperand(ExtOpNum);
01630   // This needs to be something we understand.
01631   assert((MO.isMBB() || MO.isImm()) &&
01632          "Branch with unknown extendable field type");
01633   // Mark given operand as extended.
01634   MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
01635 }
01636 
01637 DFAPacketizer *HexagonInstrInfo::
01638 CreateTargetScheduleState(const TargetMachine *TM,
01639                            const ScheduleDAG *DAG) const {
01640   const InstrItineraryData *II = TM->getInstrItineraryData();
01641   return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II);
01642 }
01643 
01644 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
01645                                             const MachineBasicBlock *MBB,
01646                                             const MachineFunction &MF) const {
01647   // Debug info is never a scheduling boundary. It's necessary to be explicit
01648   // due to the special treatment of IT instructions below, otherwise a
01649   // dbg_value followed by an IT will result in the IT instruction being
01650   // considered a scheduling hazard, which is wrong. It should be the actual
01651   // instruction preceding the dbg_value instruction(s), just like it is
01652   // when debug info is not present.
01653   if (MI->isDebugValue())
01654     return false;
01655 
01656   // Terminators and labels can't be scheduled around.
01657   if (MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm())
01658     return true;
01659 
01660   return false;
01661 }
01662 
01663 bool HexagonInstrInfo::isConstExtended(MachineInstr *MI) const {
01664 
01665   // Constant extenders are allowed only for V4 and above.
01666   if (!Subtarget.hasV4TOps())
01667     return false;
01668 
01669   const uint64_t F = MI->getDesc().TSFlags;
01670   unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
01671   if (isExtended) // Instruction must be extended.
01672     return true;
01673 
01674   unsigned isExtendable = (F >> HexagonII::ExtendablePos)
01675                           & HexagonII::ExtendableMask;
01676   if (!isExtendable)
01677     return false;
01678 
01679   short ExtOpNum = getCExtOpNum(MI);
01680   const MachineOperand &MO = MI->getOperand(ExtOpNum);
01681   // Use MO operand flags to determine if MO
01682   // has the HMOTF_ConstExtended flag set.
01683   if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
01684     return true;
01685   // If this is a Machine BB address we are talking about, and it is
01686   // not marked as extended, say so.
01687   if (MO.isMBB())
01688     return false;
01689 
01690   // We could be using an instruction with an extendable immediate and shoehorn
01691   // a global address into it. If it is a global address it will be constant
01692   // extended. We do this for COMBINE.
01693   // We currently only handle isGlobal() because it is the only kind of
01694   // object we are going to end up with here for now.
01695   // In the future we probably should add isSymbol(), etc.
01696   if (MO.isGlobal() || MO.isSymbol())
01697     return true;
01698 
01699   // If the extendable operand is not 'Immediate' type, the instruction should
01700   // have 'isExtended' flag set.
01701   assert(MO.isImm() && "Extendable operand must be Immediate type");
01702 
01703   int MinValue = getMinValue(MI);
01704   int MaxValue = getMaxValue(MI);
01705   int ImmValue = MO.getImm();
01706 
01707   return (ImmValue < MinValue || ImmValue > MaxValue);
01708 }
01709 
01710 // Returns the opcode to use when converting MI, which is a conditional jump,
01711 // into a conditional instruction which uses the .new value of the predicate.
01712 // We also use branch probabilities to add a hint to the jump.
01713 int
01714 HexagonInstrInfo::getDotNewPredJumpOp(MachineInstr *MI,
01715                                   const
01716                                   MachineBranchProbabilityInfo *MBPI) const {
01717 
01718   // We assume that block can have at most two successors.
01719   bool taken = false;
01720   MachineBasicBlock *Src = MI->getParent();
01721   MachineOperand *BrTarget = &MI->getOperand(1);
01722   MachineBasicBlock *Dst = BrTarget->getMBB();
01723 
01724   const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
01725   if (Prediction >= BranchProbability(1,2))
01726     taken = true;
01727 
01728   switch (MI->getOpcode()) {
01729   case Hexagon::JMP_t:
01730     return taken ? Hexagon::JMP_tnew_t : Hexagon::JMP_tnew_nt;
01731   case Hexagon::JMP_f:
01732     return taken ? Hexagon::JMP_fnew_t : Hexagon::JMP_fnew_nt;
01733 
01734   default:
01735     llvm_unreachable("Unexpected jump instruction.");
01736   }
01737 }
01738 // Returns true if a particular operand is extendable for an instruction.
01739 bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
01740                                          unsigned short OperandNum) const {
01741   // Constant extenders are allowed only for V4 and above.
01742   if (!Subtarget.hasV4TOps())
01743     return false;
01744 
01745   const uint64_t F = MI->getDesc().TSFlags;
01746 
01747   return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
01748           == OperandNum;
01749 }
01750 
01751 // Returns Operand Index for the constant extended instruction.
01752 unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
01753   const uint64_t F = MI->getDesc().TSFlags;
01754   return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
01755 }
01756 
01757 // Returns the min value that doesn't need to be extended.
01758 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
01759   const uint64_t F = MI->getDesc().TSFlags;
01760   unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
01761                     & HexagonII::ExtentSignedMask;
01762   unsigned bits =  (F >> HexagonII::ExtentBitsPos)
01763                     & HexagonII::ExtentBitsMask;
01764 
01765   if (isSigned) // if value is signed
01766     return -1 << (bits - 1);
01767   else
01768     return 0;
01769 }
01770 
01771 // Returns the max value that doesn't need to be extended.
01772 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
01773   const uint64_t F = MI->getDesc().TSFlags;
01774   unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
01775                     & HexagonII::ExtentSignedMask;
01776   unsigned bits =  (F >> HexagonII::ExtentBitsPos)
01777                     & HexagonII::ExtentBitsMask;
01778 
01779   if (isSigned) // if value is signed
01780     return ~(-1 << (bits - 1));
01781   else
01782     return ~(-1 << bits);
01783 }
01784 
01785 // Returns true if an instruction can be converted into a non-extended
01786 // equivalent instruction.
01787 bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr *MI) const {
01788 
01789   short NonExtOpcode;
01790   // Check if the instruction has a register form that uses register in place
01791   // of the extended operand, if so return that as the non-extended form.
01792   if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
01793     return true;
01794 
01795   if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
01796     // Check addressing mode and retrieve non-ext equivalent instruction.
01797 
01798     switch (getAddrMode(MI)) {
01799     case HexagonII::Absolute :
01800       // Load/store with absolute addressing mode can be converted into
01801       // base+offset mode.
01802       NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode());
01803       break;
01804     case HexagonII::BaseImmOffset :
01805       // Load/store with base+offset addressing mode can be converted into
01806       // base+register offset addressing mode. However left shift operand should
01807       // be set to 0.
01808       NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
01809       break;
01810     default:
01811       return false;
01812     }
01813     if (NonExtOpcode < 0)
01814       return false;
01815     return true;
01816   }
01817   return false;
01818 }
01819 
01820 // Returns opcode of the non-extended equivalent instruction.
01821 short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const {
01822 
01823   // Check if the instruction has a register form that uses register in place
01824   // of the extended operand, if so return that as the non-extended form.
01825   short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
01826     if (NonExtOpcode >= 0)
01827       return NonExtOpcode;
01828 
01829   if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
01830     // Check addressing mode and retrieve non-ext equivalent instruction.
01831     switch (getAddrMode(MI)) {
01832     case HexagonII::Absolute :
01833       return Hexagon::getBasedWithImmOffset(MI->getOpcode());
01834     case HexagonII::BaseImmOffset :
01835       return Hexagon::getBaseWithRegOffset(MI->getOpcode());
01836     default:
01837       return -1;
01838     }
01839   }
01840   return -1;
01841 }
01842 
01843 bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode) const {
01844   return (Opcode == Hexagon::JMP_t) ||
01845          (Opcode == Hexagon::JMP_f) ||
01846          (Opcode == Hexagon::JMP_tnew_t) ||
01847          (Opcode == Hexagon::JMP_fnew_t) ||
01848          (Opcode == Hexagon::JMP_tnew_nt) ||
01849          (Opcode == Hexagon::JMP_fnew_nt);
01850 }
01851 
01852 bool HexagonInstrInfo::PredOpcodeHasNot(Opcode_t Opcode) const {
01853   return (Opcode == Hexagon::JMP_f) ||
01854          (Opcode == Hexagon::JMP_fnew_t) ||
01855          (Opcode == Hexagon::JMP_fnew_nt);
01856 }