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HexagonInstrInfo.cpp
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00001 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the Hexagon implementation of the TargetInstrInfo class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "HexagonInstrInfo.h"
00015 #include "Hexagon.h"
00016 #include "HexagonRegisterInfo.h"
00017 #include "HexagonSubtarget.h"
00018 #include "llvm/ADT/STLExtras.h"
00019 #include "llvm/ADT/SmallVector.h"
00020 #include "llvm/CodeGen/DFAPacketizer.h"
00021 #include "llvm/CodeGen/MachineFrameInfo.h"
00022 #include "llvm/CodeGen/MachineInstrBuilder.h"
00023 #include "llvm/CodeGen/MachineMemOperand.h"
00024 #include "llvm/CodeGen/MachineRegisterInfo.h"
00025 #include "llvm/CodeGen/PseudoSourceValue.h"
00026 #include "llvm/Support/Debug.h"
00027 #include "llvm/Support/MathExtras.h"
00028 #include "llvm/Support/raw_ostream.h"
00029 
00030 using namespace llvm;
00031 
00032 #define DEBUG_TYPE "hexagon-instrinfo"
00033 
00034 #define GET_INSTRINFO_CTOR_DTOR
00035 #define GET_INSTRMAP_INFO
00036 #include "HexagonGenInstrInfo.inc"
00037 #include "HexagonGenDFAPacketizer.inc"
00038 
00039 ///
00040 /// Constants for Hexagon instructions.
00041 ///
00042 const int Hexagon_MEMW_OFFSET_MAX = 4095;
00043 const int Hexagon_MEMW_OFFSET_MIN = -4096;
00044 const int Hexagon_MEMD_OFFSET_MAX = 8191;
00045 const int Hexagon_MEMD_OFFSET_MIN = -8192;
00046 const int Hexagon_MEMH_OFFSET_MAX = 2047;
00047 const int Hexagon_MEMH_OFFSET_MIN = -2048;
00048 const int Hexagon_MEMB_OFFSET_MAX = 1023;
00049 const int Hexagon_MEMB_OFFSET_MIN = -1024;
00050 const int Hexagon_ADDI_OFFSET_MAX = 32767;
00051 const int Hexagon_ADDI_OFFSET_MIN = -32768;
00052 const int Hexagon_MEMD_AUTOINC_MAX = 56;
00053 const int Hexagon_MEMD_AUTOINC_MIN = -64;
00054 const int Hexagon_MEMW_AUTOINC_MAX = 28;
00055 const int Hexagon_MEMW_AUTOINC_MIN = -32;
00056 const int Hexagon_MEMH_AUTOINC_MAX = 14;
00057 const int Hexagon_MEMH_AUTOINC_MIN = -16;
00058 const int Hexagon_MEMB_AUTOINC_MAX = 7;
00059 const int Hexagon_MEMB_AUTOINC_MIN = -8;
00060 
00061 // Pin the vtable to this file.
00062 void HexagonInstrInfo::anchor() {}
00063 
00064 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
00065   : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
00066     RI(ST), Subtarget(ST) {
00067 }
00068 
00069 
00070 /// isLoadFromStackSlot - If the specified machine instruction is a direct
00071 /// load from a stack slot, return the virtual or physical register number of
00072 /// the destination along with the FrameIndex of the loaded stack slot.  If
00073 /// not, return 0.  This predicate must return 0 if the instruction has
00074 /// any side effects other than loading from the stack slot.
00075 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
00076                                              int &FrameIndex) const {
00077 
00078 
00079   switch (MI->getOpcode()) {
00080   default: break;
00081   case Hexagon::L2_loadri_io:
00082   case Hexagon::L2_loadrd_io:
00083   case Hexagon::L2_loadrh_io:
00084   case Hexagon::L2_loadrb_io:
00085   case Hexagon::L2_loadrub_io:
00086     if (MI->getOperand(2).isFI() &&
00087         MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
00088       FrameIndex = MI->getOperand(2).getIndex();
00089       return MI->getOperand(0).getReg();
00090     }
00091     break;
00092   }
00093   return 0;
00094 }
00095 
00096 
00097 /// isStoreToStackSlot - If the specified machine instruction is a direct
00098 /// store to a stack slot, return the virtual or physical register number of
00099 /// the source reg along with the FrameIndex of the loaded stack slot.  If
00100 /// not, return 0.  This predicate must return 0 if the instruction has
00101 /// any side effects other than storing to the stack slot.
00102 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
00103                                             int &FrameIndex) const {
00104   switch (MI->getOpcode()) {
00105   default: break;
00106   case Hexagon::S2_storeri_io:
00107   case Hexagon::S2_storerd_io:
00108   case Hexagon::S2_storerh_io:
00109   case Hexagon::S2_storerb_io:
00110     if (MI->getOperand(2).isFI() &&
00111         MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
00112       FrameIndex = MI->getOperand(0).getIndex();
00113       return MI->getOperand(2).getReg();
00114     }
00115     break;
00116   }
00117   return 0;
00118 }
00119 
00120 
00121 unsigned
00122 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
00123                              MachineBasicBlock *FBB,
00124                              const SmallVectorImpl<MachineOperand> &Cond,
00125                              DebugLoc DL) const{
00126 
00127     int BOpc   = Hexagon::J2_jump;
00128     int BccOpc = Hexagon::J2_jumpt;
00129 
00130     assert(TBB && "InsertBranch must not be told to insert a fallthrough");
00131 
00132     int regPos = 0;
00133     // Check if ReverseBranchCondition has asked to reverse this branch
00134     // If we want to reverse the branch an odd number of times, we want
00135     // JMP_f.
00136     if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
00137       BccOpc = Hexagon::J2_jumpf;
00138       regPos = 1;
00139     }
00140 
00141     if (!FBB) {
00142       if (Cond.empty()) {
00143         // Due to a bug in TailMerging/CFG Optimization, we need to add a
00144         // special case handling of a predicated jump followed by an
00145         // unconditional jump. If not, Tail Merging and CFG Optimization go
00146         // into an infinite loop.
00147         MachineBasicBlock *NewTBB, *NewFBB;
00148         SmallVector<MachineOperand, 4> Cond;
00149         MachineInstr *Term = MBB.getFirstTerminator();
00150         if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
00151                                                  false)) {
00152           MachineBasicBlock *NextBB =
00153             std::next(MachineFunction::iterator(&MBB));
00154           if (NewTBB == NextBB) {
00155             ReverseBranchCondition(Cond);
00156             RemoveBranch(MBB);
00157             return InsertBranch(MBB, TBB, nullptr, Cond, DL);
00158           }
00159         }
00160         BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
00161       } else {
00162         BuildMI(&MBB, DL,
00163                 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
00164       }
00165       return 1;
00166     }
00167 
00168     BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
00169     BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
00170 
00171     return 2;
00172 }
00173 
00174 
00175 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
00176                                      MachineBasicBlock *&TBB,
00177                                  MachineBasicBlock *&FBB,
00178                                  SmallVectorImpl<MachineOperand> &Cond,
00179                                  bool AllowModify) const {
00180   TBB = nullptr;
00181   FBB = nullptr;
00182 
00183   // If the block has no terminators, it just falls into the block after it.
00184   MachineBasicBlock::instr_iterator I = MBB.instr_end();
00185   if (I == MBB.instr_begin())
00186     return false;
00187 
00188   // A basic block may looks like this:
00189   //
00190   //  [   insn
00191   //     EH_LABEL
00192   //      insn
00193   //      insn
00194   //      insn
00195   //     EH_LABEL
00196   //      insn     ]
00197   //
00198   // It has two succs but does not have a terminator
00199   // Don't know how to handle it.
00200   do {
00201     --I;
00202     if (I->isEHLabel())
00203       return true;
00204   } while (I != MBB.instr_begin());
00205 
00206   I = MBB.instr_end();
00207   --I;
00208 
00209   while (I->isDebugValue()) {
00210     if (I == MBB.instr_begin())
00211       return false;
00212     --I;
00213   }
00214 
00215   // Delete the JMP if it's equivalent to a fall-through.
00216   if (AllowModify && I->getOpcode() == Hexagon::J2_jump &&
00217       MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
00218     DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
00219     I->eraseFromParent();
00220     I = MBB.instr_end();
00221     if (I == MBB.instr_begin())
00222       return false;
00223     --I;
00224   }
00225   if (!isUnpredicatedTerminator(I))
00226     return false;
00227 
00228   // Get the last instruction in the block.
00229   MachineInstr *LastInst = I;
00230   MachineInstr *SecondLastInst = nullptr;
00231   // Find one more terminator if present.
00232   do {
00233     if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(I)) {
00234       if (!SecondLastInst)
00235         SecondLastInst = I;
00236       else
00237         // This is a third branch.
00238         return true;
00239     }
00240     if (I == MBB.instr_begin())
00241       break;
00242     --I;
00243   } while(I);
00244 
00245   int LastOpcode = LastInst->getOpcode();
00246 
00247   bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
00248   bool LastOpcodeHasNot = PredOpcodeHasNot(LastOpcode);
00249 
00250   // If there is only one terminator instruction, process it.
00251   if (LastInst && !SecondLastInst) {
00252     if (LastOpcode == Hexagon::J2_jump) {
00253       TBB = LastInst->getOperand(0).getMBB();
00254       return false;
00255     }
00256     if (LastOpcode == Hexagon::ENDLOOP0) {
00257       TBB = LastInst->getOperand(0).getMBB();
00258       Cond.push_back(LastInst->getOperand(0));
00259       return false;
00260     }
00261     if (LastOpcodeHasJMP_c) {
00262       TBB = LastInst->getOperand(1).getMBB();
00263       if (LastOpcodeHasNot) {
00264         Cond.push_back(MachineOperand::CreateImm(0));
00265       }
00266       Cond.push_back(LastInst->getOperand(0));
00267       return false;
00268     }
00269     // Otherwise, don't know what this is.
00270     return true;
00271   }
00272 
00273   int SecLastOpcode = SecondLastInst->getOpcode();
00274 
00275   bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
00276   bool SecLastOpcodeHasNot = PredOpcodeHasNot(SecLastOpcode);
00277   if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
00278     TBB =  SecondLastInst->getOperand(1).getMBB();
00279     if (SecLastOpcodeHasNot)
00280       Cond.push_back(MachineOperand::CreateImm(0));
00281     Cond.push_back(SecondLastInst->getOperand(0));
00282     FBB = LastInst->getOperand(0).getMBB();
00283     return false;
00284   }
00285 
00286   // If the block ends with two Hexagon:JMPs, handle it.  The second one is not
00287   // executed, so remove it.
00288   if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
00289     TBB = SecondLastInst->getOperand(0).getMBB();
00290     I = LastInst;
00291     if (AllowModify)
00292       I->eraseFromParent();
00293     return false;
00294   }
00295 
00296   // If the block ends with an ENDLOOP, and JMP, handle it.
00297   if (SecLastOpcode == Hexagon::ENDLOOP0 &&
00298       LastOpcode == Hexagon::J2_jump) {
00299     TBB = SecondLastInst->getOperand(0).getMBB();
00300     Cond.push_back(SecondLastInst->getOperand(0));
00301     FBB = LastInst->getOperand(0).getMBB();
00302     return false;
00303   }
00304 
00305   // Otherwise, can't handle this.
00306   return true;
00307 }
00308 
00309 
00310 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
00311   int BOpc   = Hexagon::J2_jump;
00312   int BccOpc = Hexagon::J2_jumpt;
00313   int BccOpcNot = Hexagon::J2_jumpf;
00314 
00315   MachineBasicBlock::iterator I = MBB.end();
00316   if (I == MBB.begin()) return 0;
00317   --I;
00318   if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
00319       I->getOpcode() != BccOpcNot)
00320     return 0;
00321 
00322   // Remove the branch.
00323   I->eraseFromParent();
00324 
00325   I = MBB.end();
00326 
00327   if (I == MBB.begin()) return 1;
00328   --I;
00329   if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
00330     return 1;
00331 
00332   // Remove the branch.
00333   I->eraseFromParent();
00334   return 2;
00335 }
00336 
00337 
00338 /// \brief For a comparison instruction, return the source registers in
00339 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
00340 /// compares against in CmpValue. Return true if the comparison instruction
00341 /// can be analyzed.
00342 bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
00343                                       unsigned &SrcReg, unsigned &SrcReg2,
00344                                       int &Mask, int &Value) const {
00345   unsigned Opc = MI->getOpcode();
00346 
00347   // Set mask and the first source register.
00348   switch (Opc) {
00349     case Hexagon::C2_cmpeqp:
00350     case Hexagon::C2_cmpeqi:
00351     case Hexagon::C2_cmpeq:
00352     case Hexagon::C2_cmpgtp:
00353     case Hexagon::C2_cmpgtup:
00354     case Hexagon::C2_cmpgtui:
00355     case Hexagon::C2_cmpgtu:
00356     case Hexagon::C2_cmpgti:
00357     case Hexagon::C2_cmpgt:
00358       SrcReg = MI->getOperand(1).getReg();
00359       Mask = ~0;
00360       break;
00361     case Hexagon::A4_cmpbeqi:
00362     case Hexagon::A4_cmpbeq:
00363     case Hexagon::A4_cmpbgtui:
00364     case Hexagon::A4_cmpbgtu:
00365     case Hexagon::A4_cmpbgt:
00366       SrcReg = MI->getOperand(1).getReg();
00367       Mask = 0xFF;
00368       break;
00369     case Hexagon::A4_cmpheqi:
00370     case Hexagon::A4_cmpheq:
00371     case Hexagon::A4_cmphgtui:
00372     case Hexagon::A4_cmphgtu:
00373     case Hexagon::A4_cmphgt:
00374       SrcReg = MI->getOperand(1).getReg();
00375       Mask = 0xFFFF;
00376       break;
00377   }
00378 
00379   // Set the value/second source register.
00380   switch (Opc) {
00381     case Hexagon::C2_cmpeqp:
00382     case Hexagon::C2_cmpeq:
00383     case Hexagon::C2_cmpgtp:
00384     case Hexagon::C2_cmpgtup:
00385     case Hexagon::C2_cmpgtu:
00386     case Hexagon::C2_cmpgt:
00387     case Hexagon::A4_cmpbeq:
00388     case Hexagon::A4_cmpbgtu:
00389     case Hexagon::A4_cmpbgt:
00390     case Hexagon::A4_cmpheq:
00391     case Hexagon::A4_cmphgtu:
00392     case Hexagon::A4_cmphgt:
00393       SrcReg2 = MI->getOperand(2).getReg();
00394       return true;
00395 
00396     case Hexagon::C2_cmpeqi:
00397     case Hexagon::C2_cmpgtui:
00398     case Hexagon::C2_cmpgti:
00399     case Hexagon::A4_cmpbeqi:
00400     case Hexagon::A4_cmpbgtui:
00401     case Hexagon::A4_cmpheqi:
00402     case Hexagon::A4_cmphgtui:
00403       SrcReg2 = 0;
00404       Value = MI->getOperand(2).getImm();
00405       return true;
00406   }
00407 
00408   return false;
00409 }
00410 
00411 
00412 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
00413                                  MachineBasicBlock::iterator I, DebugLoc DL,
00414                                  unsigned DestReg, unsigned SrcReg,
00415                                  bool KillSrc) const {
00416   if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
00417     BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg).addReg(SrcReg);
00418     return;
00419   }
00420   if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
00421     BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg).addReg(SrcReg);
00422     return;
00423   }
00424   if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
00425     // Map Pd = Ps to Pd = or(Ps, Ps).
00426     BuildMI(MBB, I, DL, get(Hexagon::C2_or),
00427             DestReg).addReg(SrcReg).addReg(SrcReg);
00428     return;
00429   }
00430   if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
00431       Hexagon::IntRegsRegClass.contains(SrcReg)) {
00432     // We can have an overlap between single and double reg: r1:0 = r0.
00433     if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
00434         // r1:0 = r0
00435         BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
00436                 Hexagon::subreg_hireg))).addImm(0);
00437     } else {
00438         // r1:0 = r1 or no overlap.
00439         BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), (RI.getSubReg(DestReg,
00440                 Hexagon::subreg_loreg))).addReg(SrcReg);
00441         BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
00442                 Hexagon::subreg_hireg))).addImm(0);
00443     }
00444     return;
00445   }
00446   if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
00447       Hexagon::IntRegsRegClass.contains(SrcReg)) {
00448     BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg).addReg(SrcReg);
00449     return;
00450   }
00451   if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
00452       Hexagon::IntRegsRegClass.contains(DestReg)) {
00453     BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg).
00454       addReg(SrcReg, getKillRegState(KillSrc));
00455     return;
00456   }
00457   if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
00458       Hexagon::PredRegsRegClass.contains(DestReg)) {
00459     BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg).
00460       addReg(SrcReg, getKillRegState(KillSrc));
00461     return;
00462   }
00463 
00464   llvm_unreachable("Unimplemented");
00465 }
00466 
00467 
00468 void HexagonInstrInfo::
00469 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
00470                     unsigned SrcReg, bool isKill, int FI,
00471                     const TargetRegisterClass *RC,
00472                     const TargetRegisterInfo *TRI) const {
00473 
00474   DebugLoc DL = MBB.findDebugLoc(I);
00475   MachineFunction &MF = *MBB.getParent();
00476   MachineFrameInfo &MFI = *MF.getFrameInfo();
00477   unsigned Align = MFI.getObjectAlignment(FI);
00478 
00479   MachineMemOperand *MMO =
00480       MF.getMachineMemOperand(
00481                       MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
00482                       MachineMemOperand::MOStore,
00483                       MFI.getObjectSize(FI),
00484                       Align);
00485 
00486   if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
00487     BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
00488           .addFrameIndex(FI).addImm(0)
00489           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00490   } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
00491     BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
00492           .addFrameIndex(FI).addImm(0)
00493           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00494   } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
00495     BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
00496           .addFrameIndex(FI).addImm(0)
00497           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00498   } else {
00499     llvm_unreachable("Unimplemented");
00500   }
00501 }
00502 
00503 
00504 void HexagonInstrInfo::storeRegToAddr(
00505                                  MachineFunction &MF, unsigned SrcReg,
00506                                  bool isKill,
00507                                  SmallVectorImpl<MachineOperand> &Addr,
00508                                  const TargetRegisterClass *RC,
00509                                  SmallVectorImpl<MachineInstr*> &NewMIs) const
00510 {
00511   llvm_unreachable("Unimplemented");
00512 }
00513 
00514 
00515 void HexagonInstrInfo::
00516 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
00517                      unsigned DestReg, int FI,
00518                      const TargetRegisterClass *RC,
00519                      const TargetRegisterInfo *TRI) const {
00520   DebugLoc DL = MBB.findDebugLoc(I);
00521   MachineFunction &MF = *MBB.getParent();
00522   MachineFrameInfo &MFI = *MF.getFrameInfo();
00523   unsigned Align = MFI.getObjectAlignment(FI);
00524 
00525   MachineMemOperand *MMO =
00526       MF.getMachineMemOperand(
00527                       MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
00528                       MachineMemOperand::MOLoad,
00529                       MFI.getObjectSize(FI),
00530                       Align);
00531   if (RC == &Hexagon::IntRegsRegClass) {
00532     BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
00533           .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00534   } else if (RC == &Hexagon::DoubleRegsRegClass) {
00535     BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
00536           .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00537   } else if (RC == &Hexagon::PredRegsRegClass) {
00538     BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
00539           .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00540   } else {
00541     llvm_unreachable("Can't store this register to stack slot");
00542   }
00543 }
00544 
00545 
00546 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
00547                                         SmallVectorImpl<MachineOperand> &Addr,
00548                                         const TargetRegisterClass *RC,
00549                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
00550   llvm_unreachable("Unimplemented");
00551 }
00552 
00553 
00554 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
00555                                                     MachineInstr* MI,
00556                                           const SmallVectorImpl<unsigned> &Ops,
00557                                                     int FI) const {
00558   // Hexagon_TODO: Implement.
00559   return nullptr;
00560 }
00561 
00562 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
00563 
00564   MachineRegisterInfo &RegInfo = MF->getRegInfo();
00565   const TargetRegisterClass *TRC;
00566   if (VT == MVT::i1) {
00567     TRC = &Hexagon::PredRegsRegClass;
00568   } else if (VT == MVT::i32 || VT == MVT::f32) {
00569     TRC = &Hexagon::IntRegsRegClass;
00570   } else if (VT == MVT::i64 || VT == MVT::f64) {
00571     TRC = &Hexagon::DoubleRegsRegClass;
00572   } else {
00573     llvm_unreachable("Cannot handle this register class");
00574   }
00575 
00576   unsigned NewReg = RegInfo.createVirtualRegister(TRC);
00577   return NewReg;
00578 }
00579 
00580 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
00581   const MCInstrDesc &MID = MI->getDesc();
00582   const uint64_t F = MID.TSFlags;
00583   if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
00584     return true;
00585 
00586   // TODO: This is largely obsolete now. Will need to be removed
00587   // in consecutive patches.
00588   switch(MI->getOpcode()) {
00589     // TFR_FI Remains a special case.
00590     case Hexagon::TFR_FI:
00591       return true;
00592     default:
00593       return false;
00594   }
00595   return  false;
00596 }
00597 
00598 // This returns true in two cases:
00599 // - The OP code itself indicates that this is an extended instruction.
00600 // - One of MOs has been marked with HMOTF_ConstExtended flag.
00601 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
00602   // First check if this is permanently extended op code.
00603   const uint64_t F = MI->getDesc().TSFlags;
00604   if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
00605     return true;
00606   // Use MO operand flags to determine if one of MI's operands
00607   // has HMOTF_ConstExtended flag set.
00608   for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
00609        E = MI->operands_end(); I != E; ++I) {
00610     if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
00611       return true;
00612   }
00613   return  false;
00614 }
00615 
00616 bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const {
00617   return MI->getDesc().isBranch();
00618 }
00619 
00620 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
00621   if (isNewValueJump(MI))
00622     return true;
00623 
00624   if (isNewValueStore(MI))
00625     return true;
00626 
00627   return false;
00628 }
00629 
00630 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
00631   return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
00632 }
00633 
00634 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
00635   bool isPred = MI->getDesc().isPredicable();
00636 
00637   if (!isPred)
00638     return false;
00639 
00640   const int Opc = MI->getOpcode();
00641 
00642   switch(Opc) {
00643   case Hexagon::A2_tfrsi:
00644     return isInt<12>(MI->getOperand(1).getImm());
00645 
00646   case Hexagon::S2_storerd_io:
00647     return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
00648 
00649   case Hexagon::S2_storeri_io:
00650   case Hexagon::S2_storerinew_io:
00651     return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
00652 
00653   case Hexagon::S2_storerh_io:
00654   case Hexagon::S2_storerhnew_io:
00655     return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
00656 
00657   case Hexagon::S2_storerb_io:
00658   case Hexagon::S2_storerbnew_io:
00659     return isUInt<6>(MI->getOperand(1).getImm());
00660 
00661   case Hexagon::L2_loadrd_io:
00662     return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
00663 
00664   case Hexagon::L2_loadri_io:
00665     return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
00666 
00667   case Hexagon::L2_loadrh_io:
00668   case Hexagon::L2_loadruh_io:
00669     return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
00670 
00671   case Hexagon::L2_loadrb_io:
00672   case Hexagon::L2_loadrub_io:
00673     return isUInt<6>(MI->getOperand(2).getImm());
00674 
00675   case Hexagon::L2_loadrd_pi:
00676     return isShiftedInt<4,3>(MI->getOperand(3).getImm());
00677 
00678   case Hexagon::L2_loadri_pi:
00679     return isShiftedInt<4,2>(MI->getOperand(3).getImm());
00680 
00681   case Hexagon::L2_loadrh_pi:
00682   case Hexagon::L2_loadruh_pi:
00683     return isShiftedInt<4,1>(MI->getOperand(3).getImm());
00684 
00685   case Hexagon::L2_loadrb_pi:
00686   case Hexagon::L2_loadrub_pi:
00687     return isInt<4>(MI->getOperand(3).getImm());
00688 
00689   case Hexagon::S4_storeirb_io:
00690   case Hexagon::S4_storeirh_io:
00691   case Hexagon::S4_storeiri_io:
00692     return (isUInt<6>(MI->getOperand(1).getImm()) &&
00693             isInt<6>(MI->getOperand(2).getImm()));
00694 
00695   case Hexagon::A2_addi:
00696     return isInt<8>(MI->getOperand(2).getImm());
00697 
00698   case Hexagon::A2_aslh:
00699   case Hexagon::A2_asrh:
00700   case Hexagon::A2_sxtb:
00701   case Hexagon::A2_sxth:
00702   case Hexagon::A2_zxtb:
00703   case Hexagon::A2_zxth:
00704     return true;
00705   }
00706 
00707   return true;
00708 }
00709 
00710 // This function performs the following inversiones:
00711 //
00712 //  cPt    ---> cNotPt
00713 //  cNotPt ---> cPt
00714 //
00715 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
00716   int InvPredOpcode;
00717   InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
00718                                         : Hexagon::getTruePredOpcode(Opc);
00719   if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
00720     return InvPredOpcode;
00721 
00722   switch(Opc) {
00723     default: llvm_unreachable("Unexpected predicated instruction");
00724     case Hexagon::C2_ccombinewt:
00725       return Hexagon::C2_ccombinewf;
00726     case Hexagon::C2_ccombinewf:
00727       return Hexagon::C2_ccombinewt;
00728 
00729       // Dealloc_return.
00730     case Hexagon::L4_return_t:
00731       return Hexagon::L4_return_f;
00732     case Hexagon::L4_return_f:
00733       return Hexagon::L4_return_t;
00734   }
00735 }
00736 
00737 // New Value Store instructions.
00738 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
00739   const uint64_t F = MI->getDesc().TSFlags;
00740 
00741   return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
00742 }
00743 
00744 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
00745   const uint64_t F = get(Opcode).TSFlags;
00746 
00747   return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
00748 }
00749 
00750 int HexagonInstrInfo::
00751 getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
00752   enum Hexagon::PredSense inPredSense;
00753   inPredSense = invertPredicate ? Hexagon::PredSense_false :
00754                                   Hexagon::PredSense_true;
00755   int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
00756   if (CondOpcode >= 0) // Valid Conditional opcode/instruction
00757     return CondOpcode;
00758 
00759   // This switch case will be removed once all the instructions have been
00760   // modified to use relation maps.
00761   switch(Opc) {
00762   case Hexagon::TFRI_f:
00763     return !invertPredicate ? Hexagon::TFRI_cPt_f :
00764                               Hexagon::TFRI_cNotPt_f;
00765   case Hexagon::A2_combinew:
00766     return !invertPredicate ? Hexagon::C2_ccombinewt :
00767                               Hexagon::C2_ccombinewf;
00768 
00769   // DEALLOC_RETURN.
00770   case Hexagon::L4_return:
00771     return !invertPredicate ? Hexagon::L4_return_t:
00772                               Hexagon::L4_return_f;
00773   }
00774   llvm_unreachable("Unexpected predicable instruction");
00775 }
00776 
00777 
00778 bool HexagonInstrInfo::
00779 PredicateInstruction(MachineInstr *MI,
00780                      const SmallVectorImpl<MachineOperand> &Cond) const {
00781   int Opc = MI->getOpcode();
00782   assert (isPredicable(MI) && "Expected predicable instruction");
00783   bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
00784                      (Cond[0].getImm() == 0));
00785 
00786   // This will change MI's opcode to its predicate version.
00787   // However, its operand list is still the old one, i.e. the
00788   // non-predicate one.
00789   MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
00790 
00791   int oper = -1;
00792   unsigned int GAIdx = 0;
00793 
00794   // Indicates whether the current MI has a GlobalAddress operand
00795   bool hasGAOpnd = false;
00796   std::vector<MachineOperand> tmpOpnds;
00797 
00798   // Indicates whether we need to shift operands to right.
00799   bool needShift = true;
00800 
00801   // The predicate is ALWAYS the FIRST input operand !!!
00802   if (MI->getNumOperands() == 0) {
00803     // The non-predicate version of MI does not take any operands,
00804     // i.e. no outs and no ins. In this condition, the predicate
00805     // operand will be directly placed at Operands[0]. No operand
00806     // shift is needed.
00807     // Example: BARRIER
00808     needShift = false;
00809     oper = -1;
00810   }
00811   else if (   MI->getOperand(MI->getNumOperands()-1).isReg()
00812            && MI->getOperand(MI->getNumOperands()-1).isDef()
00813            && !MI->getOperand(MI->getNumOperands()-1).isImplicit()) {
00814     // The non-predicate version of MI does not have any input operands.
00815     // In this condition, we extend the length of Operands[] by one and
00816     // copy the original last operand to the newly allocated slot.
00817     // At this moment, it is just a place holder. Later, we will put
00818     // predicate operand directly into it. No operand shift is needed.
00819     // Example: r0=BARRIER (this is a faked insn used here for illustration)
00820     MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
00821     needShift = false;
00822     oper = MI->getNumOperands() - 2;
00823   }
00824   else {
00825     // We need to right shift all input operands by one. Duplicate the
00826     // last operand into the newly allocated slot.
00827     MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
00828   }
00829 
00830   if (needShift)
00831   {
00832     // Operands[ MI->getNumOperands() - 2 ] has been copied into
00833     // Operands[ MI->getNumOperands() - 1 ], so we start from
00834     // Operands[ MI->getNumOperands() - 3 ].
00835     // oper is a signed int.
00836     // It is ok if "MI->getNumOperands()-3" is -3, -2, or -1.
00837     for (oper = MI->getNumOperands() - 3; oper >= 0; --oper)
00838     {
00839       MachineOperand &MO = MI->getOperand(oper);
00840 
00841       // Opnd[0] Opnd[1] Opnd[2] Opnd[3] Opnd[4]   Opnd[5]   Opnd[6]   Opnd[7]
00842       // <Def0>  <Def1>  <Use0>  <Use1>  <ImpDef0> <ImpDef1> <ImpUse0> <ImpUse1>
00843       //               /\~
00844       //              /||\~
00845       //               ||
00846       //        Predicate Operand here
00847       if (MO.isReg() && !MO.isUse() && !MO.isImplicit()) {
00848         break;
00849       }
00850       if (MO.isReg()) {
00851         MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
00852                                                 MO.isImplicit(), MO.isKill(),
00853                                                 MO.isDead(), MO.isUndef(),
00854                                                 MO.isDebug());
00855       }
00856       else if (MO.isImm()) {
00857         MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
00858       }
00859       else if (MO.isGlobal()) {
00860         // MI can not have more than one GlobalAddress operand.
00861         assert(hasGAOpnd == false && "MI can only have one GlobalAddress opnd");
00862 
00863         // There is no member function called "ChangeToGlobalAddress" in the
00864         // MachineOperand class (not like "ChangeToRegister" and
00865         // "ChangeToImmediate"). So we have to remove them from Operands[] list
00866         // first, and then add them back after we have inserted the predicate
00867         // operand. tmpOpnds[] is to remember these operands before we remove
00868         // them.
00869         tmpOpnds.push_back(MO);
00870 
00871         // Operands[oper] is a GlobalAddress operand;
00872         // Operands[oper+1] has been copied into Operands[oper+2];
00873         hasGAOpnd = true;
00874         GAIdx = oper;
00875         continue;
00876       }
00877       else {
00878         llvm_unreachable("Unexpected operand type");
00879       }
00880     }
00881   }
00882 
00883   int regPos = invertJump ? 1 : 0;
00884   MachineOperand PredMO = Cond[regPos];
00885 
00886   // [oper] now points to the last explicit Def. Predicate operand must be
00887   // located at [oper+1]. See diagram above.
00888   // This assumes that the predicate is always the first operand,
00889   // i.e. Operands[0+numResults], in the set of inputs
00890   // It is better to have an assert here to check this. But I don't know how
00891   // to write this assert because findFirstPredOperandIdx() would return -1
00892   if (oper < -1) oper = -1;
00893 
00894   MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
00895                                           PredMO.isImplicit(), false,
00896                                           PredMO.isDead(), PredMO.isUndef(),
00897                                           PredMO.isDebug());
00898 
00899   MachineRegisterInfo &RegInfo = MI->getParent()->getParent()->getRegInfo();
00900   RegInfo.clearKillFlags(PredMO.getReg());
00901 
00902   if (hasGAOpnd)
00903   {
00904     unsigned int i;
00905 
00906     // Operands[GAIdx] is the original GlobalAddress operand, which is
00907     // already copied into tmpOpnds[0].
00908     // Operands[GAIdx] now stores a copy of Operands[GAIdx-1]
00909     // Operands[GAIdx+1] has already been copied into Operands[GAIdx+2],
00910     // so we start from [GAIdx+2]
00911     for (i = GAIdx + 2; i < MI->getNumOperands(); ++i)
00912       tmpOpnds.push_back(MI->getOperand(i));
00913 
00914     // Remove all operands in range [ (GAIdx+1) ... (MI->getNumOperands()-1) ]
00915     // It is very important that we always remove from the end of Operands[]
00916     // MI->getNumOperands() is at least 2 if program goes to here.
00917     for (i = MI->getNumOperands() - 1; i > GAIdx; --i)
00918       MI->RemoveOperand(i);
00919 
00920     for (i = 0; i < tmpOpnds.size(); ++i)
00921       MI->addOperand(tmpOpnds[i]);
00922   }
00923 
00924   return true;
00925 }
00926 
00927 
00928 bool
00929 HexagonInstrInfo::
00930 isProfitableToIfCvt(MachineBasicBlock &MBB,
00931                     unsigned NumCycles,
00932                     unsigned ExtraPredCycles,
00933                     const BranchProbability &Probability) const {
00934   return true;
00935 }
00936 
00937 
00938 bool
00939 HexagonInstrInfo::
00940 isProfitableToIfCvt(MachineBasicBlock &TMBB,
00941                     unsigned NumTCycles,
00942                     unsigned ExtraTCycles,
00943                     MachineBasicBlock &FMBB,
00944                     unsigned NumFCycles,
00945                     unsigned ExtraFCycles,
00946                     const BranchProbability &Probability) const {
00947   return true;
00948 }
00949 
00950 // Returns true if an instruction is predicated irrespective of the predicate
00951 // sense. For example, all of the following will return true.
00952 // if (p0) R1 = add(R2, R3)
00953 // if (!p0) R1 = add(R2, R3)
00954 // if (p0.new) R1 = add(R2, R3)
00955 // if (!p0.new) R1 = add(R2, R3)
00956 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
00957   const uint64_t F = MI->getDesc().TSFlags;
00958 
00959   return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
00960 }
00961 
00962 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
00963   const uint64_t F = get(Opcode).TSFlags;
00964 
00965   return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
00966 }
00967 
00968 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
00969   const uint64_t F = MI->getDesc().TSFlags;
00970 
00971   assert(isPredicated(MI));
00972   return (!((F >> HexagonII::PredicatedFalsePos) &
00973             HexagonII::PredicatedFalseMask));
00974 }
00975 
00976 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
00977   const uint64_t F = get(Opcode).TSFlags;
00978 
00979   // Make sure that the instruction is predicated.
00980   assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
00981   return (!((F >> HexagonII::PredicatedFalsePos) &
00982             HexagonII::PredicatedFalseMask));
00983 }
00984 
00985 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
00986   const uint64_t F = MI->getDesc().TSFlags;
00987 
00988   assert(isPredicated(MI));
00989   return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
00990 }
00991 
00992 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
00993   const uint64_t F = get(Opcode).TSFlags;
00994 
00995   assert(isPredicated(Opcode));
00996   return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
00997 }
00998 
00999 // Returns true, if a ST insn can be promoted to a new-value store.
01000 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const {
01001   const uint64_t F = MI->getDesc().TSFlags;
01002 
01003   return ((F >> HexagonII::mayNVStorePos) &
01004            HexagonII::mayNVStoreMask);
01005 }
01006 
01007 bool
01008 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
01009                                    std::vector<MachineOperand> &Pred) const {
01010   for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
01011     MachineOperand MO = MI->getOperand(oper);
01012     if (MO.isReg() && MO.isDef()) {
01013       const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
01014       if (RC == &Hexagon::PredRegsRegClass) {
01015         Pred.push_back(MO);
01016         return true;
01017       }
01018     }
01019   }
01020   return false;
01021 }
01022 
01023 
01024 bool
01025 HexagonInstrInfo::
01026 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
01027                   const SmallVectorImpl<MachineOperand> &Pred2) const {
01028   // TODO: Fix this
01029   return false;
01030 }
01031 
01032 
01033 //
01034 // We indicate that we want to reverse the branch by
01035 // inserting a 0 at the beginning of the Cond vector.
01036 //
01037 bool HexagonInstrInfo::
01038 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
01039   if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
01040     Cond.erase(Cond.begin());
01041   } else {
01042     Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
01043   }
01044   return false;
01045 }
01046 
01047 
01048 bool HexagonInstrInfo::
01049 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
01050                           const BranchProbability &Probability) const {
01051   return (NumInstrs <= 4);
01052 }
01053 
01054 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
01055   switch (MI->getOpcode()) {
01056   default: return false;
01057   case Hexagon::L4_return:
01058   case Hexagon::L4_return_t:
01059   case Hexagon::L4_return_f:
01060   case Hexagon::L4_return_tnew_pnt:
01061   case Hexagon::L4_return_fnew_pnt:
01062   case Hexagon::L4_return_tnew_pt:
01063   case Hexagon::L4_return_fnew_pt:
01064    return true;
01065   }
01066 }
01067 
01068 
01069 bool HexagonInstrInfo::
01070 isValidOffset(const int Opcode, const int Offset) const {
01071   // This function is to check whether the "Offset" is in the correct range of
01072   // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
01073   // inserted to calculate the final address. Due to this reason, the function
01074   // assumes that the "Offset" has correct alignment.
01075   // We used to assert if the offset was not properly aligned, however,
01076   // there are cases where a misaligned pointer recast can cause this
01077   // problem, and we need to allow for it. The front end warns of such
01078   // misaligns with respect to load size.
01079 
01080   switch(Opcode) {
01081 
01082   case Hexagon::L2_loadri_io:
01083   case Hexagon::S2_storeri_io:
01084     return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
01085       (Offset <= Hexagon_MEMW_OFFSET_MAX);
01086 
01087   case Hexagon::L2_loadrd_io:
01088   case Hexagon::S2_storerd_io:
01089     return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
01090       (Offset <= Hexagon_MEMD_OFFSET_MAX);
01091 
01092   case Hexagon::L2_loadrh_io:
01093   case Hexagon::L2_loadruh_io:
01094   case Hexagon::S2_storerh_io:
01095     return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
01096       (Offset <= Hexagon_MEMH_OFFSET_MAX);
01097 
01098   case Hexagon::L2_loadrb_io:
01099   case Hexagon::S2_storerb_io:
01100   case Hexagon::L2_loadrub_io:
01101     return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
01102       (Offset <= Hexagon_MEMB_OFFSET_MAX);
01103 
01104   case Hexagon::A2_addi:
01105   case Hexagon::TFR_FI:
01106     return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
01107       (Offset <= Hexagon_ADDI_OFFSET_MAX);
01108 
01109   case Hexagon::L4_iadd_memopw_io:
01110   case Hexagon::L4_isub_memopw_io:
01111   case Hexagon::L4_add_memopw_io:
01112   case Hexagon::L4_sub_memopw_io:
01113   case Hexagon::L4_and_memopw_io:
01114   case Hexagon::L4_or_memopw_io:
01115     return (0 <= Offset && Offset <= 255);
01116 
01117   case Hexagon::L4_iadd_memoph_io:
01118   case Hexagon::L4_isub_memoph_io:
01119   case Hexagon::L4_add_memoph_io:
01120   case Hexagon::L4_sub_memoph_io:
01121   case Hexagon::L4_and_memoph_io:
01122   case Hexagon::L4_or_memoph_io:
01123     return (0 <= Offset && Offset <= 127);
01124 
01125   case Hexagon::L4_iadd_memopb_io:
01126   case Hexagon::L4_isub_memopb_io:
01127   case Hexagon::L4_add_memopb_io:
01128   case Hexagon::L4_sub_memopb_io:
01129   case Hexagon::L4_and_memopb_io:
01130   case Hexagon::L4_or_memopb_io:
01131     return (0 <= Offset && Offset <= 63);
01132 
01133   // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
01134   // any size. Later pass knows how to handle it.
01135   case Hexagon::STriw_pred:
01136   case Hexagon::LDriw_pred:
01137     return true;
01138 
01139   case Hexagon::J2_loop0i:
01140     return isUInt<10>(Offset);
01141 
01142   // INLINEASM is very special.
01143   case Hexagon::INLINEASM:
01144     return true;
01145   }
01146 
01147   llvm_unreachable("No offset range is defined for this opcode. "
01148                    "Please define it in the above switch statement!");
01149 }
01150 
01151 
01152 //
01153 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
01154 //
01155 bool HexagonInstrInfo::
01156 isValidAutoIncImm(const EVT VT, const int Offset) const {
01157 
01158   if (VT == MVT::i64) {
01159       return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
01160               Offset <= Hexagon_MEMD_AUTOINC_MAX &&
01161               (Offset & 0x7) == 0);
01162   }
01163   if (VT == MVT::i32) {
01164       return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
01165               Offset <= Hexagon_MEMW_AUTOINC_MAX &&
01166               (Offset & 0x3) == 0);
01167   }
01168   if (VT == MVT::i16) {
01169       return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
01170               Offset <= Hexagon_MEMH_AUTOINC_MAX &&
01171               (Offset & 0x1) == 0);
01172   }
01173   if (VT == MVT::i8) {
01174       return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
01175               Offset <= Hexagon_MEMB_AUTOINC_MAX);
01176   }
01177   llvm_unreachable("Not an auto-inc opc!");
01178 }
01179 
01180 
01181 bool HexagonInstrInfo::
01182 isMemOp(const MachineInstr *MI) const {
01183 //  return MI->getDesc().mayLoad() && MI->getDesc().mayStore();
01184 
01185   switch (MI->getOpcode())
01186   {
01187   default: return false;
01188   case Hexagon::L4_iadd_memopw_io:
01189   case Hexagon::L4_isub_memopw_io:
01190   case Hexagon::L4_add_memopw_io:
01191   case Hexagon::L4_sub_memopw_io:
01192   case Hexagon::L4_and_memopw_io:
01193   case Hexagon::L4_or_memopw_io:
01194   case Hexagon::L4_iadd_memoph_io:
01195   case Hexagon::L4_isub_memoph_io:
01196   case Hexagon::L4_add_memoph_io:
01197   case Hexagon::L4_sub_memoph_io:
01198   case Hexagon::L4_and_memoph_io:
01199   case Hexagon::L4_or_memoph_io:
01200   case Hexagon::L4_iadd_memopb_io:
01201   case Hexagon::L4_isub_memopb_io:
01202   case Hexagon::L4_add_memopb_io:
01203   case Hexagon::L4_sub_memopb_io:
01204   case Hexagon::L4_and_memopb_io:
01205   case Hexagon::L4_or_memopb_io:
01206   case Hexagon::L4_ior_memopb_io:
01207   case Hexagon::L4_ior_memoph_io:
01208   case Hexagon::L4_ior_memopw_io:
01209   case Hexagon::L4_iand_memopb_io:
01210   case Hexagon::L4_iand_memoph_io:
01211   case Hexagon::L4_iand_memopw_io:
01212     return true;
01213   }
01214   return false;
01215 }
01216 
01217 
01218 bool HexagonInstrInfo::
01219 isSpillPredRegOp(const MachineInstr *MI) const {
01220   switch (MI->getOpcode()) {
01221     default: return false;
01222     case Hexagon::STriw_pred :
01223     case Hexagon::LDriw_pred :
01224       return true;
01225   }
01226 }
01227 
01228 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
01229   switch (MI->getOpcode()) {
01230     default: return false;
01231     case Hexagon::C2_cmpeq:
01232     case Hexagon::C2_cmpeqi:
01233     case Hexagon::C2_cmpgt:
01234     case Hexagon::C2_cmpgti:
01235     case Hexagon::C2_cmpgtu:
01236     case Hexagon::C2_cmpgtui:
01237       return true;
01238   }
01239 }
01240 
01241 bool HexagonInstrInfo::
01242 isConditionalTransfer (const MachineInstr *MI) const {
01243   switch (MI->getOpcode()) {
01244     default: return false;
01245     case Hexagon::A2_tfrt:
01246     case Hexagon::A2_tfrf:
01247     case Hexagon::C2_cmoveit:
01248     case Hexagon::C2_cmoveif:
01249     case Hexagon::A2_tfrtnew:
01250     case Hexagon::A2_tfrfnew:
01251     case Hexagon::C2_cmovenewit:
01252     case Hexagon::C2_cmovenewif:
01253       return true;
01254   }
01255 }
01256 
01257 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
01258   switch (MI->getOpcode())
01259   {
01260     default: return false;
01261     case Hexagon::A2_paddf:
01262     case Hexagon::A2_paddfnew:
01263     case Hexagon::A2_paddt:
01264     case Hexagon::A2_paddtnew:
01265     case Hexagon::A2_pandf:
01266     case Hexagon::A2_pandfnew:
01267     case Hexagon::A2_pandt:
01268     case Hexagon::A2_pandtnew:
01269     case Hexagon::A4_paslhf:
01270     case Hexagon::A4_paslhfnew:
01271     case Hexagon::A4_paslht:
01272     case Hexagon::A4_paslhtnew:
01273     case Hexagon::A4_pasrhf:
01274     case Hexagon::A4_pasrhfnew:
01275     case Hexagon::A4_pasrht:
01276     case Hexagon::A4_pasrhtnew:
01277     case Hexagon::A2_porf:
01278     case Hexagon::A2_porfnew:
01279     case Hexagon::A2_port:
01280     case Hexagon::A2_portnew:
01281     case Hexagon::A2_psubf:
01282     case Hexagon::A2_psubfnew:
01283     case Hexagon::A2_psubt:
01284     case Hexagon::A2_psubtnew:
01285     case Hexagon::A2_pxorf:
01286     case Hexagon::A2_pxorfnew:
01287     case Hexagon::A2_pxort:
01288     case Hexagon::A2_pxortnew:
01289     case Hexagon::A4_psxthf:
01290     case Hexagon::A4_psxthfnew:
01291     case Hexagon::A4_psxtht:
01292     case Hexagon::A4_psxthtnew:
01293     case Hexagon::A4_psxtbf:
01294     case Hexagon::A4_psxtbfnew:
01295     case Hexagon::A4_psxtbt:
01296     case Hexagon::A4_psxtbtnew:
01297     case Hexagon::A4_pzxtbf:
01298     case Hexagon::A4_pzxtbfnew:
01299     case Hexagon::A4_pzxtbt:
01300     case Hexagon::A4_pzxtbtnew:
01301     case Hexagon::A4_pzxthf:
01302     case Hexagon::A4_pzxthfnew:
01303     case Hexagon::A4_pzxtht:
01304     case Hexagon::A4_pzxthtnew:
01305     case Hexagon::A2_paddit:
01306     case Hexagon::A2_paddif:
01307     case Hexagon::C2_ccombinewt:
01308     case Hexagon::C2_ccombinewf:
01309       return true;
01310   }
01311 }
01312 
01313 bool HexagonInstrInfo::
01314 isConditionalLoad (const MachineInstr* MI) const {
01315   switch (MI->getOpcode())
01316   {
01317     default: return false;
01318     case Hexagon::L2_ploadrdt_io :
01319     case Hexagon::L2_ploadrdf_io:
01320     case Hexagon::L2_ploadrit_io:
01321     case Hexagon::L2_ploadrif_io:
01322     case Hexagon::L2_ploadrht_io:
01323     case Hexagon::L2_ploadrhf_io:
01324     case Hexagon::L2_ploadrbt_io:
01325     case Hexagon::L2_ploadrbf_io:
01326     case Hexagon::L2_ploadruht_io:
01327     case Hexagon::L2_ploadruhf_io:
01328     case Hexagon::L2_ploadrubt_io:
01329     case Hexagon::L2_ploadrubf_io:
01330     case Hexagon::L2_ploadrdt_pi:
01331     case Hexagon::L2_ploadrdf_pi:
01332     case Hexagon::L2_ploadrit_pi:
01333     case Hexagon::L2_ploadrif_pi:
01334     case Hexagon::L2_ploadrht_pi:
01335     case Hexagon::L2_ploadrhf_pi:
01336     case Hexagon::L2_ploadrbt_pi:
01337     case Hexagon::L2_ploadrbf_pi:
01338     case Hexagon::L2_ploadruht_pi:
01339     case Hexagon::L2_ploadruhf_pi:
01340     case Hexagon::L2_ploadrubt_pi:
01341     case Hexagon::L2_ploadrubf_pi:
01342     case Hexagon::L4_ploadrdt_rr:
01343     case Hexagon::L4_ploadrdf_rr:
01344     case Hexagon::L4_ploadrbt_rr:
01345     case Hexagon::L4_ploadrbf_rr:
01346     case Hexagon::L4_ploadrubt_rr:
01347     case Hexagon::L4_ploadrubf_rr:
01348     case Hexagon::L4_ploadrht_rr:
01349     case Hexagon::L4_ploadrhf_rr:
01350     case Hexagon::L4_ploadruht_rr:
01351     case Hexagon::L4_ploadruhf_rr:
01352     case Hexagon::L4_ploadrit_rr:
01353     case Hexagon::L4_ploadrif_rr:
01354       return true;
01355   }
01356 }
01357 
01358 // Returns true if an instruction is a conditional store.
01359 //
01360 // Note: It doesn't include conditional new-value stores as they can't be
01361 // converted to .new predicate.
01362 //
01363 //               p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
01364 //                ^           ^
01365 //               /             \ (not OK. it will cause new-value store to be
01366 //              /               X conditional on p0.new while R2 producer is
01367 //             /                 \ on p0)
01368 //            /                   \.
01369 //     p.new store                 p.old NV store
01370 // [if(p0.new)memw(R0+#0)=R2]    [if(p0)memw(R0+#0)=R2.new]
01371 //            ^                  ^
01372 //             \                /
01373 //              \              /
01374 //               \            /
01375 //                 p.old store
01376 //             [if (p0)memw(R0+#0)=R2]
01377 //
01378 // The above diagram shows the steps involoved in the conversion of a predicated
01379 // store instruction to its .new predicated new-value form.
01380 //
01381 // The following set of instructions further explains the scenario where
01382 // conditional new-value store becomes invalid when promoted to .new predicate
01383 // form.
01384 //
01385 // { 1) if (p0) r0 = add(r1, r2)
01386 //   2) p0 = cmp.eq(r3, #0) }
01387 //
01388 //   3) if (p0) memb(r1+#0) = r0  --> this instruction can't be grouped with
01389 // the first two instructions because in instr 1, r0 is conditional on old value
01390 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
01391 // is not valid for new-value stores.
01392 bool HexagonInstrInfo::
01393 isConditionalStore (const MachineInstr* MI) const {
01394   switch (MI->getOpcode())
01395   {
01396     default: return false;
01397     case Hexagon::S4_storeirbt_io:
01398     case Hexagon::S4_storeirbf_io:
01399     case Hexagon::S4_pstorerbt_rr:
01400     case Hexagon::S4_pstorerbf_rr:
01401     case Hexagon::S2_pstorerbt_io:
01402     case Hexagon::S2_pstorerbf_io:
01403     case Hexagon::S2_pstorerbt_pi:
01404     case Hexagon::S2_pstorerbf_pi:
01405     case Hexagon::S2_pstorerdt_io:
01406     case Hexagon::S2_pstorerdf_io:
01407     case Hexagon::S4_pstorerdt_rr:
01408     case Hexagon::S4_pstorerdf_rr:
01409     case Hexagon::S2_pstorerdt_pi:
01410     case Hexagon::S2_pstorerdf_pi:
01411     case Hexagon::S2_pstorerht_io:
01412     case Hexagon::S2_pstorerhf_io:
01413     case Hexagon::S4_storeirht_io:
01414     case Hexagon::S4_storeirhf_io:
01415     case Hexagon::S4_pstorerht_rr:
01416     case Hexagon::S4_pstorerhf_rr:
01417     case Hexagon::S2_pstorerht_pi:
01418     case Hexagon::S2_pstorerhf_pi:
01419     case Hexagon::S2_pstorerit_io:
01420     case Hexagon::S2_pstorerif_io:
01421     case Hexagon::S4_storeirit_io:
01422     case Hexagon::S4_storeirif_io:
01423     case Hexagon::S4_pstorerit_rr:
01424     case Hexagon::S4_pstorerif_rr:
01425     case Hexagon::S2_pstorerit_pi:
01426     case Hexagon::S2_pstorerif_pi:
01427 
01428     // V4 global address store before promoting to dot new.
01429     case Hexagon::S4_pstorerdt_abs:
01430     case Hexagon::S4_pstorerdf_abs:
01431     case Hexagon::S4_pstorerbt_abs:
01432     case Hexagon::S4_pstorerbf_abs:
01433     case Hexagon::S4_pstorerht_abs:
01434     case Hexagon::S4_pstorerhf_abs:
01435     case Hexagon::S4_pstorerit_abs:
01436     case Hexagon::S4_pstorerif_abs:
01437       return true;
01438 
01439     // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
01440     // from the "Conditional Store" list. Because a predicated new value store
01441     // would NOT be promoted to a double dot new store. See diagram below:
01442     // This function returns yes for those stores that are predicated but not
01443     // yet promoted to predicate dot new instructions.
01444     //
01445     //                          +---------------------+
01446     //                    /-----| if (p0) memw(..)=r0 |---------\~
01447     //                   ||     +---------------------+         ||
01448     //          promote  ||       /\       /\                   ||  promote
01449     //                   ||      /||\     /||\                  ||
01450     //                  \||/    demote     ||                  \||/
01451     //                   \/       ||       ||                   \/
01452     //       +-------------------------+   ||   +-------------------------+
01453     //       | if (p0.new) memw(..)=r0 |   ||   | if (p0) memw(..)=r0.new |
01454     //       +-------------------------+   ||   +-------------------------+
01455     //                        ||           ||         ||
01456     //                        ||         demote      \||/
01457     //                      promote        ||         \/ NOT possible
01458     //                        ||           ||         /\~
01459     //                       \||/          ||        /||\~
01460     //                        \/           ||         ||
01461     //                      +-----------------------------+
01462     //                      | if (p0.new) memw(..)=r0.new |
01463     //                      +-----------------------------+
01464     //                           Double Dot New Store
01465     //
01466   }
01467 }
01468 
01469 
01470 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
01471   if (isNewValue(MI) && isBranch(MI))
01472     return true;
01473   return false;
01474 }
01475 
01476 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
01477   return (getAddrMode(MI) == HexagonII::PostInc);
01478 }
01479 
01480 bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
01481   const uint64_t F = MI->getDesc().TSFlags;
01482   return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
01483 }
01484 
01485 // Returns true, if any one of the operands is a dot new
01486 // insn, whether it is predicated dot new or register dot new.
01487 bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
01488   return (isNewValueInst(MI) ||
01489      (isPredicated(MI) && isPredicatedNew(MI)));
01490 }
01491 
01492 // Returns the most basic instruction for the .new predicated instructions and
01493 // new-value stores.
01494 // For example, all of the following instructions will be converted back to the
01495 // same instruction:
01496 // 1) if (p0.new) memw(R0+#0) = R1.new  --->
01497 // 2) if (p0) memw(R0+#0)= R1.new      -------> if (p0) memw(R0+#0) = R1
01498 // 3) if (p0.new) memw(R0+#0) = R1      --->
01499 //
01500 
01501 int HexagonInstrInfo::GetDotOldOp(const int opc) const {
01502   int NewOp = opc;
01503   if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
01504     NewOp = Hexagon::getPredOldOpcode(NewOp);
01505     assert(NewOp >= 0 &&
01506            "Couldn't change predicate new instruction to its old form.");
01507   }
01508 
01509   if (isNewValueStore(NewOp)) { // Convert into non-new-value format
01510     NewOp = Hexagon::getNonNVStore(NewOp);
01511     assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
01512   }
01513   return NewOp;
01514 }
01515 
01516 // Return the new value instruction for a given store.
01517 int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const {
01518   int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
01519   if (NVOpcode >= 0) // Valid new-value store instruction.
01520     return NVOpcode;
01521 
01522   switch (MI->getOpcode()) {
01523   default: llvm_unreachable("Unknown .new type");
01524   // store new value byte
01525   case Hexagon::S4_storerb_ur:
01526     return Hexagon::S4_storerbnew_ur;
01527 
01528   case Hexagon::S4_storerh_ur:
01529     return Hexagon::S4_storerhnew_ur;
01530 
01531   case Hexagon::S4_storeri_ur:
01532     return Hexagon::S4_storerinew_ur;
01533 
01534   }
01535   return 0;
01536 }
01537 
01538 // Return .new predicate version for an instruction.
01539 int HexagonInstrInfo::GetDotNewPredOp(MachineInstr *MI,
01540                                       const MachineBranchProbabilityInfo
01541                                       *MBPI) const {
01542 
01543   int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
01544   if (NewOpcode >= 0) // Valid predicate new instruction
01545     return NewOpcode;
01546 
01547   switch (MI->getOpcode()) {
01548   default: llvm_unreachable("Unknown .new type");
01549   // Condtional Jumps
01550   case Hexagon::J2_jumpt:
01551   case Hexagon::J2_jumpf:
01552     return getDotNewPredJumpOp(MI, MBPI);
01553 
01554   case Hexagon::J2_jumprt:
01555     return Hexagon::J2_jumptnewpt;
01556 
01557   case Hexagon::J2_jumprf:
01558     return Hexagon::J2_jumprfnewpt;
01559 
01560   case Hexagon::JMPrett:
01561     return Hexagon::J2_jumprtnewpt;
01562 
01563   case Hexagon::JMPretf:
01564     return Hexagon::J2_jumprfnewpt;
01565 
01566 
01567   // Conditional combine
01568   case Hexagon::C2_ccombinewt:
01569     return Hexagon::C2_ccombinewnewt;
01570   case Hexagon::C2_ccombinewf:
01571     return Hexagon::C2_ccombinewnewf;
01572   }
01573 }
01574 
01575 
01576 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
01577   const uint64_t F = MI->getDesc().TSFlags;
01578 
01579   return((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
01580 }
01581 
01582 /// immediateExtend - Changes the instruction in place to one using an immediate
01583 /// extender.
01584 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
01585   assert((isExtendable(MI)||isConstExtended(MI)) &&
01586                                "Instruction must be extendable");
01587   // Find which operand is extendable.
01588   short ExtOpNum = getCExtOpNum(MI);
01589   MachineOperand &MO = MI->getOperand(ExtOpNum);
01590   // This needs to be something we understand.
01591   assert((MO.isMBB() || MO.isImm()) &&
01592          "Branch with unknown extendable field type");
01593   // Mark given operand as extended.
01594   MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
01595 }
01596 
01597 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
01598     const TargetSubtargetInfo &STI) const {
01599   const InstrItineraryData *II = STI.getInstrItineraryData();
01600   return static_cast<const HexagonSubtarget &>(STI).createDFAPacketizer(II);
01601 }
01602 
01603 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
01604                                             const MachineBasicBlock *MBB,
01605                                             const MachineFunction &MF) const {
01606   // Debug info is never a scheduling boundary. It's necessary to be explicit
01607   // due to the special treatment of IT instructions below, otherwise a
01608   // dbg_value followed by an IT will result in the IT instruction being
01609   // considered a scheduling hazard, which is wrong. It should be the actual
01610   // instruction preceding the dbg_value instruction(s), just like it is
01611   // when debug info is not present.
01612   if (MI->isDebugValue())
01613     return false;
01614 
01615   // Terminators and labels can't be scheduled around.
01616   if (MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm())
01617     return true;
01618 
01619   return false;
01620 }
01621 
01622 bool HexagonInstrInfo::isConstExtended(MachineInstr *MI) const {
01623   const uint64_t F = MI->getDesc().TSFlags;
01624   unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
01625   if (isExtended) // Instruction must be extended.
01626     return true;
01627 
01628   unsigned isExtendable = (F >> HexagonII::ExtendablePos)
01629                           & HexagonII::ExtendableMask;
01630   if (!isExtendable)
01631     return false;
01632 
01633   short ExtOpNum = getCExtOpNum(MI);
01634   const MachineOperand &MO = MI->getOperand(ExtOpNum);
01635   // Use MO operand flags to determine if MO
01636   // has the HMOTF_ConstExtended flag set.
01637   if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
01638     return true;
01639   // If this is a Machine BB address we are talking about, and it is
01640   // not marked as extended, say so.
01641   if (MO.isMBB())
01642     return false;
01643 
01644   // We could be using an instruction with an extendable immediate and shoehorn
01645   // a global address into it. If it is a global address it will be constant
01646   // extended. We do this for COMBINE.
01647   // We currently only handle isGlobal() because it is the only kind of
01648   // object we are going to end up with here for now.
01649   // In the future we probably should add isSymbol(), etc.
01650   if (MO.isGlobal() || MO.isSymbol())
01651     return true;
01652 
01653   // If the extendable operand is not 'Immediate' type, the instruction should
01654   // have 'isExtended' flag set.
01655   assert(MO.isImm() && "Extendable operand must be Immediate type");
01656 
01657   int MinValue = getMinValue(MI);
01658   int MaxValue = getMaxValue(MI);
01659   int ImmValue = MO.getImm();
01660 
01661   return (ImmValue < MinValue || ImmValue > MaxValue);
01662 }
01663 
01664 // Returns the opcode to use when converting MI, which is a conditional jump,
01665 // into a conditional instruction which uses the .new value of the predicate.
01666 // We also use branch probabilities to add a hint to the jump.
01667 int
01668 HexagonInstrInfo::getDotNewPredJumpOp(MachineInstr *MI,
01669                                   const
01670                                   MachineBranchProbabilityInfo *MBPI) const {
01671 
01672   // We assume that block can have at most two successors.
01673   bool taken = false;
01674   MachineBasicBlock *Src = MI->getParent();
01675   MachineOperand *BrTarget = &MI->getOperand(1);
01676   MachineBasicBlock *Dst = BrTarget->getMBB();
01677 
01678   const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
01679   if (Prediction >= BranchProbability(1,2))
01680     taken = true;
01681 
01682   switch (MI->getOpcode()) {
01683   case Hexagon::J2_jumpt:
01684     return taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
01685   case Hexagon::J2_jumpf:
01686     return taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
01687 
01688   default:
01689     llvm_unreachable("Unexpected jump instruction.");
01690   }
01691 }
01692 // Returns true if a particular operand is extendable for an instruction.
01693 bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
01694                                          unsigned short OperandNum) const {
01695   const uint64_t F = MI->getDesc().TSFlags;
01696 
01697   return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
01698           == OperandNum;
01699 }
01700 
01701 // Returns Operand Index for the constant extended instruction.
01702 unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
01703   const uint64_t F = MI->getDesc().TSFlags;
01704   return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
01705 }
01706 
01707 // Returns the min value that doesn't need to be extended.
01708 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
01709   const uint64_t F = MI->getDesc().TSFlags;
01710   unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
01711                     & HexagonII::ExtentSignedMask;
01712   unsigned bits =  (F >> HexagonII::ExtentBitsPos)
01713                     & HexagonII::ExtentBitsMask;
01714 
01715   if (isSigned) // if value is signed
01716     return -1U << (bits - 1);
01717   else
01718     return 0;
01719 }
01720 
01721 // Returns the max value that doesn't need to be extended.
01722 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
01723   const uint64_t F = MI->getDesc().TSFlags;
01724   unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
01725                     & HexagonII::ExtentSignedMask;
01726   unsigned bits =  (F >> HexagonII::ExtentBitsPos)
01727                     & HexagonII::ExtentBitsMask;
01728 
01729   if (isSigned) // if value is signed
01730     return ~(-1U << (bits - 1));
01731   else
01732     return ~(-1U << bits);
01733 }
01734 
01735 // Returns true if an instruction can be converted into a non-extended
01736 // equivalent instruction.
01737 bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr *MI) const {
01738 
01739   short NonExtOpcode;
01740   // Check if the instruction has a register form that uses register in place
01741   // of the extended operand, if so return that as the non-extended form.
01742   if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
01743     return true;
01744 
01745   if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
01746     // Check addressing mode and retrieve non-ext equivalent instruction.
01747 
01748     switch (getAddrMode(MI)) {
01749     case HexagonII::Absolute :
01750       // Load/store with absolute addressing mode can be converted into
01751       // base+offset mode.
01752       NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode());
01753       break;
01754     case HexagonII::BaseImmOffset :
01755       // Load/store with base+offset addressing mode can be converted into
01756       // base+register offset addressing mode. However left shift operand should
01757       // be set to 0.
01758       NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
01759       break;
01760     default:
01761       return false;
01762     }
01763     if (NonExtOpcode < 0)
01764       return false;
01765     return true;
01766   }
01767   return false;
01768 }
01769 
01770 // Returns opcode of the non-extended equivalent instruction.
01771 short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const {
01772 
01773   // Check if the instruction has a register form that uses register in place
01774   // of the extended operand, if so return that as the non-extended form.
01775   short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
01776     if (NonExtOpcode >= 0)
01777       return NonExtOpcode;
01778 
01779   if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
01780     // Check addressing mode and retrieve non-ext equivalent instruction.
01781     switch (getAddrMode(MI)) {
01782     case HexagonII::Absolute :
01783       return Hexagon::getBasedWithImmOffset(MI->getOpcode());
01784     case HexagonII::BaseImmOffset :
01785       return Hexagon::getBaseWithRegOffset(MI->getOpcode());
01786     default:
01787       return -1;
01788     }
01789   }
01790   return -1;
01791 }
01792 
01793 bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode) const {
01794   return (Opcode == Hexagon::J2_jumpt) ||
01795          (Opcode == Hexagon::J2_jumpf) ||
01796          (Opcode == Hexagon::J2_jumptnewpt) ||
01797          (Opcode == Hexagon::J2_jumpfnewpt) ||
01798          (Opcode == Hexagon::J2_jumpt) ||
01799          (Opcode == Hexagon::J2_jumpf);
01800 }
01801 
01802 bool HexagonInstrInfo::PredOpcodeHasNot(Opcode_t Opcode) const {
01803   return (Opcode == Hexagon::J2_jumpf) ||
01804          (Opcode == Hexagon::J2_jumpfnewpt) ||
01805          (Opcode == Hexagon::J2_jumpfnew);
01806 }