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HexagonInstrInfo.cpp
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00001 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the Hexagon implementation of the TargetInstrInfo class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "HexagonInstrInfo.h"
00015 #include "Hexagon.h"
00016 #include "HexagonRegisterInfo.h"
00017 #include "HexagonSubtarget.h"
00018 #include "llvm/ADT/STLExtras.h"
00019 #include "llvm/ADT/SmallVector.h"
00020 #include "llvm/CodeGen/DFAPacketizer.h"
00021 #include "llvm/CodeGen/MachineFrameInfo.h"
00022 #include "llvm/CodeGen/MachineInstrBuilder.h"
00023 #include "llvm/CodeGen/MachineMemOperand.h"
00024 #include "llvm/CodeGen/MachineRegisterInfo.h"
00025 #include "llvm/CodeGen/PseudoSourceValue.h"
00026 #include "llvm/Support/Debug.h"
00027 #include "llvm/Support/MathExtras.h"
00028 #include "llvm/Support/raw_ostream.h"
00029 
00030 using namespace llvm;
00031 
00032 #define DEBUG_TYPE "hexagon-instrinfo"
00033 
00034 #define GET_INSTRINFO_CTOR_DTOR
00035 #define GET_INSTRMAP_INFO
00036 #include "HexagonGenInstrInfo.inc"
00037 #include "HexagonGenDFAPacketizer.inc"
00038 
00039 ///
00040 /// Constants for Hexagon instructions.
00041 ///
00042 const int Hexagon_MEMW_OFFSET_MAX = 4095;
00043 const int Hexagon_MEMW_OFFSET_MIN = -4096;
00044 const int Hexagon_MEMD_OFFSET_MAX = 8191;
00045 const int Hexagon_MEMD_OFFSET_MIN = -8192;
00046 const int Hexagon_MEMH_OFFSET_MAX = 2047;
00047 const int Hexagon_MEMH_OFFSET_MIN = -2048;
00048 const int Hexagon_MEMB_OFFSET_MAX = 1023;
00049 const int Hexagon_MEMB_OFFSET_MIN = -1024;
00050 const int Hexagon_ADDI_OFFSET_MAX = 32767;
00051 const int Hexagon_ADDI_OFFSET_MIN = -32768;
00052 const int Hexagon_MEMD_AUTOINC_MAX = 56;
00053 const int Hexagon_MEMD_AUTOINC_MIN = -64;
00054 const int Hexagon_MEMW_AUTOINC_MAX = 28;
00055 const int Hexagon_MEMW_AUTOINC_MIN = -32;
00056 const int Hexagon_MEMH_AUTOINC_MAX = 14;
00057 const int Hexagon_MEMH_AUTOINC_MIN = -16;
00058 const int Hexagon_MEMB_AUTOINC_MAX = 7;
00059 const int Hexagon_MEMB_AUTOINC_MIN = -8;
00060 
00061 // Pin the vtable to this file.
00062 void HexagonInstrInfo::anchor() {}
00063 
00064 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
00065     : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
00066       RI(), Subtarget(ST) {}
00067 
00068 /// isLoadFromStackSlot - If the specified machine instruction is a direct
00069 /// load from a stack slot, return the virtual or physical register number of
00070 /// the destination along with the FrameIndex of the loaded stack slot.  If
00071 /// not, return 0.  This predicate must return 0 if the instruction has
00072 /// any side effects other than loading from the stack slot.
00073 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
00074                                              int &FrameIndex) const {
00075 
00076 
00077   switch (MI->getOpcode()) {
00078   default: break;
00079   case Hexagon::L2_loadri_io:
00080   case Hexagon::L2_loadrd_io:
00081   case Hexagon::L2_loadrh_io:
00082   case Hexagon::L2_loadrb_io:
00083   case Hexagon::L2_loadrub_io:
00084     if (MI->getOperand(2).isFI() &&
00085         MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
00086       FrameIndex = MI->getOperand(2).getIndex();
00087       return MI->getOperand(0).getReg();
00088     }
00089     break;
00090   }
00091   return 0;
00092 }
00093 
00094 
00095 /// isStoreToStackSlot - If the specified machine instruction is a direct
00096 /// store to a stack slot, return the virtual or physical register number of
00097 /// the source reg along with the FrameIndex of the loaded stack slot.  If
00098 /// not, return 0.  This predicate must return 0 if the instruction has
00099 /// any side effects other than storing to the stack slot.
00100 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
00101                                             int &FrameIndex) const {
00102   switch (MI->getOpcode()) {
00103   default: break;
00104   case Hexagon::S2_storeri_io:
00105   case Hexagon::S2_storerd_io:
00106   case Hexagon::S2_storerh_io:
00107   case Hexagon::S2_storerb_io:
00108     if (MI->getOperand(2).isFI() &&
00109         MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
00110       FrameIndex = MI->getOperand(0).getIndex();
00111       return MI->getOperand(2).getReg();
00112     }
00113     break;
00114   }
00115   return 0;
00116 }
00117 
00118 
00119 unsigned
00120 HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
00121                              MachineBasicBlock *FBB,
00122                              const SmallVectorImpl<MachineOperand> &Cond,
00123                              DebugLoc DL) const{
00124 
00125     int BOpc   = Hexagon::J2_jump;
00126     int BccOpc = Hexagon::J2_jumpt;
00127 
00128     assert(TBB && "InsertBranch must not be told to insert a fallthrough");
00129 
00130     int regPos = 0;
00131     // Check if ReverseBranchCondition has asked to reverse this branch
00132     // If we want to reverse the branch an odd number of times, we want
00133     // JMP_f.
00134     if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
00135       BccOpc = Hexagon::J2_jumpf;
00136       regPos = 1;
00137     }
00138 
00139     if (!FBB) {
00140       if (Cond.empty()) {
00141         // Due to a bug in TailMerging/CFG Optimization, we need to add a
00142         // special case handling of a predicated jump followed by an
00143         // unconditional jump. If not, Tail Merging and CFG Optimization go
00144         // into an infinite loop.
00145         MachineBasicBlock *NewTBB, *NewFBB;
00146         SmallVector<MachineOperand, 4> Cond;
00147         MachineInstr *Term = MBB.getFirstTerminator();
00148         if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
00149                                                  false)) {
00150           MachineBasicBlock *NextBB =
00151             std::next(MachineFunction::iterator(&MBB));
00152           if (NewTBB == NextBB) {
00153             ReverseBranchCondition(Cond);
00154             RemoveBranch(MBB);
00155             return InsertBranch(MBB, TBB, nullptr, Cond, DL);
00156           }
00157         }
00158         BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
00159       } else {
00160         // If Cond[0] is a basic block, insert ENDLOOP0.
00161         if (Cond[0].isMBB())
00162           BuildMI(&MBB, DL, get(Hexagon::ENDLOOP0)).addMBB(Cond[0].getMBB());
00163         else
00164           BuildMI(&MBB, DL,
00165                   get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
00166       }
00167       return 1;
00168     }
00169 
00170     // We don't handle ENDLOOP0 with a conditional branch in AnalyzeBranch.
00171     BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
00172     BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
00173     return 2;
00174 }
00175 
00176 
00177 bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
00178                                      MachineBasicBlock *&TBB,
00179                                  MachineBasicBlock *&FBB,
00180                                  SmallVectorImpl<MachineOperand> &Cond,
00181                                  bool AllowModify) const {
00182   TBB = nullptr;
00183   FBB = nullptr;
00184 
00185   // If the block has no terminators, it just falls into the block after it.
00186   MachineBasicBlock::instr_iterator I = MBB.instr_end();
00187   if (I == MBB.instr_begin())
00188     return false;
00189 
00190   // A basic block may looks like this:
00191   //
00192   //  [   insn
00193   //     EH_LABEL
00194   //      insn
00195   //      insn
00196   //      insn
00197   //     EH_LABEL
00198   //      insn     ]
00199   //
00200   // It has two succs but does not have a terminator
00201   // Don't know how to handle it.
00202   do {
00203     --I;
00204     if (I->isEHLabel())
00205       return true;
00206   } while (I != MBB.instr_begin());
00207 
00208   I = MBB.instr_end();
00209   --I;
00210 
00211   while (I->isDebugValue()) {
00212     if (I == MBB.instr_begin())
00213       return false;
00214     --I;
00215   }
00216   
00217   bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
00218                      I->getOperand(0).isMBB();
00219   // Delete the JMP if it's equivalent to a fall-through.
00220   if (AllowModify && JumpToBlock &&
00221       MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
00222     DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
00223     I->eraseFromParent();
00224     I = MBB.instr_end();
00225     if (I == MBB.instr_begin())
00226       return false;
00227     --I;
00228   }
00229   if (!isUnpredicatedTerminator(I))
00230     return false;
00231 
00232   // Get the last instruction in the block.
00233   MachineInstr *LastInst = I;
00234   MachineInstr *SecondLastInst = nullptr;
00235   // Find one more terminator if present.
00236   do {
00237     if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(I)) {
00238       if (!SecondLastInst)
00239         SecondLastInst = I;
00240       else
00241         // This is a third branch.
00242         return true;
00243     }
00244     if (I == MBB.instr_begin())
00245       break;
00246     --I;
00247   } while(I);
00248 
00249   int LastOpcode = LastInst->getOpcode();
00250   int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
00251   // If the branch target is not a basic block, it could be a tail call.
00252   // (It is, if the target is a function.)
00253   if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
00254     return true;
00255   if (SecLastOpcode == Hexagon::J2_jump &&
00256       !SecondLastInst->getOperand(0).isMBB())
00257     return true;
00258 
00259   bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
00260   bool LastOpcodeHasNot = PredOpcodeHasNot(LastOpcode);
00261 
00262   // If there is only one terminator instruction, process it.
00263   if (LastInst && !SecondLastInst) {
00264     if (LastOpcode == Hexagon::J2_jump) {
00265       TBB = LastInst->getOperand(0).getMBB();
00266       return false;
00267     }
00268     if (LastOpcode == Hexagon::ENDLOOP0) {
00269       TBB = LastInst->getOperand(0).getMBB();
00270       Cond.push_back(LastInst->getOperand(0));
00271       return false;
00272     }
00273     if (LastOpcodeHasJMP_c) {
00274       TBB = LastInst->getOperand(1).getMBB();
00275       if (LastOpcodeHasNot) {
00276         Cond.push_back(MachineOperand::CreateImm(0));
00277       }
00278       Cond.push_back(LastInst->getOperand(0));
00279       return false;
00280     }
00281     // Otherwise, don't know what this is.
00282     return true;
00283   }
00284 
00285   bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
00286   bool SecLastOpcodeHasNot = PredOpcodeHasNot(SecLastOpcode);
00287   if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
00288     TBB =  SecondLastInst->getOperand(1).getMBB();
00289     if (SecLastOpcodeHasNot)
00290       Cond.push_back(MachineOperand::CreateImm(0));
00291     Cond.push_back(SecondLastInst->getOperand(0));
00292     FBB = LastInst->getOperand(0).getMBB();
00293     return false;
00294   }
00295 
00296   // If the block ends with two Hexagon:JMPs, handle it.  The second one is not
00297   // executed, so remove it.
00298   if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
00299     TBB = SecondLastInst->getOperand(0).getMBB();
00300     I = LastInst;
00301     if (AllowModify)
00302       I->eraseFromParent();
00303     return false;
00304   }
00305 
00306   // If the block ends with an ENDLOOP, and JMP, handle it.
00307   if (SecLastOpcode == Hexagon::ENDLOOP0 &&
00308       LastOpcode == Hexagon::J2_jump) {
00309     TBB = SecondLastInst->getOperand(0).getMBB();
00310     Cond.push_back(SecondLastInst->getOperand(0));
00311     FBB = LastInst->getOperand(0).getMBB();
00312     return false;
00313   }
00314 
00315   // Otherwise, can't handle this.
00316   return true;
00317 }
00318 
00319 
00320 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
00321   MachineBasicBlock::iterator I = MBB.end();
00322   if (I == MBB.begin()) return 0;
00323   --I;
00324   unsigned Opc1 = I->getOpcode();
00325   switch (Opc1) {
00326     case Hexagon::J2_jump:
00327     case Hexagon::J2_jumpt:
00328     case Hexagon::J2_jumpf:
00329     case Hexagon::ENDLOOP0:
00330       I->eraseFromParent();
00331       break;
00332     default:
00333       return 0;
00334   }
00335 
00336   I = MBB.end();
00337 
00338   if (I == MBB.begin()) return 1;
00339   --I;
00340   unsigned Opc2 = I->getOpcode();
00341   switch (Opc2) {
00342     case Hexagon::J2_jumpt:
00343     case Hexagon::J2_jumpf:
00344     case Hexagon::ENDLOOP0:
00345       I->eraseFromParent();
00346       return 2;
00347     default:
00348       return 1;
00349   }
00350 }
00351 
00352 
00353 /// \brief For a comparison instruction, return the source registers in
00354 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
00355 /// compares against in CmpValue. Return true if the comparison instruction
00356 /// can be analyzed.
00357 bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
00358                                       unsigned &SrcReg, unsigned &SrcReg2,
00359                                       int &Mask, int &Value) const {
00360   unsigned Opc = MI->getOpcode();
00361 
00362   // Set mask and the first source register.
00363   switch (Opc) {
00364     case Hexagon::C2_cmpeqp:
00365     case Hexagon::C2_cmpeqi:
00366     case Hexagon::C2_cmpeq:
00367     case Hexagon::C2_cmpgtp:
00368     case Hexagon::C2_cmpgtup:
00369     case Hexagon::C2_cmpgtui:
00370     case Hexagon::C2_cmpgtu:
00371     case Hexagon::C2_cmpgti:
00372     case Hexagon::C2_cmpgt:
00373       SrcReg = MI->getOperand(1).getReg();
00374       Mask = ~0;
00375       break;
00376     case Hexagon::A4_cmpbeqi:
00377     case Hexagon::A4_cmpbeq:
00378     case Hexagon::A4_cmpbgtui:
00379     case Hexagon::A4_cmpbgtu:
00380     case Hexagon::A4_cmpbgt:
00381       SrcReg = MI->getOperand(1).getReg();
00382       Mask = 0xFF;
00383       break;
00384     case Hexagon::A4_cmpheqi:
00385     case Hexagon::A4_cmpheq:
00386     case Hexagon::A4_cmphgtui:
00387     case Hexagon::A4_cmphgtu:
00388     case Hexagon::A4_cmphgt:
00389       SrcReg = MI->getOperand(1).getReg();
00390       Mask = 0xFFFF;
00391       break;
00392   }
00393 
00394   // Set the value/second source register.
00395   switch (Opc) {
00396     case Hexagon::C2_cmpeqp:
00397     case Hexagon::C2_cmpeq:
00398     case Hexagon::C2_cmpgtp:
00399     case Hexagon::C2_cmpgtup:
00400     case Hexagon::C2_cmpgtu:
00401     case Hexagon::C2_cmpgt:
00402     case Hexagon::A4_cmpbeq:
00403     case Hexagon::A4_cmpbgtu:
00404     case Hexagon::A4_cmpbgt:
00405     case Hexagon::A4_cmpheq:
00406     case Hexagon::A4_cmphgtu:
00407     case Hexagon::A4_cmphgt:
00408       SrcReg2 = MI->getOperand(2).getReg();
00409       return true;
00410 
00411     case Hexagon::C2_cmpeqi:
00412     case Hexagon::C2_cmpgtui:
00413     case Hexagon::C2_cmpgti:
00414     case Hexagon::A4_cmpbeqi:
00415     case Hexagon::A4_cmpbgtui:
00416     case Hexagon::A4_cmpheqi:
00417     case Hexagon::A4_cmphgtui:
00418       SrcReg2 = 0;
00419       Value = MI->getOperand(2).getImm();
00420       return true;
00421   }
00422 
00423   return false;
00424 }
00425 
00426 
00427 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
00428                                  MachineBasicBlock::iterator I, DebugLoc DL,
00429                                  unsigned DestReg, unsigned SrcReg,
00430                                  bool KillSrc) const {
00431   if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
00432     BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg).addReg(SrcReg);
00433     return;
00434   }
00435   if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
00436     BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg).addReg(SrcReg);
00437     return;
00438   }
00439   if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
00440     // Map Pd = Ps to Pd = or(Ps, Ps).
00441     BuildMI(MBB, I, DL, get(Hexagon::C2_or),
00442             DestReg).addReg(SrcReg).addReg(SrcReg);
00443     return;
00444   }
00445   if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
00446       Hexagon::IntRegsRegClass.contains(SrcReg)) {
00447     // We can have an overlap between single and double reg: r1:0 = r0.
00448     if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
00449         // r1:0 = r0
00450         BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
00451                 Hexagon::subreg_hireg))).addImm(0);
00452     } else {
00453         // r1:0 = r1 or no overlap.
00454         BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), (RI.getSubReg(DestReg,
00455                 Hexagon::subreg_loreg))).addReg(SrcReg);
00456         BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
00457                 Hexagon::subreg_hireg))).addImm(0);
00458     }
00459     return;
00460   }
00461   if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
00462       Hexagon::IntRegsRegClass.contains(SrcReg)) {
00463     BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg).addReg(SrcReg);
00464     return;
00465   }
00466   if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
00467       Hexagon::IntRegsRegClass.contains(DestReg)) {
00468     BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg).
00469       addReg(SrcReg, getKillRegState(KillSrc));
00470     return;
00471   }
00472   if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
00473       Hexagon::PredRegsRegClass.contains(DestReg)) {
00474     BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg).
00475       addReg(SrcReg, getKillRegState(KillSrc));
00476     return;
00477   }
00478 
00479   llvm_unreachable("Unimplemented");
00480 }
00481 
00482 
00483 void HexagonInstrInfo::
00484 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
00485                     unsigned SrcReg, bool isKill, int FI,
00486                     const TargetRegisterClass *RC,
00487                     const TargetRegisterInfo *TRI) const {
00488 
00489   DebugLoc DL = MBB.findDebugLoc(I);
00490   MachineFunction &MF = *MBB.getParent();
00491   MachineFrameInfo &MFI = *MF.getFrameInfo();
00492   unsigned Align = MFI.getObjectAlignment(FI);
00493 
00494   MachineMemOperand *MMO =
00495       MF.getMachineMemOperand(
00496                       MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
00497                       MachineMemOperand::MOStore,
00498                       MFI.getObjectSize(FI),
00499                       Align);
00500 
00501   if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
00502     BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
00503           .addFrameIndex(FI).addImm(0)
00504           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00505   } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
00506     BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
00507           .addFrameIndex(FI).addImm(0)
00508           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00509   } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
00510     BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
00511           .addFrameIndex(FI).addImm(0)
00512           .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
00513   } else {
00514     llvm_unreachable("Unimplemented");
00515   }
00516 }
00517 
00518 
00519 void HexagonInstrInfo::storeRegToAddr(
00520                                  MachineFunction &MF, unsigned SrcReg,
00521                                  bool isKill,
00522                                  SmallVectorImpl<MachineOperand> &Addr,
00523                                  const TargetRegisterClass *RC,
00524                                  SmallVectorImpl<MachineInstr*> &NewMIs) const
00525 {
00526   llvm_unreachable("Unimplemented");
00527 }
00528 
00529 
00530 void HexagonInstrInfo::
00531 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
00532                      unsigned DestReg, int FI,
00533                      const TargetRegisterClass *RC,
00534                      const TargetRegisterInfo *TRI) const {
00535   DebugLoc DL = MBB.findDebugLoc(I);
00536   MachineFunction &MF = *MBB.getParent();
00537   MachineFrameInfo &MFI = *MF.getFrameInfo();
00538   unsigned Align = MFI.getObjectAlignment(FI);
00539 
00540   MachineMemOperand *MMO =
00541       MF.getMachineMemOperand(
00542                       MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
00543                       MachineMemOperand::MOLoad,
00544                       MFI.getObjectSize(FI),
00545                       Align);
00546   if (RC == &Hexagon::IntRegsRegClass) {
00547     BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
00548           .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00549   } else if (RC == &Hexagon::DoubleRegsRegClass) {
00550     BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
00551           .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00552   } else if (RC == &Hexagon::PredRegsRegClass) {
00553     BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
00554           .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
00555   } else {
00556     llvm_unreachable("Can't store this register to stack slot");
00557   }
00558 }
00559 
00560 
00561 void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
00562                                         SmallVectorImpl<MachineOperand> &Addr,
00563                                         const TargetRegisterClass *RC,
00564                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
00565   llvm_unreachable("Unimplemented");
00566 }
00567 bool
00568 HexagonInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
00569   const HexagonRegisterInfo &TRI = getRegisterInfo();
00570   MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
00571   MachineBasicBlock &MBB = *MI->getParent();
00572   DebugLoc DL = MI->getDebugLoc();
00573   unsigned Opc = MI->getOpcode();
00574 
00575   switch (Opc) {
00576     case Hexagon::TFR_PdTrue: {
00577       unsigned Reg = MI->getOperand(0).getReg();
00578       BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
00579         .addReg(Reg, RegState::Undef)
00580         .addReg(Reg, RegState::Undef);
00581       MBB.erase(MI);
00582       return true;
00583     }
00584     case Hexagon::TFR_PdFalse: {
00585       unsigned Reg = MI->getOperand(0).getReg();
00586       BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
00587         .addReg(Reg, RegState::Undef)
00588         .addReg(Reg, RegState::Undef);
00589       MBB.erase(MI);
00590       return true;
00591     }
00592     case Hexagon::VMULW: {
00593       // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
00594       unsigned DstReg = MI->getOperand(0).getReg();
00595       unsigned Src1Reg = MI->getOperand(1).getReg();
00596       unsigned Src2Reg = MI->getOperand(2).getReg();
00597       unsigned Src1SubHi = TRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
00598       unsigned Src1SubLo = TRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
00599       unsigned Src2SubHi = TRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
00600       unsigned Src2SubLo = TRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
00601       BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
00602               TRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
00603           .addReg(Src2SubHi);
00604       BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
00605               TRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
00606           .addReg(Src2SubLo);
00607       MBB.erase(MI);
00608       MRI.clearKillFlags(Src1SubHi);
00609       MRI.clearKillFlags(Src1SubLo);
00610       MRI.clearKillFlags(Src2SubHi);
00611       MRI.clearKillFlags(Src2SubLo);
00612       return true;
00613     }
00614     case Hexagon::VMULW_ACC: {
00615       // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
00616       unsigned DstReg = MI->getOperand(0).getReg();
00617       unsigned Src1Reg = MI->getOperand(1).getReg();
00618       unsigned Src2Reg = MI->getOperand(2).getReg();
00619       unsigned Src3Reg = MI->getOperand(3).getReg();
00620       unsigned Src1SubHi = TRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
00621       unsigned Src1SubLo = TRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
00622       unsigned Src2SubHi = TRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
00623       unsigned Src2SubLo = TRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
00624       unsigned Src3SubHi = TRI.getSubReg(Src3Reg, Hexagon::subreg_hireg);
00625       unsigned Src3SubLo = TRI.getSubReg(Src3Reg, Hexagon::subreg_loreg);
00626       BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
00627               TRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
00628           .addReg(Src2SubHi).addReg(Src3SubHi);
00629       BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
00630               TRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
00631           .addReg(Src2SubLo).addReg(Src3SubLo);
00632       MBB.erase(MI);
00633       MRI.clearKillFlags(Src1SubHi);
00634       MRI.clearKillFlags(Src1SubLo);
00635       MRI.clearKillFlags(Src2SubHi);
00636       MRI.clearKillFlags(Src2SubLo);
00637       MRI.clearKillFlags(Src3SubHi);
00638       MRI.clearKillFlags(Src3SubLo);
00639       return true;
00640     }
00641     case Hexagon::TCRETURNi:
00642       MI->setDesc(get(Hexagon::J2_jump));
00643       return true;
00644     case Hexagon::TCRETURNr:
00645       MI->setDesc(get(Hexagon::J2_jumpr));
00646       return true;
00647   }
00648 
00649   return false;
00650 }
00651 
00652 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
00653                                                       MachineInstr *MI,
00654                                                       ArrayRef<unsigned> Ops,
00655                                                       int FI) const {
00656   // Hexagon_TODO: Implement.
00657   return nullptr;
00658 }
00659 
00660 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
00661 
00662   MachineRegisterInfo &RegInfo = MF->getRegInfo();
00663   const TargetRegisterClass *TRC;
00664   if (VT == MVT::i1) {
00665     TRC = &Hexagon::PredRegsRegClass;
00666   } else if (VT == MVT::i32 || VT == MVT::f32) {
00667     TRC = &Hexagon::IntRegsRegClass;
00668   } else if (VT == MVT::i64 || VT == MVT::f64) {
00669     TRC = &Hexagon::DoubleRegsRegClass;
00670   } else {
00671     llvm_unreachable("Cannot handle this register class");
00672   }
00673 
00674   unsigned NewReg = RegInfo.createVirtualRegister(TRC);
00675   return NewReg;
00676 }
00677 
00678 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
00679   const MCInstrDesc &MID = MI->getDesc();
00680   const uint64_t F = MID.TSFlags;
00681   if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
00682     return true;
00683 
00684   // TODO: This is largely obsolete now. Will need to be removed
00685   // in consecutive patches.
00686   switch(MI->getOpcode()) {
00687     // TFR_FI Remains a special case.
00688     case Hexagon::TFR_FI:
00689       return true;
00690     default:
00691       return false;
00692   }
00693   return  false;
00694 }
00695 
00696 // This returns true in two cases:
00697 // - The OP code itself indicates that this is an extended instruction.
00698 // - One of MOs has been marked with HMOTF_ConstExtended flag.
00699 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
00700   // First check if this is permanently extended op code.
00701   const uint64_t F = MI->getDesc().TSFlags;
00702   if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
00703     return true;
00704   // Use MO operand flags to determine if one of MI's operands
00705   // has HMOTF_ConstExtended flag set.
00706   for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
00707        E = MI->operands_end(); I != E; ++I) {
00708     if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
00709       return true;
00710   }
00711   return  false;
00712 }
00713 
00714 bool HexagonInstrInfo::isBranch (const MachineInstr *MI) const {
00715   return MI->getDesc().isBranch();
00716 }
00717 
00718 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
00719   if (isNewValueJump(MI))
00720     return true;
00721 
00722   if (isNewValueStore(MI))
00723     return true;
00724 
00725   return false;
00726 }
00727 
00728 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
00729   return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
00730 }
00731 
00732 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
00733   bool isPred = MI->getDesc().isPredicable();
00734 
00735   if (!isPred)
00736     return false;
00737 
00738   const int Opc = MI->getOpcode();
00739 
00740   switch(Opc) {
00741   case Hexagon::A2_tfrsi:
00742     return (isOperandExtended(MI, 1) && isConstExtended(MI)) || isInt<12>(MI->getOperand(1).getImm());
00743 
00744   case Hexagon::S2_storerd_io:
00745     return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
00746 
00747   case Hexagon::S2_storeri_io:
00748   case Hexagon::S2_storerinew_io:
00749     return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
00750 
00751   case Hexagon::S2_storerh_io:
00752   case Hexagon::S2_storerhnew_io:
00753     return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
00754 
00755   case Hexagon::S2_storerb_io:
00756   case Hexagon::S2_storerbnew_io:
00757     return isUInt<6>(MI->getOperand(1).getImm());
00758 
00759   case Hexagon::L2_loadrd_io:
00760     return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
00761 
00762   case Hexagon::L2_loadri_io:
00763     return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
00764 
00765   case Hexagon::L2_loadrh_io:
00766   case Hexagon::L2_loadruh_io:
00767     return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
00768 
00769   case Hexagon::L2_loadrb_io:
00770   case Hexagon::L2_loadrub_io:
00771     return isUInt<6>(MI->getOperand(2).getImm());
00772 
00773   case Hexagon::L2_loadrd_pi:
00774     return isShiftedInt<4,3>(MI->getOperand(3).getImm());
00775 
00776   case Hexagon::L2_loadri_pi:
00777     return isShiftedInt<4,2>(MI->getOperand(3).getImm());
00778 
00779   case Hexagon::L2_loadrh_pi:
00780   case Hexagon::L2_loadruh_pi:
00781     return isShiftedInt<4,1>(MI->getOperand(3).getImm());
00782 
00783   case Hexagon::L2_loadrb_pi:
00784   case Hexagon::L2_loadrub_pi:
00785     return isInt<4>(MI->getOperand(3).getImm());
00786 
00787   case Hexagon::S4_storeirb_io:
00788   case Hexagon::S4_storeirh_io:
00789   case Hexagon::S4_storeiri_io:
00790     return (isUInt<6>(MI->getOperand(1).getImm()) &&
00791             isInt<6>(MI->getOperand(2).getImm()));
00792 
00793   case Hexagon::A2_addi:
00794     return isInt<8>(MI->getOperand(2).getImm());
00795 
00796   case Hexagon::A2_aslh:
00797   case Hexagon::A2_asrh:
00798   case Hexagon::A2_sxtb:
00799   case Hexagon::A2_sxth:
00800   case Hexagon::A2_zxtb:
00801   case Hexagon::A2_zxth:
00802     return true;
00803   }
00804 
00805   return true;
00806 }
00807 
00808 // This function performs the following inversiones:
00809 //
00810 //  cPt    ---> cNotPt
00811 //  cNotPt ---> cPt
00812 //
00813 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
00814   int InvPredOpcode;
00815   InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
00816                                         : Hexagon::getTruePredOpcode(Opc);
00817   if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
00818     return InvPredOpcode;
00819 
00820   switch(Opc) {
00821     default: llvm_unreachable("Unexpected predicated instruction");
00822     case Hexagon::C2_ccombinewt:
00823       return Hexagon::C2_ccombinewf;
00824     case Hexagon::C2_ccombinewf:
00825       return Hexagon::C2_ccombinewt;
00826 
00827       // Dealloc_return.
00828     case Hexagon::L4_return_t:
00829       return Hexagon::L4_return_f;
00830     case Hexagon::L4_return_f:
00831       return Hexagon::L4_return_t;
00832   }
00833 }
00834 
00835 // New Value Store instructions.
00836 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
00837   const uint64_t F = MI->getDesc().TSFlags;
00838 
00839   return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
00840 }
00841 
00842 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
00843   const uint64_t F = get(Opcode).TSFlags;
00844 
00845   return ((F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask);
00846 }
00847 
00848 int HexagonInstrInfo::
00849 getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
00850   enum Hexagon::PredSense inPredSense;
00851   inPredSense = invertPredicate ? Hexagon::PredSense_false :
00852                                   Hexagon::PredSense_true;
00853   int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
00854   if (CondOpcode >= 0) // Valid Conditional opcode/instruction
00855     return CondOpcode;
00856 
00857   // This switch case will be removed once all the instructions have been
00858   // modified to use relation maps.
00859   switch(Opc) {
00860   case Hexagon::TFRI_f:
00861     return !invertPredicate ? Hexagon::TFRI_cPt_f :
00862                               Hexagon::TFRI_cNotPt_f;
00863   case Hexagon::A2_combinew:
00864     return !invertPredicate ? Hexagon::C2_ccombinewt :
00865                               Hexagon::C2_ccombinewf;
00866 
00867   // DEALLOC_RETURN.
00868   case Hexagon::L4_return:
00869     return !invertPredicate ? Hexagon::L4_return_t:
00870                               Hexagon::L4_return_f;
00871   }
00872   llvm_unreachable("Unexpected predicable instruction");
00873 }
00874 
00875 
00876 bool HexagonInstrInfo::
00877 PredicateInstruction(MachineInstr *MI,
00878                      const SmallVectorImpl<MachineOperand> &Cond) const {
00879   int Opc = MI->getOpcode();
00880   assert (isPredicable(MI) && "Expected predicable instruction");
00881   bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
00882                      (Cond[0].getImm() == 0));
00883 
00884   // This will change MI's opcode to its predicate version.
00885   // However, its operand list is still the old one, i.e. the
00886   // non-predicate one.
00887   MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
00888 
00889   int oper = -1;
00890   unsigned int GAIdx = 0;
00891 
00892   // Indicates whether the current MI has a GlobalAddress operand
00893   bool hasGAOpnd = false;
00894   std::vector<MachineOperand> tmpOpnds;
00895 
00896   // Indicates whether we need to shift operands to right.
00897   bool needShift = true;
00898 
00899   // The predicate is ALWAYS the FIRST input operand !!!
00900   if (MI->getNumOperands() == 0) {
00901     // The non-predicate version of MI does not take any operands,
00902     // i.e. no outs and no ins. In this condition, the predicate
00903     // operand will be directly placed at Operands[0]. No operand
00904     // shift is needed.
00905     // Example: BARRIER
00906     needShift = false;
00907     oper = -1;
00908   }
00909   else if (   MI->getOperand(MI->getNumOperands()-1).isReg()
00910            && MI->getOperand(MI->getNumOperands()-1).isDef()
00911            && !MI->getOperand(MI->getNumOperands()-1).isImplicit()) {
00912     // The non-predicate version of MI does not have any input operands.
00913     // In this condition, we extend the length of Operands[] by one and
00914     // copy the original last operand to the newly allocated slot.
00915     // At this moment, it is just a place holder. Later, we will put
00916     // predicate operand directly into it. No operand shift is needed.
00917     // Example: r0=BARRIER (this is a faked insn used here for illustration)
00918     MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
00919     needShift = false;
00920     oper = MI->getNumOperands() - 2;
00921   }
00922   else {
00923     // We need to right shift all input operands by one. Duplicate the
00924     // last operand into the newly allocated slot.
00925     MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
00926   }
00927 
00928   if (needShift)
00929   {
00930     // Operands[ MI->getNumOperands() - 2 ] has been copied into
00931     // Operands[ MI->getNumOperands() - 1 ], so we start from
00932     // Operands[ MI->getNumOperands() - 3 ].
00933     // oper is a signed int.
00934     // It is ok if "MI->getNumOperands()-3" is -3, -2, or -1.
00935     for (oper = MI->getNumOperands() - 3; oper >= 0; --oper)
00936     {
00937       MachineOperand &MO = MI->getOperand(oper);
00938 
00939       // Opnd[0] Opnd[1] Opnd[2] Opnd[3] Opnd[4]   Opnd[5]   Opnd[6]   Opnd[7]
00940       // <Def0>  <Def1>  <Use0>  <Use1>  <ImpDef0> <ImpDef1> <ImpUse0> <ImpUse1>
00941       //               /\~
00942       //              /||\~
00943       //               ||
00944       //        Predicate Operand here
00945       if (MO.isReg() && !MO.isUse() && !MO.isImplicit()) {
00946         break;
00947       }
00948       if (MO.isReg()) {
00949         MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
00950                                                 MO.isImplicit(), MO.isKill(),
00951                                                 MO.isDead(), MO.isUndef(),
00952                                                 MO.isDebug());
00953       }
00954       else if (MO.isImm()) {
00955         MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
00956       }
00957       else if (MO.isGlobal()) {
00958         // MI can not have more than one GlobalAddress operand.
00959         assert(hasGAOpnd == false && "MI can only have one GlobalAddress opnd");
00960 
00961         // There is no member function called "ChangeToGlobalAddress" in the
00962         // MachineOperand class (not like "ChangeToRegister" and
00963         // "ChangeToImmediate"). So we have to remove them from Operands[] list
00964         // first, and then add them back after we have inserted the predicate
00965         // operand. tmpOpnds[] is to remember these operands before we remove
00966         // them.
00967         tmpOpnds.push_back(MO);
00968 
00969         // Operands[oper] is a GlobalAddress operand;
00970         // Operands[oper+1] has been copied into Operands[oper+2];
00971         hasGAOpnd = true;
00972         GAIdx = oper;
00973         continue;
00974       }
00975       else {
00976         llvm_unreachable("Unexpected operand type");
00977       }
00978     }
00979   }
00980 
00981   int regPos = invertJump ? 1 : 0;
00982   MachineOperand PredMO = Cond[regPos];
00983 
00984   // [oper] now points to the last explicit Def. Predicate operand must be
00985   // located at [oper+1]. See diagram above.
00986   // This assumes that the predicate is always the first operand,
00987   // i.e. Operands[0+numResults], in the set of inputs
00988   // It is better to have an assert here to check this. But I don't know how
00989   // to write this assert because findFirstPredOperandIdx() would return -1
00990   if (oper < -1) oper = -1;
00991 
00992   MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
00993                                           PredMO.isImplicit(), false,
00994                                           PredMO.isDead(), PredMO.isUndef(),
00995                                           PredMO.isDebug());
00996 
00997   MachineRegisterInfo &RegInfo = MI->getParent()->getParent()->getRegInfo();
00998   RegInfo.clearKillFlags(PredMO.getReg());
00999 
01000   if (hasGAOpnd)
01001   {
01002     unsigned int i;
01003 
01004     // Operands[GAIdx] is the original GlobalAddress operand, which is
01005     // already copied into tmpOpnds[0].
01006     // Operands[GAIdx] now stores a copy of Operands[GAIdx-1]
01007     // Operands[GAIdx+1] has already been copied into Operands[GAIdx+2],
01008     // so we start from [GAIdx+2]
01009     for (i = GAIdx + 2; i < MI->getNumOperands(); ++i)
01010       tmpOpnds.push_back(MI->getOperand(i));
01011 
01012     // Remove all operands in range [ (GAIdx+1) ... (MI->getNumOperands()-1) ]
01013     // It is very important that we always remove from the end of Operands[]
01014     // MI->getNumOperands() is at least 2 if program goes to here.
01015     for (i = MI->getNumOperands() - 1; i > GAIdx; --i)
01016       MI->RemoveOperand(i);
01017 
01018     for (i = 0; i < tmpOpnds.size(); ++i)
01019       MI->addOperand(tmpOpnds[i]);
01020   }
01021 
01022   return true;
01023 }
01024 
01025 
01026 bool
01027 HexagonInstrInfo::
01028 isProfitableToIfCvt(MachineBasicBlock &MBB,
01029                     unsigned NumCycles,
01030                     unsigned ExtraPredCycles,
01031                     const BranchProbability &Probability) const {
01032   return true;
01033 }
01034 
01035 
01036 bool
01037 HexagonInstrInfo::
01038 isProfitableToIfCvt(MachineBasicBlock &TMBB,
01039                     unsigned NumTCycles,
01040                     unsigned ExtraTCycles,
01041                     MachineBasicBlock &FMBB,
01042                     unsigned NumFCycles,
01043                     unsigned ExtraFCycles,
01044                     const BranchProbability &Probability) const {
01045   return true;
01046 }
01047 
01048 // Returns true if an instruction is predicated irrespective of the predicate
01049 // sense. For example, all of the following will return true.
01050 // if (p0) R1 = add(R2, R3)
01051 // if (!p0) R1 = add(R2, R3)
01052 // if (p0.new) R1 = add(R2, R3)
01053 // if (!p0.new) R1 = add(R2, R3)
01054 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
01055   const uint64_t F = MI->getDesc().TSFlags;
01056 
01057   return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
01058 }
01059 
01060 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
01061   const uint64_t F = get(Opcode).TSFlags;
01062 
01063   return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
01064 }
01065 
01066 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
01067   const uint64_t F = MI->getDesc().TSFlags;
01068 
01069   assert(isPredicated(MI));
01070   return (!((F >> HexagonII::PredicatedFalsePos) &
01071             HexagonII::PredicatedFalseMask));
01072 }
01073 
01074 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
01075   const uint64_t F = get(Opcode).TSFlags;
01076 
01077   // Make sure that the instruction is predicated.
01078   assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
01079   return (!((F >> HexagonII::PredicatedFalsePos) &
01080             HexagonII::PredicatedFalseMask));
01081 }
01082 
01083 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
01084   const uint64_t F = MI->getDesc().TSFlags;
01085 
01086   assert(isPredicated(MI));
01087   return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
01088 }
01089 
01090 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
01091   const uint64_t F = get(Opcode).TSFlags;
01092 
01093   assert(isPredicated(Opcode));
01094   return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
01095 }
01096 
01097 // Returns true, if a ST insn can be promoted to a new-value store.
01098 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const {
01099   const uint64_t F = MI->getDesc().TSFlags;
01100 
01101   return ((F >> HexagonII::mayNVStorePos) &
01102            HexagonII::mayNVStoreMask);
01103 }
01104 
01105 bool
01106 HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
01107                                    std::vector<MachineOperand> &Pred) const {
01108   for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
01109     MachineOperand MO = MI->getOperand(oper);
01110     if (MO.isReg() && MO.isDef()) {
01111       const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
01112       if (RC == &Hexagon::PredRegsRegClass) {
01113         Pred.push_back(MO);
01114         return true;
01115       }
01116     }
01117   }
01118   return false;
01119 }
01120 
01121 
01122 bool
01123 HexagonInstrInfo::
01124 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
01125                   const SmallVectorImpl<MachineOperand> &Pred2) const {
01126   // TODO: Fix this
01127   return false;
01128 }
01129 
01130 
01131 //
01132 // We indicate that we want to reverse the branch by
01133 // inserting a 0 at the beginning of the Cond vector.
01134 //
01135 bool HexagonInstrInfo::
01136 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
01137   if (!Cond.empty() && Cond[0].isMBB())
01138     return true;
01139   if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
01140     Cond.erase(Cond.begin());
01141   } else {
01142     Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
01143   }
01144   return false;
01145 }
01146 
01147 
01148 bool HexagonInstrInfo::
01149 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
01150                           const BranchProbability &Probability) const {
01151   return (NumInstrs <= 4);
01152 }
01153 
01154 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
01155   switch (MI->getOpcode()) {
01156   default: return false;
01157   case Hexagon::L4_return:
01158   case Hexagon::L4_return_t:
01159   case Hexagon::L4_return_f:
01160   case Hexagon::L4_return_tnew_pnt:
01161   case Hexagon::L4_return_fnew_pnt:
01162   case Hexagon::L4_return_tnew_pt:
01163   case Hexagon::L4_return_fnew_pt:
01164    return true;
01165   }
01166 }
01167 
01168 
01169 bool HexagonInstrInfo::
01170 isValidOffset(const int Opcode, const int Offset) const {
01171   // This function is to check whether the "Offset" is in the correct range of
01172   // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
01173   // inserted to calculate the final address. Due to this reason, the function
01174   // assumes that the "Offset" has correct alignment.
01175   // We used to assert if the offset was not properly aligned, however,
01176   // there are cases where a misaligned pointer recast can cause this
01177   // problem, and we need to allow for it. The front end warns of such
01178   // misaligns with respect to load size.
01179 
01180   switch(Opcode) {
01181 
01182   case Hexagon::L2_loadri_io:
01183   case Hexagon::S2_storeri_io:
01184     return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
01185       (Offset <= Hexagon_MEMW_OFFSET_MAX);
01186 
01187   case Hexagon::L2_loadrd_io:
01188   case Hexagon::S2_storerd_io:
01189     return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
01190       (Offset <= Hexagon_MEMD_OFFSET_MAX);
01191 
01192   case Hexagon::L2_loadrh_io:
01193   case Hexagon::L2_loadruh_io:
01194   case Hexagon::S2_storerh_io:
01195     return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
01196       (Offset <= Hexagon_MEMH_OFFSET_MAX);
01197 
01198   case Hexagon::L2_loadrb_io:
01199   case Hexagon::S2_storerb_io:
01200   case Hexagon::L2_loadrub_io:
01201     return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
01202       (Offset <= Hexagon_MEMB_OFFSET_MAX);
01203 
01204   case Hexagon::A2_addi:
01205   case Hexagon::TFR_FI:
01206     return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
01207       (Offset <= Hexagon_ADDI_OFFSET_MAX);
01208 
01209   case Hexagon::L4_iadd_memopw_io:
01210   case Hexagon::L4_isub_memopw_io:
01211   case Hexagon::L4_add_memopw_io:
01212   case Hexagon::L4_sub_memopw_io:
01213   case Hexagon::L4_and_memopw_io:
01214   case Hexagon::L4_or_memopw_io:
01215     return (0 <= Offset && Offset <= 255);
01216 
01217   case Hexagon::L4_iadd_memoph_io:
01218   case Hexagon::L4_isub_memoph_io:
01219   case Hexagon::L4_add_memoph_io:
01220   case Hexagon::L4_sub_memoph_io:
01221   case Hexagon::L4_and_memoph_io:
01222   case Hexagon::L4_or_memoph_io:
01223     return (0 <= Offset && Offset <= 127);
01224 
01225   case Hexagon::L4_iadd_memopb_io:
01226   case Hexagon::L4_isub_memopb_io:
01227   case Hexagon::L4_add_memopb_io:
01228   case Hexagon::L4_sub_memopb_io:
01229   case Hexagon::L4_and_memopb_io:
01230   case Hexagon::L4_or_memopb_io:
01231     return (0 <= Offset && Offset <= 63);
01232 
01233   // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
01234   // any size. Later pass knows how to handle it.
01235   case Hexagon::STriw_pred:
01236   case Hexagon::LDriw_pred:
01237     return true;
01238 
01239   case Hexagon::J2_loop0i:
01240     return isUInt<10>(Offset);
01241 
01242   // INLINEASM is very special.
01243   case Hexagon::INLINEASM:
01244     return true;
01245   }
01246 
01247   llvm_unreachable("No offset range is defined for this opcode. "
01248                    "Please define it in the above switch statement!");
01249 }
01250 
01251 
01252 //
01253 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
01254 //
01255 bool HexagonInstrInfo::
01256 isValidAutoIncImm(const EVT VT, const int Offset) const {
01257 
01258   if (VT == MVT::i64) {
01259       return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
01260               Offset <= Hexagon_MEMD_AUTOINC_MAX &&
01261               (Offset & 0x7) == 0);
01262   }
01263   if (VT == MVT::i32) {
01264       return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
01265               Offset <= Hexagon_MEMW_AUTOINC_MAX &&
01266               (Offset & 0x3) == 0);
01267   }
01268   if (VT == MVT::i16) {
01269       return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
01270               Offset <= Hexagon_MEMH_AUTOINC_MAX &&
01271               (Offset & 0x1) == 0);
01272   }
01273   if (VT == MVT::i8) {
01274       return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
01275               Offset <= Hexagon_MEMB_AUTOINC_MAX);
01276   }
01277   llvm_unreachable("Not an auto-inc opc!");
01278 }
01279 
01280 
01281 bool HexagonInstrInfo::
01282 isMemOp(const MachineInstr *MI) const {
01283 //  return MI->getDesc().mayLoad() && MI->getDesc().mayStore();
01284 
01285   switch (MI->getOpcode())
01286   {
01287   default: return false;
01288   case Hexagon::L4_iadd_memopw_io:
01289   case Hexagon::L4_isub_memopw_io:
01290   case Hexagon::L4_add_memopw_io:
01291   case Hexagon::L4_sub_memopw_io:
01292   case Hexagon::L4_and_memopw_io:
01293   case Hexagon::L4_or_memopw_io:
01294   case Hexagon::L4_iadd_memoph_io:
01295   case Hexagon::L4_isub_memoph_io:
01296   case Hexagon::L4_add_memoph_io:
01297   case Hexagon::L4_sub_memoph_io:
01298   case Hexagon::L4_and_memoph_io:
01299   case Hexagon::L4_or_memoph_io:
01300   case Hexagon::L4_iadd_memopb_io:
01301   case Hexagon::L4_isub_memopb_io:
01302   case Hexagon::L4_add_memopb_io:
01303   case Hexagon::L4_sub_memopb_io:
01304   case Hexagon::L4_and_memopb_io:
01305   case Hexagon::L4_or_memopb_io:
01306   case Hexagon::L4_ior_memopb_io:
01307   case Hexagon::L4_ior_memoph_io:
01308   case Hexagon::L4_ior_memopw_io:
01309   case Hexagon::L4_iand_memopb_io:
01310   case Hexagon::L4_iand_memoph_io:
01311   case Hexagon::L4_iand_memopw_io:
01312     return true;
01313   }
01314   return false;
01315 }
01316 
01317 
01318 bool HexagonInstrInfo::
01319 isSpillPredRegOp(const MachineInstr *MI) const {
01320   switch (MI->getOpcode()) {
01321     default: return false;
01322     case Hexagon::STriw_pred :
01323     case Hexagon::LDriw_pred :
01324       return true;
01325   }
01326 }
01327 
01328 bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
01329   switch (MI->getOpcode()) {
01330     default: return false;
01331     case Hexagon::C2_cmpeq:
01332     case Hexagon::C2_cmpeqi:
01333     case Hexagon::C2_cmpgt:
01334     case Hexagon::C2_cmpgti:
01335     case Hexagon::C2_cmpgtu:
01336     case Hexagon::C2_cmpgtui:
01337       return true;
01338   }
01339 }
01340 
01341 bool HexagonInstrInfo::
01342 isConditionalTransfer (const MachineInstr *MI) const {
01343   switch (MI->getOpcode()) {
01344     default: return false;
01345     case Hexagon::A2_tfrt:
01346     case Hexagon::A2_tfrf:
01347     case Hexagon::C2_cmoveit:
01348     case Hexagon::C2_cmoveif:
01349     case Hexagon::A2_tfrtnew:
01350     case Hexagon::A2_tfrfnew:
01351     case Hexagon::C2_cmovenewit:
01352     case Hexagon::C2_cmovenewif:
01353       return true;
01354   }
01355 }
01356 
01357 bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
01358   switch (MI->getOpcode())
01359   {
01360     default: return false;
01361     case Hexagon::A2_paddf:
01362     case Hexagon::A2_paddfnew:
01363     case Hexagon::A2_paddt:
01364     case Hexagon::A2_paddtnew:
01365     case Hexagon::A2_pandf:
01366     case Hexagon::A2_pandfnew:
01367     case Hexagon::A2_pandt:
01368     case Hexagon::A2_pandtnew:
01369     case Hexagon::A4_paslhf:
01370     case Hexagon::A4_paslhfnew:
01371     case Hexagon::A4_paslht:
01372     case Hexagon::A4_paslhtnew:
01373     case Hexagon::A4_pasrhf:
01374     case Hexagon::A4_pasrhfnew:
01375     case Hexagon::A4_pasrht:
01376     case Hexagon::A4_pasrhtnew:
01377     case Hexagon::A2_porf:
01378     case Hexagon::A2_porfnew:
01379     case Hexagon::A2_port:
01380     case Hexagon::A2_portnew:
01381     case Hexagon::A2_psubf:
01382     case Hexagon::A2_psubfnew:
01383     case Hexagon::A2_psubt:
01384     case Hexagon::A2_psubtnew:
01385     case Hexagon::A2_pxorf:
01386     case Hexagon::A2_pxorfnew:
01387     case Hexagon::A2_pxort:
01388     case Hexagon::A2_pxortnew:
01389     case Hexagon::A4_psxthf:
01390     case Hexagon::A4_psxthfnew:
01391     case Hexagon::A4_psxtht:
01392     case Hexagon::A4_psxthtnew:
01393     case Hexagon::A4_psxtbf:
01394     case Hexagon::A4_psxtbfnew:
01395     case Hexagon::A4_psxtbt:
01396     case Hexagon::A4_psxtbtnew:
01397     case Hexagon::A4_pzxtbf:
01398     case Hexagon::A4_pzxtbfnew:
01399     case Hexagon::A4_pzxtbt:
01400     case Hexagon::A4_pzxtbtnew:
01401     case Hexagon::A4_pzxthf:
01402     case Hexagon::A4_pzxthfnew:
01403     case Hexagon::A4_pzxtht:
01404     case Hexagon::A4_pzxthtnew:
01405     case Hexagon::A2_paddit:
01406     case Hexagon::A2_paddif:
01407     case Hexagon::C2_ccombinewt:
01408     case Hexagon::C2_ccombinewf:
01409       return true;
01410   }
01411 }
01412 
01413 bool HexagonInstrInfo::
01414 isConditionalLoad (const MachineInstr* MI) const {
01415   switch (MI->getOpcode())
01416   {
01417     default: return false;
01418     case Hexagon::L2_ploadrdt_io :
01419     case Hexagon::L2_ploadrdf_io:
01420     case Hexagon::L2_ploadrit_io:
01421     case Hexagon::L2_ploadrif_io:
01422     case Hexagon::L2_ploadrht_io:
01423     case Hexagon::L2_ploadrhf_io:
01424     case Hexagon::L2_ploadrbt_io:
01425     case Hexagon::L2_ploadrbf_io:
01426     case Hexagon::L2_ploadruht_io:
01427     case Hexagon::L2_ploadruhf_io:
01428     case Hexagon::L2_ploadrubt_io:
01429     case Hexagon::L2_ploadrubf_io:
01430     case Hexagon::L2_ploadrdt_pi:
01431     case Hexagon::L2_ploadrdf_pi:
01432     case Hexagon::L2_ploadrit_pi:
01433     case Hexagon::L2_ploadrif_pi:
01434     case Hexagon::L2_ploadrht_pi:
01435     case Hexagon::L2_ploadrhf_pi:
01436     case Hexagon::L2_ploadrbt_pi:
01437     case Hexagon::L2_ploadrbf_pi:
01438     case Hexagon::L2_ploadruht_pi:
01439     case Hexagon::L2_ploadruhf_pi:
01440     case Hexagon::L2_ploadrubt_pi:
01441     case Hexagon::L2_ploadrubf_pi:
01442     case Hexagon::L4_ploadrdt_rr:
01443     case Hexagon::L4_ploadrdf_rr:
01444     case Hexagon::L4_ploadrbt_rr:
01445     case Hexagon::L4_ploadrbf_rr:
01446     case Hexagon::L4_ploadrubt_rr:
01447     case Hexagon::L4_ploadrubf_rr:
01448     case Hexagon::L4_ploadrht_rr:
01449     case Hexagon::L4_ploadrhf_rr:
01450     case Hexagon::L4_ploadruht_rr:
01451     case Hexagon::L4_ploadruhf_rr:
01452     case Hexagon::L4_ploadrit_rr:
01453     case Hexagon::L4_ploadrif_rr:
01454       return true;
01455   }
01456 }
01457 
01458 // Returns true if an instruction is a conditional store.
01459 //
01460 // Note: It doesn't include conditional new-value stores as they can't be
01461 // converted to .new predicate.
01462 //
01463 //               p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
01464 //                ^           ^
01465 //               /             \ (not OK. it will cause new-value store to be
01466 //              /               X conditional on p0.new while R2 producer is
01467 //             /                 \ on p0)
01468 //            /                   \.
01469 //     p.new store                 p.old NV store
01470 // [if(p0.new)memw(R0+#0)=R2]    [if(p0)memw(R0+#0)=R2.new]
01471 //            ^                  ^
01472 //             \                /
01473 //              \              /
01474 //               \            /
01475 //                 p.old store
01476 //             [if (p0)memw(R0+#0)=R2]
01477 //
01478 // The above diagram shows the steps involoved in the conversion of a predicated
01479 // store instruction to its .new predicated new-value form.
01480 //
01481 // The following set of instructions further explains the scenario where
01482 // conditional new-value store becomes invalid when promoted to .new predicate
01483 // form.
01484 //
01485 // { 1) if (p0) r0 = add(r1, r2)
01486 //   2) p0 = cmp.eq(r3, #0) }
01487 //
01488 //   3) if (p0) memb(r1+#0) = r0  --> this instruction can't be grouped with
01489 // the first two instructions because in instr 1, r0 is conditional on old value
01490 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
01491 // is not valid for new-value stores.
01492 bool HexagonInstrInfo::
01493 isConditionalStore (const MachineInstr* MI) const {
01494   switch (MI->getOpcode())
01495   {
01496     default: return false;
01497     case Hexagon::S4_storeirbt_io:
01498     case Hexagon::S4_storeirbf_io:
01499     case Hexagon::S4_pstorerbt_rr:
01500     case Hexagon::S4_pstorerbf_rr:
01501     case Hexagon::S2_pstorerbt_io:
01502     case Hexagon::S2_pstorerbf_io:
01503     case Hexagon::S2_pstorerbt_pi:
01504     case Hexagon::S2_pstorerbf_pi:
01505     case Hexagon::S2_pstorerdt_io:
01506     case Hexagon::S2_pstorerdf_io:
01507     case Hexagon::S4_pstorerdt_rr:
01508     case Hexagon::S4_pstorerdf_rr:
01509     case Hexagon::S2_pstorerdt_pi:
01510     case Hexagon::S2_pstorerdf_pi:
01511     case Hexagon::S2_pstorerht_io:
01512     case Hexagon::S2_pstorerhf_io:
01513     case Hexagon::S4_storeirht_io:
01514     case Hexagon::S4_storeirhf_io:
01515     case Hexagon::S4_pstorerht_rr:
01516     case Hexagon::S4_pstorerhf_rr:
01517     case Hexagon::S2_pstorerht_pi:
01518     case Hexagon::S2_pstorerhf_pi:
01519     case Hexagon::S2_pstorerit_io:
01520     case Hexagon::S2_pstorerif_io:
01521     case Hexagon::S4_storeirit_io:
01522     case Hexagon::S4_storeirif_io:
01523     case Hexagon::S4_pstorerit_rr:
01524     case Hexagon::S4_pstorerif_rr:
01525     case Hexagon::S2_pstorerit_pi:
01526     case Hexagon::S2_pstorerif_pi:
01527 
01528     // V4 global address store before promoting to dot new.
01529     case Hexagon::S4_pstorerdt_abs:
01530     case Hexagon::S4_pstorerdf_abs:
01531     case Hexagon::S4_pstorerbt_abs:
01532     case Hexagon::S4_pstorerbf_abs:
01533     case Hexagon::S4_pstorerht_abs:
01534     case Hexagon::S4_pstorerhf_abs:
01535     case Hexagon::S4_pstorerit_abs:
01536     case Hexagon::S4_pstorerif_abs:
01537       return true;
01538 
01539     // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
01540     // from the "Conditional Store" list. Because a predicated new value store
01541     // would NOT be promoted to a double dot new store. See diagram below:
01542     // This function returns yes for those stores that are predicated but not
01543     // yet promoted to predicate dot new instructions.
01544     //
01545     //                          +---------------------+
01546     //                    /-----| if (p0) memw(..)=r0 |---------\~
01547     //                   ||     +---------------------+         ||
01548     //          promote  ||       /\       /\                   ||  promote
01549     //                   ||      /||\     /||\                  ||
01550     //                  \||/    demote     ||                  \||/
01551     //                   \/       ||       ||                   \/
01552     //       +-------------------------+   ||   +-------------------------+
01553     //       | if (p0.new) memw(..)=r0 |   ||   | if (p0) memw(..)=r0.new |
01554     //       +-------------------------+   ||   +-------------------------+
01555     //                        ||           ||         ||
01556     //                        ||         demote      \||/
01557     //                      promote        ||         \/ NOT possible
01558     //                        ||           ||         /\~
01559     //                       \||/          ||        /||\~
01560     //                        \/           ||         ||
01561     //                      +-----------------------------+
01562     //                      | if (p0.new) memw(..)=r0.new |
01563     //                      +-----------------------------+
01564     //                           Double Dot New Store
01565     //
01566   }
01567 }
01568 
01569 
01570 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
01571   if (isNewValue(MI) && isBranch(MI))
01572     return true;
01573   return false;
01574 }
01575 
01576 bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
01577   return (getAddrMode(MI) == HexagonII::PostInc);
01578 }
01579 
01580 bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
01581   const uint64_t F = MI->getDesc().TSFlags;
01582   return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
01583 }
01584 
01585 // Returns true, if any one of the operands is a dot new
01586 // insn, whether it is predicated dot new or register dot new.
01587 bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
01588   return (isNewValueInst(MI) ||
01589      (isPredicated(MI) && isPredicatedNew(MI)));
01590 }
01591 
01592 // Returns the most basic instruction for the .new predicated instructions and
01593 // new-value stores.
01594 // For example, all of the following instructions will be converted back to the
01595 // same instruction:
01596 // 1) if (p0.new) memw(R0+#0) = R1.new  --->
01597 // 2) if (p0) memw(R0+#0)= R1.new      -------> if (p0) memw(R0+#0) = R1
01598 // 3) if (p0.new) memw(R0+#0) = R1      --->
01599 //
01600 
01601 int HexagonInstrInfo::GetDotOldOp(const int opc) const {
01602   int NewOp = opc;
01603   if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
01604     NewOp = Hexagon::getPredOldOpcode(NewOp);
01605     assert(NewOp >= 0 &&
01606            "Couldn't change predicate new instruction to its old form.");
01607   }
01608 
01609   if (isNewValueStore(NewOp)) { // Convert into non-new-value format
01610     NewOp = Hexagon::getNonNVStore(NewOp);
01611     assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
01612   }
01613   return NewOp;
01614 }
01615 
01616 // Return the new value instruction for a given store.
01617 int HexagonInstrInfo::GetDotNewOp(const MachineInstr* MI) const {
01618   int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
01619   if (NVOpcode >= 0) // Valid new-value store instruction.
01620     return NVOpcode;
01621 
01622   switch (MI->getOpcode()) {
01623   default: llvm_unreachable("Unknown .new type");
01624   case Hexagon::S4_storerb_ur:
01625     return Hexagon::S4_storerbnew_ur;
01626 
01627   case Hexagon::S4_storerh_ur:
01628     return Hexagon::S4_storerhnew_ur;
01629 
01630   case Hexagon::S4_storeri_ur:
01631     return Hexagon::S4_storerinew_ur;
01632 
01633   case Hexagon::S2_storerb_pci:
01634     return Hexagon::S2_storerb_pci;
01635 
01636   case Hexagon::S2_storeri_pci:
01637     return Hexagon::S2_storeri_pci;
01638 
01639   case Hexagon::S2_storerh_pci:
01640     return Hexagon::S2_storerh_pci;
01641 
01642   case Hexagon::S2_storerd_pci:
01643     return Hexagon::S2_storerd_pci;
01644 
01645   case Hexagon::S2_storerf_pci:
01646     return Hexagon::S2_storerf_pci;
01647   }
01648   return 0;
01649 }
01650 
01651 // Return .new predicate version for an instruction.
01652 int HexagonInstrInfo::GetDotNewPredOp(MachineInstr *MI,
01653                                       const MachineBranchProbabilityInfo
01654                                       *MBPI) const {
01655 
01656   int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
01657   if (NewOpcode >= 0) // Valid predicate new instruction
01658     return NewOpcode;
01659 
01660   switch (MI->getOpcode()) {
01661   default: llvm_unreachable("Unknown .new type");
01662   // Condtional Jumps
01663   case Hexagon::J2_jumpt:
01664   case Hexagon::J2_jumpf:
01665     return getDotNewPredJumpOp(MI, MBPI);
01666 
01667   case Hexagon::J2_jumprt:
01668     return Hexagon::J2_jumptnewpt;
01669 
01670   case Hexagon::J2_jumprf:
01671     return Hexagon::J2_jumprfnewpt;
01672 
01673   case Hexagon::JMPrett:
01674     return Hexagon::J2_jumprtnewpt;
01675 
01676   case Hexagon::JMPretf:
01677     return Hexagon::J2_jumprfnewpt;
01678 
01679 
01680   // Conditional combine
01681   case Hexagon::C2_ccombinewt:
01682     return Hexagon::C2_ccombinewnewt;
01683   case Hexagon::C2_ccombinewf:
01684     return Hexagon::C2_ccombinewnewf;
01685   }
01686 }
01687 
01688 
01689 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
01690   const uint64_t F = MI->getDesc().TSFlags;
01691 
01692   return((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
01693 }
01694 
01695 /// immediateExtend - Changes the instruction in place to one using an immediate
01696 /// extender.
01697 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
01698   assert((isExtendable(MI)||isConstExtended(MI)) &&
01699                                "Instruction must be extendable");
01700   // Find which operand is extendable.
01701   short ExtOpNum = getCExtOpNum(MI);
01702   MachineOperand &MO = MI->getOperand(ExtOpNum);
01703   // This needs to be something we understand.
01704   assert((MO.isMBB() || MO.isImm()) &&
01705          "Branch with unknown extendable field type");
01706   // Mark given operand as extended.
01707   MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
01708 }
01709 
01710 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
01711     const TargetSubtargetInfo &STI) const {
01712   const InstrItineraryData *II = STI.getInstrItineraryData();
01713   return static_cast<const HexagonSubtarget &>(STI).createDFAPacketizer(II);
01714 }
01715 
01716 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
01717                                             const MachineBasicBlock *MBB,
01718                                             const MachineFunction &MF) const {
01719   // Debug info is never a scheduling boundary. It's necessary to be explicit
01720   // due to the special treatment of IT instructions below, otherwise a
01721   // dbg_value followed by an IT will result in the IT instruction being
01722   // considered a scheduling hazard, which is wrong. It should be the actual
01723   // instruction preceding the dbg_value instruction(s), just like it is
01724   // when debug info is not present.
01725   if (MI->isDebugValue())
01726     return false;
01727 
01728   // Terminators and labels can't be scheduled around.
01729   if (MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm())
01730     return true;
01731 
01732   return false;
01733 }
01734 
01735 bool HexagonInstrInfo::isConstExtended(MachineInstr *MI) const {
01736   const uint64_t F = MI->getDesc().TSFlags;
01737   unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
01738   if (isExtended) // Instruction must be extended.
01739     return true;
01740 
01741   unsigned isExtendable = (F >> HexagonII::ExtendablePos)
01742                           & HexagonII::ExtendableMask;
01743   if (!isExtendable)
01744     return false;
01745 
01746   short ExtOpNum = getCExtOpNum(MI);
01747   const MachineOperand &MO = MI->getOperand(ExtOpNum);
01748   // Use MO operand flags to determine if MO
01749   // has the HMOTF_ConstExtended flag set.
01750   if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
01751     return true;
01752   // If this is a Machine BB address we are talking about, and it is
01753   // not marked as extended, say so.
01754   if (MO.isMBB())
01755     return false;
01756 
01757   // We could be using an instruction with an extendable immediate and shoehorn
01758   // a global address into it. If it is a global address it will be constant
01759   // extended. We do this for COMBINE.
01760   // We currently only handle isGlobal() because it is the only kind of
01761   // object we are going to end up with here for now.
01762   // In the future we probably should add isSymbol(), etc.
01763   if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress())
01764     return true;
01765 
01766   // If the extendable operand is not 'Immediate' type, the instruction should
01767   // have 'isExtended' flag set.
01768   assert(MO.isImm() && "Extendable operand must be Immediate type");
01769 
01770   int MinValue = getMinValue(MI);
01771   int MaxValue = getMaxValue(MI);
01772   int ImmValue = MO.getImm();
01773 
01774   return (ImmValue < MinValue || ImmValue > MaxValue);
01775 }
01776 
01777 // Returns the opcode to use when converting MI, which is a conditional jump,
01778 // into a conditional instruction which uses the .new value of the predicate.
01779 // We also use branch probabilities to add a hint to the jump.
01780 int
01781 HexagonInstrInfo::getDotNewPredJumpOp(MachineInstr *MI,
01782                                   const
01783                                   MachineBranchProbabilityInfo *MBPI) const {
01784 
01785   // We assume that block can have at most two successors.
01786   bool taken = false;
01787   MachineBasicBlock *Src = MI->getParent();
01788   MachineOperand *BrTarget = &MI->getOperand(1);
01789   MachineBasicBlock *Dst = BrTarget->getMBB();
01790 
01791   const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
01792   if (Prediction >= BranchProbability(1,2))
01793     taken = true;
01794 
01795   switch (MI->getOpcode()) {
01796   case Hexagon::J2_jumpt:
01797     return taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
01798   case Hexagon::J2_jumpf:
01799     return taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
01800 
01801   default:
01802     llvm_unreachable("Unexpected jump instruction.");
01803   }
01804 }
01805 // Returns true if a particular operand is extendable for an instruction.
01806 bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
01807                                          unsigned short OperandNum) const {
01808   const uint64_t F = MI->getDesc().TSFlags;
01809 
01810   return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
01811           == OperandNum;
01812 }
01813 
01814 // Returns Operand Index for the constant extended instruction.
01815 unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
01816   const uint64_t F = MI->getDesc().TSFlags;
01817   return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
01818 }
01819 
01820 // Returns the min value that doesn't need to be extended.
01821 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
01822   const uint64_t F = MI->getDesc().TSFlags;
01823   unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
01824                     & HexagonII::ExtentSignedMask;
01825   unsigned bits =  (F >> HexagonII::ExtentBitsPos)
01826                     & HexagonII::ExtentBitsMask;
01827 
01828   if (isSigned) // if value is signed
01829     return -1U << (bits - 1);
01830   else
01831     return 0;
01832 }
01833 
01834 // Returns the max value that doesn't need to be extended.
01835 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
01836   const uint64_t F = MI->getDesc().TSFlags;
01837   unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
01838                     & HexagonII::ExtentSignedMask;
01839   unsigned bits =  (F >> HexagonII::ExtentBitsPos)
01840                     & HexagonII::ExtentBitsMask;
01841 
01842   if (isSigned) // if value is signed
01843     return ~(-1U << (bits - 1));
01844   else
01845     return ~(-1U << bits);
01846 }
01847 
01848 // Returns true if an instruction can be converted into a non-extended
01849 // equivalent instruction.
01850 bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr *MI) const {
01851 
01852   short NonExtOpcode;
01853   // Check if the instruction has a register form that uses register in place
01854   // of the extended operand, if so return that as the non-extended form.
01855   if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
01856     return true;
01857 
01858   if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
01859     // Check addressing mode and retrieve non-ext equivalent instruction.
01860 
01861     switch (getAddrMode(MI)) {
01862     case HexagonII::Absolute :
01863       // Load/store with absolute addressing mode can be converted into
01864       // base+offset mode.
01865       NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode());
01866       break;
01867     case HexagonII::BaseImmOffset :
01868       // Load/store with base+offset addressing mode can be converted into
01869       // base+register offset addressing mode. However left shift operand should
01870       // be set to 0.
01871       NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
01872       break;
01873     default:
01874       return false;
01875     }
01876     if (NonExtOpcode < 0)
01877       return false;
01878     return true;
01879   }
01880   return false;
01881 }
01882 
01883 // Returns opcode of the non-extended equivalent instruction.
01884 short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const {
01885 
01886   // Check if the instruction has a register form that uses register in place
01887   // of the extended operand, if so return that as the non-extended form.
01888   short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
01889     if (NonExtOpcode >= 0)
01890       return NonExtOpcode;
01891 
01892   if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
01893     // Check addressing mode and retrieve non-ext equivalent instruction.
01894     switch (getAddrMode(MI)) {
01895     case HexagonII::Absolute :
01896       return Hexagon::getBasedWithImmOffset(MI->getOpcode());
01897     case HexagonII::BaseImmOffset :
01898       return Hexagon::getBaseWithRegOffset(MI->getOpcode());
01899     default:
01900       return -1;
01901     }
01902   }
01903   return -1;
01904 }
01905 
01906 bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode) const {
01907   return (Opcode == Hexagon::J2_jumpt) ||
01908          (Opcode == Hexagon::J2_jumpf) ||
01909          (Opcode == Hexagon::J2_jumptnewpt) ||
01910          (Opcode == Hexagon::J2_jumpfnewpt) ||
01911          (Opcode == Hexagon::J2_jumpt) ||
01912          (Opcode == Hexagon::J2_jumpf);
01913 }
01914 
01915 bool HexagonInstrInfo::PredOpcodeHasNot(Opcode_t Opcode) const {
01916   return (Opcode == Hexagon::J2_jumpf) ||
01917          (Opcode == Hexagon::J2_jumpfnewpt) ||
01918          (Opcode == Hexagon::J2_jumpfnew);
01919 }