LLVM  6.0.0svn
Macros | Enumerations | Functions | Variables
ARMExpandPseudoInsts.cpp File Reference
#include "ARM.h"
#include "ARMBaseInstrInfo.h"
#include "ARMBaseRegisterInfo.h"
#include "ARMConstantPoolValue.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMSubtarget.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
Include dependency graph for ARMExpandPseudoInsts.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "arm-pseudo"
 
#define ARM_EXPAND_PSEUDO_NAME   "ARM pseudo instruction expansion pass"
 

Enumerations

enum  NEONRegSpacing
 

Functions

 INITIALIZE_PASS (ARMExpandPseudo, DEBUG_TYPE, ARM_EXPAND_PSEUDO_NAME, false, false) void ARMExpandPseudo
 TransferImpOps - Transfer implicit operands on the pseudo instruction to the instructions created from the expansion. More...
 
static const NEONLdStTableEntry * LookupNEONLdSt (unsigned Opcode)
 LookupNEONLdSt - Search the NEONLdStTable for information about a NEON load or store pseudo instruction. More...
 
static void GetDSubRegs (unsigned Reg, NEONRegSpacing RegSpc, const TargetRegisterInfo *TRI, unsigned &D0, unsigned &D1, unsigned &D2, unsigned &D3)
 GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, corresponding to the specified register spacing. More...
 
static bool IsAnAddressOperand (const MachineOperand &MO)
 
static MachineOperand makeImplicit (const MachineOperand &MO)
 
static void addExclusiveRegPair (MachineInstrBuilder &MIB, MachineOperand &Reg, unsigned Flags, bool IsThumb, const TargetRegisterInfo *TRI)
 ARM's ldrexd/strexd take a consecutive register pair (represented as a single GPRPair register), Thumb's take two separate registers so we need to extract the subregs from the pair. More...
 

Variables

static cl::opt< boolVerifyARMPseudo ("verify-arm-pseudo-expand", cl::Hidden, cl::desc("Verify machine code after expanding ARM pseudos"))
 
static const NEONLdStTableEntry NEONLdStTable []
 

Macro Definition Documentation

◆ ARM_EXPAND_PSEUDO_NAME

#define ARM_EXPAND_PSEUDO_NAME   "ARM pseudo instruction expansion pass"

Definition at line 36 of file ARMExpandPseudoInsts.cpp.

◆ DEBUG_TYPE

#define DEBUG_TYPE   "arm-pseudo"

Definition at line 30 of file ARMExpandPseudoInsts.cpp.

Enumeration Type Documentation

◆ NEONRegSpacing

Definition at line 111 of file ARMExpandPseudoInsts.cpp.

Function Documentation

◆ addExclusiveRegPair()

static void addExclusiveRegPair ( MachineInstrBuilder MIB,
MachineOperand Reg,
unsigned  Flags,
bool  IsThumb,
const TargetRegisterInfo TRI 
)
static

ARM's ldrexd/strexd take a consecutive register pair (represented as a single GPRPair register), Thumb's take two separate registers so we need to extract the subregs from the pair.

Definition at line 879 of file ARMExpandPseudoInsts.cpp.

References llvm::ARM_AM::add, llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addExternalSymbol(), llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::addRegisterKilled(), llvm::MachineBasicBlock::addSuccessor(), llvm::ARMCC::AL, llvm::ARM_AM::asr, assert(), llvm::MachineBasicBlock::begin(), llvm::ARCISD::BL, llvm::BuildMI(), llvm::computeAndAddLiveIns(), llvm::condCodeOp(), llvm::ARMCP::CPValue, llvm::ARMConstantPoolConstant::Create(), llvm::ARMConstantPoolSymbol::Create(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::RegState::Define, E, llvm::emitARMRegPlusImmediate(), llvm::emitT2RegPlusImmediate(), llvm::emitThumbRegPlusImmediate(), llvm::MachineBasicBlock::end(), llvm::ARMCC::EQ, llvm::MachineBasicBlock::erase(), llvm::MachineInstr::eraseFromParent(), FramePtr, llvm::MachineBasicBlock::getBasicBlock(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), llvm::Function::getContext(), llvm::getDeadRegState(), llvm::MachineInstr::getDebugLoc(), llvm::MachineFunction::getFrameInfo(), llvm::TargetSubtargetInfo::getFrameLowering(), llvm::ARMBaseRegisterInfo::getFrameRegister(), llvm::MachineFunction::getFunction(), llvm::MachineOperand::getGlobal(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getInfo(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::getKillRegState(), llvm::MachineBasicBlock::getLastNonDebugInstr(), llvm::MachineFrameInfo::getMaxAlignment(), llvm::MachineOperand::getOffset(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::ARMBaseInstrInfo::getRegisterInfo(), llvm::ARM_AM::getSORegOpc(), llvm::MCRegisterInfo::getSubReg(), llvm::MachineFunction::getSubtarget(), llvm::MachineOperand::getSymbolName(), llvm::MachineOperand::getTargetFlags(), llvm::ARMCP::GOT_PREL, llvm::ARMBaseRegisterInfo::hasBasePointer(), llvm::TargetFrameLowering::hasFP(), llvm::RegState::ImplicitDefine, llvm::MachineFunction::insert(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isSymbol(), llvm::MachineOperand::isUndef(), llvm::RegState::Kill, llvm_unreachable, llvm::ARM_AM::lsr, makeImplicit(), llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_end(), MI, llvm::ARMII::MO_HI16, llvm::ARMII::MO_LO16, Modified, llvm::ARMCC::NE, llvm::ARMCP::no_modifier, llvm::predOps(), R6, llvm::ARM_AM::rrx, llvm::ARMISD::RRX, llvm::MachineOperand::setIsKill(), llvm::MachineInstrBuilder::setMemRefs(), llvm::MachineInstr::setMemRefs(), TII, llvm::RegState::Undef, llvm::AArch64_AM::UXTB, llvm::AArch64_AM::UXTH, and VerifyARMPseudo.

◆ GetDSubRegs()

static void GetDSubRegs ( unsigned  Reg,
NEONRegSpacing  RegSpc,
const TargetRegisterInfo TRI,
unsigned D0,
unsigned D1,
unsigned D2,
unsigned D3 
)
static

◆ INITIALIZE_PASS()

INITIALIZE_PASS ( ARMExpandPseudo  ,
DEBUG_TYPE  ,
ARM_EXPAND_PSEUDO_NAME  ,
false  ,
false   
)

TransferImpOps - Transfer implicit operands on the pseudo instruction to the instructions created from the expansion.

Definition at line 86 of file ARMExpandPseudoInsts.cpp.

References assert(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isUse().

◆ IsAnAddressOperand()

static bool IsAnAddressOperand ( const MachineOperand MO)
static

◆ LookupNEONLdSt()

static const NEONLdStTableEntry* LookupNEONLdSt ( unsigned  Opcode)
static

LookupNEONLdSt - Search the NEONLdStTable for information about a NEON load or store pseudo instruction.

Definition at line 347 of file ARMExpandPseudoInsts.cpp.

References assert(), llvm::sys::path::begin(), llvm::sys::path::end(), I, and llvm::lower_bound().

Referenced by GetDSubRegs().

◆ makeImplicit()

static MachineOperand makeImplicit ( const MachineOperand MO)
static

Definition at line 667 of file ARMExpandPseudoInsts.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addExternalSymbol(), llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::computeAndAddLiveIns(), llvm::condCodeOp(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::RegState::Define, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), llvm::finalizeBundle(), llvm::MachineBasicBlock::getBasicBlock(), llvm::getDeadRegState(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getGlobal(), llvm::MachineOperand::getImm(), llvm::getInstrPredicate(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::getKillRegState(), llvm::MachineOperand::getOffset(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::ARM_AM::getSOImmTwoPartFirst(), llvm::ARM_AM::getSOImmTwoPartSecond(), llvm::MachineOperand::getSymbolName(), llvm::MachineOperand::getTargetFlags(), llvm::MachineOperand::getType(), llvm::MachineFunction::insert(), IsAnAddressOperand(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isUndef(), llvm::RegState::Kill, llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_end(), MI, llvm::MachineOperand::MO_ExternalSymbol, llvm::ARMII::MO_HI16, llvm::MachineOperand::MO_Immediate, llvm::ARMII::MO_LO16, llvm::ARMCC::NE, llvm::predOps(), llvm::MachineOperand::setImplicit(), llvm::MachineInstr::setMemRefs(), and TII.

Referenced by addExclusiveRegPair().

Variable Documentation

◆ NEONLdStTable

const NEONLdStTableEntry NEONLdStTable[]
static

Definition at line 149 of file ARMExpandPseudoInsts.cpp.

◆ VerifyARMPseudo

cl::opt<bool> VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden, cl::desc("Verify machine code after expanding ARM pseudos"))
static

Referenced by addExclusiveRegPair().