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R600MachineScheduler.h
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1 //===-- R600MachineScheduler.h - R600 Scheduler Interface -*- C++ -*-------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// R600 Machine Scheduler interface
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H
15 #define LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H
16 
18 #include <vector>
19 
20 using namespace llvm;
21 
22 namespace llvm {
23 
24 class R600InstrInfo;
25 struct R600RegisterInfo;
26 
28  const ScheduleDAGMILive *DAG = nullptr;
29  const R600InstrInfo *TII = nullptr;
30  const R600RegisterInfo *TRI = nullptr;
31  MachineRegisterInfo *MRI = nullptr;
32 
33  enum InstKind {
34  IDAlu,
35  IDFetch,
36  IDOther,
37  IDLast
38  };
39 
40  enum AluKind {
41  AluAny,
42  AluT_X,
43  AluT_Y,
44  AluT_Z,
45  AluT_W,
46  AluT_XYZW,
47  AluPredX,
48  AluTrans,
49  AluDiscarded, // LLVM Instructions that are going to be eliminated
50  AluLast
51  };
52 
53  std::vector<SUnit *> Available[IDLast], Pending[IDLast];
54  std::vector<SUnit *> AvailableAlus[AluLast];
55  std::vector<SUnit *> PhysicalRegCopy;
56 
57  InstKind CurInstKind;
58  int CurEmitted;
59  InstKind NextInstKind;
60 
61  unsigned AluInstCount;
62  unsigned FetchInstCount;
63 
64  int InstKindLimit[IDLast];
65 
66  int OccupedSlotsMask;
67 
68 public:
69  R600SchedStrategy() = default;
70  ~R600SchedStrategy() override = default;
71 
72  void initialize(ScheduleDAGMI *dag) override;
73  SUnit *pickNode(bool &IsTopNode) override;
74  void schedNode(SUnit *SU, bool IsTopNode) override;
75  void releaseTopNode(SUnit *SU) override;
76  void releaseBottomNode(SUnit *SU) override;
77 
78 private:
79  std::vector<MachineInstr *> InstructionsGroupCandidate;
80  bool VLIW5;
81 
82  int getInstKind(SUnit *SU);
83  bool regBelongsToClass(unsigned Reg, const TargetRegisterClass *RC) const;
84  AluKind getAluKind(SUnit *SU) const;
85  void LoadAlu();
86  unsigned AvailablesAluCount() const;
87  SUnit *AttemptFillSlot (unsigned Slot, bool AnyAlu);
88  void PrepareNextSlot();
89  SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU);
90 
91  void AssignSlot(MachineInstr *MI, unsigned Slot);
92  SUnit* pickAlu();
93  SUnit* pickOther(int QID);
94  void MoveUnits(std::vector<SUnit *> &QSrc, std::vector<SUnit *> &QDst);
95 };
96 
97 } // end namespace llvm
98 
99 #endif // LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H
void schedNode(SUnit *SU, bool IsTopNode) override
Notify MachineSchedStrategy that ScheduleDAGMI has scheduled an instruction and updated scheduled/rem...
~R600SchedStrategy() override=default
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void initialize(ScheduleDAGMI *dag) override
Initialize the strategy after building the DAG for a new region.
unsigned Reg
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
void releaseBottomNode(SUnit *SU) override
When all successor dependencies have been resolved, free this node for bottom-up scheduling.
SUnit * pickNode(bool &IsTopNode) override
Pick the next node to schedule, or return NULL.
void releaseTopNode(SUnit *SU) override
When all predecessor dependencies have been resolved, free this node for top-down scheduling...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:64
MachineSchedStrategy - Interface to the scheduling algorithm used by ScheduleDAGMI.
IRTranslator LLVM IR MI
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242