LLVM 22.0.0git
AMDGPUInstPrinter.cpp
Go to the documentation of this file.
1//===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7// \file
8//===----------------------------------------------------------------------===//
9
10#include "AMDGPUInstPrinter.h"
12#include "SIDefines.h"
15#include "llvm/MC/MCAsmInfo.h"
16#include "llvm/MC/MCExpr.h"
17#include "llvm/MC/MCInst.h"
18#include "llvm/MC/MCInstrDesc.h"
19#include "llvm/MC/MCInstrInfo.h"
23
24using namespace llvm;
25using namespace llvm::AMDGPU;
26
28 // FIXME: The current implementation of
29 // AsmParser::parseRegisterOrRegisterNumber in MC implies we either emit this
30 // as an integer or we provide a name which represents a physical register.
31 // For CFI instructions we really want to emit a name for the DWARF register
32 // instead, because there may be multiple DWARF registers corresponding to a
33 // single physical register. One case where this problem manifests is with
34 // wave32/wave64 where using the physical register name is ambiguous: if we
35 // write e.g. `.cfi_undefined v0` we lose information about the wavefront
36 // size which we need to encode the register in the final DWARF. Ideally we
37 // would extend MC to support parsing DWARF register names so we could do
38 // something like `.cfi_undefined dwarf_wave32_v0`. For now we just live with
39 // non-pretty DWARF register names in assembly text.
40 OS << Reg.id();
41}
42
44 StringRef Annot, const MCSubtargetInfo &STI,
45 raw_ostream &OS) {
46 printInstruction(MI, Address, STI, OS);
47 printAnnotation(OS, Annot);
48}
49
50void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
51 const MCSubtargetInfo &STI,
52 raw_ostream &O) {
53 const MCOperand &Op = MI->getOperand(OpNo);
54 if (Op.isExpr()) {
55 MAI.printExpr(O, *Op.getExpr());
56 return;
57 }
58
59 // It's possible to end up with a 32-bit literal used with a 16-bit operand
60 // with ignored high bits. Print as 32-bit anyway in that case.
61 int64_t Imm = Op.getImm();
62 if (isInt<16>(Imm) || isUInt<16>(Imm))
63 O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
64 else
65 printU32ImmOperand(MI, OpNo, STI, O);
66}
67
68void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
69 raw_ostream &O) {
70 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
71}
72
73void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
74 const MCSubtargetInfo &STI,
75 raw_ostream &O) {
76 const MCOperand &Op = MI->getOperand(OpNo);
77 if (Op.isExpr()) {
78 MAI.printExpr(O, *Op.getExpr());
79 return;
80 }
81
82 O << formatHex(Op.getImm() & 0xffffffff);
83}
84
85void AMDGPUInstPrinter::printFP64ImmOperand(const MCInst *MI, unsigned OpNo,
86 const MCSubtargetInfo &STI,
87 raw_ostream &O) {
88 // KIMM64
89 const MCOperand &Op = MI->getOperand(OpNo);
90 if (Op.isExpr()) {
91 MAI.printExpr(O, *Op.getExpr());
92 return;
93 }
94
95 printLiteral64(Op.getImm(), O, /*IsFP=*/true);
96}
97
98void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo,
99 raw_ostream &O, StringRef BitName) {
100 if (MI->getOperand(OpNo).getImm()) {
101 O << ' ' << BitName;
102 }
103}
104
105void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
106 const MCSubtargetInfo &STI,
107 raw_ostream &O) {
108 uint32_t Imm = MI->getOperand(OpNo).getImm();
109 if (Imm != 0) {
110 O << " offset:";
111
112 // GFX12 uses a 24-bit signed offset for VBUFFER.
113 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
114 bool IsVBuffer = Desc.TSFlags & (SIInstrFlags::MUBUF | SIInstrFlags::MTBUF);
115 if (AMDGPU::isGFX12(STI) && IsVBuffer)
116 O << formatDec(SignExtend32<24>(Imm));
117 else
118 printU16ImmDecOperand(MI, OpNo, O);
119 }
120}
121
122void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
123 const MCSubtargetInfo &STI,
124 raw_ostream &O) {
125 uint32_t Imm = MI->getOperand(OpNo).getImm();
126 if (Imm != 0) {
127 O << " offset:";
128
129 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
130 bool AllowNegative = (Desc.TSFlags & (SIInstrFlags::FlatGlobal |
132 AMDGPU::isGFX12(STI);
133
134 if (AllowNegative) // Signed offset
136 else // Unsigned offset
137 printU16ImmDecOperand(MI, OpNo, O);
138 }
139}
140
141void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
142 const MCSubtargetInfo &STI,
143 raw_ostream &O) {
144 printU32ImmOperand(MI, OpNo, STI, O);
145}
146
147void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo,
148 const MCSubtargetInfo &STI,
149 raw_ostream &O) {
150 O << formatHex(MI->getOperand(OpNo).getImm());
151}
152
153void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
154 const MCSubtargetInfo &STI,
155 raw_ostream &O) {
156 printU32ImmOperand(MI, OpNo, STI, O);
157}
158
159void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo,
160 const MCSubtargetInfo &STI, raw_ostream &O) {
161 auto Imm = MI->getOperand(OpNo).getImm();
162
163 if (AMDGPU::isGFX12Plus(STI)) {
164 const int64_t TH = Imm & CPol::TH;
165 const int64_t Scope = Imm & CPol::SCOPE;
166
167 if (Imm & CPol::SCAL)
168 O << " scale_offset";
169
170 printTH(MI, TH, Scope, O);
171 printScope(Scope, O);
172
173 if (Imm & CPol::NV)
174 O << " nv";
175
176 return;
177 }
178
179 if (Imm & CPol::GLC)
180 O << ((AMDGPU::isGFX940(STI) &&
181 !(MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SMRD)) ? " sc0"
182 : " glc");
183 if (Imm & CPol::SLC)
184 O << (AMDGPU::isGFX940(STI) ? " nt" : " slc");
185 if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI))
186 O << " dlc";
187 if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI))
188 O << (AMDGPU::isGFX940(STI) ? " sc1" : " scc");
189 if (Imm & ~CPol::ALL_pregfx12)
190 O << " /* unexpected cache policy bit */";
191}
192
193void AMDGPUInstPrinter::printTH(const MCInst *MI, int64_t TH, int64_t Scope,
194 raw_ostream &O) {
195 // For th = 0 do not print this field
196 if (TH == 0)
197 return;
198
199 const unsigned Opcode = MI->getOpcode();
200 const MCInstrDesc &TID = MII.get(Opcode);
201 unsigned THType = AMDGPU::getTemporalHintType(TID);
202 bool IsStore = (THType == AMDGPU::CPol::TH_TYPE_STORE);
203
204 O << " th:";
205
206 if (THType == AMDGPU::CPol::TH_TYPE_ATOMIC) {
207 O << "TH_ATOMIC_";
209 if (Scope >= AMDGPU::CPol::SCOPE_DEV)
210 O << "CASCADE" << (TH & AMDGPU::CPol::TH_ATOMIC_NT ? "_NT" : "_RT");
211 else
212 O << formatHex(TH);
213 } else if (TH & AMDGPU::CPol::TH_ATOMIC_NT)
214 O << "NT" << (TH & AMDGPU::CPol::TH_ATOMIC_RETURN ? "_RETURN" : "");
215 else if (TH & AMDGPU::CPol::TH_ATOMIC_RETURN)
216 O << "RETURN";
217 else
218 O << formatHex(TH);
219 } else {
220 if (!IsStore && TH == AMDGPU::CPol::TH_RESERVED)
221 O << formatHex(TH);
222 else {
223 O << (IsStore ? "TH_STORE_" : "TH_LOAD_");
224 switch (TH) {
226 O << "NT";
227 break;
229 O << "HT";
230 break;
231 case AMDGPU::CPol::TH_BYPASS: // or LU or WB
232 O << (Scope == AMDGPU::CPol::SCOPE_SYS ? "BYPASS"
233 : (IsStore ? "WB" : "LU"));
234 break;
236 O << "NT_RT";
237 break;
239 O << "RT_NT";
240 break;
242 O << "NT_HT";
243 break;
245 O << "NT_WB";
246 break;
247 default:
248 llvm_unreachable("unexpected th value");
249 }
250 }
251 }
252}
253
254void AMDGPUInstPrinter::printScope(int64_t Scope, raw_ostream &O) {
255 if (Scope == CPol::SCOPE_CU)
256 return;
257
258 O << " scope:";
259
260 if (Scope == CPol::SCOPE_SE)
261 O << "SCOPE_SE";
262 else if (Scope == CPol::SCOPE_DEV)
263 O << "SCOPE_DEV";
264 else if (Scope == CPol::SCOPE_SYS)
265 O << "SCOPE_SYS";
266 else
267 llvm_unreachable("unexpected scope policy value");
268}
269
270void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
271 const MCSubtargetInfo &STI, raw_ostream &O) {
272 unsigned Dim = MI->getOperand(OpNo).getImm();
273 O << " dim:SQ_RSRC_IMG_";
274
275 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);
276 if (DimInfo)
277 O << DimInfo->AsmSuffix;
278 else
279 O << Dim;
280}
281
282void AMDGPUInstPrinter::printR128A16(const MCInst *MI, unsigned OpNo,
283 const MCSubtargetInfo &STI, raw_ostream &O) {
284 if (STI.hasFeature(AMDGPU::FeatureR128A16))
285 printNamedBit(MI, OpNo, O, "a16");
286 else
287 printNamedBit(MI, OpNo, O, "r128");
288}
289
290void AMDGPUInstPrinter::printFORMAT(const MCInst *MI, unsigned OpNo,
291 const MCSubtargetInfo &STI,
292 raw_ostream &O) {
293}
294
295void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI,
296 const MCSubtargetInfo &STI,
297 raw_ostream &O) {
298 using namespace llvm::AMDGPU::MTBUFFormat;
299
300 int OpNo =
301 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::format);
302 assert(OpNo != -1);
303
304 unsigned Val = MI->getOperand(OpNo).getImm();
305 if (AMDGPU::isGFX10Plus(STI)) {
306 if (Val == UFMT_DEFAULT)
307 return;
308 if (isValidUnifiedFormat(Val, STI)) {
309 O << " format:[" << getUnifiedFormatName(Val, STI) << ']';
310 } else {
311 O << " format:" << Val;
312 }
313 } else {
314 if (Val == DFMT_NFMT_DEFAULT)
315 return;
316 if (isValidDfmtNfmt(Val, STI)) {
317 unsigned Dfmt;
318 unsigned Nfmt;
319 decodeDfmtNfmt(Val, Dfmt, Nfmt);
320 O << " format:[";
321 if (Dfmt != DFMT_DEFAULT) {
322 O << getDfmtName(Dfmt);
323 if (Nfmt != NFMT_DEFAULT) {
324 O << ',';
325 }
326 }
327 if (Nfmt != NFMT_DEFAULT) {
328 O << getNfmtName(Nfmt, STI);
329 }
330 O << ']';
331 } else {
332 O << " format:" << Val;
333 }
334 }
335}
336
337// \returns a low 256 vgpr representing a high vgpr \p Reg [v256..v1023] or
338// \p Reg itself otherwise.
340 unsigned Enc = MRI.getEncodingValue(Reg);
341 unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK;
342 if (Idx < 0x100)
343 return Reg;
344
345 unsigned RegNo = Idx % 0x100;
347 if (RC->getID() == AMDGPU::VGPR_16RegClassID) {
348 // This class has 2048 registers with interleaved lo16 and hi16.
349 RegNo *= 2;
351 ++RegNo;
352 }
353
354 return RC->getRegister(RegNo);
355}
356
357// Restore MSBs of a VGPR above 255 from the MCInstrAnalysis.
358static MCPhysReg getRegFromMIA(MCPhysReg Reg, unsigned OpNo,
359 const MCInstrDesc &Desc,
360 const MCRegisterInfo &MRI,
361 const AMDGPUMCInstrAnalysis &MIA) {
362 unsigned VgprMSBs = MIA.getVgprMSBs();
363 if (!VgprMSBs)
364 return Reg;
365
366 unsigned Enc = MRI.getEncodingValue(Reg);
367 if (!(Enc & AMDGPU::HWEncoding::IS_VGPR))
368 return Reg;
369
371 if (!Ops.first)
372 return Reg;
373 unsigned Opc = Desc.getOpcode();
374 unsigned I;
375 for (I = 0; I < 4; ++I) {
376 if (Ops.first[I] != AMDGPU::OpName::NUM_OPERAND_NAMES &&
377 (unsigned)AMDGPU::getNamedOperandIdx(Opc, Ops.first[I]) == OpNo)
378 break;
379 if (Ops.second && Ops.second[I] != AMDGPU::OpName::NUM_OPERAND_NAMES &&
380 (unsigned)AMDGPU::getNamedOperandIdx(Opc, Ops.second[I]) == OpNo)
381 break;
382 }
383 if (I == 4)
384 return Reg;
385 unsigned OpMSBs = (VgprMSBs >> (I * 2)) & 3;
386 if (!OpMSBs)
387 return Reg;
388 if (MCRegister NewReg = AMDGPU::getVGPRWithMSBs(Reg, OpMSBs, MRI))
389 return NewReg;
390 return Reg;
391}
392
394 const MCRegisterInfo &MRI) {
395#if !defined(NDEBUG)
396 switch (Reg.id()) {
397 case AMDGPU::FP_REG:
398 case AMDGPU::SP_REG:
399 case AMDGPU::PRIVATE_RSRC_REG:
400 llvm_unreachable("pseudo-register should not ever be emitted");
401 default:
402 break;
403 }
404#endif
405
406 unsigned PrintReg = getRegForPrinting(Reg, MRI);
407 O << getRegisterName(PrintReg);
408
409 if (PrintReg != Reg.id())
410 O << " /*" << getRegisterName(Reg) << "*/";
411}
412
414 unsigned OpNo, raw_ostream &O,
415 const MCRegisterInfo &MRI) {
416 if (MIA)
417 Reg = getRegFromMIA(Reg, OpNo, MII.get(Opc), MRI,
418 *static_cast<const AMDGPUMCInstrAnalysis *>(MIA));
419 printRegOperand(Reg, O, MRI);
420}
421
422void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
423 const MCSubtargetInfo &STI, raw_ostream &O) {
424 auto Opcode = MI->getOpcode();
425 auto Flags = MII.get(Opcode).TSFlags;
426 if (OpNo == 0) {
427 if (Flags & SIInstrFlags::VOP3 && Flags & SIInstrFlags::DPP)
428 O << "_e64_dpp";
429 else if (Flags & SIInstrFlags::VOP3) {
430 if (!getVOP3IsSingle(Opcode))
431 O << "_e64";
432 } else if (Flags & SIInstrFlags::DPP)
433 O << "_dpp";
434 else if (Flags & SIInstrFlags::SDWA)
435 O << "_sdwa";
436 else if (((Flags & SIInstrFlags::VOP1) && !getVOP1IsSingle(Opcode)) ||
437 ((Flags & SIInstrFlags::VOP2) && !getVOP2IsSingle(Opcode)))
438 O << "_e32";
439 O << " ";
440 }
441
442 printRegularOperand(MI, OpNo, STI, O);
443
444 // Print default vcc/vcc_lo operand.
445 switch (Opcode) {
446 default: break;
447
448 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
449 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
450 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
451 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
452 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
453 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
454 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
455 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
456 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
457 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
458 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
459 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
460 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
461 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
462 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
463 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
464 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
465 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
466 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
467 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
468 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
469 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx12:
470 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx12:
471 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx12:
472 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx12:
473 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx12:
474 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx12:
475 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx12:
476 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx12:
477 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx12:
478 printDefaultVccOperand(false, STI, O);
479 break;
480 }
481}
482
483void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo,
484 const MCSubtargetInfo &STI, raw_ostream &O) {
485 if (AMDGPU::isSI(STI) || AMDGPU::isCI(STI))
486 O << " ";
487 else
488 O << "_e32 ";
489
490 printRegularOperand(MI, OpNo, STI, O);
491}
492
493void AMDGPUInstPrinter::printImmediateInt16(uint32_t Imm,
494 const MCSubtargetInfo &STI,
495 raw_ostream &O) {
496 int32_t SImm = static_cast<int32_t>(Imm);
497 if (isInlinableIntLiteral(SImm)) {
498 O << SImm;
499 return;
500 }
501
502 if (printImmediateFloat32(Imm, STI, O))
503 return;
504
505 O << formatHex(static_cast<uint64_t>(Imm & 0xffff));
506}
507
509 raw_ostream &O) {
510 if (Imm == 0x3C00)
511 O << "1.0";
512 else if (Imm == 0xBC00)
513 O << "-1.0";
514 else if (Imm == 0x3800)
515 O << "0.5";
516 else if (Imm == 0xB800)
517 O << "-0.5";
518 else if (Imm == 0x4000)
519 O << "2.0";
520 else if (Imm == 0xC000)
521 O << "-2.0";
522 else if (Imm == 0x4400)
523 O << "4.0";
524 else if (Imm == 0xC400)
525 O << "-4.0";
526 else if (Imm == 0x3118 && STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
527 O << "0.15915494";
528 else
529 return false;
530
531 return true;
532}
533
535 raw_ostream &O) {
536 if (Imm == 0x3F80)
537 O << "1.0";
538 else if (Imm == 0xBF80)
539 O << "-1.0";
540 else if (Imm == 0x3F00)
541 O << "0.5";
542 else if (Imm == 0xBF00)
543 O << "-0.5";
544 else if (Imm == 0x4000)
545 O << "2.0";
546 else if (Imm == 0xC000)
547 O << "-2.0";
548 else if (Imm == 0x4080)
549 O << "4.0";
550 else if (Imm == 0xC080)
551 O << "-4.0";
552 else if (Imm == 0x3E22 && STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
553 O << "0.15915494";
554 else
555 return false;
556
557 return true;
558}
559
560void AMDGPUInstPrinter::printImmediateBF16(uint32_t Imm,
561 const MCSubtargetInfo &STI,
562 raw_ostream &O) {
563 int16_t SImm = static_cast<int16_t>(Imm);
564 if (isInlinableIntLiteral(SImm)) {
565 O << SImm;
566 return;
567 }
568
569 if (printImmediateBFloat16(static_cast<uint16_t>(Imm), STI, O))
570 return;
571
572 O << formatHex(static_cast<uint64_t>(Imm));
573}
574
575void AMDGPUInstPrinter::printImmediateF16(uint32_t Imm,
576 const MCSubtargetInfo &STI,
577 raw_ostream &O) {
578 int16_t SImm = static_cast<int16_t>(Imm);
579 if (isInlinableIntLiteral(SImm)) {
580 O << SImm;
581 return;
582 }
583
584 uint16_t HImm = static_cast<uint16_t>(Imm);
585 if (printImmediateFP16(HImm, STI, O))
586 return;
587
588 uint64_t Imm16 = static_cast<uint16_t>(Imm);
589 O << formatHex(Imm16);
590}
591
592void AMDGPUInstPrinter::printImmediateV216(uint32_t Imm, uint8_t OpType,
593 const MCSubtargetInfo &STI,
594 raw_ostream &O) {
595 int32_t SImm = static_cast<int32_t>(Imm);
596 if (isInlinableIntLiteral(SImm)) {
597 O << SImm;
598 return;
599 }
600
601 switch (OpType) {
604 if (printImmediateFloat32(Imm, STI, O))
605 return;
606 break;
609 if (isUInt<16>(Imm) &&
610 printImmediateFP16(static_cast<uint16_t>(Imm), STI, O))
611 return;
612 break;
615 if (isUInt<16>(Imm) &&
616 printImmediateBFloat16(static_cast<uint16_t>(Imm), STI, O))
617 return;
618 break;
620 break;
621 default:
622 llvm_unreachable("bad operand type");
623 }
624
625 O << formatHex(static_cast<uint64_t>(Imm));
626}
627
628bool AMDGPUInstPrinter::printImmediateFloat32(uint32_t Imm,
629 const MCSubtargetInfo &STI,
630 raw_ostream &O) {
631 if (Imm == llvm::bit_cast<uint32_t>(0.0f))
632 O << "0.0";
633 else if (Imm == llvm::bit_cast<uint32_t>(1.0f))
634 O << "1.0";
635 else if (Imm == llvm::bit_cast<uint32_t>(-1.0f))
636 O << "-1.0";
637 else if (Imm == llvm::bit_cast<uint32_t>(0.5f))
638 O << "0.5";
639 else if (Imm == llvm::bit_cast<uint32_t>(-0.5f))
640 O << "-0.5";
641 else if (Imm == llvm::bit_cast<uint32_t>(2.0f))
642 O << "2.0";
643 else if (Imm == llvm::bit_cast<uint32_t>(-2.0f))
644 O << "-2.0";
645 else if (Imm == llvm::bit_cast<uint32_t>(4.0f))
646 O << "4.0";
647 else if (Imm == llvm::bit_cast<uint32_t>(-4.0f))
648 O << "-4.0";
649 else if (Imm == 0x3e22f983 &&
650 STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
651 O << "0.15915494";
652 else
653 return false;
654
655 return true;
656}
657
658void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
659 const MCSubtargetInfo &STI,
660 raw_ostream &O) {
661 int32_t SImm = static_cast<int32_t>(Imm);
662 if (isInlinableIntLiteral(SImm)) {
663 O << SImm;
664 return;
665 }
666
667 if (printImmediateFloat32(Imm, STI, O))
668 return;
669
670 O << formatHex(static_cast<uint64_t>(Imm));
671}
672
673void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
674 const MCSubtargetInfo &STI,
675 raw_ostream &O, bool IsFP) {
676 int64_t SImm = static_cast<int64_t>(Imm);
677 if (SImm >= -16 && SImm <= 64) {
678 O << SImm;
679 return;
680 }
681
682 if (Imm == llvm::bit_cast<uint64_t>(0.0))
683 O << "0.0";
684 else if (Imm == llvm::bit_cast<uint64_t>(1.0))
685 O << "1.0";
686 else if (Imm == llvm::bit_cast<uint64_t>(-1.0))
687 O << "-1.0";
688 else if (Imm == llvm::bit_cast<uint64_t>(0.5))
689 O << "0.5";
690 else if (Imm == llvm::bit_cast<uint64_t>(-0.5))
691 O << "-0.5";
692 else if (Imm == llvm::bit_cast<uint64_t>(2.0))
693 O << "2.0";
694 else if (Imm == llvm::bit_cast<uint64_t>(-2.0))
695 O << "-2.0";
696 else if (Imm == llvm::bit_cast<uint64_t>(4.0))
697 O << "4.0";
698 else if (Imm == llvm::bit_cast<uint64_t>(-4.0))
699 O << "-4.0";
700 else if (Imm == 0x3fc45f306dc9c882 &&
701 STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
702 O << "0.15915494309189532";
703 else
704 printLiteral64(Imm, O, IsFP);
705}
706
707void AMDGPUInstPrinter::printLiteral64(uint64_t Imm, raw_ostream &O,
708 bool IsFP) {
709 if (IsFP && Lo_32(Imm) == 0)
710 O << formatHex(static_cast<uint64_t>(Hi_32(Imm)));
711 else
712 O << formatHex(Imm);
713}
714
715void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
716 const MCSubtargetInfo &STI,
717 raw_ostream &O) {
718 unsigned Imm = MI->getOperand(OpNo).getImm();
719 if (!Imm)
720 return;
721
722 if (AMDGPU::isGFX940(STI)) {
723 switch (MI->getOpcode()) {
724 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd:
725 case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd:
726 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd:
727 case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd:
728 O << " neg:[" << (Imm & 1) << ',' << ((Imm >> 1) & 1) << ','
729 << ((Imm >> 2) & 1) << ']';
730 return;
731 }
732 }
733
734 O << " blgp:" << Imm;
735}
736
737void AMDGPUInstPrinter::printDefaultVccOperand(bool FirstOperand,
738 const MCSubtargetInfo &STI,
739 raw_ostream &O) {
740 if (!FirstOperand)
741 O << ", ";
742 printRegOperand(STI.hasFeature(AMDGPU::FeatureWavefrontSize32)
743 ? AMDGPU::VCC_LO
744 : AMDGPU::VCC,
745 O, MRI);
746 if (FirstOperand)
747 O << ", ";
748}
749
750bool AMDGPUInstPrinter::needsImpliedVcc(const MCInstrDesc &Desc,
751 unsigned OpNo) const {
752 return OpNo == 0 && (Desc.TSFlags & SIInstrFlags::DPP) &&
753 (Desc.TSFlags & SIInstrFlags::VOPC) &&
754 !isVOPCAsmOnly(Desc.getOpcode()) &&
755 (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
756 Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO));
757}
758
759// Print default vcc/vcc_lo operand of VOPC.
760void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
761 const MCSubtargetInfo &STI,
762 raw_ostream &O) {
763 unsigned Opc = MI->getOpcode();
764 const MCInstrDesc &Desc = MII.get(Opc);
765 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
766 // 0, 1 and 2 are the first printed operands in different cases
767 // If there are printed modifiers, printOperandAndFPInputMods or
768 // printOperandAndIntInputMods will be called instead
769 if ((OpNo == 0 ||
770 (OpNo == 1 && (Desc.TSFlags & SIInstrFlags::DPP) && ModIdx != -1)) &&
771 (Desc.TSFlags & SIInstrFlags::VOPC) && !isVOPCAsmOnly(Desc.getOpcode()) &&
772 (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
773 Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
774 printDefaultVccOperand(true, STI, O);
775
776 printRegularOperand(MI, OpNo, STI, O);
777}
778
779// Print operands after vcc or modifier handling.
780void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
781 const MCSubtargetInfo &STI,
782 raw_ostream &O) {
783 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
784
785 if (OpNo >= MI->getNumOperands()) {
786 O << "/*Missing OP" << OpNo << "*/";
787 return;
788 }
789
790 const MCOperand &Op = MI->getOperand(OpNo);
791 if (Op.isReg()) {
792 printRegOperand(Op.getReg(), MI->getOpcode(), OpNo, O, MRI);
793
794 // Check if operand register class contains register used.
795 // Intention: print disassembler message when invalid code is decoded,
796 // for example sgpr register used in VReg or VISrc(VReg or imm) operand.
797 const MCOperandInfo &OpInfo = Desc.operands()[OpNo];
798 int16_t RCID = MII.getOpRegClassID(
800 if (RCID != -1) {
801 const MCRegisterClass &RC = MRI.getRegClass(RCID);
802 auto Reg = mc2PseudoReg(Op.getReg());
803 if (!RC.contains(Reg) && !isInlineValue(Reg)) {
804 O << "/*Invalid register, operand has \'" << MRI.getRegClassName(&RC)
805 << "\' register class*/";
806 }
807 }
808 } else if (Op.isImm()) {
809 const uint8_t OpTy = Desc.operands()[OpNo].OperandType;
810 switch (OpTy) {
821 printImmediate32(Op.getImm(), STI, O);
822 break;
825 printImmediate64(Op.getImm(), STI, O, false);
826 break;
830 printImmediate64(Op.getImm(), STI, O, true);
831 break;
834 printImmediateInt16(Op.getImm(), STI, O);
835 break;
838 printImmediateF16(Op.getImm(), STI, O);
839 break;
842 printImmediateBF16(Op.getImm(), STI, O);
843 break;
851 printImmediateV216(Op.getImm(), OpTy, STI, O);
852 break;
855 O << formatDec(Op.getImm());
856 break;
858 // Disassembler does not fail when operand should not allow immediate
859 // operands but decodes them into 32bit immediate operand.
860 printImmediate32(Op.getImm(), STI, O);
861 O << "/*Invalid immediate*/";
862 break;
863 default:
864 // We hit this for the immediate instruction bits that don't yet have a
865 // custom printer.
866 llvm_unreachable("unexpected immediate operand type");
867 }
868 } else if (Op.isExpr()) {
869 const MCExpr *Exp = Op.getExpr();
870 MAI.printExpr(O, *Exp);
871 } else {
872 O << "/*INV_OP*/";
873 }
874
875 // Print default vcc/vcc_lo operand of v_cndmask_b32_e32.
876 switch (MI->getOpcode()) {
877 default: break;
878
879 case AMDGPU::V_CNDMASK_B32_e32_gfx10:
880 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10:
881 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10:
882 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
883 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10:
884 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10:
885 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10:
886 case AMDGPU::V_CNDMASK_B32_dpp8_gfx10:
887 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
888 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
889 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
890 case AMDGPU::V_CNDMASK_B32_e32_gfx11:
891 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
892 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
893 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
894 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
895 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
896 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
897 case AMDGPU::V_CNDMASK_B32_dpp8_gfx11:
898 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
899 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
900 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
901 case AMDGPU::V_CNDMASK_B32_e32_gfx12:
902 case AMDGPU::V_ADD_CO_CI_U32_e32_gfx12:
903 case AMDGPU::V_SUB_CO_CI_U32_e32_gfx12:
904 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx12:
905 case AMDGPU::V_CNDMASK_B32_dpp_gfx12:
906 case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx12:
907 case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx12:
908 case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx12:
909 case AMDGPU::V_CNDMASK_B32_dpp8_gfx12:
910 case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx12:
911 case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx12:
912 case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx12:
913
914 case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
915 case AMDGPU::V_CNDMASK_B32_e32_vi:
916 if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
917 AMDGPU::OpName::src1))
918 printDefaultVccOperand(OpNo == 0, STI, O);
919 break;
920 }
921
922 if (Desc.TSFlags & SIInstrFlags::MTBUF) {
923 int SOffsetIdx =
924 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::soffset);
925 assert(SOffsetIdx != -1);
926 if ((int)OpNo == SOffsetIdx)
927 printSymbolicFormat(MI, STI, O);
928 }
929}
930
931void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
932 unsigned OpNo,
933 const MCSubtargetInfo &STI,
934 raw_ostream &O) {
935 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
936 if (needsImpliedVcc(Desc, OpNo))
937 printDefaultVccOperand(true, STI, O);
938
939 unsigned InputModifiers = MI->getOperand(OpNo).getImm();
940
941 // Use 'neg(...)' instead of '-' to avoid ambiguity.
942 // This is important for integer literals because
943 // -1 is not the same value as neg(1).
944 bool NegMnemo = false;
945
946 if (InputModifiers & SISrcMods::NEG) {
947 if (OpNo + 1 < MI->getNumOperands() &&
948 (InputModifiers & SISrcMods::ABS) == 0) {
949 const MCOperand &Op = MI->getOperand(OpNo + 1);
950 NegMnemo = Op.isImm();
951 }
952 if (NegMnemo) {
953 O << "neg(";
954 } else {
955 O << '-';
956 }
957 }
958
959 if (InputModifiers & SISrcMods::ABS)
960 O << '|';
961 printRegularOperand(MI, OpNo + 1, STI, O);
962 if (InputModifiers & SISrcMods::ABS)
963 O << '|';
964
965 if (NegMnemo) {
966 O << ')';
967 }
968
969 // Print default vcc/vcc_lo operand of VOP2b.
970 switch (MI->getOpcode()) {
971 default:
972 break;
973
974 case AMDGPU::V_CNDMASK_B32_sdwa_gfx10:
975 case AMDGPU::V_CNDMASK_B32_dpp_gfx10:
976 case AMDGPU::V_CNDMASK_B32_dpp_gfx11:
977 if ((int)OpNo + 1 ==
978 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::src1))
979 printDefaultVccOperand(OpNo == 0, STI, O);
980 break;
981 }
982}
983
984void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
985 unsigned OpNo,
986 const MCSubtargetInfo &STI,
987 raw_ostream &O) {
988 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
989 if (needsImpliedVcc(Desc, OpNo))
990 printDefaultVccOperand(true, STI, O);
991
992 unsigned InputModifiers = MI->getOperand(OpNo).getImm();
993 if (InputModifiers & SISrcMods::SEXT)
994 O << "sext(";
995 printRegularOperand(MI, OpNo + 1, STI, O);
996 if (InputModifiers & SISrcMods::SEXT)
997 O << ')';
998
999 // Print default vcc/vcc_lo operand of VOP2b.
1000 switch (MI->getOpcode()) {
1001 default: break;
1002
1003 case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10:
1004 case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10:
1005 case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
1006 if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1007 AMDGPU::OpName::src1))
1008 printDefaultVccOperand(OpNo == 0, STI, O);
1009 break;
1010 }
1011}
1012
1013void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo,
1014 const MCSubtargetInfo &STI,
1015 raw_ostream &O) {
1016 if (!AMDGPU::isGFX10Plus(STI))
1017 llvm_unreachable("dpp8 is not supported on ASICs earlier than GFX10");
1018
1019 unsigned Imm = MI->getOperand(OpNo).getImm();
1020 O << "dpp8:[" << formatDec(Imm & 0x7);
1021 for (size_t i = 1; i < 8; ++i) {
1022 O << ',' << formatDec((Imm >> (3 * i)) & 0x7);
1023 }
1024 O << ']';
1025}
1026
1027void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
1028 const MCSubtargetInfo &STI,
1029 raw_ostream &O) {
1030 using namespace AMDGPU::DPP;
1031
1032 unsigned Imm = MI->getOperand(OpNo).getImm();
1033 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
1034
1036 AMDGPU::isDPALU_DPP(Desc, MII, STI)) {
1037 O << " /* DP ALU dpp only supports "
1038 << (isGFX12(STI) ? "row_share" : "row_newbcast") << " */";
1039 return;
1040 }
1041 if (Imm <= DppCtrl::QUAD_PERM_LAST) {
1042 O << "quad_perm:[";
1043 O << formatDec(Imm & 0x3) << ',';
1044 O << formatDec((Imm & 0xc) >> 2) << ',';
1045 O << formatDec((Imm & 0x30) >> 4) << ',';
1046 O << formatDec((Imm & 0xc0) >> 6) << ']';
1047 } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
1048 (Imm <= DppCtrl::ROW_SHL_LAST)) {
1049 O << "row_shl:" << formatDec(Imm - DppCtrl::ROW_SHL0);
1050 } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
1051 (Imm <= DppCtrl::ROW_SHR_LAST)) {
1052 O << "row_shr:" << formatDec(Imm - DppCtrl::ROW_SHR0);
1053 } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
1054 (Imm <= DppCtrl::ROW_ROR_LAST)) {
1055 O << "row_ror:" << formatDec(Imm - DppCtrl::ROW_ROR0);
1056 } else if (Imm == DppCtrl::WAVE_SHL1) {
1057 if (AMDGPU::isGFX10Plus(STI)) {
1058 O << "/* wave_shl is not supported starting from GFX10 */";
1059 return;
1060 }
1061 O << "wave_shl:1";
1062 } else if (Imm == DppCtrl::WAVE_ROL1) {
1063 if (AMDGPU::isGFX10Plus(STI)) {
1064 O << "/* wave_rol is not supported starting from GFX10 */";
1065 return;
1066 }
1067 O << "wave_rol:1";
1068 } else if (Imm == DppCtrl::WAVE_SHR1) {
1069 if (AMDGPU::isGFX10Plus(STI)) {
1070 O << "/* wave_shr is not supported starting from GFX10 */";
1071 return;
1072 }
1073 O << "wave_shr:1";
1074 } else if (Imm == DppCtrl::WAVE_ROR1) {
1075 if (AMDGPU::isGFX10Plus(STI)) {
1076 O << "/* wave_ror is not supported starting from GFX10 */";
1077 return;
1078 }
1079 O << "wave_ror:1";
1080 } else if (Imm == DppCtrl::ROW_MIRROR) {
1081 O << "row_mirror";
1082 } else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
1083 O << "row_half_mirror";
1084 } else if (Imm == DppCtrl::BCAST15) {
1085 if (AMDGPU::isGFX10Plus(STI)) {
1086 O << "/* row_bcast is not supported starting from GFX10 */";
1087 return;
1088 }
1089 O << "row_bcast:15";
1090 } else if (Imm == DppCtrl::BCAST31) {
1091 if (AMDGPU::isGFX10Plus(STI)) {
1092 O << "/* row_bcast is not supported starting from GFX10 */";
1093 return;
1094 }
1095 O << "row_bcast:31";
1096 } else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
1097 (Imm <= DppCtrl::ROW_SHARE_LAST)) {
1098 if (AMDGPU::isGFX90A(STI)) {
1099 O << "row_newbcast:";
1100 } else if (AMDGPU::isGFX10Plus(STI)) {
1101 O << "row_share:";
1102 } else {
1103 O << " /* row_newbcast/row_share is not supported on ASICs earlier "
1104 "than GFX90A/GFX10 */";
1105 return;
1106 }
1107 O << formatDec(Imm - DppCtrl::ROW_SHARE_FIRST);
1108 } else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
1109 (Imm <= DppCtrl::ROW_XMASK_LAST)) {
1110 if (!AMDGPU::isGFX10Plus(STI)) {
1111 O << "/* row_xmask is not supported on ASICs earlier than GFX10 */";
1112 return;
1113 }
1114 O << "row_xmask:" << formatDec(Imm - DppCtrl::ROW_XMASK_FIRST);
1115 } else {
1116 O << "/* Invalid dpp_ctrl value */";
1117 }
1118}
1119
1120void AMDGPUInstPrinter::printDppBoundCtrl(const MCInst *MI, unsigned OpNo,
1121 const MCSubtargetInfo &STI,
1122 raw_ostream &O) {
1123 unsigned Imm = MI->getOperand(OpNo).getImm();
1124 if (Imm) {
1125 O << " bound_ctrl:1";
1126 }
1127}
1128
1129void AMDGPUInstPrinter::printDppFI(const MCInst *MI, unsigned OpNo,
1130 const MCSubtargetInfo &STI, raw_ostream &O) {
1131 using namespace llvm::AMDGPU::DPP;
1132 unsigned Imm = MI->getOperand(OpNo).getImm();
1133 if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) {
1134 O << " fi:1";
1135 }
1136}
1137
1138void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo,
1139 raw_ostream &O) {
1140 using namespace llvm::AMDGPU::SDWA;
1141
1142 unsigned Imm = MI->getOperand(OpNo).getImm();
1143 switch (Imm) {
1144 case SdwaSel::BYTE_0: O << "BYTE_0"; break;
1145 case SdwaSel::BYTE_1: O << "BYTE_1"; break;
1146 case SdwaSel::BYTE_2: O << "BYTE_2"; break;
1147 case SdwaSel::BYTE_3: O << "BYTE_3"; break;
1148 case SdwaSel::WORD_0: O << "WORD_0"; break;
1149 case SdwaSel::WORD_1: O << "WORD_1"; break;
1150 case SdwaSel::DWORD: O << "DWORD"; break;
1151 default: llvm_unreachable("Invalid SDWA data select operand");
1152 }
1153}
1154
1155void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo,
1156 const MCSubtargetInfo &STI,
1157 raw_ostream &O) {
1158 O << "dst_sel:";
1159 printSDWASel(MI, OpNo, O);
1160}
1161
1162void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo,
1163 const MCSubtargetInfo &STI,
1164 raw_ostream &O) {
1165 O << "src0_sel:";
1166 printSDWASel(MI, OpNo, O);
1167}
1168
1169void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo,
1170 const MCSubtargetInfo &STI,
1171 raw_ostream &O) {
1172 O << "src1_sel:";
1173 printSDWASel(MI, OpNo, O);
1174}
1175
1176void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
1177 const MCSubtargetInfo &STI,
1178 raw_ostream &O) {
1179 using namespace llvm::AMDGPU::SDWA;
1180
1181 O << "dst_unused:";
1182 unsigned Imm = MI->getOperand(OpNo).getImm();
1183 switch (Imm) {
1184 case DstUnused::UNUSED_PAD: O << "UNUSED_PAD"; break;
1185 case DstUnused::UNUSED_SEXT: O << "UNUSED_SEXT"; break;
1186 case DstUnused::UNUSED_PRESERVE: O << "UNUSED_PRESERVE"; break;
1187 default: llvm_unreachable("Invalid SDWA dest_unused operand");
1188 }
1189}
1190
1191void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo,
1192 const MCSubtargetInfo &STI, raw_ostream &O,
1193 unsigned N) {
1194 unsigned Opc = MI->getOpcode();
1195 int EnIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::en);
1196 unsigned En = MI->getOperand(EnIdx).getImm();
1197
1198 int ComprIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::compr);
1199
1200 // If compr is set, print as src0, src0, src1, src1
1201 if (MI->getOperand(ComprIdx).getImm())
1202 OpNo = OpNo - N + N / 2;
1203
1204 if (En & (1 << N))
1205 printRegOperand(MI->getOperand(OpNo).getReg(), Opc, OpNo, O, MRI);
1206 else
1207 O << "off";
1208}
1209
1210void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo,
1211 const MCSubtargetInfo &STI,
1212 raw_ostream &O) {
1213 printExpSrcN(MI, OpNo, STI, O, 0);
1214}
1215
1216void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo,
1217 const MCSubtargetInfo &STI,
1218 raw_ostream &O) {
1219 printExpSrcN(MI, OpNo, STI, O, 1);
1220}
1221
1222void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo,
1223 const MCSubtargetInfo &STI,
1224 raw_ostream &O) {
1225 printExpSrcN(MI, OpNo, STI, O, 2);
1226}
1227
1228void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo,
1229 const MCSubtargetInfo &STI,
1230 raw_ostream &O) {
1231 printExpSrcN(MI, OpNo, STI, O, 3);
1232}
1233
1234void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
1235 const MCSubtargetInfo &STI,
1236 raw_ostream &O) {
1237 using namespace llvm::AMDGPU::Exp;
1238
1239 // This is really a 6 bit field.
1240 unsigned Id = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
1241
1242 int Index;
1243 StringRef TgtName;
1244 if (getTgtName(Id, TgtName, Index) && isSupportedTgtId(Id, STI)) {
1245 O << ' ' << TgtName;
1246 if (Index >= 0)
1247 O << Index;
1248 } else {
1249 O << " invalid_target_" << Id;
1250 }
1251}
1252
1253static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod,
1254 bool IsPacked, bool HasDstSel) {
1255 int DefaultValue = IsPacked && (Mod == SISrcMods::OP_SEL_1);
1256
1257 for (int I = 0; I < NumOps; ++I) {
1258 if (!!(Ops[I] & Mod) != DefaultValue)
1259 return false;
1260 }
1261
1262 if (HasDstSel && (Ops[0] & SISrcMods::DST_OP_SEL) != 0)
1263 return false;
1264
1265 return true;
1266}
1267
1268void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
1269 StringRef Name,
1270 unsigned Mod,
1271 raw_ostream &O) {
1272 unsigned Opc = MI->getOpcode();
1273 int NumOps = 0;
1274 int Ops[3];
1275
1276 std::pair<AMDGPU::OpName, AMDGPU::OpName> MOps[] = {
1277 {AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src0},
1278 {AMDGPU::OpName::src1_modifiers, AMDGPU::OpName::src1},
1279 {AMDGPU::OpName::src2_modifiers, AMDGPU::OpName::src2}};
1280 int DefaultValue = (Mod == SISrcMods::OP_SEL_1);
1281
1282 for (auto [SrcMod, Src] : MOps) {
1283 if (!AMDGPU::hasNamedOperand(Opc, Src))
1284 break;
1285
1286 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, SrcMod);
1287 Ops[NumOps++] =
1288 (ModIdx != -1) ? MI->getOperand(ModIdx).getImm() : DefaultValue;
1289 }
1290
1291 // Some instructions, e.g. v_interp_p2_f16 in GFX9, have src0, src2, but no
1292 // src1.
1293 if (NumOps == 1 && AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src2) &&
1294 !AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1)) {
1295 Ops[NumOps++] = DefaultValue; // Set src1_modifiers to default.
1296 int Mod2Idx =
1297 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2_modifiers);
1298 assert(Mod2Idx != -1);
1299 Ops[NumOps++] = MI->getOperand(Mod2Idx).getImm();
1300 }
1301
1302 const bool HasDst =
1303 (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst) != -1) ||
1304 (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sdst) != -1);
1305
1306 // Print three values of neg/opsel for wmma instructions (prints 0 when there
1307 // is no src_modifier operand instead of not printing anything).
1308 if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsSWMMAC ||
1309 MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsWMMA) {
1310 NumOps = 0;
1311 int DefaultValue = Mod == SISrcMods::OP_SEL_1;
1312 for (AMDGPU::OpName OpName :
1313 {AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src1_modifiers,
1314 AMDGPU::OpName::src2_modifiers}) {
1315 int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName);
1316 if (Idx != -1)
1317 Ops[NumOps++] = MI->getOperand(Idx).getImm();
1318 else
1319 Ops[NumOps++] = DefaultValue;
1320 }
1321 }
1322
1323 const bool HasDstSel =
1324 HasDst && NumOps > 0 && Mod == SISrcMods::OP_SEL_0 &&
1325 MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL;
1326
1327 const bool IsPacked =
1328 MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked;
1329
1330 if (allOpsDefaultValue(Ops, NumOps, Mod, IsPacked, HasDstSel))
1331 return;
1332
1333 O << Name;
1334 for (int I = 0; I < NumOps; ++I) {
1335 if (I != 0)
1336 O << ',';
1337
1338 O << !!(Ops[I] & Mod);
1339 }
1340
1341 if (HasDstSel) {
1342 O << ',' << !!(Ops[0] & SISrcMods::DST_OP_SEL);
1343 }
1344
1345 O << ']';
1346}
1347
1348void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned,
1349 const MCSubtargetInfo &STI,
1350 raw_ostream &O) {
1351 unsigned Opc = MI->getOpcode();
1353 auto SrcMod =
1354 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
1355 unsigned Mod = MI->getOperand(SrcMod).getImm();
1356 unsigned Index0 = !!(Mod & SISrcMods::OP_SEL_0);
1357 unsigned Index1 = !!(Mod & SISrcMods::OP_SEL_1);
1358 if (Index0 || Index1)
1359 O << " op_sel:[" << Index0 << ',' << Index1 << ']';
1360 return;
1361 }
1362 if (isPermlane16(Opc)) {
1363 auto FIN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
1364 auto BCN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers);
1365 unsigned FI = !!(MI->getOperand(FIN).getImm() & SISrcMods::OP_SEL_0);
1366 unsigned BC = !!(MI->getOperand(BCN).getImm() & SISrcMods::OP_SEL_0);
1367 if (FI || BC)
1368 O << " op_sel:[" << FI << ',' << BC << ']';
1369 return;
1370 }
1371
1372 printPackedModifier(MI, " op_sel:[", SISrcMods::OP_SEL_0, O);
1373}
1374
1375void AMDGPUInstPrinter::printOpSelHi(const MCInst *MI, unsigned OpNo,
1376 const MCSubtargetInfo &STI,
1377 raw_ostream &O) {
1378 printPackedModifier(MI, " op_sel_hi:[", SISrcMods::OP_SEL_1, O);
1379}
1380
1381void AMDGPUInstPrinter::printNegLo(const MCInst *MI, unsigned OpNo,
1382 const MCSubtargetInfo &STI,
1383 raw_ostream &O) {
1384 printPackedModifier(MI, " neg_lo:[", SISrcMods::NEG, O);
1385}
1386
1387void AMDGPUInstPrinter::printNegHi(const MCInst *MI, unsigned OpNo,
1388 const MCSubtargetInfo &STI,
1389 raw_ostream &O) {
1390 printPackedModifier(MI, " neg_hi:[", SISrcMods::NEG_HI, O);
1391}
1392
1393void AMDGPUInstPrinter::printIndexKey8bit(const MCInst *MI, unsigned OpNo,
1394 const MCSubtargetInfo &STI,
1395 raw_ostream &O) {
1396 auto Imm = MI->getOperand(OpNo).getImm() & 0x7;
1397 if (Imm == 0)
1398 return;
1399
1400 O << " index_key:" << Imm;
1401}
1402
1403void AMDGPUInstPrinter::printIndexKey16bit(const MCInst *MI, unsigned OpNo,
1404 const MCSubtargetInfo &STI,
1405 raw_ostream &O) {
1406 auto Imm = MI->getOperand(OpNo).getImm() & 0x7;
1407 if (Imm == 0)
1408 return;
1409
1410 O << " index_key:" << Imm;
1411}
1412
1413void AMDGPUInstPrinter::printIndexKey32bit(const MCInst *MI, unsigned OpNo,
1414 const MCSubtargetInfo &STI,
1415 raw_ostream &O) {
1416 auto Imm = MI->getOperand(OpNo).getImm() & 0x7;
1417 if (Imm == 0)
1418 return;
1419
1420 O << " index_key:" << Imm;
1421}
1422
1423void AMDGPUInstPrinter::printMatrixFMT(const MCInst *MI, unsigned OpNo,
1424 const MCSubtargetInfo &STI,
1425 raw_ostream &O, char AorB) {
1426 auto Imm = MI->getOperand(OpNo).getImm() & 0x7;
1427 if (Imm == 0)
1428 return;
1429
1430 O << " matrix_" << AorB << "_fmt:";
1431 switch (Imm) {
1432 default:
1433 O << Imm;
1434 break;
1435 case WMMA::MatrixFMT::MATRIX_FMT_FP8:
1436 O << "MATRIX_FMT_FP8";
1437 break;
1438 case WMMA::MatrixFMT::MATRIX_FMT_BF8:
1439 O << "MATRIX_FMT_BF8";
1440 break;
1441 case WMMA::MatrixFMT::MATRIX_FMT_FP6:
1442 O << "MATRIX_FMT_FP6";
1443 break;
1444 case WMMA::MatrixFMT::MATRIX_FMT_BF6:
1445 O << "MATRIX_FMT_BF6";
1446 break;
1447 case WMMA::MatrixFMT::MATRIX_FMT_FP4:
1448 O << "MATRIX_FMT_FP4";
1449 break;
1450 }
1451}
1452
1453void AMDGPUInstPrinter::printMatrixAFMT(const MCInst *MI, unsigned OpNo,
1454 const MCSubtargetInfo &STI,
1455 raw_ostream &O) {
1456 printMatrixFMT(MI, OpNo, STI, O, 'a');
1457}
1458
1459void AMDGPUInstPrinter::printMatrixBFMT(const MCInst *MI, unsigned OpNo,
1460 const MCSubtargetInfo &STI,
1461 raw_ostream &O) {
1462 printMatrixFMT(MI, OpNo, STI, O, 'b');
1463}
1464
1465void AMDGPUInstPrinter::printMatrixScale(const MCInst *MI, unsigned OpNo,
1466 const MCSubtargetInfo &STI,
1467 raw_ostream &O, char AorB) {
1468 auto Imm = MI->getOperand(OpNo).getImm() & 1;
1469 if (Imm == 0)
1470 return;
1471
1472 O << " matrix_" << AorB << "_scale:";
1473 switch (Imm) {
1474 default:
1475 O << Imm;
1476 break;
1477 case WMMA::MatrixScale::MATRIX_SCALE_ROW0:
1478 O << "MATRIX_SCALE_ROW0";
1479 break;
1480 case WMMA::MatrixScale::MATRIX_SCALE_ROW1:
1481 O << "MATRIX_SCALE_ROW1";
1482 break;
1483 }
1484}
1485
1486void AMDGPUInstPrinter::printMatrixAScale(const MCInst *MI, unsigned OpNo,
1487 const MCSubtargetInfo &STI,
1488 raw_ostream &O) {
1489 printMatrixScale(MI, OpNo, STI, O, 'a');
1490}
1491
1492void AMDGPUInstPrinter::printMatrixBScale(const MCInst *MI, unsigned OpNo,
1493 const MCSubtargetInfo &STI,
1494 raw_ostream &O) {
1495 printMatrixScale(MI, OpNo, STI, O, 'b');
1496}
1497
1498void AMDGPUInstPrinter::printMatrixScaleFmt(const MCInst *MI, unsigned OpNo,
1499 const MCSubtargetInfo &STI,
1500 raw_ostream &O, char AorB) {
1501 auto Imm = MI->getOperand(OpNo).getImm() & 3;
1502 if (Imm == 0)
1503 return;
1504
1505 O << " matrix_" << AorB << "_scale_fmt:";
1506 switch (Imm) {
1507 default:
1508 O << Imm;
1509 break;
1510 case WMMA::MatrixScaleFmt::MATRIX_SCALE_FMT_E8:
1511 O << "MATRIX_SCALE_FMT_E8";
1512 break;
1513 case WMMA::MatrixScaleFmt::MATRIX_SCALE_FMT_E5M3:
1514 O << "MATRIX_SCALE_FMT_E5M3";
1515 break;
1516 case WMMA::MatrixScaleFmt::MATRIX_SCALE_FMT_E4M3:
1517 O << "MATRIX_SCALE_FMT_E4M3";
1518 break;
1519 }
1520}
1521
1522void AMDGPUInstPrinter::printMatrixAScaleFmt(const MCInst *MI, unsigned OpNo,
1523 const MCSubtargetInfo &STI,
1524 raw_ostream &O) {
1525 printMatrixScaleFmt(MI, OpNo, STI, O, 'a');
1526}
1527
1528void AMDGPUInstPrinter::printMatrixBScaleFmt(const MCInst *MI, unsigned OpNo,
1529 const MCSubtargetInfo &STI,
1530 raw_ostream &O) {
1531 printMatrixScaleFmt(MI, OpNo, STI, O, 'b');
1532}
1533
1534void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
1535 const MCSubtargetInfo &STI,
1536 raw_ostream &O) {
1537 unsigned Imm = MI->getOperand(OpNum).getImm();
1538 switch (Imm) {
1539 case 0:
1540 O << "p10";
1541 break;
1542 case 1:
1543 O << "p20";
1544 break;
1545 case 2:
1546 O << "p0";
1547 break;
1548 default:
1549 O << "invalid_param_" << Imm;
1550 }
1551}
1552
1553void AMDGPUInstPrinter::printInterpAttr(const MCInst *MI, unsigned OpNum,
1554 const MCSubtargetInfo &STI,
1555 raw_ostream &O) {
1556 unsigned Attr = MI->getOperand(OpNum).getImm();
1557 O << "attr" << Attr;
1558}
1559
1560void AMDGPUInstPrinter::printInterpAttrChan(const MCInst *MI, unsigned OpNum,
1561 const MCSubtargetInfo &STI,
1562 raw_ostream &O) {
1563 unsigned Chan = MI->getOperand(OpNum).getImm();
1564 O << '.' << "xyzw"[Chan & 0x3];
1565}
1566
1567void AMDGPUInstPrinter::printGPRIdxMode(const MCInst *MI, unsigned OpNo,
1568 const MCSubtargetInfo &STI,
1569 raw_ostream &O) {
1570 using namespace llvm::AMDGPU::VGPRIndexMode;
1571 unsigned Val = MI->getOperand(OpNo).getImm();
1572
1573 if ((Val & ~ENABLE_MASK) != 0) {
1574 O << formatHex(static_cast<uint64_t>(Val));
1575 } else {
1576 O << "gpr_idx(";
1577 bool NeedComma = false;
1578 for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {
1579 if (Val & (1 << ModeId)) {
1580 if (NeedComma)
1581 O << ',';
1582 O << IdSymbolic[ModeId];
1583 NeedComma = true;
1584 }
1585 }
1586 O << ')';
1587 }
1588}
1589
1590void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
1591 const MCSubtargetInfo &STI,
1592 raw_ostream &O) {
1593 printRegularOperand(MI, OpNo, STI, O);
1594 O << ", ";
1595 printRegularOperand(MI, OpNo + 1, STI, O);
1596}
1597
1598void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1599 raw_ostream &O, StringRef Asm,
1601 const MCOperand &Op = MI->getOperand(OpNo);
1602 assert(Op.isImm());
1603 if (Op.getImm() == 1) {
1604 O << Asm;
1605 } else {
1606 O << Default;
1607 }
1608}
1609
1610void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
1611 raw_ostream &O, char Asm) {
1612 const MCOperand &Op = MI->getOperand(OpNo);
1613 assert(Op.isImm());
1614 if (Op.getImm() == 1)
1615 O << Asm;
1616}
1617
1618void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo,
1619 const MCSubtargetInfo &STI,
1620 raw_ostream &O) {
1621 int Imm = MI->getOperand(OpNo).getImm();
1622 if (Imm == SIOutMods::MUL2)
1623 O << " mul:2";
1624 else if (Imm == SIOutMods::MUL4)
1625 O << " mul:4";
1626 else if (Imm == SIOutMods::DIV2)
1627 O << " div:2";
1628}
1629
1630void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
1631 const MCSubtargetInfo &STI,
1632 raw_ostream &O) {
1633 using namespace llvm::AMDGPU::SendMsg;
1634
1635 const unsigned Imm16 = MI->getOperand(OpNo).getImm();
1636
1637 uint16_t MsgId;
1638 uint16_t OpId;
1640 decodeMsg(Imm16, MsgId, OpId, StreamId, STI);
1641
1642 StringRef MsgName = getMsgName(MsgId, STI);
1643
1644 if (!MsgName.empty() && isValidMsgOp(MsgId, OpId, STI) &&
1645 isValidMsgStream(MsgId, OpId, StreamId, STI)) {
1646 O << "sendmsg(" << MsgName;
1647 if (msgRequiresOp(MsgId, STI)) {
1648 O << ", " << getMsgOpName(MsgId, OpId, STI);
1649 if (msgSupportsStream(MsgId, OpId, STI)) {
1650 O << ", " << StreamId;
1651 }
1652 }
1653 O << ')';
1654 } else if (encodeMsg(MsgId, OpId, StreamId) == Imm16) {
1655 O << "sendmsg(" << MsgId << ", " << OpId << ", " << StreamId << ')';
1656 } else {
1657 O << Imm16; // Unknown imm16 code.
1658 }
1659}
1660
1661static void printSwizzleBitmask(const uint16_t AndMask,
1662 const uint16_t OrMask,
1663 const uint16_t XorMask,
1664 raw_ostream &O) {
1665 using namespace llvm::AMDGPU::Swizzle;
1666
1667 uint16_t Probe0 = ((0 & AndMask) | OrMask) ^ XorMask;
1668 uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask;
1669
1670 O << "\"";
1671
1672 for (unsigned Mask = 1 << (BITMASK_WIDTH - 1); Mask > 0; Mask >>= 1) {
1673 uint16_t p0 = Probe0 & Mask;
1674 uint16_t p1 = Probe1 & Mask;
1675
1676 if (p0 == p1) {
1677 if (p0 == 0) {
1678 O << "0";
1679 } else {
1680 O << "1";
1681 }
1682 } else {
1683 if (p0 == 0) {
1684 O << "p";
1685 } else {
1686 O << "i";
1687 }
1688 }
1689 }
1690
1691 O << "\"";
1692}
1693
1694void AMDGPUInstPrinter::printSwizzle(const MCInst *MI, unsigned OpNo,
1695 const MCSubtargetInfo &STI,
1696 raw_ostream &O) {
1697 using namespace llvm::AMDGPU::Swizzle;
1698
1699 uint16_t Imm = MI->getOperand(OpNo).getImm();
1700 if (Imm == 0) {
1701 return;
1702 }
1703
1704 O << " offset:";
1705
1706 // Rotate and FFT modes
1707 if (Imm >= ROTATE_MODE_LO && AMDGPU::isGFX9Plus(STI)) {
1708 if (Imm >= FFT_MODE_LO) {
1709 O << "swizzle(" << IdSymbolic[ID_FFT] << ',' << (Imm & FFT_SWIZZLE_MASK)
1710 << ')';
1711 } else if (Imm >= ROTATE_MODE_LO) {
1712 O << "swizzle(" << IdSymbolic[ID_ROTATE] << ','
1713 << ((Imm >> ROTATE_DIR_SHIFT) & ROTATE_DIR_MASK) << ','
1714 << ((Imm >> ROTATE_SIZE_SHIFT) & ROTATE_SIZE_MASK) << ')';
1715 }
1716 return;
1717 }
1718
1719 // Basic mode
1721 O << "swizzle(" << IdSymbolic[ID_QUAD_PERM];
1722 for (unsigned I = 0; I < LANE_NUM; ++I) {
1723 O << ",";
1724 O << formatDec(Imm & LANE_MASK);
1725 Imm >>= LANE_SHIFT;
1726 }
1727 O << ")";
1728
1729 } else if ((Imm & BITMASK_PERM_ENC_MASK) == BITMASK_PERM_ENC) {
1730
1731 uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK;
1732 uint16_t OrMask = (Imm >> BITMASK_OR_SHIFT) & BITMASK_MASK;
1733 uint16_t XorMask = (Imm >> BITMASK_XOR_SHIFT) & BITMASK_MASK;
1734
1735 if (AndMask == BITMASK_MAX && OrMask == 0 && llvm::popcount(XorMask) == 1) {
1736
1737 O << "swizzle(" << IdSymbolic[ID_SWAP];
1738 O << ",";
1739 O << formatDec(XorMask);
1740 O << ")";
1741
1742 } else if (AndMask == BITMASK_MAX && OrMask == 0 && XorMask > 0 &&
1743 isPowerOf2_64(XorMask + 1)) {
1744
1745 O << "swizzle(" << IdSymbolic[ID_REVERSE];
1746 O << ",";
1747 O << formatDec(XorMask + 1);
1748 O << ")";
1749
1750 } else {
1751
1752 uint16_t GroupSize = BITMASK_MAX - AndMask + 1;
1753 if (GroupSize > 1 &&
1754 isPowerOf2_64(GroupSize) &&
1755 OrMask < GroupSize &&
1756 XorMask == 0) {
1757
1758 O << "swizzle(" << IdSymbolic[ID_BROADCAST];
1759 O << ",";
1760 O << formatDec(GroupSize);
1761 O << ",";
1762 O << formatDec(OrMask);
1763 O << ")";
1764
1765 } else {
1766 O << "swizzle(" << IdSymbolic[ID_BITMASK_PERM];
1767 O << ",";
1768 printSwizzleBitmask(AndMask, OrMask, XorMask, O);
1769 O << ")";
1770 }
1771 }
1772 } else {
1773 printU16ImmDecOperand(MI, OpNo, O);
1774 }
1775}
1776
1777void AMDGPUInstPrinter::printSWaitCnt(const MCInst *MI, unsigned OpNo,
1778 const MCSubtargetInfo &STI,
1779 raw_ostream &O) {
1781
1782 unsigned SImm16 = MI->getOperand(OpNo).getImm();
1783 unsigned Vmcnt, Expcnt, Lgkmcnt;
1784 decodeWaitcnt(ISA, SImm16, Vmcnt, Expcnt, Lgkmcnt);
1785
1786 bool IsDefaultVmcnt = Vmcnt == getVmcntBitMask(ISA);
1787 bool IsDefaultExpcnt = Expcnt == getExpcntBitMask(ISA);
1788 bool IsDefaultLgkmcnt = Lgkmcnt == getLgkmcntBitMask(ISA);
1789 bool PrintAll = IsDefaultVmcnt && IsDefaultExpcnt && IsDefaultLgkmcnt;
1790
1791 bool NeedSpace = false;
1792
1793 if (!IsDefaultVmcnt || PrintAll) {
1794 O << "vmcnt(" << Vmcnt << ')';
1795 NeedSpace = true;
1796 }
1797
1798 if (!IsDefaultExpcnt || PrintAll) {
1799 if (NeedSpace)
1800 O << ' ';
1801 O << "expcnt(" << Expcnt << ')';
1802 NeedSpace = true;
1803 }
1804
1805 if (!IsDefaultLgkmcnt || PrintAll) {
1806 if (NeedSpace)
1807 O << ' ';
1808 O << "lgkmcnt(" << Lgkmcnt << ')';
1809 }
1810}
1811
1812void AMDGPUInstPrinter::printDepCtr(const MCInst *MI, unsigned OpNo,
1813 const MCSubtargetInfo &STI,
1814 raw_ostream &O) {
1815 using namespace llvm::AMDGPU::DepCtr;
1816
1817 uint64_t Imm16 = MI->getOperand(OpNo).getImm() & 0xffff;
1818
1819 bool HasNonDefaultVal = false;
1820 if (isSymbolicDepCtrEncoding(Imm16, HasNonDefaultVal, STI)) {
1821 int Id = 0;
1822 StringRef Name;
1823 unsigned Val;
1824 bool IsDefault;
1825 bool NeedSpace = false;
1826 while (decodeDepCtr(Imm16, Id, Name, Val, IsDefault, STI)) {
1827 if (!IsDefault || !HasNonDefaultVal) {
1828 if (NeedSpace)
1829 O << ' ';
1830 O << Name << '(' << Val << ')';
1831 NeedSpace = true;
1832 }
1833 }
1834 } else {
1835 O << formatHex(Imm16);
1836 }
1837}
1838
1840 const MCSubtargetInfo &STI,
1841 raw_ostream &O) {
1842 const char *BadInstId = "/* invalid instid value */";
1843 static const std::array<const char *, 12> InstIds = {
1844 "NO_DEP", "VALU_DEP_1", "VALU_DEP_2",
1845 "VALU_DEP_3", "VALU_DEP_4", "TRANS32_DEP_1",
1846 "TRANS32_DEP_2", "TRANS32_DEP_3", "FMA_ACCUM_CYCLE_1",
1847 "SALU_CYCLE_1", "SALU_CYCLE_2", "SALU_CYCLE_3"};
1848
1849 const char *BadInstSkip = "/* invalid instskip value */";
1850 static const std::array<const char *, 6> InstSkips = {
1851 "SAME", "NEXT", "SKIP_1", "SKIP_2", "SKIP_3", "SKIP_4"};
1852
1853 unsigned SImm16 = MI->getOperand(OpNo).getImm();
1854 const char *Prefix = "";
1855
1856 unsigned Value = SImm16 & 0xF;
1857 if (Value) {
1858 const char *Name = Value < InstIds.size() ? InstIds[Value] : BadInstId;
1859 O << Prefix << "instid0(" << Name << ')';
1860 Prefix = " | ";
1861 }
1862
1863 Value = (SImm16 >> 4) & 7;
1864 if (Value) {
1865 const char *Name =
1866 Value < InstSkips.size() ? InstSkips[Value] : BadInstSkip;
1867 O << Prefix << "instskip(" << Name << ')';
1868 Prefix = " | ";
1869 }
1870
1871 Value = (SImm16 >> 7) & 0xF;
1872 if (Value) {
1873 const char *Name = Value < InstIds.size() ? InstIds[Value] : BadInstId;
1874 O << Prefix << "instid1(" << Name << ')';
1875 Prefix = " | ";
1876 }
1877
1878 if (!*Prefix)
1879 O << "0";
1880}
1881
1882void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo,
1883 const MCSubtargetInfo &STI, raw_ostream &O) {
1884 using namespace llvm::AMDGPU::Hwreg;
1885 unsigned Val = MI->getOperand(OpNo).getImm();
1886 auto [Id, Offset, Width] = HwregEncoding::decode(Val);
1887 StringRef HwRegName = getHwreg(Id, STI);
1888
1889 O << "hwreg(";
1890 if (!HwRegName.empty()) {
1891 O << HwRegName;
1892 } else {
1893 O << Id;
1894 }
1896 O << ", " << Offset << ", " << Width;
1897 O << ')';
1898}
1899
1900void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo,
1901 const MCSubtargetInfo &STI,
1902 raw_ostream &O) {
1903 uint16_t Imm = MI->getOperand(OpNo).getImm();
1904 if (Imm == 0) {
1905 return;
1906 }
1907
1908 O << ' ' << formatDec(Imm);
1909}
1910
1911void AMDGPUInstPrinter::printNamedInt(const MCInst *MI, unsigned OpNo,
1912 const MCSubtargetInfo &STI,
1913 raw_ostream &O, StringRef Prefix,
1914 bool PrintInHex, bool AlwaysPrint) {
1915 int64_t V = MI->getOperand(OpNo).getImm();
1916 if (AlwaysPrint || V != 0)
1917 O << ' ' << Prefix << ':' << (PrintInHex ? formatHex(V) : formatDec(V));
1918}
1919
1920void AMDGPUInstPrinter::printBitOp3(const MCInst *MI, unsigned OpNo,
1921 const MCSubtargetInfo &STI,
1922 raw_ostream &O) {
1923 uint8_t Imm = MI->getOperand(OpNo).getImm();
1924 if (!Imm)
1925 return;
1926
1927 O << " bitop3:";
1928 if (Imm <= 10)
1929 O << formatDec(Imm);
1930 else
1931 O << formatHex(static_cast<uint64_t>(Imm));
1932}
1933
1934void AMDGPUInstPrinter::printScaleSel(const MCInst *MI, unsigned OpNo,
1935 const MCSubtargetInfo &STI,
1936 raw_ostream &O) {
1937 uint8_t Imm = MI->getOperand(OpNo).getImm();
1938 if (!Imm)
1939 return;
1940
1941 O << " scale_sel:" << formatDec(Imm);
1942}
1943
1944#include "AMDGPUGenAsmWriter.inc"
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
static void printSwizzleBitmask(const uint16_t AndMask, const uint16_t OrMask, const uint16_t XorMask, raw_ostream &O)
static bool printImmediateBFloat16(uint32_t Imm, const MCSubtargetInfo &STI, raw_ostream &O)
static bool allOpsDefaultValue(const int *Ops, int NumOps, int Mod, bool IsPacked, bool HasDstSel)
static MCPhysReg getRegFromMIA(MCPhysReg Reg, unsigned OpNo, const MCInstrDesc &Desc, const MCRegisterInfo &MRI, const AMDGPUMCInstrAnalysis &MIA)
static MCPhysReg getRegForPrinting(MCPhysReg Reg, const MCRegisterInfo &MRI)
static bool printImmediateFP16(uint32_t Imm, const MCSubtargetInfo &STI, raw_ostream &O)
Provides AMDGPU specific target descriptions.
IRTranslator LLVM IR MI
const size_t AbstractManglingParser< Derived, Alloc >::NumOps
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
#define I(x, y, z)
Definition MD5.cpp:58
Register Reg
if(auto Err=PB.parsePassPipeline(MPM, Passes)) return wrap(std MPM run * Mod
void printSwizzle(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printEndpgm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
static const char * getRegisterName(MCRegister Reg)
static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O, StringRef Asm, StringRef Default="")
void printDepCtr(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printHwreg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printSendMsg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
static void printRegOperand(MCRegister Reg, raw_ostream &O, const MCRegisterInfo &MRI)
void printRegName(raw_ostream &OS, MCRegister Reg) override
Print the assembler register name.
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override
Print the specified MCInst to the specified raw_ostream.
void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)
void printSWaitCnt(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printOModSI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printSDelayALU(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printExpr(raw_ostream &, const MCExpr &) const
format_object< int64_t > formatHex(int64_t Value) const
const MCInstrInfo & MII
format_object< int64_t > formatDec(int64_t Value) const
Utility functions to print decimal/hexadecimal values.
const MCRegisterInfo & MRI
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
const MCAsmInfo & MAI
const MCInstrAnalysis * MIA
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
Describe properties that are true of each instruction in the target description file.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition MCInstrInfo.h:90
Instances of this class represent operands of the MCInst class.
Definition MCInst.h:40
MCRegisterClass - Base class of TargetRegisterClass.
unsigned getID() const
getID() - Return the register class ID number.
MCRegister getRegister(unsigned i) const
getRegister - Return the specified register in the class.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Wrapper class representing physical registers. Should be passed by value.
Definition MCRegister.h:33
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
StringRef getCPU() const
virtual unsigned getHwMode(enum HwModeType type=HwMode_Default) const
HwMode ID corresponding to the 'type' parameter is retrieved from the HwMode bit set of the current s...
StringRef - Represent a constant reference to a string, i.e.
Definition StringRef.h:55
constexpr bool empty() const
empty - Check if the string is empty.
Definition StringRef.h:143
LLVM Value Representation.
Definition Value.h:75
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
StringRef getHwreg(uint64_t Encoding, const MCSubtargetInfo &STI)
bool isValidUnifiedFormat(unsigned Id, const MCSubtargetInfo &STI)
StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI)
bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI)
StringRef getDfmtName(unsigned Id)
StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI)
void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId, const MCSubtargetInfo &STI)
StringRef getMsgName(uint64_t Encoding, const MCSubtargetInfo &STI)
Map from an encoding to the symbolic name for a msg_id immediate.
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
StringRef getMsgOpName(int64_t MsgId, uint64_t Encoding, const MCSubtargetInfo &STI)
Map from an encoding to the symbolic name for a sendmsg operation.
bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI)
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
const char *const IdSymbolic[]
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
bool isVOPCAsmOnly(unsigned Opc)
unsigned getTemporalHintType(const MCInstrDesc TID)
const MCRegisterClass * getVGPRPhysRegClass(MCPhysReg Reg, const MCRegisterInfo &MRI)
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST)
For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.
bool isGFX12Plus(const MCSubtargetInfo &STI)
bool isGFX940(const MCSubtargetInfo &STI)
LLVM_ABI IsaVersion getIsaVersion(StringRef GPU)
LLVM_READNONE bool isLegalDPALU_DPPControl(const MCSubtargetInfo &ST, unsigned DC)
bool isSI(const MCSubtargetInfo &STI)
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, OpName NamedIdx)
bool getVOP3IsSingle(unsigned Opc)
bool getVOP1IsSingle(unsigned Opc)
bool isGFX90A(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
bool isGFX12(const MCSubtargetInfo &STI)
unsigned getVmcntBitMask(const IsaVersion &Version)
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
unsigned getLgkmcntBitMask(const IsaVersion &Version)
std::pair< const AMDGPU::OpName *, const AMDGPU::OpName * > getVGPRLoweringOperandTables(const MCInstrDesc &Desc)
unsigned getExpcntBitMask(const IsaVersion &Version)
bool isInlineValue(unsigned Reg)
bool isGFX10Plus(const MCSubtargetInfo &STI)
@ OPERAND_REG_IMM_INT64
Definition SIDefines.h:202
@ OPERAND_REG_IMM_V2FP16
Definition SIDefines.h:209
@ OPERAND_REG_INLINE_C_FP64
Definition SIDefines.h:222
@ OPERAND_REG_INLINE_C_BF16
Definition SIDefines.h:219
@ OPERAND_REG_INLINE_C_V2BF16
Definition SIDefines.h:224
@ OPERAND_REG_IMM_V2INT16
Definition SIDefines.h:210
@ OPERAND_REG_IMM_BF16
Definition SIDefines.h:206
@ OPERAND_REG_IMM_INT32
Operands with register, 32-bit, or 64-bit immediate.
Definition SIDefines.h:201
@ OPERAND_REG_IMM_V2BF16
Definition SIDefines.h:208
@ OPERAND_REG_IMM_FP16
Definition SIDefines.h:207
@ OPERAND_REG_INLINE_C_INT64
Definition SIDefines.h:218
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
Definition SIDefines.h:216
@ OPERAND_REG_IMM_NOINLINE_V2FP16
Definition SIDefines.h:211
@ OPERAND_REG_IMM_FP64
Definition SIDefines.h:205
@ OPERAND_REG_INLINE_C_V2FP16
Definition SIDefines.h:225
@ OPERAND_REG_INLINE_AC_INT32
Operands with an AccVGPR register or inline constant.
Definition SIDefines.h:236
@ OPERAND_REG_INLINE_AC_FP32
Definition SIDefines.h:237
@ OPERAND_REG_IMM_V2INT32
Definition SIDefines.h:212
@ OPERAND_REG_IMM_FP32
Definition SIDefines.h:204
@ OPERAND_REG_INLINE_C_FP32
Definition SIDefines.h:221
@ OPERAND_REG_INLINE_C_INT32
Definition SIDefines.h:217
@ OPERAND_REG_INLINE_C_V2INT16
Definition SIDefines.h:223
@ OPERAND_REG_IMM_V2FP32
Definition SIDefines.h:213
@ OPERAND_REG_INLINE_AC_FP64
Definition SIDefines.h:238
@ OPERAND_REG_INLINE_C_FP16
Definition SIDefines.h:220
@ OPERAND_REG_IMM_INT16
Definition SIDefines.h:203
@ OPERAND_INLINE_SPLIT_BARRIER_INT32
Definition SIDefines.h:228
bool isDPALU_DPP(const MCInstrDesc &OpDesc, const MCInstrInfo &MII, const MCSubtargetInfo &ST)
bool isGFX9Plus(const MCSubtargetInfo &STI)
MCPhysReg getVGPRWithMSBs(MCPhysReg Reg, unsigned MSBs, const MCRegisterInfo &MRI)
If Reg is a low VGPR return a corresponding high VGPR with MSBs set.
bool isCvt_F32_Fp8_Bf8_e64(unsigned Opc)
MCRegister mc2PseudoReg(MCRegister Reg)
Convert hardware register Reg to a pseudo register.
bool isCI(const MCSubtargetInfo &STI)
bool getVOP2IsSingle(unsigned Opc)
bool isPermlane16(unsigned Opc)
@ OPERAND_IMMEDIATE
Definition MCInstrDesc.h:62
This is an optimization pass for GlobalISel generic memory operations.
@ Offset
Definition DWP.cpp:477
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
Definition MathExtras.h:174
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
Definition MathExtras.h:293
Op::Description Desc
MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
constexpr uint32_t Hi_32(uint64_t Value)
Return the high 32 bits of a 64 bit value.
Definition MathExtras.h:159
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
Definition MathExtras.h:198
constexpr uint32_t Lo_32(uint64_t Value)
Return the low 32 bits of a 64 bit value.
Definition MathExtras.h:164
@ Mod
The access may modify the value stored in memory.
Definition ModRef.h:34
To bit_cast(const From &from) noexcept
Definition bit.h:90
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition MCRegister.h:21
DWARFExpression::Operation Op
constexpr int32_t SignExtend32(uint32_t X)
Sign-extend the number in the bottom B bits of X to a 32-bit integer.
Definition MathExtras.h:565
@ Default
The result values are uniform if and only if all operands are uniform.
Definition Uniformity.h:20
int popcount(T Value) noexcept
Count the number of set bits in a value.
Definition bit.h:154
#define N
static std::tuple< typename Fields::ValueType... > decode(uint64_t Encoded)
Instruction set architecture version.