26#define GET_INSTRINFO_CTOR_DTOR
27#include "MSP430GenInstrInfo.inc"
30void MSP430InstrInfo::anchor() {}
50 if (RC == &MSP430::GR16RegClass)
54 else if (RC == &MSP430::GR8RegClass)
78 if (RC == &MSP430::GR16RegClass)
82 else if (RC == &MSP430::GR8RegClass)
95 if (MSP430::GR16RegClass.
contains(DestReg, SrcReg))
96 Opc = MSP430::MOV16rr;
97 else if (MSP430::GR8RegClass.
contains(DestReg, SrcReg))
107 int *BytesRemoved)
const {
108 assert(!BytesRemoved &&
"code size not handled");
115 if (
I->isDebugInstr())
117 if (
I->getOpcode() != MSP430::JMP &&
118 I->getOpcode() != MSP430::JCC &&
119 I->getOpcode() != MSP430::Bi &&
120 I->getOpcode() != MSP430::Br &&
121 I->getOpcode() != MSP430::Bm)
124 I->eraseFromParent();
134 assert(
Cond.size() == 1 &&
"Invalid Xbranch condition!");
168 bool AllowModify)
const {
174 if (
I->isDebugInstr())
179 if (!isUnpredicatedTerminator(*
I))
188 if (
I->getOpcode() == MSP430::Br ||
189 I->getOpcode() == MSP430::Bm)
193 if (
I->getOpcode() == MSP430::JMP ||
I->getOpcode() == MSP430::Bi) {
195 TBB =
I->getOperand(0).getMBB();
207 I->eraseFromParent();
213 TBB =
I->getOperand(0).getMBB();
218 assert(
I->getOpcode() == MSP430::JCC &&
"Invalid conditional branch");
227 TBB =
I->getOperand(0).getMBB();
239 if (
TBB !=
I->getOperand(0).getMBB())
244 if (OldBranchCode == BranchCode)
258 int *BytesAdded)
const {
260 assert(
TBB &&
"insertBranch must not be told to insert a fallthrough");
262 "MSP430 branch conditions have one component!");
263 assert(!BytesAdded &&
"code size not handled");
267 assert(!FBB &&
"Unconditional branch with multiple successors!");
291 switch (
Desc.getOpcode()) {
292 case TargetOpcode::CFI_INSTRUCTION:
293 case TargetOpcode::EH_LABEL:
294 case TargetOpcode::IMPLICIT_DEF:
295 case TargetOpcode::KILL:
296 case TargetOpcode::DBG_VALUE:
298 case TargetOpcode::INLINEASM:
299 case TargetOpcode::INLINEASM_BR: {
307 return Desc.getSize();
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const override
Measure the specified inline asm to determine an approximation of its length.
Describe properties that are true of each instruction in the target description file.
Wrapper class representing physical registers. Should be passed by value.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
MSP430InstrInfo(MSP430Subtarget &STI)
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
GetInstSize - Return the number of bytes of code the specified instruction may be.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Representation of each machine instruction.
A description of a memory reference used in the backend.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
static MachineOperand CreateImm(int64_t Val)
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
TargetInstrInfo - Interface to description of machine instruction set.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetInstrInfo * getInstrInfo() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
unsigned getDefRegState(bool B)
unsigned getKillRegState(bool B)
Description of the encoding of one expression Op.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.