LLVM 20.0.0git
PPCAsmBackend.cpp
Go to the documentation of this file.
1//===-- PPCAsmBackend.cpp - PPC Assembler Backend -------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
14#include "llvm/MC/MCAssembler.h"
21#include "llvm/MC/MCSymbolELF.h"
23#include "llvm/MC/MCValue.h"
26using namespace llvm;
27
28static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
29 switch (Kind) {
30 default:
31 llvm_unreachable("Unknown fixup kind!");
32 case FK_Data_1:
33 case FK_Data_2:
34 case FK_Data_4:
35 case FK_Data_8:
37 return Value;
40 return Value & 0xfffc;
44 return Value & 0x3fffffc;
46 return Value & 0xffff;
49 return Value & 0xfffc;
52 return Value & 0x3ffffffff;
53 }
54}
55
56static unsigned getFixupKindNumBytes(unsigned Kind) {
57 switch (Kind) {
58 default:
59 llvm_unreachable("Unknown fixup kind!");
60 case FK_Data_1:
61 return 1;
62 case FK_Data_2:
66 return 2;
67 case FK_Data_4:
73 return 4;
76 case FK_Data_8:
77 return 8;
79 return 0;
80 }
81}
82
83namespace {
84
85class PPCAsmBackend : public MCAsmBackend {
86protected:
87 Triple TT;
88public:
89 PPCAsmBackend(const Target &T, const Triple &TT)
90 : MCAsmBackend(TT.isLittleEndian() ? llvm::endianness::little
91 : llvm::endianness::big),
92 TT(TT) {}
93
94 unsigned getNumFixupKinds() const override {
96 }
97
98 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
99 const static MCFixupKindInfo InfosBE[PPC::NumTargetFixupKinds] = {
100 // name offset bits flags
101 { "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
102 { "fixup_ppc_br24_notoc", 6, 24, MCFixupKindInfo::FKF_IsPCRel },
103 { "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel },
104 { "fixup_ppc_br24abs", 6, 24, 0 },
105 { "fixup_ppc_brcond14abs", 16, 14, 0 },
106 { "fixup_ppc_half16", 0, 16, 0 },
107 { "fixup_ppc_half16ds", 0, 14, 0 },
108 { "fixup_ppc_pcrel34", 0, 34, MCFixupKindInfo::FKF_IsPCRel },
109 { "fixup_ppc_imm34", 0, 34, 0 },
110 { "fixup_ppc_nofixup", 0, 0, 0 }
111 };
112 const static MCFixupKindInfo InfosLE[PPC::NumTargetFixupKinds] = {
113 // name offset bits flags
114 { "fixup_ppc_br24", 2, 24, MCFixupKindInfo::FKF_IsPCRel },
115 { "fixup_ppc_br24_notoc", 2, 24, MCFixupKindInfo::FKF_IsPCRel },
116 { "fixup_ppc_brcond14", 2, 14, MCFixupKindInfo::FKF_IsPCRel },
117 { "fixup_ppc_br24abs", 2, 24, 0 },
118 { "fixup_ppc_brcond14abs", 2, 14, 0 },
119 { "fixup_ppc_half16", 0, 16, 0 },
120 { "fixup_ppc_half16ds", 2, 14, 0 },
121 { "fixup_ppc_pcrel34", 0, 34, MCFixupKindInfo::FKF_IsPCRel },
122 { "fixup_ppc_imm34", 0, 34, 0 },
123 { "fixup_ppc_nofixup", 0, 0, 0 }
124 };
125
126 // Fixup kinds from .reloc directive are like R_PPC_NONE/R_PPC64_NONE. They
127 // do not require any extra processing.
128 if (Kind >= FirstLiteralRelocationKind)
130
131 if (Kind < FirstTargetFixupKind)
133
134 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
135 "Invalid kind!");
136 return (Endian == llvm::endianness::little
137 ? InfosLE
138 : InfosBE)[Kind - FirstTargetFixupKind];
139 }
140
141 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
143 uint64_t Value, bool IsResolved,
144 const MCSubtargetInfo *STI) const override {
145 MCFixupKind Kind = Fixup.getKind();
146 if (Kind >= FirstLiteralRelocationKind)
147 return;
149 if (!Value) return; // Doesn't change encoding.
150
151 unsigned Offset = Fixup.getOffset();
152 unsigned NumBytes = getFixupKindNumBytes(Kind);
153
154 // For each byte of the fragment that the fixup touches, mask in the bits
155 // from the fixup value. The Value has been "split up" into the appropriate
156 // bitfields above.
157 for (unsigned i = 0; i != NumBytes; ++i) {
158 unsigned Idx =
159 Endian == llvm::endianness::little ? i : (NumBytes - 1 - i);
160 Data[Offset + i] |= uint8_t((Value >> (Idx * 8)) & 0xff);
161 }
162 }
163
164 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
165 const MCValue &Target,
166 const MCSubtargetInfo *STI) override {
167 MCFixupKind Kind = Fixup.getKind();
168 switch ((unsigned)Kind) {
169 default:
174 // If the target symbol has a local entry point we must not attempt
175 // to resolve the fixup directly. Emit a relocation and leave
176 // resolution of the final target address to the linker.
177 if (const MCSymbolRefExpr *A = Target.getSymA()) {
178 if (const auto *S = dyn_cast<MCSymbolELF>(&A->getSymbol())) {
179 // The "other" values are stored in the last 6 bits of the second
180 // byte. The traditional defines for STO values assume the full byte
181 // and thus the shift to pack it.
182 unsigned Other = S->getOther() << 2;
183 if ((Other & ELF::STO_PPC64_LOCAL_MASK) != 0)
184 return true;
185 } else if (const auto *S = dyn_cast<MCSymbolXCOFF>(&A->getSymbol())) {
186 return !Target.isAbsolute() && S->isExternal() &&
187 S->getStorageClass() == XCOFF::C_WEAKEXT;
188 }
189 }
190 return false;
191 }
192 }
193
194 void relaxInstruction(MCInst &Inst,
195 const MCSubtargetInfo &STI) const override {
196 // FIXME.
197 llvm_unreachable("relaxInstruction() unimplemented");
198 }
199
200 bool writeNopData(raw_ostream &OS, uint64_t Count,
201 const MCSubtargetInfo *STI) const override {
202 uint64_t NumNops = Count / 4;
203 for (uint64_t i = 0; i != NumNops; ++i)
204 support::endian::write<uint32_t>(OS, 0x60000000, Endian);
205
206 OS.write_zeros(Count % 4);
207
208 return true;
209 }
210};
211} // end anonymous namespace
212
213
214// FIXME: This should be in a separate file.
215namespace {
216
217class ELFPPCAsmBackend : public PPCAsmBackend {
218public:
219 ELFPPCAsmBackend(const Target &T, const Triple &TT) : PPCAsmBackend(T, TT) {}
220
221 std::unique_ptr<MCObjectTargetWriter>
222 createObjectTargetWriter() const override {
223 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
224 bool Is64 = TT.isPPC64();
225 return createPPCELFObjectWriter(Is64, OSABI);
226 }
227
228 std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;
229};
230
231class XCOFFPPCAsmBackend : public PPCAsmBackend {
232public:
233 XCOFFPPCAsmBackend(const Target &T, const Triple &TT)
234 : PPCAsmBackend(T, TT) {}
235
236 std::unique_ptr<MCObjectTargetWriter>
237 createObjectTargetWriter() const override {
238 return createPPCXCOFFObjectWriter(TT.isArch64Bit());
239 }
240
241 std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;
242};
243
244} // end anonymous namespace
245
246std::optional<MCFixupKind>
247ELFPPCAsmBackend::getFixupKind(StringRef Name) const {
248 if (TT.isOSBinFormatELF()) {
249 unsigned Type;
250 if (TT.isPPC64()) {
252#define ELF_RELOC(X, Y) .Case(#X, Y)
253#include "llvm/BinaryFormat/ELFRelocs/PowerPC64.def"
254#undef ELF_RELOC
255 .Case("BFD_RELOC_NONE", ELF::R_PPC64_NONE)
256 .Case("BFD_RELOC_16", ELF::R_PPC64_ADDR16)
257 .Case("BFD_RELOC_32", ELF::R_PPC64_ADDR32)
258 .Case("BFD_RELOC_64", ELF::R_PPC64_ADDR64)
259 .Default(-1u);
260 } else {
262#define ELF_RELOC(X, Y) .Case(#X, Y)
263#include "llvm/BinaryFormat/ELFRelocs/PowerPC.def"
264#undef ELF_RELOC
265 .Case("BFD_RELOC_NONE", ELF::R_PPC_NONE)
266 .Case("BFD_RELOC_16", ELF::R_PPC_ADDR16)
267 .Case("BFD_RELOC_32", ELF::R_PPC_ADDR32)
268 .Default(-1u);
269 }
270 if (Type != -1u)
271 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
272 }
273 return std::nullopt;
274}
275
276std::optional<MCFixupKind>
277XCOFFPPCAsmBackend::getFixupKind(StringRef Name) const {
279 .Case("R_REF", (MCFixupKind)PPC::fixup_ppc_nofixup)
280 .Default(std::nullopt);
281}
282
284 const MCSubtargetInfo &STI,
285 const MCRegisterInfo &MRI,
286 const MCTargetOptions &Options) {
287 const Triple &TT = STI.getTargetTriple();
288 if (TT.isOSBinFormatXCOFF())
289 return new XCOFFPPCAsmBackend(T, TT);
290
291 return new ELFPPCAsmBackend(T, TT);
292}
unsigned const MachineRegisterInfo * MRI
static unsigned getFixupKindNumBytes(unsigned Kind)
The number of bytes the fixup may change.
static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
@ Default
Definition: DwarfDebug.cpp:87
std::string Name
std::optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1309
static LVOptions Options
Definition: LVOptions.cpp:25
static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value)
static unsigned getFixupKindNumBytes(unsigned Kind)
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
endianness Endian
raw_pwrite_stream & OS
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:42
virtual bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const =0
Write an (optimal) nop sequence of Count bytes to the given output.
virtual void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const
Relax the instruction in the given fragment to the next wider instruction.
Definition: MCAsmBackend.h:179
virtual bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, const MCSubtargetInfo *STI)
Hook to check if a relocation is needed for some target specific reason.
Definition: MCAsmBackend.h:96
virtual unsigned getNumFixupKinds() const =0
Get the number of target specific fixup kinds.
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
virtual void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const =0
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:188
This represents an "assembler immediate".
Definition: MCValue.h:36
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
raw_ostream & write_zeros(unsigned NumZeros)
write_zeros - Insert 'NumZeros' nulls.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ STO_PPC64_LOCAL_MASK
Definition: ELF.h:413
@ fixup_ppc_pcrel34
Definition: PPCFixupKinds.h:44
@ fixup_ppc_brcond14abs
14-bit absolute relocation for conditional branches.
Definition: PPCFixupKinds.h:33
@ fixup_ppc_half16
A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like 'li' or 'addis'.
Definition: PPCFixupKinds.h:37
@ NumTargetFixupKinds
Definition: PPCFixupKinds.h:61
@ fixup_ppc_br24_notoc
Definition: PPCFixupKinds.h:24
@ fixup_ppc_brcond14
14-bit PC relative relocation for conditional branches.
Definition: PPCFixupKinds.h:27
@ fixup_ppc_half16dq
A 16-bit fixup corresponding to lo16(_foo) with implied 3 zero bits for instrs like 'lxv'.
Definition: PPCFixupKinds.h:57
@ fixup_ppc_half16ds
A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for instrs like 'std'.
Definition: PPCFixupKinds.h:41
@ fixup_ppc_nofixup
Not a true fixup, but ties a symbol to a call to __tls_get_addr for the TLS general and local dynamic...
Definition: PPCFixupKinds.h:53
@ fixup_ppc_br24abs
24-bit absolute relocation for direct branches like 'ba' and 'bla'.
Definition: PPCFixupKinds.h:30
@ C_WEAKEXT
Definition: XCOFF.h:199
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
MCAsmBackend * createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter > createPPCXCOFFObjectWriter(bool Is64Bit)
Construct a PPC XCOFF object writer.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
@ FirstTargetFixupKind
Definition: MCFixup.h:45
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
Definition: MCFixup.h:50
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
@ FK_NONE
A no-op fixup.
Definition: MCFixup.h:22
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
std::unique_ptr< MCObjectTargetWriter > createPPCELFObjectWriter(bool Is64Bit, uint8_t OSABI)
Construct an PPC ELF object writer.
endianness
Definition: bit.h:70
Target independent information on a fixup kind.
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...