36 AArch64AsmBackend(
const Target &
T,
const Triple &TT,
bool IsLittleEndian)
50 {
"fixup_aarch64_pcrel_adr_imm21", 0, 32, 0},
51 {
"fixup_aarch64_pcrel_adrp_imm21", 0, 32, 0},
52 {
"fixup_aarch64_add_imm12", 10, 12, 0},
53 {
"fixup_aarch64_ldst_imm12_scale1", 10, 12, 0},
54 {
"fixup_aarch64_ldst_imm12_scale2", 10, 12, 0},
55 {
"fixup_aarch64_ldst_imm12_scale4", 10, 12, 0},
56 {
"fixup_aarch64_ldst_imm12_scale8", 10, 12, 0},
57 {
"fixup_aarch64_ldst_imm12_scale16", 10, 12, 0},
58 {
"fixup_aarch64_ldr_pcrel_imm19", 5, 19, 0},
59 {
"fixup_aarch64_movw", 5, 16, 0},
60 {
"fixup_aarch64_pcrel_branch9", 5, 9, 0},
61 {
"fixup_aarch64_pcrel_branch14", 5, 14, 0},
62 {
"fixup_aarch64_pcrel_branch16", 5, 16, 0},
63 {
"fixup_aarch64_pcrel_branch19", 5, 19, 0},
64 {
"fixup_aarch64_pcrel_branch26", 0, 26, 0},
65 {
"fixup_aarch64_pcrel_call26", 0, 26, 0}};
89 unsigned getFixupKindContainereSizeInBytes(
unsigned Kind)
const;
135 unsigned lo2 =
Value & 0x3;
136 unsigned hi19 = (
Value & 0x1ffffc) >> 2;
137 return (hi19 << 5) | (lo2 << 29);
142 const Triple &TheTriple,
bool IsResolved) {
143 int64_t SignedValue =
static_cast<int64_t
>(
Value);
144 switch (
Fixup.getKind()) {
148 if (!isInt<21>(SignedValue))
154 if (!isInt<21>(SignedValue))
162 if (!isInt<21>(SignedValue))
167 return (
Value >> 2) & 0x7ffff;
173 if (!isUInt<12>(
Value))
180 if (!isUInt<13>(
Value))
189 if (!isUInt<14>(
Value))
198 if (!isUInt<15>(
Value))
207 if (!isUInt<16>(
Value))
219 if (SignedValue > 0xFFFF || SignedValue < -0xFFFF)
221 "fixup value out of range [-0xFFFF, 0xFFFF]");
225 SignedValue = ~SignedValue;
231 "relocation for a thread-local variable points to an "
249 SignedValue = SignedValue >> 16;
252 SignedValue = SignedValue >> 32;
255 SignedValue = SignedValue >> 48;
282 if (SignedValue > 0xFFFF || SignedValue < -0xFFFF)
287 SignedValue = ~SignedValue;
289 }
else if (
Value > 0xFFFF) {
296 if (!isInt<11>(SignedValue))
301 return (
Value >> 2) & 0x1ff;
304 if (!isInt<16>(SignedValue))
309 return (
Value >> 2) & 0x3fff;
312 SignedValue = -SignedValue;
315 if (SignedValue < 0 || SignedValue > ((1 << 18) - 1))
320 return (
Value >> 2) & 0xffff;
327 "cannot perform a PC-relative fixup with a non-zero "
331 if (!isInt<28>(SignedValue))
336 return (
Value >> 2) & 0x3ffffff;
347std::optional<MCFixupKind>
353#define ELF_RELOC(X, Y) .Case(#X, Y)
354#include "llvm/BinaryFormat/ELFRelocs/AArch64.def"
356 .
Case(
"BFD_RELOC_NONE", ELF::R_AARCH64_NONE)
357 .
Case(
"BFD_RELOC_16", ELF::R_AARCH64_ABS16)
358 .
Case(
"BFD_RELOC_32", ELF::R_AARCH64_ABS32)
359 .
Case(
"BFD_RELOC_64", ELF::R_AARCH64_ABS64)
368unsigned AArch64AsmBackend::getFixupKindContainereSizeInBytes(
unsigned Kind)
const {
436 const auto *Expr = dyn_cast<AArch64AuthMCExpr>(
Fixup.getValue());
438 getContext().reportError(
Fixup.getValue()->getLoc(),
439 "expected relocatable expression");
445 (
uint64_t(Expr->hasAddressDiversity()) << 63);
454 int64_t SignedValue =
static_cast<int64_t
>(
Value);
462 "Invalid fixup offset!");
465 unsigned FulleSizeInBytes = getFixupKindContainereSizeInBytes(
Fixup.getKind());
469 if (FulleSizeInBytes == 0) {
471 for (
unsigned i = 0; i != NumBytes; ++i) {
476 assert(
Fixup.getOffset() + FulleSizeInBytes <=
F.getSize() &&
477 "Invalid fixup size!");
478 assert(NumBytes <= FulleSizeInBytes &&
"Invalid fixup size!");
479 for (
unsigned i = 0; i != NumBytes; ++i) {
480 unsigned Idx = FulleSizeInBytes - 1 - i;
494 Data[3] &= ~(1 << 6);
500bool AArch64AsmBackend::fixupNeedsRelaxation(
const MCFixup &
Fixup,
506 return int64_t(
Value) != int64_t(int8_t(
Value));
518 for (
uint64_t i = 0; i != Count; ++i)
519 OS.
write(
"\x1f\x20\x03\xd5", 4);
531 UNWIND_ARM64_MODE_FRAMELESS = 0x02000000,
538 UNWIND_ARM64_MODE_DWARF = 0x03000000,
546 UNWIND_ARM64_MODE_FRAME = 0x04000000,
549 UNWIND_ARM64_FRAME_X19_X20_PAIR = 0x00000001,
550 UNWIND_ARM64_FRAME_X21_X22_PAIR = 0x00000002,
551 UNWIND_ARM64_FRAME_X23_X24_PAIR = 0x00000004,
552 UNWIND_ARM64_FRAME_X25_X26_PAIR = 0x00000008,
553 UNWIND_ARM64_FRAME_X27_X28_PAIR = 0x00000010,
554 UNWIND_ARM64_FRAME_D8_D9_PAIR = 0x00000100,
555 UNWIND_ARM64_FRAME_D10_D11_PAIR = 0x00000200,
556 UNWIND_ARM64_FRAME_D12_D13_PAIR = 0x00000400,
557 UNWIND_ARM64_FRAME_D14_D15_PAIR = 0x00000800
563class DarwinAArch64AsmBackend :
public AArch64AsmBackend {
570 return (StackSize / 16) << 12;
578 std::unique_ptr<MCObjectTargetWriter>
579 createObjectTargetWriter()
const override {
591 return CU::UNWIND_ARM64_MODE_FRAMELESS;
592 if (!isDarwinCanonicalPersonality(FI->
Personality) &&
594 return CU::UNWIND_ARM64_MODE_DWARF;
600 int64_t CurOffset = 0;
601 for (
size_t i = 0, e = Instrs.
size(); i != e; ++i) {
607 return CU::UNWIND_ARM64_MODE_DWARF;
617 if (XReg != AArch64::FP)
618 return CU::UNWIND_ARM64_MODE_DWARF;
621 return CU::UNWIND_ARM64_MODE_DWARF;
625 return CU::UNWIND_ARM64_MODE_DWARF;
628 return CU::UNWIND_ARM64_MODE_DWARF;
631 return CU::UNWIND_ARM64_MODE_DWARF;
640 if (LRReg != AArch64::LR ||
FPReg != AArch64::FP)
641 return CU::UNWIND_ARM64_MODE_DWARF;
644 CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAME;
650 return CU::UNWIND_ARM64_MODE_DWARF;
659 return CU::UNWIND_ARM64_MODE_DWARF;
661 if (CurOffset != 0 && Inst.
getOffset() != CurOffset - 8)
662 return CU::UNWIND_ARM64_MODE_DWARF;
667 return CU::UNWIND_ARM64_MODE_DWARF;
671 return CU::UNWIND_ARM64_MODE_DWARF;
685 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 &&
686 (CompactUnwindEncoding & 0xF1E) == 0)
687 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X19_X20_PAIR;
688 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 &&
689 (CompactUnwindEncoding & 0xF1C) == 0)
690 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X21_X22_PAIR;
691 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 &&
692 (CompactUnwindEncoding & 0xF18) == 0)
693 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X23_X24_PAIR;
694 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 &&
695 (CompactUnwindEncoding & 0xF10) == 0)
696 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X25_X26_PAIR;
697 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 &&
698 (CompactUnwindEncoding & 0xF00) == 0)
699 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X27_X28_PAIR;
708 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 &&
709 (CompactUnwindEncoding & 0xE00) == 0)
710 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D8_D9_PAIR;
711 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 &&
712 (CompactUnwindEncoding & 0xC00) == 0)
713 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D10_D11_PAIR;
714 else if (Reg1 == AArch64::D12 && Reg2 == AArch64::D13 &&
715 (CompactUnwindEncoding & 0x800) == 0)
716 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D12_D13_PAIR;
717 else if (Reg1 == AArch64::D14 && Reg2 == AArch64::D15)
718 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D14_D15_PAIR;
721 return CU::UNWIND_ARM64_MODE_DWARF;
732 if (StackSize > 65520)
733 return CU::UNWIND_ARM64_MODE_DWARF;
735 CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAMELESS;
736 CompactUnwindEncoding |= encodeStackAdjustment(StackSize);
739 return CompactUnwindEncoding;
747class ELFAArch64AsmBackend :
public AArch64AsmBackend {
753 bool IsLittleEndian,
bool IsILP32)
754 : AArch64AsmBackend(
T,
TT, IsLittleEndian), OSABI(OSABI),
757 std::unique_ptr<MCObjectTargetWriter>
758 createObjectTargetWriter()
const override {
766class COFFAArch64AsmBackend :
public AArch64AsmBackend {
768 COFFAArch64AsmBackend(
const Target &
T,
const Triple &TheTriple)
769 : AArch64AsmBackend(
T, TheTriple,
true) {}
771 std::unique_ptr<MCObjectTargetWriter>
772 createObjectTargetWriter()
const override {
784 return new DarwinAArch64AsmBackend(
T, TheTriple,
MRI);
788 return new COFFAArch64AsmBackend(
T, TheTriple);
794 return new ELFAArch64AsmBackend(
T, TheTriple, OSABI,
true,
804 "Big endian is only supported for ELF targets!");
807 return new ELFAArch64AsmBackend(
T, TheTriple, OSABI,
false,
unsigned const MachineRegisterInfo * MRI
static unsigned AdrImmBits(unsigned Value)
static unsigned getFixupKindNumBytes(unsigned Kind)
The number of bytes the fixup may change.
static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)
static bool shouldForceRelocation(const MCFixup &Fixup)
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
Analysis containing CSE Info
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
PowerPC TLS Dynamic Call Fixup
static constexpr MCPhysReg FPReg
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
Generic interface to target specific assembler backends.
virtual bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const =0
Write an (optimal) nop sequence of Count bytes to the given output.
virtual MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value) const
Simple predicate for targets where !Resolved implies requiring relaxation.
virtual std::optional< MCFixupKind > getFixupKind(StringRef Name) const
Map a relocation name used in .reloc to a fixup kind.
virtual void applyFixup(const MCFragment &, const MCFixup &, const MCValue &Target, uint8_t *Data, uint64_t Value, bool IsResolved)=0
unsigned getRegister() const
OpType getOperation() const
int64_t getOffset() const
Context object for machine code objects.
LLVM_ABI bool emitCompactUnwindNonCanonical() const
LLVM_ABI void reportError(SMLoc L, const Twine &Msg)
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Wrapper class representing physical registers. Should be passed by value.
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
StringRef - Represent a constant reference to a string, i.e.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
OSType getOS() const
Get the parsed operating system type of this triple.
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
LLVM_ABI bool isArch32Bit() const
Test whether the architecture is 32-bit.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
raw_ostream & write_zeros(unsigned NumZeros)
write_zeros - Insert 'NumZeros' nulls.
raw_ostream & write(unsigned char C)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
CompactUnwindEncodings
Compact unwind encoding values.
Specifier getSymbolLoc(Specifier S)
@ fixup_aarch64_pcrel_branch9
@ fixup_aarch64_pcrel_branch16
@ fixup_aarch64_ldst_imm12_scale4
@ fixup_aarch64_pcrel_call26
@ fixup_aarch64_pcrel_branch26
@ fixup_aarch64_pcrel_branch19
@ fixup_aarch64_ldr_pcrel_imm19
@ fixup_aarch64_pcrel_adr_imm21
@ fixup_aarch64_pcrel_branch14
@ fixup_aarch64_ldst_imm12_scale2
@ fixup_aarch64_ldst_imm12_scale16
@ fixup_aarch64_pcrel_adrp_imm21
@ fixup_aarch64_add_imm12
@ fixup_aarch64_ldst_imm12_scale8
@ fixup_aarch64_ldst_imm12_scale1
Specifier getAddressFrag(Specifier S)
LLVM_ABI Expected< uint32_t > getCPUSubType(const Triple &T)
LLVM_ABI Expected< uint32_t > getCPUType(const Triple &T)
bool isRelocation(MCFixupKind FixupKind)
This is an optimization pass for GlobalISel generic memory operations.
@ FK_SecRel_2
A two-byte section relative fixup.
@ FirstLiteralRelocationKind
@ FK_Data_8
A eight-byte fixup.
@ FK_Data_1
A one-byte fixup.
@ FK_Data_4
A four-byte fixup.
@ FK_SecRel_4
A four-byte section relative fixup.
@ FK_Data_2
A two-byte fixup.
std::unique_ptr< MCObjectTargetWriter > createAArch64WinCOFFObjectWriter(const Triple &TheTriple)
MCAsmBackend * createAArch64leAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
void cantFail(Error Err, const char *Msg=nullptr)
Report a fatal error if Err is a failure value.
static MCRegister getXRegFromWReg(MCRegister Reg)
std::unique_ptr< MCObjectTargetWriter > createAArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype, bool IsILP32)
MCAsmBackend * createAArch64beAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
static MCRegister getDRegFromBReg(MCRegister Reg)
std::unique_ptr< MCObjectTargetWriter > createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
const MCSymbol * Personality
std::vector< MCCFIInstruction > Instructions
Target independent information on a fixup kind.