LLVM 23.0.0git
RISCVExpandPseudoInsts.cpp
Go to the documentation of this file.
1//===-- RISCVExpandPseudoInsts.cpp - Expand pseudo instructions -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a pass that expands pseudo instructions into target
10// instructions. This pass should be run after register allocation but before
11// the post-regalloc scheduling pass.
12//
13//===----------------------------------------------------------------------===//
14
15#include "RISCV.h"
16#include "RISCVInstrInfo.h"
17#include "RISCVTargetMachine.h"
18
19#include "llvm/CodeGen/LivePhysRegs.h"
20#include "llvm/CodeGen/MachineFunctionPass.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/MC/MCContext.h"
23
24using namespace llvm;
25
26#define RISCV_EXPAND_PSEUDO_NAME "RISC-V pseudo instruction expansion pass"
27#define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISC-V Pre-RA pseudo instruction expansion pass"
28
29namespace {
30
31class RISCVExpandPseudo : public MachineFunctionPass {
32public:
33 const RISCVSubtarget *STI;
34 const RISCVInstrInfo *TII;
35 static char ID;
36
37 RISCVExpandPseudo() : MachineFunctionPass(ID) {}
38
39 bool runOnMachineFunction(MachineFunction &MF) override;
40
41 StringRef getPassName() const override { return RISCV_EXPAND_PSEUDO_NAME; }
42
43private:
44 bool expandMBB(MachineBasicBlock &MBB);
45 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
46 MachineBasicBlock::iterator &NextMBBI);
47 bool expandCCOp(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
48 MachineBasicBlock::iterator &NextMBBI);
49 bool expandCCOpToCMov(MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator MBBI);
51 bool expandVMSET_VMCLR(MachineBasicBlock &MBB,
52 MachineBasicBlock::iterator MBBI, unsigned Opcode);
53 bool expandMV_FPR16INX(MachineBasicBlock &MBB,
54 MachineBasicBlock::iterator MBBI);
55 bool expandMV_FPR32INX(MachineBasicBlock &MBB,
56 MachineBasicBlock::iterator MBBI);
57 bool expandRV32ZdinxStore(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator MBBI);
59 bool expandRV32ZdinxLoad(MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator MBBI);
61 bool expandPseudoReadVLENBViaVSETVLIX0(MachineBasicBlock &MBB,
62 MachineBasicBlock::iterator MBBI);
63 bool expandPseudoClearFPR64(MachineBasicBlock &MBB,
64 MachineBasicBlock::iterator MBBI);
65#ifndef NDEBUG
66 unsigned getInstSizeInBytes(const MachineFunction &MF) const {
67 unsigned Size = 0;
68 for (auto &MBB : MF)
69 for (auto &MI : MBB)
70 Size += TII->getInstSizeInBytes(MI);
71 return Size;
72 }
73#endif
74};
75
76char RISCVExpandPseudo::ID = 0;
77
78bool RISCVExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
79 STI = &MF.getSubtarget<RISCVSubtarget>();
80 TII = STI->getInstrInfo();
81
82#ifndef NDEBUG
83 const unsigned OldSize = getInstSizeInBytes(MF);
84#endif
85
86 bool Modified = false;
87 for (auto &MBB : MF)
88 Modified |= expandMBB(MBB);
89
90#ifndef NDEBUG
91 const unsigned NewSize = getInstSizeInBytes(MF);
92 assert(OldSize >= NewSize);
93#endif
94 return Modified;
95}
96
97bool RISCVExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
98 bool Modified = false;
99
100 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
101 while (MBBI != E) {
102 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
103 Modified |= expandMI(MBB, MBBI, NMBBI);
104 MBBI = NMBBI;
105 }
106
107 return Modified;
108}
109
110bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
111 MachineBasicBlock::iterator MBBI,
112 MachineBasicBlock::iterator &NextMBBI) {
113 // RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
114 // expanded instructions for each pseudo is correct in the Size field of the
115 // tablegen definition for the pseudo.
116 switch (MBBI->getOpcode()) {
117 case RISCV::PseudoMV_FPR16INX:
118 return expandMV_FPR16INX(MBB, MBBI);
119 case RISCV::PseudoMV_FPR32INX:
120 return expandMV_FPR32INX(MBB, MBBI);
121 case RISCV::PseudoRV32ZdinxSD:
122 return expandRV32ZdinxStore(MBB, MBBI);
123 case RISCV::PseudoRV32ZdinxLD:
124 return expandRV32ZdinxLoad(MBB, MBBI);
125 case RISCV::PseudoCCMOVGPRNoX0:
126 case RISCV::PseudoCCMOVGPR:
127 case RISCV::PseudoCCADD:
128 case RISCV::PseudoCCSUB:
129 case RISCV::PseudoCCAND:
130 case RISCV::PseudoCCOR:
131 case RISCV::PseudoCCXOR:
132 case RISCV::PseudoCCMAX:
133 case RISCV::PseudoCCMAXU:
134 case RISCV::PseudoCCMIN:
135 case RISCV::PseudoCCMINU:
136 case RISCV::PseudoCCMUL:
137 case RISCV::PseudoCCLUI:
138 case RISCV::PseudoCCQC_E_LB:
139 case RISCV::PseudoCCQC_E_LH:
140 case RISCV::PseudoCCQC_E_LW:
141 case RISCV::PseudoCCQC_E_LHU:
142 case RISCV::PseudoCCQC_E_LBU:
143 case RISCV::PseudoCCLB:
144 case RISCV::PseudoCCLH:
145 case RISCV::PseudoCCLW:
146 case RISCV::PseudoCCLHU:
147 case RISCV::PseudoCCLBU:
148 case RISCV::PseudoCCLWU:
149 case RISCV::PseudoCCLD:
150 case RISCV::PseudoCCQC_LI:
151 case RISCV::PseudoCCQC_E_LI:
152 case RISCV::PseudoCCADDW:
153 case RISCV::PseudoCCSUBW:
154 case RISCV::PseudoCCSLL:
155 case RISCV::PseudoCCSRL:
156 case RISCV::PseudoCCSRA:
157 case RISCV::PseudoCCADDI:
158 case RISCV::PseudoCCSLLI:
159 case RISCV::PseudoCCSRLI:
160 case RISCV::PseudoCCSRAI:
161 case RISCV::PseudoCCANDI:
162 case RISCV::PseudoCCORI:
163 case RISCV::PseudoCCXORI:
164 case RISCV::PseudoCCSLLW:
165 case RISCV::PseudoCCSRLW:
166 case RISCV::PseudoCCSRAW:
167 case RISCV::PseudoCCADDIW:
168 case RISCV::PseudoCCSLLIW:
169 case RISCV::PseudoCCSRLIW:
170 case RISCV::PseudoCCSRAIW:
171 case RISCV::PseudoCCANDN:
172 case RISCV::PseudoCCORN:
173 case RISCV::PseudoCCXNOR:
174 case RISCV::PseudoCCNDS_BFOS:
175 case RISCV::PseudoCCNDS_BFOZ:
176 return expandCCOp(MBB, MBBI, NextMBBI);
177 case RISCV::PseudoVMCLR_M_B1:
178 case RISCV::PseudoVMCLR_M_B2:
179 case RISCV::PseudoVMCLR_M_B4:
180 case RISCV::PseudoVMCLR_M_B8:
181 case RISCV::PseudoVMCLR_M_B16:
182 case RISCV::PseudoVMCLR_M_B32:
183 case RISCV::PseudoVMCLR_M_B64:
184 // vmclr.m vd => vmxor.mm vd, vd, vd
185 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXOR_MM);
186 case RISCV::PseudoVMSET_M_B1:
187 case RISCV::PseudoVMSET_M_B2:
188 case RISCV::PseudoVMSET_M_B4:
189 case RISCV::PseudoVMSET_M_B8:
190 case RISCV::PseudoVMSET_M_B16:
191 case RISCV::PseudoVMSET_M_B32:
192 case RISCV::PseudoVMSET_M_B64:
193 // vmset.m vd => vmxnor.mm vd, vd, vd
194 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM);
195 case RISCV::PseudoReadVLENBViaVSETVLIX0:
196 return expandPseudoReadVLENBViaVSETVLIX0(MBB, MBBI);
197 case RISCV::PseudoClearFPR64:
198 return expandPseudoClearFPR64(MBB, MBBI);
199 }
200
201 return false;
202}
203
204bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
205 MachineBasicBlock::iterator MBBI,
206 MachineBasicBlock::iterator &NextMBBI) {
207 // First try expanding to a Conditional Move rather than a branch+mv
208 if (expandCCOpToCMov(MBB, MBBI))
209 return true;
210
211 MachineFunction *MF = MBB.getParent();
212 MachineInstr &MI = *MBBI;
213 DebugLoc DL = MI.getDebugLoc();
214
215 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
216 MachineBasicBlock *MergeBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
217
218 MF->insert(++MBB.getIterator(), TrueBB);
219 MF->insert(++TrueBB->getIterator(), MergeBB);
220
221 // We want to copy the "true" value only when the branch is executed.
222 // The SDNodeXform is responsible for the inversion.
223 unsigned BranchOpCode =
224 MI.getOperand(MI.getNumExplicitOperands() - 3).getImm();
225
226 // Insert branch instruction.
227 BuildMI(MBB, MBBI, DL, TII->get(BranchOpCode))
228 .add(MI.getOperand(MI.getNumExplicitOperands() - 2))
229 .add(MI.getOperand(MI.getNumExplicitOperands() - 1))
230 .addMBB(MergeBB);
231
232 Register DestReg = MI.getOperand(0).getReg();
233 assert(MI.getOperand(1).getReg() == DestReg);
234
235 if (MI.getOpcode() == RISCV::PseudoCCMOVGPR ||
236 MI.getOpcode() == RISCV::PseudoCCMOVGPRNoX0) {
237 // Add MV.
238 BuildMI(TrueBB, DL, TII->get(RISCV::ADDI), DestReg)
239 .add(MI.getOperand(2))
240 .addImm(0);
241 } else {
242 unsigned NewOpc;
243 // clang-format off
244 switch (MI.getOpcode()) {
245 default:
246 llvm_unreachable("Unexpected opcode!");
247 case RISCV::PseudoCCADD: NewOpc = RISCV::ADD; break;
248 case RISCV::PseudoCCSUB: NewOpc = RISCV::SUB; break;
249 case RISCV::PseudoCCSLL: NewOpc = RISCV::SLL; break;
250 case RISCV::PseudoCCSRL: NewOpc = RISCV::SRL; break;
251 case RISCV::PseudoCCSRA: NewOpc = RISCV::SRA; break;
252 case RISCV::PseudoCCAND: NewOpc = RISCV::AND; break;
253 case RISCV::PseudoCCOR: NewOpc = RISCV::OR; break;
254 case RISCV::PseudoCCXOR: NewOpc = RISCV::XOR; break;
255 case RISCV::PseudoCCMAX: NewOpc = RISCV::MAX; break;
256 case RISCV::PseudoCCMIN: NewOpc = RISCV::MIN; break;
257 case RISCV::PseudoCCMAXU: NewOpc = RISCV::MAXU; break;
258 case RISCV::PseudoCCMINU: NewOpc = RISCV::MINU; break;
259 case RISCV::PseudoCCMUL: NewOpc = RISCV::MUL; break;
260 case RISCV::PseudoCCLUI: NewOpc = RISCV::LUI; break;
261 case RISCV::PseudoCCQC_E_LB: NewOpc = RISCV::QC_E_LB; break;
262 case RISCV::PseudoCCQC_E_LH: NewOpc = RISCV::QC_E_LH; break;
263 case RISCV::PseudoCCQC_E_LW: NewOpc = RISCV::QC_E_LW; break;
264 case RISCV::PseudoCCQC_E_LHU: NewOpc = RISCV::QC_E_LHU; break;
265 case RISCV::PseudoCCQC_E_LBU: NewOpc = RISCV::QC_E_LBU; break;
266 case RISCV::PseudoCCLB: NewOpc = RISCV::LB; break;
267 case RISCV::PseudoCCLH: NewOpc = RISCV::LH; break;
268 case RISCV::PseudoCCLW: NewOpc = RISCV::LW; break;
269 case RISCV::PseudoCCLHU: NewOpc = RISCV::LHU; break;
270 case RISCV::PseudoCCLBU: NewOpc = RISCV::LBU; break;
271 case RISCV::PseudoCCLWU: NewOpc = RISCV::LWU; break;
272 case RISCV::PseudoCCLD: NewOpc = RISCV::LD; break;
273 case RISCV::PseudoCCQC_LI: NewOpc = RISCV::QC_LI; break;
274 case RISCV::PseudoCCQC_E_LI: NewOpc = RISCV::QC_E_LI; break;
275 case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break;
276 case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI; break;
277 case RISCV::PseudoCCSRLI: NewOpc = RISCV::SRLI; break;
278 case RISCV::PseudoCCSRAI: NewOpc = RISCV::SRAI; break;
279 case RISCV::PseudoCCANDI: NewOpc = RISCV::ANDI; break;
280 case RISCV::PseudoCCORI: NewOpc = RISCV::ORI; break;
281 case RISCV::PseudoCCXORI: NewOpc = RISCV::XORI; break;
282 case RISCV::PseudoCCADDW: NewOpc = RISCV::ADDW; break;
283 case RISCV::PseudoCCSUBW: NewOpc = RISCV::SUBW; break;
284 case RISCV::PseudoCCSLLW: NewOpc = RISCV::SLLW; break;
285 case RISCV::PseudoCCSRLW: NewOpc = RISCV::SRLW; break;
286 case RISCV::PseudoCCSRAW: NewOpc = RISCV::SRAW; break;
287 case RISCV::PseudoCCADDIW: NewOpc = RISCV::ADDIW; break;
288 case RISCV::PseudoCCSLLIW: NewOpc = RISCV::SLLIW; break;
289 case RISCV::PseudoCCSRLIW: NewOpc = RISCV::SRLIW; break;
290 case RISCV::PseudoCCSRAIW: NewOpc = RISCV::SRAIW; break;
291 case RISCV::PseudoCCANDN: NewOpc = RISCV::ANDN; break;
292 case RISCV::PseudoCCORN: NewOpc = RISCV::ORN; break;
293 case RISCV::PseudoCCXNOR: NewOpc = RISCV::XNOR; break;
294 case RISCV::PseudoCCNDS_BFOS: NewOpc = RISCV::NDS_BFOS; break;
295 case RISCV::PseudoCCNDS_BFOZ: NewOpc = RISCV::NDS_BFOZ; break;
296 }
297 // clang-format on
298
299 if (NewOpc == RISCV::NDS_BFOZ || NewOpc == RISCV::NDS_BFOS) {
300 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
301 .add(MI.getOperand(2))
302 .add(MI.getOperand(3))
303 .add(MI.getOperand(4));
304 } else if (NewOpc == RISCV::LUI || NewOpc == RISCV::QC_LI ||
305 NewOpc == RISCV::QC_E_LI) {
306 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg).add(MI.getOperand(2));
307 } else {
308 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
309 .add(MI.getOperand(2))
310 .add(MI.getOperand(3));
311 }
312 }
313
314 TrueBB->addSuccessor(MergeBB);
315
316 MergeBB->splice(MergeBB->end(), &MBB, MI, MBB.end());
317 MergeBB->transferSuccessors(&MBB);
318
319 MBB.addSuccessor(TrueBB);
320 MBB.addSuccessor(MergeBB);
321
322 NextMBBI = MBB.end();
323 MI.eraseFromParent();
324
325 // Make sure live-ins are correctly attached to this new basic block.
326 LivePhysRegs LiveRegs;
327 computeAndAddLiveIns(LiveRegs, *TrueBB);
328 computeAndAddLiveIns(LiveRegs, *MergeBB);
329
330 return true;
331}
332
333bool RISCVExpandPseudo::expandCCOpToCMov(MachineBasicBlock &MBB,
334 MachineBasicBlock::iterator MBBI) {
335 MachineInstr &MI = *MBBI;
336 DebugLoc DL = MI.getDebugLoc();
337
338 if (MI.getOpcode() != RISCV::PseudoCCMOVGPR &&
339 MI.getOpcode() != RISCV::PseudoCCMOVGPRNoX0)
340 return false;
341
342 if (!STI->hasVendorXqcicm())
343 return false;
344
345 MachineOperand &LHS = MI.getOperand(MI.getNumExplicitOperands() - 2);
346 MachineOperand &RHS = MI.getOperand(MI.getNumExplicitOperands() - 1);
347
348 // FIXME: Would be wonderful to support LHS=X0, but not very easy.
349 if (LHS.getReg() == RISCV::X0 || MI.getOperand(1).getReg() == RISCV::X0 ||
350 MI.getOperand(2).getReg() == RISCV::X0)
351 return false;
352
353 // Use branch opcode to select appropriate Xqcicm instruction
354 unsigned BCC = MI.getOperand(MI.getNumExplicitOperands() - 3).getImm();
355 std::optional<unsigned> CMovRegOpcode;
356 unsigned CMovImmOpcode;
357 switch (BCC) {
358 default:
359 return false; // Unhandled branch opcodes
360 case RISCV::BNE:
361 CMovRegOpcode = RISCV::QC_MVEQ;
362 CMovImmOpcode = RISCV::QC_MVEQI;
363 break;
364 case RISCV::BEQ:
365 CMovRegOpcode = RISCV::QC_MVNE;
366 CMovImmOpcode = RISCV::QC_MVNEI;
367 break;
368 case RISCV::BGE:
369 CMovRegOpcode = RISCV::QC_MVLT;
370 CMovImmOpcode = RISCV::QC_MVLTI;
371 break;
372 case RISCV::BLT:
373 CMovRegOpcode = RISCV::QC_MVGE;
374 CMovImmOpcode = RISCV::QC_MVGEI;
375 break;
376 case RISCV::BGEU:
377 CMovRegOpcode = RISCV::QC_MVLTU;
378 CMovImmOpcode = RISCV::QC_MVLTUI;
379 break;
380 case RISCV::BLTU:
381 CMovRegOpcode = RISCV::QC_MVGEU;
382 CMovImmOpcode = RISCV::QC_MVGEUI;
383 break;
384 case RISCV::QC_BEQI:
385 CMovImmOpcode = RISCV::QC_MVEQI;
386 break;
387 case RISCV::QC_BNEI:
388 CMovImmOpcode = RISCV::QC_MVNEI;
389 break;
390 case RISCV::QC_BLTI:
391 CMovImmOpcode = RISCV::QC_MVLTI;
392 break;
393 case RISCV::QC_BGEI:
394 CMovImmOpcode = RISCV::QC_MVGEI;
395 break;
396 case RISCV::QC_BLTUI:
397 CMovImmOpcode = RISCV::QC_MVLTUI;
398 break;
399 case RISCV::QC_BGEUI:
400 CMovImmOpcode = RISCV::QC_MVGEUI;
401 break;
402 }
403
404 if (RHS.isImm() && isInt<5>(RHS.getImm())) {
405 // $dst = PseudoCCMOVGPR $falsev(=$dst), $truev, $opcode, $lhs, $rhs_imm
406 // $dst = PseudoCCMOVGPRNoX0 $falsev(=$dst), $truev, $opcode, $lhs, $rhs_imm
407 // =>
408 // $dst = QC_MVccI $falsev (=$dst), $lhs, $rhs_imm, $truev
409 BuildMI(MBB, MBBI, DL, TII->get(CMovImmOpcode))
410 .addDef(MI.getOperand(0).getReg())
411 .addReg(MI.getOperand(1).getReg())
412 .addReg(LHS.getReg())
413 .add(RHS)
414 .addReg(MI.getOperand(2).getReg());
415
416 MI.eraseFromParent();
417 return true;
418 }
419
420 if (RHS.getReg() == RISCV::X0) {
421 // $dst = PseudoCCMOVGPR $falsev (=$dst), $truev, $opcode, $lhs, X0
422 // $dst = PseudoCCMOVGPRNoX0 $falsev (=$dst), $truev, $opcode, $lhs, X0
423 // =>
424 // $dst = QC_MVccI $falsev (=$dst), $lhs, 0, $truev
425 BuildMI(MBB, MBBI, DL, TII->get(CMovImmOpcode))
426 .addDef(MI.getOperand(0).getReg())
427 .addReg(MI.getOperand(1).getReg())
428 .addReg(LHS.getReg())
429 .addImm(0)
430 .addReg(MI.getOperand(2).getReg());
431
432 MI.eraseFromParent();
433 return true;
434 }
435
436 if (!CMovRegOpcode)
437 return false;
438
439 // $dst = PseudoCCMOVGPR $falsev (=$dst), $truev, $opcode, $lhs, $rhs
440 // $dst = PseudoCCMOVGPRNoX0 $falsev (=$dst), $truev, $opcode, $lhs, $rhs
441 // =>
442 // $dst = QC_MVcc $falsev (=$dst), $lhs, $rhs, $truev
443 BuildMI(MBB, MBBI, DL, TII->get(*CMovRegOpcode))
444 .addDef(MI.getOperand(0).getReg())
445 .addReg(MI.getOperand(1).getReg())
446 .addReg(LHS.getReg())
447 .addReg(RHS.getReg())
448 .addReg(MI.getOperand(2).getReg());
449 MI.eraseFromParent();
450 return true;
451}
452
453bool RISCVExpandPseudo::expandVMSET_VMCLR(MachineBasicBlock &MBB,
454 MachineBasicBlock::iterator MBBI,
455 unsigned Opcode) {
456 DebugLoc DL = MBBI->getDebugLoc();
457 Register DstReg = MBBI->getOperand(0).getReg();
458 const MCInstrDesc &Desc = TII->get(Opcode);
459 BuildMI(MBB, MBBI, DL, Desc, DstReg)
460 .addReg(DstReg, RegState::Undef)
461 .addReg(DstReg, RegState::Undef);
462 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
463 return true;
464}
465
466bool RISCVExpandPseudo::expandMV_FPR16INX(MachineBasicBlock &MBB,
467 MachineBasicBlock::iterator MBBI) {
468 DebugLoc DL = MBBI->getDebugLoc();
469 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
470 Register DstReg = TRI->getMatchingSuperReg(
471 MBBI->getOperand(0).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
472 Register SrcReg = TRI->getMatchingSuperReg(
473 MBBI->getOperand(1).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
474
475 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
476 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
477 .addImm(0);
478
479 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
480 return true;
481}
482
483bool RISCVExpandPseudo::expandMV_FPR32INX(MachineBasicBlock &MBB,
484 MachineBasicBlock::iterator MBBI) {
485 DebugLoc DL = MBBI->getDebugLoc();
486 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
487 Register DstReg = TRI->getMatchingSuperReg(
488 MBBI->getOperand(0).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
489 Register SrcReg = TRI->getMatchingSuperReg(
490 MBBI->getOperand(1).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
491
492 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
493 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
494 .addImm(0);
495
496 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
497 return true;
498}
499
500// This function expands the PseudoRV32ZdinxSD for storing a double-precision
501// floating-point value into memory by generating an equivalent instruction
502// sequence for RV32.
503bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
504 MachineBasicBlock::iterator MBBI) {
505 DebugLoc DL = MBBI->getDebugLoc();
506 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
507 Register Lo =
508 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
509 Register Hi =
510 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
511 if (Hi == RISCV::DUMMY_REG_PAIR_WITH_X0)
512 Hi = RISCV::X0;
513
514 auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
515 .addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
516 .addReg(MBBI->getOperand(1).getReg())
517 .add(MBBI->getOperand(2));
518
519 MachineInstrBuilder MIBHi;
520 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
521 assert(MBBI->getOperand(2).getOffset() % 8 == 0);
522 MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
523 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
524 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
525 .add(MBBI->getOperand(1))
526 .add(MBBI->getOperand(2));
527 } else {
528 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
529 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
530 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
531 .add(MBBI->getOperand(1))
532 .addImm(MBBI->getOperand(2).getImm() + 4);
533 }
534
535 MachineFunction *MF = MBB.getParent();
536 SmallVector<MachineMemOperand *> NewLoMMOs;
537 SmallVector<MachineMemOperand *> NewHiMMOs;
538 for (const MachineMemOperand *MMO : MBBI->memoperands()) {
539 NewLoMMOs.push_back(MF->getMachineMemOperand(MMO, 0, 4));
540 NewHiMMOs.push_back(MF->getMachineMemOperand(MMO, 4, 4));
541 }
542 MIBLo.setMemRefs(NewLoMMOs);
543 MIBHi.setMemRefs(NewHiMMOs);
544
545 MBBI->eraseFromParent();
546 return true;
547}
548
549// This function expands PseudoRV32ZdinxLoad for loading a double-precision
550// floating-point value from memory into an equivalent instruction sequence for
551// RV32.
552bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
553 MachineBasicBlock::iterator MBBI) {
554 DebugLoc DL = MBBI->getDebugLoc();
555 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
556 Register Lo =
557 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
558 Register Hi =
559 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
560 assert(Hi != RISCV::DUMMY_REG_PAIR_WITH_X0 && "Cannot write to X0_Pair");
561
562 MachineInstrBuilder MIBLo, MIBHi;
563
564 // If the register of operand 1 is equal to the Lo register, then swap the
565 // order of loading the Lo and Hi statements.
566 bool IsOp1EqualToLo = Lo == MBBI->getOperand(1).getReg();
567 // Order: Lo, Hi
568 if (!IsOp1EqualToLo) {
569 MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
570 .addReg(MBBI->getOperand(1).getReg())
571 .add(MBBI->getOperand(2));
572 }
573
574 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
575 auto Offset = MBBI->getOperand(2).getOffset();
576 assert(Offset % 8 == 0);
577 MBBI->getOperand(2).setOffset(Offset + 4);
578 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
579 .addReg(MBBI->getOperand(1).getReg())
580 .add(MBBI->getOperand(2));
581 MBBI->getOperand(2).setOffset(Offset);
582 } else {
583 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
584 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
585 .addReg(MBBI->getOperand(1).getReg())
586 .addImm(MBBI->getOperand(2).getImm() + 4);
587 }
588
589 // Order: Hi, Lo
590 if (IsOp1EqualToLo) {
591 MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
592 .addReg(MBBI->getOperand(1).getReg())
593 .add(MBBI->getOperand(2));
594 }
595
596 MachineFunction *MF = MBB.getParent();
597 SmallVector<MachineMemOperand *> NewLoMMOs;
598 SmallVector<MachineMemOperand *> NewHiMMOs;
599 for (const MachineMemOperand *MMO : MBBI->memoperands()) {
600 NewLoMMOs.push_back(MF->getMachineMemOperand(MMO, 0, 4));
601 NewHiMMOs.push_back(MF->getMachineMemOperand(MMO, 4, 4));
602 }
603 MIBLo.setMemRefs(NewLoMMOs);
604 MIBHi.setMemRefs(NewHiMMOs);
605
606 MBBI->eraseFromParent();
607 return true;
608}
609
610bool RISCVExpandPseudo::expandPseudoReadVLENBViaVSETVLIX0(
611 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
612 DebugLoc DL = MBBI->getDebugLoc();
613 Register Dst = MBBI->getOperand(0).getReg();
614 unsigned Mul = MBBI->getOperand(1).getImm();
615 RISCVVType::VLMUL VLMUL = RISCVVType::encodeLMUL(Mul, /*Fractional=*/false);
616 unsigned VTypeImm = RISCVVType::encodeVTYPE(
617 VLMUL, /*SEW=*/8, /*TailAgnostic=*/true, /*MaskAgnostic=*/true);
618
619 BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoVSETVLIX0))
620 .addReg(Dst, RegState::Define)
621 .addReg(RISCV::X0, RegState::Kill)
622 .addImm(VTypeImm);
623
624 MBBI->eraseFromParent();
625 return true;
626}
627
628bool RISCVExpandPseudo::expandPseudoClearFPR64(
629 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
630 const DebugLoc &DL = MBBI->getDebugLoc();
631 Register Dst = MBBI->getOperand(0).getReg();
632
633 if (STI->is64Bit()) {
634 BuildMI(MBB, MBBI, DL, TII->get(RISCV::FMV_D_X), Dst).addReg(RISCV::X0);
635 } else {
636 BuildMI(MBB, MBBI, DL, TII->get(RISCV::FCVT_D_W), Dst)
637 .addReg(RISCV::X0)
638 .addImm(RISCVFPRndMode::RNE);
639 }
640
641 MBBI->eraseFromParent();
642 return true;
643}
644
645class RISCVPreRAExpandPseudo : public MachineFunctionPass {
646public:
647 const RISCVSubtarget *STI;
648 const RISCVInstrInfo *TII;
649 static char ID;
650
651 RISCVPreRAExpandPseudo() : MachineFunctionPass(ID) {}
652
653 bool runOnMachineFunction(MachineFunction &MF) override;
654
655 void getAnalysisUsage(AnalysisUsage &AU) const override {
656 AU.setPreservesCFG();
657 MachineFunctionPass::getAnalysisUsage(AU);
658 }
659 StringRef getPassName() const override {
660 return RISCV_PRERA_EXPAND_PSEUDO_NAME;
661 }
662
663private:
664 bool expandMBB(MachineBasicBlock &MBB);
665 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
666 MachineBasicBlock::iterator &NextMBBI);
667 bool expandAuipcInstPair(MachineBasicBlock &MBB,
668 MachineBasicBlock::iterator MBBI,
669 MachineBasicBlock::iterator &NextMBBI,
670 unsigned FlagsHi, unsigned SecondOpcode);
671 bool expandLoadLocalAddress(MachineBasicBlock &MBB,
672 MachineBasicBlock::iterator MBBI,
673 MachineBasicBlock::iterator &NextMBBI);
674 bool expandLoadGlobalAddress(MachineBasicBlock &MBB,
675 MachineBasicBlock::iterator MBBI,
676 MachineBasicBlock::iterator &NextMBBI);
677 bool expandLoadTLSIEAddress(MachineBasicBlock &MBB,
678 MachineBasicBlock::iterator MBBI,
679 MachineBasicBlock::iterator &NextMBBI);
680 bool expandLoadTLSGDAddress(MachineBasicBlock &MBB,
681 MachineBasicBlock::iterator MBBI,
682 MachineBasicBlock::iterator &NextMBBI);
683 bool expandLoadTLSDescAddress(MachineBasicBlock &MBB,
684 MachineBasicBlock::iterator MBBI,
685 MachineBasicBlock::iterator &NextMBBI);
686
687#ifndef NDEBUG
688 unsigned getInstSizeInBytes(const MachineFunction &MF) const {
689 unsigned Size = 0;
690 for (auto &MBB : MF)
691 for (auto &MI : MBB)
692 Size += TII->getInstSizeInBytes(MI);
693 return Size;
694 }
695#endif
696};
697
698char RISCVPreRAExpandPseudo::ID = 0;
699
700bool RISCVPreRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
701 STI = &MF.getSubtarget<RISCVSubtarget>();
702 TII = STI->getInstrInfo();
703
704#ifndef NDEBUG
705 const unsigned OldSize = getInstSizeInBytes(MF);
706#endif
707
708 bool Modified = false;
709 for (auto &MBB : MF)
710 Modified |= expandMBB(MBB);
711
712#ifndef NDEBUG
713 const unsigned NewSize = getInstSizeInBytes(MF);
714 assert(OldSize >= NewSize);
715#endif
716 return Modified;
717}
718
719bool RISCVPreRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
720 bool Modified = false;
721
722 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
723 while (MBBI != E) {
724 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
725 Modified |= expandMI(MBB, MBBI, NMBBI);
726 MBBI = NMBBI;
727 }
728
729 return Modified;
730}
731
732bool RISCVPreRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
733 MachineBasicBlock::iterator MBBI,
734 MachineBasicBlock::iterator &NextMBBI) {
735
736 switch (MBBI->getOpcode()) {
737 case RISCV::PseudoLLA:
738 return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
739 case RISCV::PseudoLGA:
740 return expandLoadGlobalAddress(MBB, MBBI, NextMBBI);
741 case RISCV::PseudoLA_TLS_IE:
742 return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
743 case RISCV::PseudoLA_TLS_GD:
744 return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);
745 case RISCV::PseudoLA_TLSDESC:
746 return expandLoadTLSDescAddress(MBB, MBBI, NextMBBI);
747 }
748 return false;
749}
750
751bool RISCVPreRAExpandPseudo::expandAuipcInstPair(
752 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
753 MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
754 unsigned SecondOpcode) {
755 MachineFunction *MF = MBB.getParent();
756 MachineInstr &MI = *MBBI;
757 DebugLoc DL = MI.getDebugLoc();
758
759 Register DestReg = MI.getOperand(0).getReg();
760 Register ScratchReg =
761 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
762
763 MachineOperand &Symbol = MI.getOperand(1);
764 Symbol.setTargetFlags(FlagsHi);
765 MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("pcrel_hi");
766
767 MachineInstr *MIAUIPC =
768 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
769 MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
770
771 MachineInstr *SecondMI =
772 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
773 .addReg(ScratchReg)
774 .addSym(AUIPCSymbol, RISCVII::MO_PCREL_LO);
775
776 if (MI.hasOneMemOperand())
777 SecondMI->addMemOperand(*MF, *MI.memoperands_begin());
778
779 MI.eraseFromParent();
780 return true;
781}
782
783bool RISCVPreRAExpandPseudo::expandLoadLocalAddress(
784 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
785 MachineBasicBlock::iterator &NextMBBI) {
786 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
787 RISCV::ADDI);
788}
789
790bool RISCVPreRAExpandPseudo::expandLoadGlobalAddress(
791 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
792 MachineBasicBlock::iterator &NextMBBI) {
793 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
794 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_GOT_HI,
795 SecondOpcode);
796}
797
798bool RISCVPreRAExpandPseudo::expandLoadTLSIEAddress(
799 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
800 MachineBasicBlock::iterator &NextMBBI) {
801 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
802 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
803 SecondOpcode);
804}
805
806bool RISCVPreRAExpandPseudo::expandLoadTLSGDAddress(
807 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
808 MachineBasicBlock::iterator &NextMBBI) {
809 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
810 RISCV::ADDI);
811}
812
813bool RISCVPreRAExpandPseudo::expandLoadTLSDescAddress(
814 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
815 MachineBasicBlock::iterator &NextMBBI) {
816 MachineFunction *MF = MBB.getParent();
817 MachineInstr &MI = *MBBI;
818 DebugLoc DL = MI.getDebugLoc();
819
820 const auto &STI = MF->getSubtarget<RISCVSubtarget>();
821 unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
822
823 Register FinalReg = MI.getOperand(0).getReg();
824 Register DestReg =
825 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
826 Register ScratchReg =
827 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
828
829 MachineOperand &Symbol = MI.getOperand(1);
830 Symbol.setTargetFlags(RISCVII::MO_TLSDESC_HI);
831 MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("tlsdesc_hi");
832
833 MachineInstr *MIAUIPC =
834 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
835 MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
836
837 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
838 .addReg(ScratchReg)
839 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_LOAD_LO);
840
841 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), RISCV::X10)
842 .addReg(ScratchReg)
843 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_ADD_LO);
844
845 BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoTLSDESCCall), RISCV::X5)
846 .addReg(DestReg)
847 .addImm(0)
848 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_CALL);
849
850 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), FinalReg)
851 .addReg(RISCV::X10)
852 .addReg(RISCV::X4);
853
854 MI.eraseFromParent();
855 return true;
856}
857
858} // end of anonymous namespace
859
860INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo",
861 RISCV_EXPAND_PSEUDO_NAME, false, false)
862
863INITIALIZE_PASS(RISCVPreRAExpandPseudo, "riscv-prera-expand-pseudo",
864 RISCV_PRERA_EXPAND_PSEUDO_NAME, false, false)
865
866namespace llvm {
867
868FunctionPass *createRISCVExpandPseudoPass() { return new RISCVExpandPseudo(); }
869FunctionPass *createRISCVPreRAExpandPseudoPass() { return new RISCVPreRAExpandPseudo(); }
870
871} // end of namespace llvm
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MBB
MachineBasicBlock & MBB
Definition ARMSLSHardening.cpp:71
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition ARMSLSHardening.cpp:73
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition ARMSLSHardening.cpp:72
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
TII
const HexagonInstrInfo * TII
Definition HexagonCopyToCombine.cpp:118
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:110
LivePhysRegs.h
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
TRI
Register const TargetRegisterInfo * TRI
Definition MachineSink.cpp:2127
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition PassSupport.h:56
RISCV_PRERA_EXPAND_PSEUDO_NAME
#define RISCV_PRERA_EXPAND_PSEUDO_NAME
Definition RISCVExpandPseudoInsts.cpp:27
RISCV_EXPAND_PSEUDO_NAME
#define RISCV_EXPAND_PSEUDO_NAME
Definition RISCVExpandPseudoInsts.cpp:26
getInstSizeInBytes
static unsigned getInstSizeInBytes(const MachineInstr &MI, const SystemZInstrInfo *TII)
Definition SystemZLongBranch.cpp:211
RHS
Value * RHS
Definition X86PartialReduction.cpp:81
LHS
Value * LHS
Definition X86PartialReduction.cpp:80
Mul
BinaryOperator * Mul
Definition X86PartialReduction.cpp:75
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition PassAnalysisSupport.h:48
llvm::AnalysisUsage::setPreservesCFG
LLVM_ABI void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition Pass.cpp:275
llvm::DebugLoc
A debug info location.
Definition DebugLoc.h:126
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition Pass.h:314
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition LivePhysRegs.h:52
llvm::MCContext::createNamedTempSymbol
LLVM_ABI MCSymbol * createNamedTempSymbol()
Create a temporary symbol with a unique name whose name cannot be omitted in the symbol table.
Definition MCContext.cpp:400
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition MCInstrDesc.h:199
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition MCSymbol.h:42
llvm::MachineBasicBlock::transferSuccessors
LLVM_ABI void transferSuccessors(MachineBasicBlock *FromMBB)
Transfers all the successors from MBB to this machine basic block (i.e., copies all the successors Fr...
Definition MachineBasicBlock.cpp:947
llvm::MachineBasicBlock::addSuccessor
LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition MachineBasicBlock.cpp:825
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition MachineBasicBlock.h:1157
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition MachineBasicBlock.h:342
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition MachineFunctionPass.h:31
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition MachineFunctionPass.cpp:135
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition MachineFunction.h:788
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition MachineFunction.cpp:581
llvm::MachineFunction::getContext
MCContext & getContext() const
Definition MachineFunction.h:735
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition MachineFunction.h:798
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineInstr - Allocate a new MachineInstr.
Definition MachineFunction.cpp:544
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition MachineFunction.h:1026
llvm::MachineInstrBuilder::setMemRefs
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
Definition MachineInstrBuilder.h:310
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, RegState Flags={}, unsigned SubReg=0) const
Add a new virtual register operand.
Definition MachineInstrBuilder.h:199
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition MachineInstrBuilder.h:233
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition MachineInstrBuilder.h:326
llvm::MachineInstrBuilder::addSym
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
Definition MachineInstrBuilder.h:373
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition MachineInstrBuilder.h:248
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, RegState Flags={}, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition MachineInstrBuilder.h:218
llvm::MachineInstr
Representation of each machine instruction.
Definition MachineInstr.h:73
llvm::MachineInstr::setPreInstrSymbol
LLVM_ABI void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
Definition MachineInstr.cpp:476
llvm::MachineInstr::addMemOperand
LLVM_ABI void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition MachineInstr.cpp:381
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition MachineMemOperand.h:130
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition MachineOperand.h:49
llvm::MachineRegisterInfo::createVirtualRegister
LLVM_ABI Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition MachineRegisterInfo.cpp:154
llvm::RISCVSubtarget::getRegisterInfo
const RISCVRegisterInfo * getRegisterInfo() const override
Definition RISCVSubtarget.h:148
llvm::RISCVSubtarget::getInstrInfo
const RISCVInstrInfo * getInstrInfo() const override
Definition RISCVSubtarget.h:147
llvm::Register
Wrapper class representing virtual and physical registers.
Definition Register.h:20
llvm::SmallVectorTemplateBase::push_back
void push_back(const T &Elt)
Definition SmallVector.h:423
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition SmallVector.h:1236
llvm::StringRef
Represent a constant reference to a string, i.e.
Definition StringRef.h:56
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition TargetRegisterInfo.h:244
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition ilist_node.h:123
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
INITIALIZE_PASS
TargetPassConfig.
Definition TargetPassConfig.cpp:394
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition CallingConv.h:24
llvm::RISCVVType::encodeLMUL
static VLMUL encodeLMUL(unsigned LMUL, bool Fractional)
Definition RISCVTargetParser.h:186
llvm::RISCVVType::encodeVTYPE
LLVM_ABI unsigned encodeVTYPE(VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic, bool AltFmt=false)
Definition RISCVTargetParser.cpp:366
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition FunctionInfo.h:25
llvm::Offset
@ Offset
Definition DWP.cpp:558
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition MachineInstrBuilder.h:449
llvm::isInt
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
Definition MathExtras.h:165
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition MachineInstrBuilder.h:61
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition MachineInstrBuilder.h:65
llvm::RegState::Define
@ Define
Register definition.
Definition MachineInstrBuilder.h:57
llvm::getKillRegState
constexpr RegState getKillRegState(bool B)
Definition MachineInstrBuilder.h:90
llvm::Desc
Op::Description Desc
Definition DWARFExpressionPrinter.cpp:26
llvm::computeAndAddLiveIns
LLVM_ABI void computeAndAddLiveIns(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB)
Convenience function combining computeLiveIns() and addLiveIns().
Definition LivePhysRegs.cpp:345
llvm::createRISCVExpandPseudoPass
FunctionPass * createRISCVExpandPseudoPass()
Definition RISCVExpandPseudoInsts.cpp:868
llvm::createRISCVPreRAExpandPseudoPass
FunctionPass * createRISCVPreRAExpandPseudoPass()
Definition RISCVExpandPseudoInsts.cpp:869
Generated on for LLVM by doxygen 1.14.0