LLVM 20.0.0git
RISCVExpandPseudoInsts.cpp
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1//===-- RISCVExpandPseudoInsts.cpp - Expand pseudo instructions -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a pass that expands pseudo instructions into target
10// instructions. This pass should be run after register allocation but before
11// the post-regalloc scheduling pass.
12//
13//===----------------------------------------------------------------------===//
14
15#include "RISCV.h"
16#include "RISCVInstrInfo.h"
17#include "RISCVTargetMachine.h"
18
19#include "llvm/CodeGen/LivePhysRegs.h"
20#include "llvm/CodeGen/MachineFunctionPass.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/MC/MCContext.h"
23
24using namespace llvm;
25
26#define RISCV_EXPAND_PSEUDO_NAME "RISC-V pseudo instruction expansion pass"
27#define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISC-V Pre-RA pseudo instruction expansion pass"
28
29namespace {
30
31class RISCVExpandPseudo : public MachineFunctionPass {
32public:
33 const RISCVSubtarget *STI;
34 const RISCVInstrInfo *TII;
35 static char ID;
36
37 RISCVExpandPseudo() : MachineFunctionPass(ID) {}
38
39 bool runOnMachineFunction(MachineFunction &MF) override;
40
41 StringRef getPassName() const override { return RISCV_EXPAND_PSEUDO_NAME; }
42
43private:
44 bool expandMBB(MachineBasicBlock &MBB);
45 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
46 MachineBasicBlock::iterator &NextMBBI);
47 bool expandCCOp(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
48 MachineBasicBlock::iterator &NextMBBI);
49 bool expandVMSET_VMCLR(MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator MBBI, unsigned Opcode);
51 bool expandRV32ZdinxStore(MachineBasicBlock &MBB,
52 MachineBasicBlock::iterator MBBI);
53 bool expandRV32ZdinxLoad(MachineBasicBlock &MBB,
54 MachineBasicBlock::iterator MBBI);
55#ifndef NDEBUG
56 unsigned getInstSizeInBytes(const MachineFunction &MF) const {
57 unsigned Size = 0;
58 for (auto &MBB : MF)
59 for (auto &MI : MBB)
60 Size += TII->getInstSizeInBytes(MI);
61 return Size;
62 }
63#endif
64};
65
66char RISCVExpandPseudo::ID = 0;
67
68bool RISCVExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
69 STI = &MF.getSubtarget<RISCVSubtarget>();
70 TII = STI->getInstrInfo();
71
72#ifndef NDEBUG
73 const unsigned OldSize = getInstSizeInBytes(MF);
74#endif
75
76 bool Modified = false;
77 for (auto &MBB : MF)
78 Modified |= expandMBB(MBB);
79
80#ifndef NDEBUG
81 const unsigned NewSize = getInstSizeInBytes(MF);
82 assert(OldSize >= NewSize);
83#endif
84 return Modified;
85}
86
87bool RISCVExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
88 bool Modified = false;
89
90 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
91 while (MBBI != E) {
92 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
93 Modified |= expandMI(MBB, MBBI, NMBBI);
94 MBBI = NMBBI;
95 }
96
97 return Modified;
98}
99
100bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
101 MachineBasicBlock::iterator MBBI,
102 MachineBasicBlock::iterator &NextMBBI) {
103 // RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
104 // expanded instructions for each pseudo is correct in the Size field of the
105 // tablegen definition for the pseudo.
106 switch (MBBI->getOpcode()) {
107 case RISCV::PseudoRV32ZdinxSD:
108 return expandRV32ZdinxStore(MBB, MBBI);
109 case RISCV::PseudoRV32ZdinxLD:
110 return expandRV32ZdinxLoad(MBB, MBBI);
111 case RISCV::PseudoCCMOVGPRNoX0:
112 case RISCV::PseudoCCMOVGPR:
113 case RISCV::PseudoCCADD:
114 case RISCV::PseudoCCSUB:
115 case RISCV::PseudoCCAND:
116 case RISCV::PseudoCCOR:
117 case RISCV::PseudoCCXOR:
118 case RISCV::PseudoCCADDW:
119 case RISCV::PseudoCCSUBW:
120 case RISCV::PseudoCCSLL:
121 case RISCV::PseudoCCSRL:
122 case RISCV::PseudoCCSRA:
123 case RISCV::PseudoCCADDI:
124 case RISCV::PseudoCCSLLI:
125 case RISCV::PseudoCCSRLI:
126 case RISCV::PseudoCCSRAI:
127 case RISCV::PseudoCCANDI:
128 case RISCV::PseudoCCORI:
129 case RISCV::PseudoCCXORI:
130 case RISCV::PseudoCCSLLW:
131 case RISCV::PseudoCCSRLW:
132 case RISCV::PseudoCCSRAW:
133 case RISCV::PseudoCCADDIW:
134 case RISCV::PseudoCCSLLIW:
135 case RISCV::PseudoCCSRLIW:
136 case RISCV::PseudoCCSRAIW:
137 case RISCV::PseudoCCANDN:
138 case RISCV::PseudoCCORN:
139 case RISCV::PseudoCCXNOR:
140 return expandCCOp(MBB, MBBI, NextMBBI);
141 case RISCV::PseudoVMCLR_M_B1:
142 case RISCV::PseudoVMCLR_M_B2:
143 case RISCV::PseudoVMCLR_M_B4:
144 case RISCV::PseudoVMCLR_M_B8:
145 case RISCV::PseudoVMCLR_M_B16:
146 case RISCV::PseudoVMCLR_M_B32:
147 case RISCV::PseudoVMCLR_M_B64:
148 // vmclr.m vd => vmxor.mm vd, vd, vd
149 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXOR_MM);
150 case RISCV::PseudoVMSET_M_B1:
151 case RISCV::PseudoVMSET_M_B2:
152 case RISCV::PseudoVMSET_M_B4:
153 case RISCV::PseudoVMSET_M_B8:
154 case RISCV::PseudoVMSET_M_B16:
155 case RISCV::PseudoVMSET_M_B32:
156 case RISCV::PseudoVMSET_M_B64:
157 // vmset.m vd => vmxnor.mm vd, vd, vd
158 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM);
159 }
160
161 return false;
162}
163
164bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
165 MachineBasicBlock::iterator MBBI,
166 MachineBasicBlock::iterator &NextMBBI) {
167
168 MachineFunction *MF = MBB.getParent();
169 MachineInstr &MI = *MBBI;
170 DebugLoc DL = MI.getDebugLoc();
171
172 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
173 MachineBasicBlock *MergeBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
174
175 MF->insert(++MBB.getIterator(), TrueBB);
176 MF->insert(++TrueBB->getIterator(), MergeBB);
177
178 // We want to copy the "true" value when the condition is true which means
179 // we need to invert the branch condition to jump over TrueBB when the
180 // condition is false.
181 auto CC = static_cast<RISCVCC::CondCode>(MI.getOperand(3).getImm());
182 CC = RISCVCC::getOppositeBranchCondition(CC);
183
184 // Insert branch instruction.
185 BuildMI(MBB, MBBI, DL, TII->getBrCond(CC))
186 .addReg(MI.getOperand(1).getReg())
187 .addReg(MI.getOperand(2).getReg())
188 .addMBB(MergeBB);
189
190 Register DestReg = MI.getOperand(0).getReg();
191 assert(MI.getOperand(4).getReg() == DestReg);
192
193 if (MI.getOpcode() == RISCV::PseudoCCMOVGPR ||
194 MI.getOpcode() == RISCV::PseudoCCMOVGPRNoX0) {
195 // Add MV.
196 BuildMI(TrueBB, DL, TII->get(RISCV::ADDI), DestReg)
197 .add(MI.getOperand(5))
198 .addImm(0);
199 } else {
200 unsigned NewOpc;
201 switch (MI.getOpcode()) {
202 default:
203 llvm_unreachable("Unexpected opcode!");
204 case RISCV::PseudoCCADD: NewOpc = RISCV::ADD; break;
205 case RISCV::PseudoCCSUB: NewOpc = RISCV::SUB; break;
206 case RISCV::PseudoCCSLL: NewOpc = RISCV::SLL; break;
207 case RISCV::PseudoCCSRL: NewOpc = RISCV::SRL; break;
208 case RISCV::PseudoCCSRA: NewOpc = RISCV::SRA; break;
209 case RISCV::PseudoCCAND: NewOpc = RISCV::AND; break;
210 case RISCV::PseudoCCOR: NewOpc = RISCV::OR; break;
211 case RISCV::PseudoCCXOR: NewOpc = RISCV::XOR; break;
212 case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break;
213 case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI; break;
214 case RISCV::PseudoCCSRLI: NewOpc = RISCV::SRLI; break;
215 case RISCV::PseudoCCSRAI: NewOpc = RISCV::SRAI; break;
216 case RISCV::PseudoCCANDI: NewOpc = RISCV::ANDI; break;
217 case RISCV::PseudoCCORI: NewOpc = RISCV::ORI; break;
218 case RISCV::PseudoCCXORI: NewOpc = RISCV::XORI; break;
219 case RISCV::PseudoCCADDW: NewOpc = RISCV::ADDW; break;
220 case RISCV::PseudoCCSUBW: NewOpc = RISCV::SUBW; break;
221 case RISCV::PseudoCCSLLW: NewOpc = RISCV::SLLW; break;
222 case RISCV::PseudoCCSRLW: NewOpc = RISCV::SRLW; break;
223 case RISCV::PseudoCCSRAW: NewOpc = RISCV::SRAW; break;
224 case RISCV::PseudoCCADDIW: NewOpc = RISCV::ADDIW; break;
225 case RISCV::PseudoCCSLLIW: NewOpc = RISCV::SLLIW; break;
226 case RISCV::PseudoCCSRLIW: NewOpc = RISCV::SRLIW; break;
227 case RISCV::PseudoCCSRAIW: NewOpc = RISCV::SRAIW; break;
228 case RISCV::PseudoCCANDN: NewOpc = RISCV::ANDN; break;
229 case RISCV::PseudoCCORN: NewOpc = RISCV::ORN; break;
230 case RISCV::PseudoCCXNOR: NewOpc = RISCV::XNOR; break;
231 }
232 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
233 .add(MI.getOperand(5))
234 .add(MI.getOperand(6));
235 }
236
237 TrueBB->addSuccessor(MergeBB);
238
239 MergeBB->splice(MergeBB->end(), &MBB, MI, MBB.end());
240 MergeBB->transferSuccessors(&MBB);
241
242 MBB.addSuccessor(TrueBB);
243 MBB.addSuccessor(MergeBB);
244
245 NextMBBI = MBB.end();
246 MI.eraseFromParent();
247
248 // Make sure live-ins are correctly attached to this new basic block.
249 LivePhysRegs LiveRegs;
250 computeAndAddLiveIns(LiveRegs, *TrueBB);
251 computeAndAddLiveIns(LiveRegs, *MergeBB);
252
253 return true;
254}
255
256bool RISCVExpandPseudo::expandVMSET_VMCLR(MachineBasicBlock &MBB,
257 MachineBasicBlock::iterator MBBI,
258 unsigned Opcode) {
259 DebugLoc DL = MBBI->getDebugLoc();
260 Register DstReg = MBBI->getOperand(0).getReg();
261 const MCInstrDesc &Desc = TII->get(Opcode);
262 BuildMI(MBB, MBBI, DL, Desc, DstReg)
263 .addReg(DstReg, RegState::Undef)
264 .addReg(DstReg, RegState::Undef);
265 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
266 return true;
267}
268
269// This function expands the PseudoRV32ZdinxSD for storing a double-precision
270// floating-point value into memory by generating an equivalent instruction
271// sequence for RV32.
272bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
273 MachineBasicBlock::iterator MBBI) {
274 DebugLoc DL = MBBI->getDebugLoc();
275 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
276 Register Lo =
277 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
278 Register Hi =
279 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
280
281 assert(MBBI->hasOneMemOperand() && "Expected mem operand");
282 MachineMemOperand *OldMMO = MBBI->memoperands().front();
283 MachineFunction *MF = MBB.getParent();
284 MachineMemOperand *MMOLo = MF->getMachineMemOperand(OldMMO, 0, 4);
285 MachineMemOperand *MMOHi = MF->getMachineMemOperand(OldMMO, 4, 4);
286
287 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
288 .addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
289 .addReg(MBBI->getOperand(1).getReg())
290 .add(MBBI->getOperand(2))
291 .setMemRefs(MMOLo);
292
293 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
294 // FIXME: Zdinx RV32 can not work on unaligned scalar memory.
295 assert(!STI->enableUnalignedScalarMem());
296
297 assert(MBBI->getOperand(2).getOffset() % 8 == 0);
298 MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
299 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
300 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
301 .add(MBBI->getOperand(1))
302 .add(MBBI->getOperand(2))
303 .setMemRefs(MMOHi);
304 } else {
305 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
306 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
307 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
308 .add(MBBI->getOperand(1))
309 .addImm(MBBI->getOperand(2).getImm() + 4)
310 .setMemRefs(MMOHi);
311 }
312 MBBI->eraseFromParent();
313 return true;
314}
315
316// This function expands PseudoRV32ZdinxLoad for loading a double-precision
317// floating-point value from memory into an equivalent instruction sequence for
318// RV32.
319bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
320 MachineBasicBlock::iterator MBBI) {
321 DebugLoc DL = MBBI->getDebugLoc();
322 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
323 Register Lo =
324 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
325 Register Hi =
326 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
327
328 assert(MBBI->hasOneMemOperand() && "Expected mem operand");
329 MachineMemOperand *OldMMO = MBBI->memoperands().front();
330 MachineFunction *MF = MBB.getParent();
331 MachineMemOperand *MMOLo = MF->getMachineMemOperand(OldMMO, 0, 4);
332 MachineMemOperand *MMOHi = MF->getMachineMemOperand(OldMMO, 4, 4);
333
334 // If the register of operand 1 is equal to the Lo register, then swap the
335 // order of loading the Lo and Hi statements.
336 bool IsOp1EqualToLo = Lo == MBBI->getOperand(1).getReg();
337 // Order: Lo, Hi
338 if (!IsOp1EqualToLo) {
339 BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
340 .addReg(MBBI->getOperand(1).getReg())
341 .add(MBBI->getOperand(2))
342 .setMemRefs(MMOLo);
343 }
344
345 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
346 auto Offset = MBBI->getOperand(2).getOffset();
347 assert(MBBI->getOperand(2).getOffset() % 8 == 0);
348 MBBI->getOperand(2).setOffset(Offset + 4);
349 BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
350 .addReg(MBBI->getOperand(1).getReg())
351 .add(MBBI->getOperand(2))
352 .setMemRefs(MMOHi);
353 MBBI->getOperand(2).setOffset(Offset);
354 } else {
355 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
356 BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
357 .addReg(MBBI->getOperand(1).getReg())
358 .addImm(MBBI->getOperand(2).getImm() + 4)
359 .setMemRefs(MMOHi);
360 }
361
362 // Order: Hi, Lo
363 if (IsOp1EqualToLo) {
364 BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
365 .addReg(MBBI->getOperand(1).getReg())
366 .add(MBBI->getOperand(2))
367 .setMemRefs(MMOLo);
368 }
369
370 MBBI->eraseFromParent();
371 return true;
372}
373
374class RISCVPreRAExpandPseudo : public MachineFunctionPass {
375public:
376 const RISCVSubtarget *STI;
377 const RISCVInstrInfo *TII;
378 static char ID;
379
380 RISCVPreRAExpandPseudo() : MachineFunctionPass(ID) {}
381
382 bool runOnMachineFunction(MachineFunction &MF) override;
383
384 void getAnalysisUsage(AnalysisUsage &AU) const override {
385 AU.setPreservesCFG();
386 MachineFunctionPass::getAnalysisUsage(AU);
387 }
388 StringRef getPassName() const override {
389 return RISCV_PRERA_EXPAND_PSEUDO_NAME;
390 }
391
392private:
393 bool expandMBB(MachineBasicBlock &MBB);
394 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
395 MachineBasicBlock::iterator &NextMBBI);
396 bool expandAuipcInstPair(MachineBasicBlock &MBB,
397 MachineBasicBlock::iterator MBBI,
398 MachineBasicBlock::iterator &NextMBBI,
399 unsigned FlagsHi, unsigned SecondOpcode);
400 bool expandLoadLocalAddress(MachineBasicBlock &MBB,
401 MachineBasicBlock::iterator MBBI,
402 MachineBasicBlock::iterator &NextMBBI);
403 bool expandLoadGlobalAddress(MachineBasicBlock &MBB,
404 MachineBasicBlock::iterator MBBI,
405 MachineBasicBlock::iterator &NextMBBI);
406 bool expandLoadTLSIEAddress(MachineBasicBlock &MBB,
407 MachineBasicBlock::iterator MBBI,
408 MachineBasicBlock::iterator &NextMBBI);
409 bool expandLoadTLSGDAddress(MachineBasicBlock &MBB,
410 MachineBasicBlock::iterator MBBI,
411 MachineBasicBlock::iterator &NextMBBI);
412 bool expandLoadTLSDescAddress(MachineBasicBlock &MBB,
413 MachineBasicBlock::iterator MBBI,
414 MachineBasicBlock::iterator &NextMBBI);
415
416#ifndef NDEBUG
417 unsigned getInstSizeInBytes(const MachineFunction &MF) const {
418 unsigned Size = 0;
419 for (auto &MBB : MF)
420 for (auto &MI : MBB)
421 Size += TII->getInstSizeInBytes(MI);
422 return Size;
423 }
424#endif
425};
426
427char RISCVPreRAExpandPseudo::ID = 0;
428
429bool RISCVPreRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
430 STI = &MF.getSubtarget<RISCVSubtarget>();
431 TII = STI->getInstrInfo();
432
433#ifndef NDEBUG
434 const unsigned OldSize = getInstSizeInBytes(MF);
435#endif
436
437 bool Modified = false;
438 for (auto &MBB : MF)
439 Modified |= expandMBB(MBB);
440
441#ifndef NDEBUG
442 const unsigned NewSize = getInstSizeInBytes(MF);
443 assert(OldSize >= NewSize);
444#endif
445 return Modified;
446}
447
448bool RISCVPreRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
449 bool Modified = false;
450
451 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
452 while (MBBI != E) {
453 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
454 Modified |= expandMI(MBB, MBBI, NMBBI);
455 MBBI = NMBBI;
456 }
457
458 return Modified;
459}
460
461bool RISCVPreRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
462 MachineBasicBlock::iterator MBBI,
463 MachineBasicBlock::iterator &NextMBBI) {
464
465 switch (MBBI->getOpcode()) {
466 case RISCV::PseudoLLA:
467 return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
468 case RISCV::PseudoLGA:
469 return expandLoadGlobalAddress(MBB, MBBI, NextMBBI);
470 case RISCV::PseudoLA_TLS_IE:
471 return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
472 case RISCV::PseudoLA_TLS_GD:
473 return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);
474 case RISCV::PseudoLA_TLSDESC:
475 return expandLoadTLSDescAddress(MBB, MBBI, NextMBBI);
476 }
477 return false;
478}
479
480bool RISCVPreRAExpandPseudo::expandAuipcInstPair(
481 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
482 MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
483 unsigned SecondOpcode) {
484 MachineFunction *MF = MBB.getParent();
485 MachineInstr &MI = *MBBI;
486 DebugLoc DL = MI.getDebugLoc();
487
488 Register DestReg = MI.getOperand(0).getReg();
489 Register ScratchReg =
490 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
491
492 MachineOperand &Symbol = MI.getOperand(1);
493 Symbol.setTargetFlags(FlagsHi);
494 MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("pcrel_hi");
495
496 MachineInstr *MIAUIPC =
497 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
498 MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
499
500 MachineInstr *SecondMI =
501 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
502 .addReg(ScratchReg)
503 .addSym(AUIPCSymbol, RISCVII::MO_PCREL_LO);
504
505 if (MI.hasOneMemOperand())
506 SecondMI->addMemOperand(*MF, *MI.memoperands_begin());
507
508 MI.eraseFromParent();
509 return true;
510}
511
512bool RISCVPreRAExpandPseudo::expandLoadLocalAddress(
513 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
514 MachineBasicBlock::iterator &NextMBBI) {
515 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
516 RISCV::ADDI);
517}
518
519bool RISCVPreRAExpandPseudo::expandLoadGlobalAddress(
520 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
521 MachineBasicBlock::iterator &NextMBBI) {
522 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
523 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_GOT_HI,
524 SecondOpcode);
525}
526
527bool RISCVPreRAExpandPseudo::expandLoadTLSIEAddress(
528 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
529 MachineBasicBlock::iterator &NextMBBI) {
530 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
531 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
532 SecondOpcode);
533}
534
535bool RISCVPreRAExpandPseudo::expandLoadTLSGDAddress(
536 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
537 MachineBasicBlock::iterator &NextMBBI) {
538 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
539 RISCV::ADDI);
540}
541
542bool RISCVPreRAExpandPseudo::expandLoadTLSDescAddress(
543 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
544 MachineBasicBlock::iterator &NextMBBI) {
545 MachineFunction *MF = MBB.getParent();
546 MachineInstr &MI = *MBBI;
547 DebugLoc DL = MI.getDebugLoc();
548
549 const auto &STI = MF->getSubtarget<RISCVSubtarget>();
550 unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
551
552 Register FinalReg = MI.getOperand(0).getReg();
553 Register DestReg =
554 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
555 Register ScratchReg =
556 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
557
558 MachineOperand &Symbol = MI.getOperand(1);
559 Symbol.setTargetFlags(RISCVII::MO_TLSDESC_HI);
560 MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("tlsdesc_hi");
561
562 MachineInstr *MIAUIPC =
563 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
564 MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
565
566 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
567 .addReg(ScratchReg)
568 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_LOAD_LO);
569
570 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), RISCV::X10)
571 .addReg(ScratchReg)
572 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_ADD_LO);
573
574 BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoTLSDESCCall), RISCV::X5)
575 .addReg(DestReg)
576 .addImm(0)
577 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_CALL);
578
579 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), FinalReg)
580 .addReg(RISCV::X10)
581 .addReg(RISCV::X4);
582
583 MI.eraseFromParent();
584 return true;
585}
586
587} // end of anonymous namespace
588
589INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo",
590 RISCV_EXPAND_PSEUDO_NAME, false, false)
591
592INITIALIZE_PASS(RISCVPreRAExpandPseudo, "riscv-prera-expand-pseudo",
593 RISCV_PRERA_EXPAND_PSEUDO_NAME, false, false)
594
595namespace llvm {
596
597FunctionPass *createRISCVExpandPseudoPass() { return new RISCVExpandPseudo(); }
598FunctionPass *createRISCVPreRAExpandPseudoPass() { return new RISCVPreRAExpandPseudo(); }
599
600} // end of namespace llvm
MBB
MachineBasicBlock & MBB
Definition: ARMSLSHardening.cpp:71
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: ARMSLSHardening.cpp:73
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: ARMSLSHardening.cpp:72
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
expand
static Expected< BitVector > expand(StringRef S, StringRef Original)
Definition: GlobPattern.cpp:21
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:113
LivePhysRegs.h
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1928
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
RISCV_PRERA_EXPAND_PSEUDO_NAME
#define RISCV_PRERA_EXPAND_PSEUDO_NAME
Definition: RISCVExpandPseudoInsts.cpp:27
RISCV_EXPAND_PSEUDO_NAME
#define RISCV_EXPAND_PSEUDO_NAME
Definition: RISCVExpandPseudoInsts.cpp:26
pseudo
riscv prera expand pseudo
Definition: RISCVExpandPseudoInsts.cpp:592
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
getInstSizeInBytes
static unsigned getInstSizeInBytes(const MachineInstr &MI, const SystemZInstrInfo *TII)
Definition: SystemZLongBranch.cpp:214
Lo
support::ulittle16_t & Lo
Definition: aarch32.cpp:206
Hi
support::ulittle16_t & Hi
Definition: aarch32.cpp:205
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::AnalysisUsage::setPreservesCFG
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:256
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:310
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:52
llvm::MCContext::createNamedTempSymbol
MCSymbol * createNamedTempSymbol()
Create a temporary symbol with a unique name whose name cannot be omitted in the symbol table.
Definition: MCContext.cpp:348
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::MachineBasicBlock::transferSuccessors
void transferSuccessors(MachineBasicBlock *FromMBB)
Transfers all the successors from MBB to this machine basic block (i.e., copies all the successors Fr...
Definition: MachineBasicBlock.cpp:915
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:255
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:796
llvm::MachineBasicBlock::eraseFromParent
void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
Definition: MachineBasicBlock.cpp:1474
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:310
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:1101
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:169
llvm::MachineFunctionPass::runOnMachineFunction
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:718
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:502
llvm::MachineFunction::getContext
MCContext & getContext() const
Definition: MachineFunction.h:670
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:728
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:463
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:946
llvm::MachineInstrBuilder::setMemRefs
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
Definition: MachineInstrBuilder.h:210
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:133
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:226
llvm::MachineInstrBuilder::addSym
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
Definition: MachineInstrBuilder.h:269
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:99
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:148
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:69
llvm::MachineInstr::setPreInstrSymbol
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
Definition: MachineInstr.cpp:476
llvm::MachineInstr::addMemOperand
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition: MachineInstr.cpp:381
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:129
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:157
llvm::Pass::getPassName
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:238
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:132
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
INITIALIZE_PASS
TargetPassConfig.
Definition: TargetPassConfig.cpp:362
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::RISCVCC::getOppositeBranchCondition
CondCode getOppositeBranchCondition(CondCode)
Definition: RISCVInstrInfo.cpp:907
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:54
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::Offset
@ Offset
Definition: DWP.cpp:480
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:373
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:555
llvm::computeAndAddLiveIns
void computeAndAddLiveIns(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB)
Convenience function combining computeLiveIns() and addLiveIns().
Definition: LivePhysRegs.cpp:336
llvm::createRISCVExpandPseudoPass
FunctionPass * createRISCVExpandPseudoPass()
Definition: RISCVExpandPseudoInsts.cpp:597
llvm::createRISCVPreRAExpandPseudoPass
FunctionPass * createRISCVPreRAExpandPseudoPass()
Definition: RISCVExpandPseudoInsts.cpp:598
llvm::DWARFExpression::Operation::Description
Description of the encoding of one expression Op.
Definition: DWARFExpression.h:66
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