LLVM 22.0.0git
RISCVExpandPseudoInsts.cpp
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1//===-- RISCVExpandPseudoInsts.cpp - Expand pseudo instructions -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a pass that expands pseudo instructions into target
10// instructions. This pass should be run after register allocation but before
11// the post-regalloc scheduling pass.
12//
13//===----------------------------------------------------------------------===//
14
15#include "RISCV.h"
16#include "RISCVInstrInfo.h"
17#include "RISCVTargetMachine.h"
18
19#include "llvm/CodeGen/LivePhysRegs.h"
20#include "llvm/CodeGen/MachineFunctionPass.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/MC/MCContext.h"
23
24using namespace llvm;
25
26#define RISCV_EXPAND_PSEUDO_NAME "RISC-V pseudo instruction expansion pass"
27#define RISCV_PRERA_EXPAND_PSEUDO_NAME "RISC-V Pre-RA pseudo instruction expansion pass"
28
29namespace {
30
31class RISCVExpandPseudo : public MachineFunctionPass {
32public:
33 const RISCVSubtarget *STI;
34 const RISCVInstrInfo *TII;
35 static char ID;
36
37 RISCVExpandPseudo() : MachineFunctionPass(ID) {}
38
39 bool runOnMachineFunction(MachineFunction &MF) override;
40
41 StringRef getPassName() const override { return RISCV_EXPAND_PSEUDO_NAME; }
42
43private:
44 bool expandMBB(MachineBasicBlock &MBB);
45 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
46 MachineBasicBlock::iterator &NextMBBI);
47 bool expandCCOp(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
48 MachineBasicBlock::iterator &NextMBBI);
49 bool expandVMSET_VMCLR(MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator MBBI, unsigned Opcode);
51 bool expandMV_FPR16INX(MachineBasicBlock &MBB,
52 MachineBasicBlock::iterator MBBI);
53 bool expandMV_FPR32INX(MachineBasicBlock &MBB,
54 MachineBasicBlock::iterator MBBI);
55 bool expandRV32ZdinxStore(MachineBasicBlock &MBB,
56 MachineBasicBlock::iterator MBBI);
57 bool expandRV32ZdinxLoad(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator MBBI);
59 bool expandPseudoReadVLENBViaVSETVLIX0(MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator MBBI);
61#ifndef NDEBUG
62 unsigned getInstSizeInBytes(const MachineFunction &MF) const {
63 unsigned Size = 0;
64 for (auto &MBB : MF)
65 for (auto &MI : MBB)
66 Size += TII->getInstSizeInBytes(MI);
67 return Size;
68 }
69#endif
70};
71
72char RISCVExpandPseudo::ID = 0;
73
74bool RISCVExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
75 STI = &MF.getSubtarget<RISCVSubtarget>();
76 TII = STI->getInstrInfo();
77
78#ifndef NDEBUG
79 const unsigned OldSize = getInstSizeInBytes(MF);
80#endif
81
82 bool Modified = false;
83 for (auto &MBB : MF)
84 Modified |= expandMBB(MBB);
85
86#ifndef NDEBUG
87 const unsigned NewSize = getInstSizeInBytes(MF);
88 assert(OldSize >= NewSize);
89#endif
90 return Modified;
91}
92
93bool RISCVExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
94 bool Modified = false;
95
96 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
97 while (MBBI != E) {
98 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
99 Modified |= expandMI(MBB, MBBI, NMBBI);
100 MBBI = NMBBI;
101 }
102
103 return Modified;
104}
105
106bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
107 MachineBasicBlock::iterator MBBI,
108 MachineBasicBlock::iterator &NextMBBI) {
109 // RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
110 // expanded instructions for each pseudo is correct in the Size field of the
111 // tablegen definition for the pseudo.
112 switch (MBBI->getOpcode()) {
113 case RISCV::PseudoMV_FPR16INX:
114 return expandMV_FPR16INX(MBB, MBBI);
115 case RISCV::PseudoMV_FPR32INX:
116 return expandMV_FPR32INX(MBB, MBBI);
117 case RISCV::PseudoRV32ZdinxSD:
118 return expandRV32ZdinxStore(MBB, MBBI);
119 case RISCV::PseudoRV32ZdinxLD:
120 return expandRV32ZdinxLoad(MBB, MBBI);
121 case RISCV::PseudoCCMOVGPRNoX0:
122 case RISCV::PseudoCCMOVGPR:
123 case RISCV::PseudoCCADD:
124 case RISCV::PseudoCCSUB:
125 case RISCV::PseudoCCAND:
126 case RISCV::PseudoCCOR:
127 case RISCV::PseudoCCXOR:
128 case RISCV::PseudoCCADDW:
129 case RISCV::PseudoCCSUBW:
130 case RISCV::PseudoCCSLL:
131 case RISCV::PseudoCCSRL:
132 case RISCV::PseudoCCSRA:
133 case RISCV::PseudoCCADDI:
134 case RISCV::PseudoCCSLLI:
135 case RISCV::PseudoCCSRLI:
136 case RISCV::PseudoCCSRAI:
137 case RISCV::PseudoCCANDI:
138 case RISCV::PseudoCCORI:
139 case RISCV::PseudoCCXORI:
140 case RISCV::PseudoCCSLLW:
141 case RISCV::PseudoCCSRLW:
142 case RISCV::PseudoCCSRAW:
143 case RISCV::PseudoCCADDIW:
144 case RISCV::PseudoCCSLLIW:
145 case RISCV::PseudoCCSRLIW:
146 case RISCV::PseudoCCSRAIW:
147 case RISCV::PseudoCCANDN:
148 case RISCV::PseudoCCORN:
149 case RISCV::PseudoCCXNOR:
150 case RISCV::PseudoCCNDS_BFOS:
151 case RISCV::PseudoCCNDS_BFOZ:
152 return expandCCOp(MBB, MBBI, NextMBBI);
153 case RISCV::PseudoVMCLR_M_B1:
154 case RISCV::PseudoVMCLR_M_B2:
155 case RISCV::PseudoVMCLR_M_B4:
156 case RISCV::PseudoVMCLR_M_B8:
157 case RISCV::PseudoVMCLR_M_B16:
158 case RISCV::PseudoVMCLR_M_B32:
159 case RISCV::PseudoVMCLR_M_B64:
160 // vmclr.m vd => vmxor.mm vd, vd, vd
161 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXOR_MM);
162 case RISCV::PseudoVMSET_M_B1:
163 case RISCV::PseudoVMSET_M_B2:
164 case RISCV::PseudoVMSET_M_B4:
165 case RISCV::PseudoVMSET_M_B8:
166 case RISCV::PseudoVMSET_M_B16:
167 case RISCV::PseudoVMSET_M_B32:
168 case RISCV::PseudoVMSET_M_B64:
169 // vmset.m vd => vmxnor.mm vd, vd, vd
170 return expandVMSET_VMCLR(MBB, MBBI, RISCV::VMXNOR_MM);
171 case RISCV::PseudoReadVLENBViaVSETVLIX0:
172 return expandPseudoReadVLENBViaVSETVLIX0(MBB, MBBI);
173 }
174
175 return false;
176}
177
178bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
179 MachineBasicBlock::iterator MBBI,
180 MachineBasicBlock::iterator &NextMBBI) {
181
182 MachineFunction *MF = MBB.getParent();
183 MachineInstr &MI = *MBBI;
184 DebugLoc DL = MI.getDebugLoc();
185
186 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
187 MachineBasicBlock *MergeBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
188
189 MF->insert(++MBB.getIterator(), TrueBB);
190 MF->insert(++TrueBB->getIterator(), MergeBB);
191
192 // We want to copy the "true" value when the condition is true which means
193 // we need to invert the branch condition to jump over TrueBB when the
194 // condition is false.
195 auto CC = static_cast<RISCVCC::CondCode>(MI.getOperand(3).getImm());
196 CC = RISCVCC::getOppositeBranchCondition(CC);
197
198 // Insert branch instruction.
199 BuildMI(MBB, MBBI, DL, TII->get(RISCVCC::getBrCond(CC)))
200 .addReg(MI.getOperand(1).getReg())
201 .addReg(MI.getOperand(2).getReg())
202 .addMBB(MergeBB);
203
204 Register DestReg = MI.getOperand(0).getReg();
205 assert(MI.getOperand(4).getReg() == DestReg);
206
207 if (MI.getOpcode() == RISCV::PseudoCCMOVGPR ||
208 MI.getOpcode() == RISCV::PseudoCCMOVGPRNoX0) {
209 // Add MV.
210 BuildMI(TrueBB, DL, TII->get(RISCV::ADDI), DestReg)
211 .add(MI.getOperand(5))
212 .addImm(0);
213 } else {
214 unsigned NewOpc;
215 switch (MI.getOpcode()) {
216 default:
217 llvm_unreachable("Unexpected opcode!");
218 case RISCV::PseudoCCADD: NewOpc = RISCV::ADD; break;
219 case RISCV::PseudoCCSUB: NewOpc = RISCV::SUB; break;
220 case RISCV::PseudoCCSLL: NewOpc = RISCV::SLL; break;
221 case RISCV::PseudoCCSRL: NewOpc = RISCV::SRL; break;
222 case RISCV::PseudoCCSRA: NewOpc = RISCV::SRA; break;
223 case RISCV::PseudoCCAND: NewOpc = RISCV::AND; break;
224 case RISCV::PseudoCCOR: NewOpc = RISCV::OR; break;
225 case RISCV::PseudoCCXOR: NewOpc = RISCV::XOR; break;
226 case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break;
227 case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI; break;
228 case RISCV::PseudoCCSRLI: NewOpc = RISCV::SRLI; break;
229 case RISCV::PseudoCCSRAI: NewOpc = RISCV::SRAI; break;
230 case RISCV::PseudoCCANDI: NewOpc = RISCV::ANDI; break;
231 case RISCV::PseudoCCORI: NewOpc = RISCV::ORI; break;
232 case RISCV::PseudoCCXORI: NewOpc = RISCV::XORI; break;
233 case RISCV::PseudoCCADDW: NewOpc = RISCV::ADDW; break;
234 case RISCV::PseudoCCSUBW: NewOpc = RISCV::SUBW; break;
235 case RISCV::PseudoCCSLLW: NewOpc = RISCV::SLLW; break;
236 case RISCV::PseudoCCSRLW: NewOpc = RISCV::SRLW; break;
237 case RISCV::PseudoCCSRAW: NewOpc = RISCV::SRAW; break;
238 case RISCV::PseudoCCADDIW: NewOpc = RISCV::ADDIW; break;
239 case RISCV::PseudoCCSLLIW: NewOpc = RISCV::SLLIW; break;
240 case RISCV::PseudoCCSRLIW: NewOpc = RISCV::SRLIW; break;
241 case RISCV::PseudoCCSRAIW: NewOpc = RISCV::SRAIW; break;
242 case RISCV::PseudoCCANDN: NewOpc = RISCV::ANDN; break;
243 case RISCV::PseudoCCORN: NewOpc = RISCV::ORN; break;
244 case RISCV::PseudoCCXNOR: NewOpc = RISCV::XNOR; break;
245 case RISCV::PseudoCCNDS_BFOS: NewOpc = RISCV::NDS_BFOS; break;
246 case RISCV::PseudoCCNDS_BFOZ: NewOpc = RISCV::NDS_BFOZ; break;
247 }
248
249 if (NewOpc == RISCV::NDS_BFOZ || NewOpc == RISCV::NDS_BFOS) {
250 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
251 .add(MI.getOperand(5))
252 .add(MI.getOperand(6))
253 .add(MI.getOperand(7));
254 } else {
255 BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
256 .add(MI.getOperand(5))
257 .add(MI.getOperand(6));
258 }
259 }
260
261 TrueBB->addSuccessor(MergeBB);
262
263 MergeBB->splice(MergeBB->end(), &MBB, MI, MBB.end());
264 MergeBB->transferSuccessors(&MBB);
265
266 MBB.addSuccessor(TrueBB);
267 MBB.addSuccessor(MergeBB);
268
269 NextMBBI = MBB.end();
270 MI.eraseFromParent();
271
272 // Make sure live-ins are correctly attached to this new basic block.
273 LivePhysRegs LiveRegs;
274 computeAndAddLiveIns(LiveRegs, *TrueBB);
275 computeAndAddLiveIns(LiveRegs, *MergeBB);
276
277 return true;
278}
279
280bool RISCVExpandPseudo::expandVMSET_VMCLR(MachineBasicBlock &MBB,
281 MachineBasicBlock::iterator MBBI,
282 unsigned Opcode) {
283 DebugLoc DL = MBBI->getDebugLoc();
284 Register DstReg = MBBI->getOperand(0).getReg();
285 const MCInstrDesc &Desc = TII->get(Opcode);
286 BuildMI(MBB, MBBI, DL, Desc, DstReg)
287 .addReg(DstReg, RegState::Undef)
288 .addReg(DstReg, RegState::Undef);
289 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
290 return true;
291}
292
293bool RISCVExpandPseudo::expandMV_FPR16INX(MachineBasicBlock &MBB,
294 MachineBasicBlock::iterator MBBI) {
295 DebugLoc DL = MBBI->getDebugLoc();
296 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
297 Register DstReg = TRI->getMatchingSuperReg(
298 MBBI->getOperand(0).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
299 Register SrcReg = TRI->getMatchingSuperReg(
300 MBBI->getOperand(1).getReg(), RISCV::sub_16, &RISCV::GPRRegClass);
301
302 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
303 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
304 .addImm(0);
305
306 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
307 return true;
308}
309
310bool RISCVExpandPseudo::expandMV_FPR32INX(MachineBasicBlock &MBB,
311 MachineBasicBlock::iterator MBBI) {
312 DebugLoc DL = MBBI->getDebugLoc();
313 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
314 Register DstReg = TRI->getMatchingSuperReg(
315 MBBI->getOperand(0).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
316 Register SrcReg = TRI->getMatchingSuperReg(
317 MBBI->getOperand(1).getReg(), RISCV::sub_32, &RISCV::GPRRegClass);
318
319 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg)
320 .addReg(SrcReg, getKillRegState(MBBI->getOperand(1).isKill()))
321 .addImm(0);
322
323 MBBI->eraseFromParent(); // The pseudo instruction is gone now.
324 return true;
325}
326
327// This function expands the PseudoRV32ZdinxSD for storing a double-precision
328// floating-point value into memory by generating an equivalent instruction
329// sequence for RV32.
330bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
331 MachineBasicBlock::iterator MBBI) {
332 DebugLoc DL = MBBI->getDebugLoc();
333 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
334 Register Lo =
335 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
336 Register Hi =
337 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
338 if (Hi == RISCV::DUMMY_REG_PAIR_WITH_X0)
339 Hi = RISCV::X0;
340
341 auto MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
342 .addReg(Lo, getKillRegState(MBBI->getOperand(0).isKill()))
343 .addReg(MBBI->getOperand(1).getReg())
344 .add(MBBI->getOperand(2));
345
346 MachineInstrBuilder MIBHi;
347 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
348 assert(MBBI->getOperand(2).getOffset() % 8 == 0);
349 MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
350 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
351 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
352 .add(MBBI->getOperand(1))
353 .add(MBBI->getOperand(2));
354 } else {
355 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
356 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
357 .addReg(Hi, getKillRegState(MBBI->getOperand(0).isKill()))
358 .add(MBBI->getOperand(1))
359 .addImm(MBBI->getOperand(2).getImm() + 4);
360 }
361
362 MachineFunction *MF = MBB.getParent();
363 SmallVector<MachineMemOperand *> NewLoMMOs;
364 SmallVector<MachineMemOperand *> NewHiMMOs;
365 for (const MachineMemOperand *MMO : MBBI->memoperands()) {
366 NewLoMMOs.push_back(MF->getMachineMemOperand(MMO, 0, 4));
367 NewHiMMOs.push_back(MF->getMachineMemOperand(MMO, 4, 4));
368 }
369 MIBLo.setMemRefs(NewLoMMOs);
370 MIBHi.setMemRefs(NewHiMMOs);
371
372 MBBI->eraseFromParent();
373 return true;
374}
375
376// This function expands PseudoRV32ZdinxLoad for loading a double-precision
377// floating-point value from memory into an equivalent instruction sequence for
378// RV32.
379bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
380 MachineBasicBlock::iterator MBBI) {
381 DebugLoc DL = MBBI->getDebugLoc();
382 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
383 Register Lo =
384 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_even);
385 Register Hi =
386 TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_gpr_odd);
387 assert(Hi != RISCV::DUMMY_REG_PAIR_WITH_X0 && "Cannot write to X0_Pair");
388
389 MachineInstrBuilder MIBLo, MIBHi;
390
391 // If the register of operand 1 is equal to the Lo register, then swap the
392 // order of loading the Lo and Hi statements.
393 bool IsOp1EqualToLo = Lo == MBBI->getOperand(1).getReg();
394 // Order: Lo, Hi
395 if (!IsOp1EqualToLo) {
396 MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
397 .addReg(MBBI->getOperand(1).getReg())
398 .add(MBBI->getOperand(2));
399 }
400
401 if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
402 auto Offset = MBBI->getOperand(2).getOffset();
403 assert(Offset % 8 == 0);
404 MBBI->getOperand(2).setOffset(Offset + 4);
405 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
406 .addReg(MBBI->getOperand(1).getReg())
407 .add(MBBI->getOperand(2));
408 MBBI->getOperand(2).setOffset(Offset);
409 } else {
410 assert(isInt<12>(MBBI->getOperand(2).getImm() + 4));
411 MIBHi = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Hi)
412 .addReg(MBBI->getOperand(1).getReg())
413 .addImm(MBBI->getOperand(2).getImm() + 4);
414 }
415
416 // Order: Hi, Lo
417 if (IsOp1EqualToLo) {
418 MIBLo = BuildMI(MBB, MBBI, DL, TII->get(RISCV::LW), Lo)
419 .addReg(MBBI->getOperand(1).getReg())
420 .add(MBBI->getOperand(2));
421 }
422
423 MachineFunction *MF = MBB.getParent();
424 SmallVector<MachineMemOperand *> NewLoMMOs;
425 SmallVector<MachineMemOperand *> NewHiMMOs;
426 for (const MachineMemOperand *MMO : MBBI->memoperands()) {
427 NewLoMMOs.push_back(MF->getMachineMemOperand(MMO, 0, 4));
428 NewHiMMOs.push_back(MF->getMachineMemOperand(MMO, 4, 4));
429 }
430 MIBLo.setMemRefs(NewLoMMOs);
431 MIBHi.setMemRefs(NewHiMMOs);
432
433 MBBI->eraseFromParent();
434 return true;
435}
436
437bool RISCVExpandPseudo::expandPseudoReadVLENBViaVSETVLIX0(
438 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
439 DebugLoc DL = MBBI->getDebugLoc();
440 Register Dst = MBBI->getOperand(0).getReg();
441 unsigned Mul = MBBI->getOperand(1).getImm();
442 RISCVVType::VLMUL VLMUL = RISCVVType::encodeLMUL(Mul, /*Fractional=*/false);
443 unsigned VTypeImm = RISCVVType::encodeVTYPE(
444 VLMUL, /*SEW=*/8, /*TailAgnostic=*/true, /*MaskAgnostic=*/true);
445
446 BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoVSETVLIX0))
447 .addReg(Dst, RegState::Define)
448 .addReg(RISCV::X0, RegState::Kill)
449 .addImm(VTypeImm);
450
451 MBBI->eraseFromParent();
452 return true;
453}
454
455class RISCVPreRAExpandPseudo : public MachineFunctionPass {
456public:
457 const RISCVSubtarget *STI;
458 const RISCVInstrInfo *TII;
459 static char ID;
460
461 RISCVPreRAExpandPseudo() : MachineFunctionPass(ID) {}
462
463 bool runOnMachineFunction(MachineFunction &MF) override;
464
465 void getAnalysisUsage(AnalysisUsage &AU) const override {
466 AU.setPreservesCFG();
467 MachineFunctionPass::getAnalysisUsage(AU);
468 }
469 StringRef getPassName() const override {
470 return RISCV_PRERA_EXPAND_PSEUDO_NAME;
471 }
472
473private:
474 bool expandMBB(MachineBasicBlock &MBB);
475 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
476 MachineBasicBlock::iterator &NextMBBI);
477 bool expandAuipcInstPair(MachineBasicBlock &MBB,
478 MachineBasicBlock::iterator MBBI,
479 MachineBasicBlock::iterator &NextMBBI,
480 unsigned FlagsHi, unsigned SecondOpcode);
481 bool expandLoadLocalAddress(MachineBasicBlock &MBB,
482 MachineBasicBlock::iterator MBBI,
483 MachineBasicBlock::iterator &NextMBBI);
484 bool expandLoadGlobalAddress(MachineBasicBlock &MBB,
485 MachineBasicBlock::iterator MBBI,
486 MachineBasicBlock::iterator &NextMBBI);
487 bool expandLoadTLSIEAddress(MachineBasicBlock &MBB,
488 MachineBasicBlock::iterator MBBI,
489 MachineBasicBlock::iterator &NextMBBI);
490 bool expandLoadTLSGDAddress(MachineBasicBlock &MBB,
491 MachineBasicBlock::iterator MBBI,
492 MachineBasicBlock::iterator &NextMBBI);
493 bool expandLoadTLSDescAddress(MachineBasicBlock &MBB,
494 MachineBasicBlock::iterator MBBI,
495 MachineBasicBlock::iterator &NextMBBI);
496
497#ifndef NDEBUG
498 unsigned getInstSizeInBytes(const MachineFunction &MF) const {
499 unsigned Size = 0;
500 for (auto &MBB : MF)
501 for (auto &MI : MBB)
502 Size += TII->getInstSizeInBytes(MI);
503 return Size;
504 }
505#endif
506};
507
508char RISCVPreRAExpandPseudo::ID = 0;
509
510bool RISCVPreRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
511 STI = &MF.getSubtarget<RISCVSubtarget>();
512 TII = STI->getInstrInfo();
513
514#ifndef NDEBUG
515 const unsigned OldSize = getInstSizeInBytes(MF);
516#endif
517
518 bool Modified = false;
519 for (auto &MBB : MF)
520 Modified |= expandMBB(MBB);
521
522#ifndef NDEBUG
523 const unsigned NewSize = getInstSizeInBytes(MF);
524 assert(OldSize >= NewSize);
525#endif
526 return Modified;
527}
528
529bool RISCVPreRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
530 bool Modified = false;
531
532 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
533 while (MBBI != E) {
534 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
535 Modified |= expandMI(MBB, MBBI, NMBBI);
536 MBBI = NMBBI;
537 }
538
539 return Modified;
540}
541
542bool RISCVPreRAExpandPseudo::expandMI(MachineBasicBlock &MBB,
543 MachineBasicBlock::iterator MBBI,
544 MachineBasicBlock::iterator &NextMBBI) {
545
546 switch (MBBI->getOpcode()) {
547 case RISCV::PseudoLLA:
548 return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
549 case RISCV::PseudoLGA:
550 return expandLoadGlobalAddress(MBB, MBBI, NextMBBI);
551 case RISCV::PseudoLA_TLS_IE:
552 return expandLoadTLSIEAddress(MBB, MBBI, NextMBBI);
553 case RISCV::PseudoLA_TLS_GD:
554 return expandLoadTLSGDAddress(MBB, MBBI, NextMBBI);
555 case RISCV::PseudoLA_TLSDESC:
556 return expandLoadTLSDescAddress(MBB, MBBI, NextMBBI);
557 }
558 return false;
559}
560
561bool RISCVPreRAExpandPseudo::expandAuipcInstPair(
562 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
563 MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
564 unsigned SecondOpcode) {
565 MachineFunction *MF = MBB.getParent();
566 MachineInstr &MI = *MBBI;
567 DebugLoc DL = MI.getDebugLoc();
568
569 Register DestReg = MI.getOperand(0).getReg();
570 Register ScratchReg =
571 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
572
573 MachineOperand &Symbol = MI.getOperand(1);
574 Symbol.setTargetFlags(FlagsHi);
575 MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("pcrel_hi");
576
577 MachineInstr *MIAUIPC =
578 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
579 MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
580
581 MachineInstr *SecondMI =
582 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
583 .addReg(ScratchReg)
584 .addSym(AUIPCSymbol, RISCVII::MO_PCREL_LO);
585
586 if (MI.hasOneMemOperand())
587 SecondMI->addMemOperand(*MF, *MI.memoperands_begin());
588
589 MI.eraseFromParent();
590 return true;
591}
592
593bool RISCVPreRAExpandPseudo::expandLoadLocalAddress(
594 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
595 MachineBasicBlock::iterator &NextMBBI) {
596 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_PCREL_HI,
597 RISCV::ADDI);
598}
599
600bool RISCVPreRAExpandPseudo::expandLoadGlobalAddress(
601 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
602 MachineBasicBlock::iterator &NextMBBI) {
603 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
604 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_GOT_HI,
605 SecondOpcode);
606}
607
608bool RISCVPreRAExpandPseudo::expandLoadTLSIEAddress(
609 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
610 MachineBasicBlock::iterator &NextMBBI) {
611 unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
612 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
613 SecondOpcode);
614}
615
616bool RISCVPreRAExpandPseudo::expandLoadTLSGDAddress(
617 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
618 MachineBasicBlock::iterator &NextMBBI) {
619 return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GD_HI,
620 RISCV::ADDI);
621}
622
623bool RISCVPreRAExpandPseudo::expandLoadTLSDescAddress(
624 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
625 MachineBasicBlock::iterator &NextMBBI) {
626 MachineFunction *MF = MBB.getParent();
627 MachineInstr &MI = *MBBI;
628 DebugLoc DL = MI.getDebugLoc();
629
630 const auto &STI = MF->getSubtarget<RISCVSubtarget>();
631 unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
632
633 Register FinalReg = MI.getOperand(0).getReg();
634 Register DestReg =
635 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
636 Register ScratchReg =
637 MF->getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
638
639 MachineOperand &Symbol = MI.getOperand(1);
640 Symbol.setTargetFlags(RISCVII::MO_TLSDESC_HI);
641 MCSymbol *AUIPCSymbol = MF->getContext().createNamedTempSymbol("tlsdesc_hi");
642
643 MachineInstr *MIAUIPC =
644 BuildMI(MBB, MBBI, DL, TII->get(RISCV::AUIPC), ScratchReg).add(Symbol);
645 MIAUIPC->setPreInstrSymbol(*MF, AUIPCSymbol);
646
647 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
648 .addReg(ScratchReg)
649 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_LOAD_LO);
650
651 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), RISCV::X10)
652 .addReg(ScratchReg)
653 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_ADD_LO);
654
655 BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoTLSDESCCall), RISCV::X5)
656 .addReg(DestReg)
657 .addImm(0)
658 .addSym(AUIPCSymbol, RISCVII::MO_TLSDESC_CALL);
659
660 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD), FinalReg)
661 .addReg(RISCV::X10)
662 .addReg(RISCV::X4);
663
664 MI.eraseFromParent();
665 return true;
666}
667
668} // end of anonymous namespace
669
670INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo",
671 RISCV_EXPAND_PSEUDO_NAME, false, false)
672
673INITIALIZE_PASS(RISCVPreRAExpandPseudo, "riscv-prera-expand-pseudo",
674 RISCV_PRERA_EXPAND_PSEUDO_NAME, false, false)
675
676namespace llvm {
677
678FunctionPass *createRISCVExpandPseudoPass() { return new RISCVExpandPseudo(); }
679FunctionPass *createRISCVPreRAExpandPseudoPass() { return new RISCVPreRAExpandPseudo(); }
680
681} // end of namespace llvm
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MBB
MachineBasicBlock & MBB
Definition: ARMSLSHardening.cpp:71
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: ARMSLSHardening.cpp:73
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: ARMSLSHardening.cpp:72
Size
uint64_t Size
Definition: ELFObjHandler.cpp:81
expand
static Expected< BitVector > expand(StringRef S, StringRef Original)
Definition: GlobPattern.cpp:21
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:118
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:110
LivePhysRegs.h
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
TRI
Register const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:2118
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:56
RISCV_PRERA_EXPAND_PSEUDO_NAME
#define RISCV_PRERA_EXPAND_PSEUDO_NAME
Definition: RISCVExpandPseudoInsts.cpp:27
RISCV_EXPAND_PSEUDO_NAME
#define RISCV_EXPAND_PSEUDO_NAME
Definition: RISCVExpandPseudoInsts.cpp:26
pseudo
riscv prera expand pseudo
Definition: RISCVExpandPseudoInsts.cpp:673
getInstSizeInBytes
static unsigned getInstSizeInBytes(const MachineInstr &MI, const SystemZInstrInfo *TII)
Definition: SystemZLongBranch.cpp:211
Mul
BinaryOperator * Mul
Definition: X86PartialReduction.cpp:68
Lo
support::ulittle16_t & Lo
Definition: aarch32.cpp:205
Hi
support::ulittle16_t & Hi
Definition: aarch32.cpp:204
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:48
llvm::AnalysisUsage::setPreservesCFG
LLVM_ABI void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:270
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:124
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:314
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:52
llvm::MCContext::createNamedTempSymbol
LLVM_ABI MCSymbol * createNamedTempSymbol()
Create a temporary symbol with a unique name whose name cannot be omitted in the symbol table.
Definition: MCContext.cpp:388
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:199
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:42
llvm::MachineBasicBlock::transferSuccessors
LLVM_ABI void transferSuccessors(MachineBasicBlock *FromMBB)
Transfers all the successors from MBB to this machine basic block (i.e., copies all the successors Fr...
Definition: MachineBasicBlock.cpp:915
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:253
llvm::MachineBasicBlock::addSuccessor
LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:796
llvm::MachineBasicBlock::eraseFromParent
LLVM_ABI void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
Definition: MachineBasicBlock.cpp:1483
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:323
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Definition: MachineBasicBlock.h:1149
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:31
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:184
llvm::MachineFunctionPass::runOnMachineFunction
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:762
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:536
llvm::MachineFunction::getContext
MCContext & getContext() const
Definition: MachineFunction.h:719
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:772
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:499
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:1003
llvm::MachineInstrBuilder::setMemRefs
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
Definition: MachineInstrBuilder.h:237
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:160
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:253
llvm::MachineInstrBuilder::addSym
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
Definition: MachineInstrBuilder.h:295
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:126
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:175
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:72
llvm::MachineInstr::setPreInstrSymbol
LLVM_ABI void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
Definition: MachineInstr.cpp:478
llvm::MachineInstr::addMemOperand
LLVM_ABI void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
Definition: MachineInstr.cpp:383
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:130
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MachineRegisterInfo::createVirtualRegister
LLVM_ABI Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::Pass::getPassName
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:85
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SmallVectorTemplateBase::push_back
void push_back(const T &Elt)
Definition: SmallVector.h:414
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1197
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:55
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:134
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:164
INITIALIZE_PASS
TargetPassConfig.
Definition: TargetPassConfig.cpp:369
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::RISCVCC::getOppositeBranchCondition
CondCode getOppositeBranchCondition(CondCode)
Definition: RISCVInstrInfo.cpp:1125
llvm::RISCVCC::getBrCond
unsigned getBrCond(CondCode CC, unsigned SelectOpc=0)
Definition: RISCVInstrInfo.cpp:1024
llvm::RISCVVType::encodeLMUL
static VLMUL encodeLMUL(unsigned LMUL, bool Fractional)
Definition: RISCVTargetParser.h:113
llvm::RISCVVType::encodeVTYPE
LLVM_ABI unsigned encodeVTYPE(VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic, bool AltFmt=false)
Definition: RISCVTargetParser.cpp:161
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:47
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:51
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:55
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::Offset
@ Offset
Definition: DWP.cpp:477
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:369
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:543
llvm::computeAndAddLiveIns
void computeAndAddLiveIns(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB)
Convenience function combining computeLiveIns() and addLiveIns().
Definition: LivePhysRegs.cpp:345
llvm::createRISCVExpandPseudoPass
FunctionPass * createRISCVExpandPseudoPass()
Definition: RISCVExpandPseudoInsts.cpp:678
llvm::createRISCVPreRAExpandPseudoPass
FunctionPass * createRISCVPreRAExpandPseudoPass()
Definition: RISCVExpandPseudoInsts.cpp:679
llvm::DWARFExpression::Operation::Description
Description of the encoding of one expression Op.
Definition: DWARFExpression.h:67
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