64#define FIXUPBW_DESC "X86 Byte/Word Instruction Fixup"
65#define FIXUPBW_NAME "x86-fixup-bw-insts"
67#define DEBUG_TYPE FIXUPBW_NAME
72 cl::desc(
"Change byte and word instructions to larger sizes"),
127 MachineFunctionProperties::Property::NoVRegs);
139 bool OptForSize =
false;
147char FixupBWInstPass::ID = 0;
161 PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
162 MBFI = (PSI && PSI->hasProfileSummary()) ?
163 &getAnalysis<LazyMachineBlockFrequencyInfoPass>().getBFI() :
165 LiveUnits.init(
TII->getRegisterInfo());
171 processBasicBlock(MF,
MBB);
189 const auto SubRegIdx =
TRI->getSubRegIndex(SuperDestReg, OrigDestReg);
195 if (SubRegIdx == X86::sub_8bit_hi)
201 bool SuperIsLive =
false;
202 auto Range =
TRI->regunits(OrigDestReg);
205 I = std::lower_bound(
I, E, S);
206 if ((
I == E || *
I > S) && LiveUnits.getBitVector().test(S)) {
248 if (Opc != X86::MOV8rm && Opc != X86::MOV16rm && Opc != X86::MOV8rr &&
252 bool IsDefined =
false;
257 if (MO.isDef() &&
TRI->isSuperRegisterEq(OrigDestReg, MO.getReg()))
264 if (MO.isUse() && !
TRI->isSubRegisterEq(OrigDestReg, MO.getReg()) &&
265 TRI->regsOverlap(SuperDestReg, MO.getReg()))
277MachineInstr *FixupBWInstPass::tryReplaceLoad(
unsigned New32BitOpcode,
283 Register NewDestReg = getSuperRegDestIfDead(
MI);
291 unsigned NumArgs =
MI->getNumOperands();
292 for (
unsigned i = 1; i < NumArgs; ++i)
293 MIB.
add(
MI->getOperand(i));
298 if (
unsigned OldInstrNum =
MI->peekDebugInstrNum()) {
300 MI->getOperand(0).getReg());
302 MF->makeDebugValueSubstitution({OldInstrNum, 0}, {NewInstrNum, 0}, Subreg);
309 assert(
MI->getNumExplicitOperands() == 2);
310 auto &OldDest =
MI->getOperand(0);
311 auto &OldSrc =
MI->getOperand(1);
313 Register NewDestReg = getSuperRegDestIfDead(
MI);
323 if (
TRI->getSubRegIndex(NewSrcReg, OldSrc.getReg()) !=
324 TRI->getSubRegIndex(NewDestReg, OldDest.getReg()))
338 for (
auto &
Op :
MI->implicit_operands())
339 if (
Op.getReg() != (
Op.isDef() ? NewDestReg : NewSrcReg))
345MachineInstr *FixupBWInstPass::tryReplaceExtend(
unsigned New32BitOpcode,
347 Register NewDestReg = getSuperRegDestIfDead(
MI);
354 if (
MI->getOpcode() == X86::MOVSX16rr8 &&
355 MI->getOperand(0).getReg() == X86::AX &&
356 MI->getOperand(1).getReg() == X86::AL)
363 unsigned NumArgs =
MI->getNumOperands();
364 for (
unsigned i = 1; i < NumArgs; ++i)
365 MIB.
add(
MI->getOperand(i));
369 if (
unsigned OldInstrNum =
MI->peekDebugInstrNum()) {
371 MI->getOperand(0).getReg());
373 MF->makeDebugValueSubstitution({OldInstrNum, 0}, {NewInstrNum, 0}, Subreg);
382 switch (
MI->getOpcode()) {
390 return tryReplaceLoad(X86::MOVZX32rm8,
MI);
398 return tryReplaceLoad(X86::MOVZX32rm16,
MI);
406 return tryReplaceCopy(
MI);
408 case X86::MOVSX16rr8:
409 return tryReplaceExtend(X86::MOVSX32rr8,
MI);
410 case X86::MOVSX16rm8:
411 return tryReplaceExtend(X86::MOVSX32rm8,
MI);
412 case X86::MOVZX16rr8:
413 return tryReplaceExtend(X86::MOVZX32rr8,
MI);
414 case X86::MOVZX16rm8:
415 return tryReplaceExtend(X86::MOVZX32rm8,
MI);
444 LiveUnits.addLiveOuts(
MBB);
450 MIReplacements.
push_back(std::make_pair(&
MI, NewMI));
453 LiveUnits.stepBackward(
MI);
456 while (!MIReplacements.
empty()) {
const HexagonInstrInfo * TII
===- LazyMachineBlockFrequencyInfo.h - Lazy Block Frequency -*- C++ -*–===//
unsigned const TargetRegisterInfo * TRI
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
static cl::opt< bool > FixupBWInsts("fixup-byte-word-insts", cl::desc("Change byte and word instructions to larger sizes"), cl::init(true), cl::Hidden)
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
This class represents an Operation in the Expression.
FunctionPass class - This class is used to implement most global optimizations.
This is an alternative analysis pass to MachineBlockFrequencyInfo.
A set of register units used to track register liveness.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
iterator_range< mop_iterator > implicit_operands()
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
const MachineOperand & getOperand(unsigned i) const
Register getReg() const
getReg - Returns the register number.
const TargetRegisterInfo * getTargetRegisterInfo() const
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
An analysis pass based on legacy pass manager to deliver ProfileSummaryInfo.
Analysis providing profile information.
Wrapper class representing virtual and physical registers.
constexpr bool isValid() const
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Undef
Value of the register doesn't matter.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MCRegister getX86SubSuperRegister(MCRegister Reg, unsigned Size, bool High=false)
FunctionPass * createX86FixupBWInsts()
Return a Machine IR pass that selectively replaces certain byte and word instructions by equivalent 3...
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
auto reverse(ContainerTy &&C)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.