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HexagonISelDAGToDAG.cpp
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00001 //===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file defines an instruction selector for the Hexagon target.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "Hexagon.h"
00015 #include "HexagonISelLowering.h"
00016 #include "HexagonMachineFunctionInfo.h"
00017 #include "HexagonTargetMachine.h"
00018 #include "llvm/ADT/DenseMap.h"
00019 #include "llvm/CodeGen/FunctionLoweringInfo.h"
00020 #include "llvm/CodeGen/MachineInstrBuilder.h"
00021 #include "llvm/CodeGen/SelectionDAGISel.h"
00022 #include "llvm/IR/Intrinsics.h"
00023 #include "llvm/Support/CommandLine.h"
00024 #include "llvm/Support/Compiler.h"
00025 #include "llvm/Support/Debug.h"
00026 using namespace llvm;
00027 
00028 #define DEBUG_TYPE "hexagon-isel"
00029 
00030 static
00031 cl::opt<unsigned>
00032 MaxNumOfUsesForConstExtenders("ga-max-num-uses-for-constant-extenders",
00033   cl::Hidden, cl::init(2),
00034   cl::desc("Maximum number of uses of a global address such that we still us a"
00035            "constant extended instruction"));
00036 
00037 //===----------------------------------------------------------------------===//
00038 // Instruction Selector Implementation
00039 //===----------------------------------------------------------------------===//
00040 
00041 namespace llvm {
00042   void initializeHexagonDAGToDAGISelPass(PassRegistry&);
00043 }
00044 
00045 //===--------------------------------------------------------------------===//
00046 /// HexagonDAGToDAGISel - Hexagon specific code to select Hexagon machine
00047 /// instructions for SelectionDAG operations.
00048 ///
00049 namespace {
00050 class HexagonDAGToDAGISel : public SelectionDAGISel {
00051   const HexagonTargetMachine& HTM;
00052   const HexagonSubtarget *HST;
00053   const HexagonInstrInfo *HII;
00054   const HexagonRegisterInfo *HRI;
00055 public:
00056   explicit HexagonDAGToDAGISel(HexagonTargetMachine &tm,
00057                                CodeGenOpt::Level OptLevel)
00058       : SelectionDAGISel(tm, OptLevel), HTM(tm), HST(nullptr), HII(nullptr),
00059         HRI(nullptr) {
00060     initializeHexagonDAGToDAGISelPass(*PassRegistry::getPassRegistry());
00061   }
00062 
00063   bool runOnMachineFunction(MachineFunction &MF) override {
00064     // Reset the subtarget each time through.
00065     HST = &MF.getSubtarget<HexagonSubtarget>();
00066     HII = HST->getInstrInfo();
00067     HRI = HST->getRegisterInfo();
00068     SelectionDAGISel::runOnMachineFunction(MF);
00069     return true;
00070   }
00071 
00072   virtual void PreprocessISelDAG() override;
00073   virtual void EmitFunctionEntryCode() override;
00074 
00075   SDNode *Select(SDNode *N) override;
00076 
00077   // Complex Pattern Selectors.
00078   inline bool SelectAddrGA(SDValue &N, SDValue &R);
00079   inline bool SelectAddrGP(SDValue &N, SDValue &R);
00080   bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP);
00081   bool SelectAddrFI(SDValue &N, SDValue &R);
00082 
00083   const char *getPassName() const override {
00084     return "Hexagon DAG->DAG Pattern Instruction Selection";
00085   }
00086 
00087   SDNode *SelectFrameIndex(SDNode *N);
00088   /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
00089   /// inline asm expressions.
00090   bool SelectInlineAsmMemoryOperand(const SDValue &Op,
00091                                     unsigned ConstraintID,
00092                                     std::vector<SDValue> &OutOps) override;
00093   SDNode *SelectLoad(SDNode *N);
00094   SDNode *SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl);
00095   SDNode *SelectIndexedLoad(LoadSDNode *LD, SDLoc dl);
00096   SDNode *SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
00097                                         SDLoc dl);
00098   SDNode *SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode,
00099                                         SDLoc dl);
00100   SDNode *SelectBaseOffsetStore(StoreSDNode *ST, SDLoc dl);
00101   SDNode *SelectIndexedStore(StoreSDNode *ST, SDLoc dl);
00102   SDNode *SelectStore(SDNode *N);
00103   SDNode *SelectSHL(SDNode *N);
00104   SDNode *SelectMul(SDNode *N);
00105   SDNode *SelectZeroExtend(SDNode *N);
00106   SDNode *SelectIntrinsicWChain(SDNode *N);
00107   SDNode *SelectIntrinsicWOChain(SDNode *N);
00108   SDNode *SelectConstant(SDNode *N);
00109   SDNode *SelectConstantFP(SDNode *N);
00110   SDNode *SelectAdd(SDNode *N);
00111   SDNode *SelectBitOp(SDNode *N);
00112 
00113   // XformMskToBitPosU5Imm - Returns the bit position which
00114   // the single bit 32 bit mask represents.
00115   // Used in Clr and Set bit immediate memops.
00116   SDValue XformMskToBitPosU5Imm(uint32_t Imm, SDLoc DL) {
00117     int32_t bitPos;
00118     bitPos = Log2_32(Imm);
00119     assert(bitPos >= 0 && bitPos < 32 &&
00120            "Constant out of range for 32 BitPos Memops");
00121     return CurDAG->getTargetConstant(bitPos, DL, MVT::i32);
00122   }
00123 
00124   // XformMskToBitPosU4Imm - Returns the bit position which the single-bit
00125   // 16 bit mask represents. Used in Clr and Set bit immediate memops.
00126   SDValue XformMskToBitPosU4Imm(uint16_t Imm, SDLoc DL) {
00127     return XformMskToBitPosU5Imm(Imm, DL);
00128   }
00129 
00130   // XformMskToBitPosU3Imm - Returns the bit position which the single-bit
00131   // 8 bit mask represents. Used in Clr and Set bit immediate memops.
00132   SDValue XformMskToBitPosU3Imm(uint8_t Imm, SDLoc DL) {
00133     return XformMskToBitPosU5Imm(Imm, DL);
00134   }
00135 
00136   // Return true if there is exactly one bit set in V, i.e., if V is one of the
00137   // following integers: 2^0, 2^1, ..., 2^31.
00138   bool ImmIsSingleBit(uint32_t v) const {
00139     return isPowerOf2_32(v);
00140   }
00141 
00142   // XformM5ToU5Imm - Return a target constant with the specified value, of
00143   // type i32 where the negative literal is transformed into a positive literal
00144   // for use in -= memops.
00145   inline SDValue XformM5ToU5Imm(signed Imm, SDLoc DL) {
00146      assert((Imm >= -31 && Imm <= -1)  && "Constant out of range for Memops");
00147      return CurDAG->getTargetConstant(-Imm, DL, MVT::i32);
00148   }
00149 
00150   // XformU7ToU7M1Imm - Return a target constant decremented by 1, in range
00151   // [1..128], used in cmpb.gtu instructions.
00152   inline SDValue XformU7ToU7M1Imm(signed Imm, SDLoc DL) {
00153     assert((Imm >= 1 && Imm <= 128) && "Constant out of range for cmpb op");
00154     return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i8);
00155   }
00156 
00157   // XformS8ToS8M1Imm - Return a target constant decremented by 1.
00158   inline SDValue XformSToSM1Imm(signed Imm, SDLoc DL) {
00159     return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i32);
00160   }
00161 
00162   // XformU8ToU8M1Imm - Return a target constant decremented by 1.
00163   inline SDValue XformUToUM1Imm(unsigned Imm, SDLoc DL) {
00164     assert((Imm >= 1) && "Cannot decrement unsigned int less than 1");
00165     return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i32);
00166   }
00167 
00168   // XformSToSM2Imm - Return a target constant decremented by 2.
00169   inline SDValue XformSToSM2Imm(unsigned Imm, SDLoc DL) {
00170     return CurDAG->getTargetConstant(Imm - 2, DL, MVT::i32);
00171   }
00172 
00173   // XformSToSM3Imm - Return a target constant decremented by 3.
00174   inline SDValue XformSToSM3Imm(unsigned Imm, SDLoc DL) {
00175     return CurDAG->getTargetConstant(Imm - 3, DL, MVT::i32);
00176   }
00177 
00178   // Include the pieces autogenerated from the target description.
00179   #include "HexagonGenDAGISel.inc"
00180 
00181 private:
00182   bool isValueExtension(const SDValue &Val, unsigned FromBits, SDValue &Src);
00183 }; // end HexagonDAGToDAGISel
00184 }  // end anonymous namespace
00185 
00186 
00187 /// createHexagonISelDag - This pass converts a legalized DAG into a
00188 /// Hexagon-specific DAG, ready for instruction scheduling.
00189 ///
00190 namespace llvm {
00191 FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
00192                                    CodeGenOpt::Level OptLevel) {
00193   return new HexagonDAGToDAGISel(TM, OptLevel);
00194 }
00195 }
00196 
00197 static void initializePassOnce(PassRegistry &Registry) {
00198   const char *Name = "Hexagon DAG->DAG Pattern Instruction Selection";
00199   PassInfo *PI = new PassInfo(Name, "hexagon-isel",
00200                               &SelectionDAGISel::ID, nullptr, false, false);
00201   Registry.registerPass(*PI, true);
00202 }
00203 
00204 void llvm::initializeHexagonDAGToDAGISelPass(PassRegistry &Registry) {
00205   CALL_ONCE_INITIALIZATION(initializePassOnce)
00206 }
00207 
00208 
00209 // Intrinsics that return a a predicate.
00210 static bool doesIntrinsicReturnPredicate(unsigned ID) {
00211   switch (ID) {
00212     default:
00213       return false;
00214     case Intrinsic::hexagon_C2_cmpeq:
00215     case Intrinsic::hexagon_C2_cmpgt:
00216     case Intrinsic::hexagon_C2_cmpgtu:
00217     case Intrinsic::hexagon_C2_cmpgtup:
00218     case Intrinsic::hexagon_C2_cmpgtp:
00219     case Intrinsic::hexagon_C2_cmpeqp:
00220     case Intrinsic::hexagon_C2_bitsset:
00221     case Intrinsic::hexagon_C2_bitsclr:
00222     case Intrinsic::hexagon_C2_cmpeqi:
00223     case Intrinsic::hexagon_C2_cmpgti:
00224     case Intrinsic::hexagon_C2_cmpgtui:
00225     case Intrinsic::hexagon_C2_cmpgei:
00226     case Intrinsic::hexagon_C2_cmpgeui:
00227     case Intrinsic::hexagon_C2_cmplt:
00228     case Intrinsic::hexagon_C2_cmpltu:
00229     case Intrinsic::hexagon_C2_bitsclri:
00230     case Intrinsic::hexagon_C2_and:
00231     case Intrinsic::hexagon_C2_or:
00232     case Intrinsic::hexagon_C2_xor:
00233     case Intrinsic::hexagon_C2_andn:
00234     case Intrinsic::hexagon_C2_not:
00235     case Intrinsic::hexagon_C2_orn:
00236     case Intrinsic::hexagon_C2_pxfer_map:
00237     case Intrinsic::hexagon_C2_any8:
00238     case Intrinsic::hexagon_C2_all8:
00239     case Intrinsic::hexagon_A2_vcmpbeq:
00240     case Intrinsic::hexagon_A2_vcmpbgtu:
00241     case Intrinsic::hexagon_A2_vcmpheq:
00242     case Intrinsic::hexagon_A2_vcmphgt:
00243     case Intrinsic::hexagon_A2_vcmphgtu:
00244     case Intrinsic::hexagon_A2_vcmpweq:
00245     case Intrinsic::hexagon_A2_vcmpwgt:
00246     case Intrinsic::hexagon_A2_vcmpwgtu:
00247     case Intrinsic::hexagon_C2_tfrrp:
00248     case Intrinsic::hexagon_S2_tstbit_i:
00249     case Intrinsic::hexagon_S2_tstbit_r:
00250       return true;
00251   }
00252 }
00253 
00254 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
00255                                                            unsigned Opcode,
00256                                                            SDLoc dl) {
00257   SDValue Chain = LD->getChain();
00258   EVT LoadedVT = LD->getMemoryVT();
00259   SDValue Base = LD->getBasePtr();
00260   SDValue Offset = LD->getOffset();
00261   SDNode *OffsetNode = Offset.getNode();
00262   int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
00263 
00264   if (HII->isValidAutoIncImm(LoadedVT, Val)) {
00265     SDValue TargetConst = CurDAG->getTargetConstant(Val, dl, MVT::i32);
00266     SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32,
00267                                               MVT::Other, Base, TargetConst,
00268                                               Chain);
00269     SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
00270                                               SDValue(Result_1, 0));
00271     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00272     MemOp[0] = LD->getMemOperand();
00273     cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00274     const SDValue Froms[] = { SDValue(LD, 0),
00275                               SDValue(LD, 1),
00276                               SDValue(LD, 2) };
00277     const SDValue Tos[]   = { SDValue(Result_2, 0),
00278                               SDValue(Result_1, 1),
00279                               SDValue(Result_1, 2) };
00280     ReplaceUses(Froms, Tos, 3);
00281     return Result_2;
00282   }
00283 
00284   SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
00285   SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
00286   SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Other,
00287                                             Base, TargetConst0, Chain);
00288   SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
00289                                             SDValue(Result_1, 0));
00290   SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
00291                                             Base, TargetConstVal,
00292                                             SDValue(Result_1, 1));
00293   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00294   MemOp[0] = LD->getMemOperand();
00295   cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00296   const SDValue Froms[] = { SDValue(LD, 0),
00297                             SDValue(LD, 1),
00298                             SDValue(LD, 2) };
00299   const SDValue Tos[]   = { SDValue(Result_2, 0),
00300                             SDValue(Result_3, 0),
00301                             SDValue(Result_1, 1) };
00302   ReplaceUses(Froms, Tos, 3);
00303   return Result_2;
00304 }
00305 
00306 
00307 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
00308                                                            unsigned Opcode,
00309                                                            SDLoc dl) {
00310   SDValue Chain = LD->getChain();
00311   EVT LoadedVT = LD->getMemoryVT();
00312   SDValue Base = LD->getBasePtr();
00313   SDValue Offset = LD->getOffset();
00314   SDNode *OffsetNode = Offset.getNode();
00315   int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
00316 
00317   if (HII->isValidAutoIncImm(LoadedVT, Val)) {
00318     SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
00319     SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
00320     SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
00321                                               MVT::i32, MVT::Other, Base,
00322                                               TargetConstVal, Chain);
00323     SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A4_combineir, dl,
00324                                               MVT::i64, MVT::Other,
00325                                               TargetConst0,
00326                                               SDValue(Result_1,0));
00327     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00328     MemOp[0] = LD->getMemOperand();
00329     cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00330     const SDValue Froms[] = { SDValue(LD, 0),
00331                               SDValue(LD, 1),
00332                               SDValue(LD, 2) };
00333     const SDValue Tos[]   = { SDValue(Result_2, 0),
00334                               SDValue(Result_1, 1),
00335                               SDValue(Result_1, 2) };
00336     ReplaceUses(Froms, Tos, 3);
00337     return Result_2;
00338   }
00339 
00340   // Generate an indirect load.
00341   SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
00342   SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
00343   SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
00344                                             MVT::Other, Base, TargetConst0,
00345                                             Chain);
00346   SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A4_combineir, dl,
00347                                             MVT::i64, MVT::Other,
00348                                             TargetConst0,
00349                                             SDValue(Result_1,0));
00350   // Add offset to base.
00351   SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
00352                                             Base, TargetConstVal,
00353                                             SDValue(Result_1, 1));
00354   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00355   MemOp[0] = LD->getMemOperand();
00356   cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00357   const SDValue Froms[] = { SDValue(LD, 0),
00358                             SDValue(LD, 1),
00359                             SDValue(LD, 2) };
00360   const SDValue Tos[]   = { SDValue(Result_2, 0), // Load value.
00361                             SDValue(Result_3, 0), // New address.
00362                             SDValue(Result_1, 1) };
00363   ReplaceUses(Froms, Tos, 3);
00364   return Result_2;
00365 }
00366 
00367 
00368 SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
00369   SDValue Chain = LD->getChain();
00370   SDValue Base = LD->getBasePtr();
00371   SDValue Offset = LD->getOffset();
00372   SDNode *OffsetNode = Offset.getNode();
00373   // Get the constant value.
00374   int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
00375   EVT LoadedVT = LD->getMemoryVT();
00376   unsigned Opcode = 0;
00377 
00378   // Check for zero extended loads. Treat any-extend loads as zero extended
00379   // loads.
00380   ISD::LoadExtType ExtType = LD->getExtensionType();
00381   bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD);
00382   bool HasVecOffset = false;
00383 
00384   // Figure out the opcode.
00385   if (LoadedVT == MVT::i64) {
00386     if (HII->isValidAutoIncImm(LoadedVT, Val))
00387       Opcode = Hexagon::L2_loadrd_pi;
00388     else
00389       Opcode = Hexagon::L2_loadrd_io;
00390   } else if (LoadedVT == MVT::i32) {
00391     if (HII->isValidAutoIncImm(LoadedVT, Val))
00392       Opcode = Hexagon::L2_loadri_pi;
00393     else
00394       Opcode = Hexagon::L2_loadri_io;
00395   } else if (LoadedVT == MVT::i16) {
00396     if (HII->isValidAutoIncImm(LoadedVT, Val))
00397       Opcode = IsZeroExt ? Hexagon::L2_loadruh_pi : Hexagon::L2_loadrh_pi;
00398     else
00399       Opcode = IsZeroExt ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io;
00400   } else if (LoadedVT == MVT::i8) {
00401     if (HII->isValidAutoIncImm(LoadedVT, Val))
00402       Opcode = IsZeroExt ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrb_pi;
00403     else
00404       Opcode = IsZeroExt ? Hexagon::L2_loadrub_io : Hexagon::L2_loadrb_io;
00405   } else if (LoadedVT == MVT::v16i32 || LoadedVT == MVT::v8i64 ||
00406              LoadedVT == MVT::v32i16 || LoadedVT == MVT::v64i8) {
00407     HasVecOffset = true;
00408     if (HII->isValidAutoIncImm(LoadedVT, Val)) {
00409       Opcode = Hexagon::V6_vL32b_pi;
00410     }
00411     else
00412       Opcode = Hexagon::V6_vL32b_ai;
00413   // 128B
00414   } else if (LoadedVT == MVT::v32i32 || LoadedVT == MVT::v16i64 ||
00415              LoadedVT == MVT::v64i16 || LoadedVT == MVT::v128i8) {
00416     HasVecOffset = true;
00417     if (HII->isValidAutoIncImm(LoadedVT, Val)) {
00418       Opcode = Hexagon::V6_vL32b_pi_128B;
00419     }
00420     else
00421       Opcode = Hexagon::V6_vL32b_ai_128B;
00422   } else
00423     llvm_unreachable("unknown memory type");
00424 
00425   // For zero extended i64 loads, we need to add combine instructions.
00426   if (LD->getValueType(0) == MVT::i64 && IsZeroExt)
00427     return SelectIndexedLoadZeroExtend64(LD, Opcode, dl);
00428   // Handle sign extended i64 loads.
00429   if (LD->getValueType(0) == MVT::i64 && ExtType == ISD::SEXTLOAD)
00430     return SelectIndexedLoadSignExtend64(LD, Opcode, dl);
00431 
00432   if (HII->isValidAutoIncImm(LoadedVT, Val)) {
00433     SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
00434     SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
00435                                             LD->getValueType(0),
00436                                             MVT::i32, MVT::Other, Base,
00437                                             TargetConstVal, Chain);
00438     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00439     MemOp[0] = LD->getMemOperand();
00440     cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
00441     if (HasVecOffset) {
00442       const SDValue Froms[] = { SDValue(LD, 0),
00443                                 SDValue(LD, 2)
00444       };
00445       const SDValue Tos[]   = { SDValue(Result, 0),
00446                                 SDValue(Result, 2)
00447       };
00448       ReplaceUses(Froms, Tos, 2);
00449     } else {
00450       const SDValue Froms[] = { SDValue(LD, 0),
00451                                 SDValue(LD, 1),
00452                                 SDValue(LD, 2)
00453       };
00454       const SDValue Tos[]   = { SDValue(Result, 0),
00455                                 SDValue(Result, 1),
00456                                 SDValue(Result, 2)
00457       };
00458       ReplaceUses(Froms, Tos, 3);
00459     }
00460     return Result;
00461   } else {
00462     SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
00463     SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
00464     SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl,
00465                                               LD->getValueType(0),
00466                                               MVT::Other, Base, TargetConst0,
00467                                               Chain);
00468     SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
00469                                               Base, TargetConstVal,
00470                                               SDValue(Result_1, 1));
00471     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00472     MemOp[0] = LD->getMemOperand();
00473     cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00474     const SDValue Froms[] = { SDValue(LD, 0),
00475                               SDValue(LD, 1),
00476                               SDValue(LD, 2)
00477     };
00478     const SDValue Tos[]   = { SDValue(Result_1, 0),
00479                               SDValue(Result_2, 0),
00480                               SDValue(Result_1, 1)
00481     };
00482     ReplaceUses(Froms, Tos, 3);
00483     return Result_1;
00484   }
00485 }
00486 
00487 
00488 SDNode *HexagonDAGToDAGISel::SelectLoad(SDNode *N) {
00489   SDNode *result;
00490   SDLoc dl(N);
00491   LoadSDNode *LD = cast<LoadSDNode>(N);
00492   ISD::MemIndexedMode AM = LD->getAddressingMode();
00493 
00494   // Handle indexed loads.
00495   if (AM != ISD::UNINDEXED) {
00496     result = SelectIndexedLoad(LD, dl);
00497   } else {
00498     result = SelectCode(LD);
00499   }
00500 
00501   return result;
00502 }
00503 
00504 
00505 SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) {
00506   SDValue Chain = ST->getChain();
00507   SDValue Base = ST->getBasePtr();
00508   SDValue Offset = ST->getOffset();
00509   SDValue Value = ST->getValue();
00510   SDNode *OffsetNode = Offset.getNode();
00511   // Get the constant value.
00512   int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
00513   EVT StoredVT = ST->getMemoryVT();
00514   EVT ValueVT = Value.getValueType();
00515 
00516   // Offset value must be within representable range
00517   // and must have correct alignment properties.
00518   if (HII->isValidAutoIncImm(StoredVT, Val)) {
00519     unsigned Opcode = 0;
00520 
00521     // Figure out the post inc version of opcode.
00522     if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_pi;
00523     else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_pi;
00524     else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_pi;
00525     else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_pi;
00526     else if (StoredVT == MVT::v16i32 || StoredVT == MVT::v8i64 ||
00527              StoredVT == MVT::v32i16 || StoredVT == MVT::v64i8) {
00528       Opcode = Hexagon::V6_vS32b_pi;
00529     }
00530     // 128B
00531     else if (StoredVT == MVT::v32i32 || StoredVT == MVT::v16i64 ||
00532              StoredVT == MVT::v64i16 || StoredVT == MVT::v128i8) {
00533       Opcode = Hexagon::V6_vS32b_pi_128B;
00534     } else llvm_unreachable("unknown memory type");
00535 
00536     if (ST->isTruncatingStore() && ValueVT.getSizeInBits() == 64) {
00537       assert(StoredVT.getSizeInBits() < 64 && "Not a truncating store");
00538       Value = CurDAG->getTargetExtractSubreg(Hexagon::subreg_loreg,
00539                                              dl, MVT::i32, Value);
00540     }
00541     SDValue Ops[] = {Base, CurDAG->getTargetConstant(Val, dl, MVT::i32), Value,
00542                      Chain};
00543     // Build post increment store.
00544     SDNode* Result = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
00545                                             MVT::Other, Ops);
00546     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00547     MemOp[0] = ST->getMemOperand();
00548     cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
00549 
00550     ReplaceUses(ST, Result);
00551     ReplaceUses(SDValue(ST,1), SDValue(Result,1));
00552     return Result;
00553   }
00554 
00555   // Note: Order of operands matches the def of instruction:
00556   // def S2_storerd_io
00557   //   : STInst<(outs), (ins IntRegs:$base, imm:$offset, DoubleRegs:$src1), ...
00558   // and it differs for POST_ST* for instance.
00559   SDValue Ops[] = { Base, CurDAG->getTargetConstant(0, dl, MVT::i32), Value,
00560                     Chain};
00561   unsigned Opcode = 0;
00562 
00563   // Figure out the opcode.
00564   if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_io;
00565   else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_io;
00566   else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_io;
00567   else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_io;
00568   else if (StoredVT == MVT::v16i32 || StoredVT == MVT::v8i64 ||
00569            StoredVT == MVT::v32i16 || StoredVT == MVT::v64i8)
00570      Opcode = Hexagon::V6_vS32b_ai;
00571   // 128B
00572   else if (StoredVT == MVT::v32i32 || StoredVT == MVT::v16i64 ||
00573            StoredVT == MVT::v64i16 || StoredVT == MVT::v128i8)
00574      Opcode = Hexagon::V6_vS32b_ai_128B;
00575   else llvm_unreachable("unknown memory type");
00576 
00577   // Build regular store.
00578   SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
00579   SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
00580   // Build splitted incriment instruction.
00581   SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
00582                                             Base,
00583                                             TargetConstVal,
00584                                             SDValue(Result_1, 0));
00585   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00586   MemOp[0] = ST->getMemOperand();
00587   cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00588 
00589   ReplaceUses(SDValue(ST,0), SDValue(Result_2,0));
00590   ReplaceUses(SDValue(ST,1), SDValue(Result_1,0));
00591   return Result_2;
00592 }
00593 
00594 SDNode *HexagonDAGToDAGISel::SelectStore(SDNode *N) {
00595   SDLoc dl(N);
00596   StoreSDNode *ST = cast<StoreSDNode>(N);
00597   ISD::MemIndexedMode AM = ST->getAddressingMode();
00598 
00599   // Handle indexed stores.
00600   if (AM != ISD::UNINDEXED) {
00601     return SelectIndexedStore(ST, dl);
00602   }
00603 
00604   return SelectCode(ST);
00605 }
00606 
00607 SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
00608   SDLoc dl(N);
00609 
00610   //
00611   // %conv.i = sext i32 %tmp1 to i64
00612   // %conv2.i = sext i32 %add to i64
00613   // %mul.i = mul nsw i64 %conv2.i, %conv.i
00614   //
00615   //   --- match with the following ---
00616   //
00617   // %mul.i = mpy (%tmp1, %add)
00618   //
00619 
00620   if (N->getValueType(0) == MVT::i64) {
00621     // Shifting a i64 signed multiply.
00622     SDValue MulOp0 = N->getOperand(0);
00623     SDValue MulOp1 = N->getOperand(1);
00624 
00625     SDValue OP0;
00626     SDValue OP1;
00627 
00628     // Handle sign_extend and sextload.
00629     if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
00630       SDValue Sext0 = MulOp0.getOperand(0);
00631       if (Sext0.getNode()->getValueType(0) != MVT::i32) {
00632         return SelectCode(N);
00633       }
00634 
00635       OP0 = Sext0;
00636     } else if (MulOp0.getOpcode() == ISD::LOAD) {
00637       LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
00638       if (LD->getMemoryVT() != MVT::i32 ||
00639           LD->getExtensionType() != ISD::SEXTLOAD ||
00640           LD->getAddressingMode() != ISD::UNINDEXED) {
00641         return SelectCode(N);
00642       }
00643 
00644       SDValue Chain = LD->getChain();
00645       SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
00646       OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
00647                                             MVT::Other,
00648                                             LD->getBasePtr(), TargetConst0,
00649                                             Chain), 0);
00650     } else {
00651       return SelectCode(N);
00652     }
00653 
00654     // Same goes for the second operand.
00655     if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
00656       SDValue Sext1 = MulOp1.getOperand(0);
00657       if (Sext1.getNode()->getValueType(0) != MVT::i32) {
00658         return SelectCode(N);
00659       }
00660 
00661       OP1 = Sext1;
00662     } else if (MulOp1.getOpcode() == ISD::LOAD) {
00663       LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
00664       if (LD->getMemoryVT() != MVT::i32 ||
00665           LD->getExtensionType() != ISD::SEXTLOAD ||
00666           LD->getAddressingMode() != ISD::UNINDEXED) {
00667         return SelectCode(N);
00668       }
00669 
00670       SDValue Chain = LD->getChain();
00671       SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
00672       OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
00673                                             MVT::Other,
00674                                             LD->getBasePtr(), TargetConst0,
00675                                             Chain), 0);
00676     } else {
00677       return SelectCode(N);
00678     }
00679 
00680     // Generate a mpy instruction.
00681     SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_dpmpyss_s0, dl, MVT::i64,
00682                                             OP0, OP1);
00683     ReplaceUses(N, Result);
00684     return Result;
00685   }
00686 
00687   return SelectCode(N);
00688 }
00689 
00690 SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
00691   SDLoc dl(N);
00692   if (N->getValueType(0) == MVT::i32) {
00693     SDValue Shl_0 = N->getOperand(0);
00694     SDValue Shl_1 = N->getOperand(1);
00695     // RHS is const.
00696     if (Shl_1.getOpcode() == ISD::Constant) {
00697       if (Shl_0.getOpcode() == ISD::MUL) {
00698         SDValue Mul_0 = Shl_0.getOperand(0); // Val
00699         SDValue Mul_1 = Shl_0.getOperand(1); // Const
00700         // RHS of mul is const.
00701         if (Mul_1.getOpcode() == ISD::Constant) {
00702           int32_t ShlConst =
00703             cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
00704           int32_t MulConst =
00705             cast<ConstantSDNode>(Mul_1.getNode())->getSExtValue();
00706           int32_t ValConst = MulConst << ShlConst;
00707           SDValue Val = CurDAG->getTargetConstant(ValConst, dl,
00708                                                   MVT::i32);
00709           if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val.getNode()))
00710             if (isInt<9>(CN->getSExtValue())) {
00711               SDNode* Result =
00712                 CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl,
00713                                        MVT::i32, Mul_0, Val);
00714               ReplaceUses(N, Result);
00715               return Result;
00716             }
00717 
00718         }
00719       } else if (Shl_0.getOpcode() == ISD::SUB) {
00720         SDValue Sub_0 = Shl_0.getOperand(0); // Const 0
00721         SDValue Sub_1 = Shl_0.getOperand(1); // Val
00722         if (Sub_0.getOpcode() == ISD::Constant) {
00723           int32_t SubConst =
00724             cast<ConstantSDNode>(Sub_0.getNode())->getSExtValue();
00725           if (SubConst == 0) {
00726             if (Sub_1.getOpcode() == ISD::SHL) {
00727               SDValue Shl2_0 = Sub_1.getOperand(0); // Val
00728               SDValue Shl2_1 = Sub_1.getOperand(1); // Const
00729               if (Shl2_1.getOpcode() == ISD::Constant) {
00730                 int32_t ShlConst =
00731                   cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
00732                 int32_t Shl2Const =
00733                   cast<ConstantSDNode>(Shl2_1.getNode())->getSExtValue();
00734                 int32_t ValConst = 1 << (ShlConst+Shl2Const);
00735                 SDValue Val = CurDAG->getTargetConstant(-ValConst, dl,
00736                                                         MVT::i32);
00737                 if (ConstantSDNode *CN =
00738                     dyn_cast<ConstantSDNode>(Val.getNode()))
00739                   if (isInt<9>(CN->getSExtValue())) {
00740                     SDNode* Result =
00741                       CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl, MVT::i32,
00742                                              Shl2_0, Val);
00743                     ReplaceUses(N, Result);
00744                     return Result;
00745                   }
00746               }
00747             }
00748           }
00749         }
00750       }
00751     }
00752   }
00753   return SelectCode(N);
00754 }
00755 
00756 
00757 //
00758 // If there is an zero_extend followed an intrinsic in DAG (this means - the
00759 // result of the intrinsic is predicate); convert the zero_extend to
00760 // transfer instruction.
00761 //
00762 // Zero extend -> transfer is lowered here. Otherwise, zero_extend will be
00763 // converted into a MUX as predicate registers defined as 1 bit in the
00764 // compiler. Architecture defines them as 8-bit registers.
00765 // We want to preserve all the lower 8-bits and, not just 1 LSB bit.
00766 //
00767 SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) {
00768   SDLoc dl(N);
00769 
00770   SDValue Op0 = N->getOperand(0);
00771   EVT OpVT = Op0.getValueType();
00772   unsigned OpBW = OpVT.getSizeInBits();
00773 
00774   // Special handling for zero-extending a vector of booleans.
00775   if (OpVT.isVector() && OpVT.getVectorElementType() == MVT::i1 && OpBW <= 64) {
00776     SDNode *Mask = CurDAG->getMachineNode(Hexagon::C2_mask, dl, MVT::i64, Op0);
00777     unsigned NE = OpVT.getVectorNumElements();
00778     EVT ExVT = N->getValueType(0);
00779     unsigned ES = ExVT.getVectorElementType().getSizeInBits();
00780     uint64_t MV = 0, Bit = 1;
00781     for (unsigned i = 0; i < NE; ++i) {
00782       MV |= Bit;
00783       Bit <<= ES;
00784     }
00785     SDValue Ones = CurDAG->getTargetConstant(MV, dl, MVT::i64);
00786     SDNode *OnesReg = CurDAG->getMachineNode(Hexagon::CONST64_Int_Real, dl,
00787                                              MVT::i64, Ones);
00788     if (ExVT.getSizeInBits() == 32) {
00789       SDNode *And = CurDAG->getMachineNode(Hexagon::A2_andp, dl, MVT::i64,
00790                                            SDValue(Mask,0), SDValue(OnesReg,0));
00791       SDValue SubR = CurDAG->getTargetConstant(Hexagon::subreg_loreg, dl,
00792                                                MVT::i32);
00793       return CurDAG->getMachineNode(Hexagon::EXTRACT_SUBREG, dl, ExVT,
00794                                     SDValue(And,0), SubR);
00795     }
00796     return CurDAG->getMachineNode(Hexagon::A2_andp, dl, ExVT,
00797                                   SDValue(Mask,0), SDValue(OnesReg,0));
00798   }
00799 
00800   SDNode *IsIntrinsic = N->getOperand(0).getNode();
00801   if ((IsIntrinsic->getOpcode() == ISD::INTRINSIC_WO_CHAIN)) {
00802     unsigned ID =
00803       cast<ConstantSDNode>(IsIntrinsic->getOperand(0))->getZExtValue();
00804     if (doesIntrinsicReturnPredicate(ID)) {
00805       // Now we need to differentiate target data types.
00806       if (N->getValueType(0) == MVT::i64) {
00807         // Convert the zero_extend to Rs = Pd followed by A2_combinew(0,Rs).
00808         SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
00809         SDNode *Result_1 = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
00810                                                   MVT::i32,
00811                                                   SDValue(IsIntrinsic, 0));
00812         SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl,
00813                                                   MVT::i32,
00814                                                   TargetConst0);
00815         SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl,
00816                                                   MVT::i64, MVT::Other,
00817                                                   SDValue(Result_2, 0),
00818                                                   SDValue(Result_1, 0));
00819         ReplaceUses(N, Result_3);
00820         return Result_3;
00821       }
00822       if (N->getValueType(0) == MVT::i32) {
00823         // Convert the zero_extend to Rs = Pd
00824         SDNode* RsPd = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
00825                                               MVT::i32,
00826                                               SDValue(IsIntrinsic, 0));
00827         ReplaceUses(N, RsPd);
00828         return RsPd;
00829       }
00830       llvm_unreachable("Unexpected value type");
00831     }
00832   }
00833   return SelectCode(N);
00834 }
00835 
00836 //
00837 // Checking for intrinsics circular load/store, and bitreverse load/store
00838 // instrisics in order to select the correct lowered operation.
00839 //
00840 SDNode *HexagonDAGToDAGISel::SelectIntrinsicWChain(SDNode *N) {
00841   unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
00842   if (IntNo == Intrinsic::hexagon_circ_ldd  ||
00843       IntNo == Intrinsic::hexagon_circ_ldw  ||
00844       IntNo == Intrinsic::hexagon_circ_lduh ||
00845       IntNo == Intrinsic::hexagon_circ_ldh  ||
00846       IntNo == Intrinsic::hexagon_circ_ldub ||
00847       IntNo == Intrinsic::hexagon_circ_ldb) {
00848     SDLoc dl(N);
00849     SDValue Chain = N->getOperand(0);
00850     SDValue Base = N->getOperand(2);
00851     SDValue Load = N->getOperand(3);
00852     SDValue ModifierExpr = N->getOperand(4);
00853     SDValue Offset = N->getOperand(5);
00854 
00855     // We need to add the rerurn type for the load.  This intrinsic has
00856     // two return types, one for the load and one for the post-increment.
00857     // Only the *_ld instructions push the extra return type, and bump the
00858     // result node operand number correspondingly.
00859     std::vector<EVT> ResTys;
00860     unsigned opc;
00861     unsigned memsize, align;
00862     MVT MvtSize = MVT::i32;
00863 
00864     if (IntNo == Intrinsic::hexagon_circ_ldd) {
00865       ResTys.push_back(MVT::i32);
00866       ResTys.push_back(MVT::i64);
00867       opc = Hexagon::L2_loadrd_pci_pseudo;
00868       memsize = 8;
00869       align = 8;
00870     } else if (IntNo == Intrinsic::hexagon_circ_ldw) {
00871       ResTys.push_back(MVT::i32);
00872       ResTys.push_back(MVT::i32);
00873       opc = Hexagon::L2_loadri_pci_pseudo;
00874       memsize = 4;
00875       align = 4;
00876     } else if (IntNo == Intrinsic::hexagon_circ_ldh) {
00877       ResTys.push_back(MVT::i32);
00878       ResTys.push_back(MVT::i32);
00879       opc = Hexagon::L2_loadrh_pci_pseudo;
00880       memsize = 2;
00881       align = 2;
00882       MvtSize = MVT::i16;
00883     } else if (IntNo == Intrinsic::hexagon_circ_lduh) {
00884       ResTys.push_back(MVT::i32);
00885       ResTys.push_back(MVT::i32);
00886       opc = Hexagon::L2_loadruh_pci_pseudo;
00887       memsize = 2;
00888       align = 2;
00889       MvtSize = MVT::i16;
00890     } else if (IntNo == Intrinsic::hexagon_circ_ldb) {
00891       ResTys.push_back(MVT::i32);
00892       ResTys.push_back(MVT::i32);
00893       opc = Hexagon::L2_loadrb_pci_pseudo;
00894       memsize = 1;
00895       align = 1;
00896       MvtSize = MVT::i8;
00897     } else if (IntNo == Intrinsic::hexagon_circ_ldub) {
00898       ResTys.push_back(MVT::i32);
00899       ResTys.push_back(MVT::i32);
00900       opc = Hexagon::L2_loadrub_pci_pseudo;
00901       memsize = 1;
00902       align = 1;
00903       MvtSize = MVT::i8;
00904     } else
00905       llvm_unreachable("no opc");
00906 
00907     ResTys.push_back(MVT::Other);
00908 
00909     // Copy over the arguments, which are the same mostly.
00910     SmallVector<SDValue, 5> Ops;
00911     Ops.push_back(Base);
00912     Ops.push_back(Load);
00913     Ops.push_back(ModifierExpr);
00914     int32_t Val = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
00915     Ops.push_back(CurDAG->getTargetConstant(Val, dl, MVT::i32));
00916     Ops.push_back(Chain);
00917     SDNode* Result = CurDAG->getMachineNode(opc, dl, ResTys, Ops);
00918 
00919     SDValue ST;
00920     MachineMemOperand *Mem =
00921       MF->getMachineMemOperand(MachinePointerInfo(),
00922                                MachineMemOperand::MOStore, memsize, align);
00923     if (MvtSize != MVT::i32)
00924       ST = CurDAG->getTruncStore(Chain, dl, SDValue(Result, 1), Load,
00925                                  MvtSize, Mem);
00926     else
00927       ST = CurDAG->getStore(Chain, dl, SDValue(Result, 1), Load, Mem);
00928 
00929     SDNode* Store = SelectStore(ST.getNode());
00930 
00931     const SDValue Froms[] = { SDValue(N, 0),
00932                               SDValue(N, 1) };
00933     const SDValue Tos[]   = { SDValue(Result, 0),
00934                               SDValue(Store, 0) };
00935     ReplaceUses(Froms, Tos, 2);
00936     return Result;
00937   }
00938 
00939   if (IntNo == Intrinsic::hexagon_brev_ldd  ||
00940       IntNo == Intrinsic::hexagon_brev_ldw  ||
00941       IntNo == Intrinsic::hexagon_brev_ldh  ||
00942       IntNo == Intrinsic::hexagon_brev_lduh ||
00943       IntNo == Intrinsic::hexagon_brev_ldb  ||
00944       IntNo == Intrinsic::hexagon_brev_ldub) {
00945     SDLoc dl(N);
00946     SDValue Chain = N->getOperand(0);
00947     SDValue Base = N->getOperand(2);
00948     SDValue Load = N->getOperand(3);
00949     SDValue ModifierExpr = N->getOperand(4);
00950 
00951     // We need to add the rerurn type for the load.  This intrinsic has
00952     // two return types, one for the load and one for the post-increment.
00953     std::vector<EVT> ResTys;
00954     unsigned opc;
00955     unsigned memsize, align;
00956     MVT MvtSize = MVT::i32;
00957 
00958     if (IntNo == Intrinsic::hexagon_brev_ldd) {
00959       ResTys.push_back(MVT::i32);
00960       ResTys.push_back(MVT::i64);
00961       opc = Hexagon::L2_loadrd_pbr_pseudo;
00962       memsize = 8;
00963       align = 8;
00964     } else if (IntNo == Intrinsic::hexagon_brev_ldw) {
00965       ResTys.push_back(MVT::i32);
00966       ResTys.push_back(MVT::i32);
00967       opc = Hexagon::L2_loadri_pbr_pseudo;
00968       memsize = 4;
00969       align = 4;
00970     } else if (IntNo == Intrinsic::hexagon_brev_ldh) {
00971       ResTys.push_back(MVT::i32);
00972       ResTys.push_back(MVT::i32);
00973       opc = Hexagon::L2_loadrh_pbr_pseudo;
00974       memsize = 2;
00975       align = 2;
00976       MvtSize = MVT::i16;
00977     } else if (IntNo == Intrinsic::hexagon_brev_lduh) {
00978       ResTys.push_back(MVT::i32);
00979       ResTys.push_back(MVT::i32);
00980       opc = Hexagon::L2_loadruh_pbr_pseudo;
00981       memsize = 2;
00982       align = 2;
00983       MvtSize = MVT::i16;
00984     } else if (IntNo == Intrinsic::hexagon_brev_ldb) {
00985       ResTys.push_back(MVT::i32);
00986       ResTys.push_back(MVT::i32);
00987       opc = Hexagon::L2_loadrb_pbr_pseudo;
00988       memsize = 1;
00989       align = 1;
00990       MvtSize = MVT::i8;
00991     } else if (IntNo == Intrinsic::hexagon_brev_ldub) {
00992       ResTys.push_back(MVT::i32);
00993       ResTys.push_back(MVT::i32);
00994       opc = Hexagon::L2_loadrub_pbr_pseudo;
00995       memsize = 1;
00996       align = 1;
00997       MvtSize = MVT::i8;
00998     } else
00999       llvm_unreachable("no opc");
01000 
01001     ResTys.push_back(MVT::Other);
01002 
01003     // Copy over the arguments, which are the same mostly.
01004     SmallVector<SDValue, 4> Ops;
01005     Ops.push_back(Base);
01006     Ops.push_back(Load);
01007     Ops.push_back(ModifierExpr);
01008     Ops.push_back(Chain);
01009     SDNode* Result = CurDAG->getMachineNode(opc, dl, ResTys, Ops);
01010     SDValue ST;
01011     MachineMemOperand *Mem =
01012       MF->getMachineMemOperand(MachinePointerInfo(),
01013                                MachineMemOperand::MOStore, memsize, align);
01014     if (MvtSize != MVT::i32)
01015       ST = CurDAG->getTruncStore(Chain, dl, SDValue(Result, 1), Load,
01016                                  MvtSize, Mem);
01017     else
01018       ST = CurDAG->getStore(Chain, dl, SDValue(Result, 1), Load, Mem);
01019 
01020     SDNode* Store = SelectStore(ST.getNode());
01021 
01022     const SDValue Froms[] = { SDValue(N, 0),
01023                               SDValue(N, 1) };
01024     const SDValue Tos[]   = { SDValue(Result, 0),
01025                               SDValue(Store, 0) };
01026     ReplaceUses(Froms, Tos, 2);
01027     return Result;
01028   }
01029 
01030   return SelectCode(N);
01031 }
01032 
01033 //
01034 // Checking for intrinsics which have predicate registers as operand(s)
01035 // and lowering to the actual intrinsic.
01036 //
01037 SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
01038   unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
01039   unsigned Bits;
01040   switch (IID) {
01041   case Intrinsic::hexagon_S2_vsplatrb:
01042     Bits = 8;
01043     break;
01044   case Intrinsic::hexagon_S2_vsplatrh:
01045     Bits = 16;
01046     break;
01047   default:
01048     return SelectCode(N);
01049   }
01050 
01051   SDValue const &V = N->getOperand(1);
01052   SDValue U;
01053   if (isValueExtension(V, Bits, U)) {
01054     SDValue R = CurDAG->getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
01055       N->getOperand(0), U);
01056     return SelectCode(R.getNode());
01057   }
01058   return SelectCode(N);
01059 }
01060 
01061 //
01062 // Map floating point constant values.
01063 //
01064 SDNode *HexagonDAGToDAGISel::SelectConstantFP(SDNode *N) {
01065   SDLoc dl(N);
01066   ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
01067   APFloat APF = CN->getValueAPF();
01068   if (N->getValueType(0) == MVT::f32) {
01069     return CurDAG->getMachineNode(Hexagon::TFRI_f, dl, MVT::f32,
01070               CurDAG->getTargetConstantFP(APF.convertToFloat(), dl, MVT::f32));
01071   }
01072   else if (N->getValueType(0) == MVT::f64) {
01073     return CurDAG->getMachineNode(Hexagon::CONST64_Float_Real, dl, MVT::f64,
01074               CurDAG->getTargetConstantFP(APF.convertToDouble(), dl, MVT::f64));
01075   }
01076 
01077   return SelectCode(N);
01078 }
01079 
01080 //
01081 // Map predicate true (encoded as -1 in LLVM) to a XOR.
01082 //
01083 SDNode *HexagonDAGToDAGISel::SelectConstant(SDNode *N) {
01084   SDLoc dl(N);
01085   if (N->getValueType(0) == MVT::i1) {
01086     SDNode* Result = 0;
01087     int32_t Val = cast<ConstantSDNode>(N)->getSExtValue();
01088     if (Val == -1) {
01089       Result = CurDAG->getMachineNode(Hexagon::TFR_PdTrue, dl, MVT::i1);
01090     } else if (Val == 0) {
01091       Result = CurDAG->getMachineNode(Hexagon::TFR_PdFalse, dl, MVT::i1);
01092     }
01093     if (Result) {
01094       ReplaceUses(N, Result);
01095       return Result;
01096     }
01097   }
01098 
01099   return SelectCode(N);
01100 }
01101 
01102 
01103 //
01104 // Map add followed by a asr -> asr +=.
01105 //
01106 SDNode *HexagonDAGToDAGISel::SelectAdd(SDNode *N) {
01107   SDLoc dl(N);
01108   if (N->getValueType(0) != MVT::i32) {
01109     return SelectCode(N);
01110   }
01111   // Identify nodes of the form: add(asr(...)).
01112   SDNode* Src1 = N->getOperand(0).getNode();
01113   if (Src1->getOpcode() != ISD::SRA || !Src1->hasOneUse()
01114       || Src1->getValueType(0) != MVT::i32) {
01115     return SelectCode(N);
01116   }
01117 
01118   // Build Rd = Rd' + asr(Rs, Rt). The machine constraints will ensure that
01119   // Rd and Rd' are assigned to the same register
01120   SDNode* Result = CurDAG->getMachineNode(Hexagon::S2_asr_r_r_acc, dl, MVT::i32,
01121                                           N->getOperand(1),
01122                                           Src1->getOperand(0),
01123                                           Src1->getOperand(1));
01124   ReplaceUses(N, Result);
01125 
01126   return Result;
01127 }
01128 
01129 //
01130 // Map the following, where possible.
01131 // AND/FABS -> clrbit
01132 // OR -> setbit
01133 // XOR/FNEG ->toggle_bit.
01134 //
01135 SDNode *HexagonDAGToDAGISel::SelectBitOp(SDNode *N) {
01136   SDLoc dl(N);
01137   EVT ValueVT = N->getValueType(0);
01138 
01139   // We handle only 32 and 64-bit bit ops.
01140   if (!(ValueVT == MVT::i32 || ValueVT == MVT::i64 ||
01141         ValueVT == MVT::f32 || ValueVT == MVT::f64))
01142     return SelectCode(N);
01143 
01144   // We handly only fabs and fneg for V5.
01145   unsigned Opc = N->getOpcode();
01146   if ((Opc == ISD::FABS || Opc == ISD::FNEG) && !HST->hasV5TOps())
01147     return SelectCode(N);
01148 
01149   int64_t Val = 0;
01150   if (Opc != ISD::FABS && Opc != ISD::FNEG) {
01151     if (N->getOperand(1).getOpcode() == ISD::Constant)
01152       Val = cast<ConstantSDNode>((N)->getOperand(1))->getSExtValue();
01153     else
01154      return SelectCode(N);
01155   }
01156 
01157   if (Opc == ISD::AND) {
01158     // Check if this is a bit-clearing AND, if not select code the usual way.
01159     if ((ValueVT == MVT::i32 && isPowerOf2_32(~Val)) ||
01160         (ValueVT == MVT::i64 && isPowerOf2_64(~Val)))
01161       Val = ~Val;
01162     else
01163       return SelectCode(N);
01164   }
01165 
01166   // If OR or AND is being fed by shl, srl and, sra don't do this change,
01167   // because Hexagon provide |= &= on shl, srl, and sra.
01168   // Traverse the DAG to see if there is shl, srl and sra.
01169   if (Opc == ISD::OR || Opc == ISD::AND) {
01170     switch (N->getOperand(0)->getOpcode()) {
01171       default:
01172         break;
01173       case ISD::SRA:
01174       case ISD::SRL:
01175       case ISD::SHL:
01176         return SelectCode(N);
01177     }
01178   }
01179 
01180   // Make sure it's power of 2.
01181   unsigned BitPos = 0;
01182   if (Opc != ISD::FABS && Opc != ISD::FNEG) {
01183     if ((ValueVT == MVT::i32 && !isPowerOf2_32(Val)) ||
01184         (ValueVT == MVT::i64 && !isPowerOf2_64(Val)))
01185       return SelectCode(N);
01186 
01187     // Get the bit position.
01188     BitPos = countTrailingZeros(uint64_t(Val));
01189   } else {
01190     // For fabs and fneg, it's always the 31st bit.
01191     BitPos = 31;
01192   }
01193 
01194   unsigned BitOpc = 0;
01195   // Set the right opcode for bitwise operations.
01196   switch (Opc) {
01197     default:
01198       llvm_unreachable("Only bit-wise/abs/neg operations are allowed.");
01199     case ISD::AND:
01200     case ISD::FABS:
01201       BitOpc = Hexagon::S2_clrbit_i;
01202       break;
01203     case ISD::OR:
01204       BitOpc = Hexagon::S2_setbit_i;
01205       break;
01206     case ISD::XOR:
01207     case ISD::FNEG:
01208       BitOpc = Hexagon::S2_togglebit_i;
01209       break;
01210   }
01211 
01212   SDNode *Result;
01213   // Get the right SDVal for the opcode.
01214   SDValue SDVal = CurDAG->getTargetConstant(BitPos, dl, MVT::i32);
01215 
01216   if (ValueVT == MVT::i32 || ValueVT == MVT::f32) {
01217     Result = CurDAG->getMachineNode(BitOpc, dl, ValueVT,
01218                                     N->getOperand(0), SDVal);
01219   } else {
01220     // 64-bit gymnastic to use REG_SEQUENCE. But it's worth it.
01221     EVT SubValueVT;
01222     if (ValueVT == MVT::i64)
01223       SubValueVT = MVT::i32;
01224     else
01225       SubValueVT = MVT::f32;
01226 
01227     SDNode *Reg = N->getOperand(0).getNode();
01228     SDValue RegClass = CurDAG->getTargetConstant(Hexagon::DoubleRegsRegClassID,
01229                                                  dl, MVT::i64);
01230 
01231     SDValue SubregHiIdx = CurDAG->getTargetConstant(Hexagon::subreg_hireg, dl,
01232                                                     MVT::i32);
01233     SDValue SubregLoIdx = CurDAG->getTargetConstant(Hexagon::subreg_loreg, dl,
01234                                                     MVT::i32);
01235 
01236     SDValue SubregHI = CurDAG->getTargetExtractSubreg(Hexagon::subreg_hireg, dl,
01237                                                     MVT::i32, SDValue(Reg, 0));
01238 
01239     SDValue SubregLO = CurDAG->getTargetExtractSubreg(Hexagon::subreg_loreg, dl,
01240                                                     MVT::i32, SDValue(Reg, 0));
01241 
01242     // Clear/set/toggle hi or lo registers depending on the bit position.
01243     if (SubValueVT != MVT::f32 && BitPos < 32) {
01244       SDNode *Result0 = CurDAG->getMachineNode(BitOpc, dl, SubValueVT,
01245                                                SubregLO, SDVal);
01246       const SDValue Ops[] = { RegClass, SubregHI, SubregHiIdx,
01247                               SDValue(Result0, 0), SubregLoIdx };
01248       Result = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
01249                                       dl, ValueVT, Ops);
01250     } else {
01251       if (Opc != ISD::FABS && Opc != ISD::FNEG)
01252         SDVal = CurDAG->getTargetConstant(BitPos-32, dl, MVT::i32);
01253       SDNode *Result0 = CurDAG->getMachineNode(BitOpc, dl, SubValueVT,
01254                                                SubregHI, SDVal);
01255       const SDValue Ops[] = { RegClass, SDValue(Result0, 0), SubregHiIdx,
01256                               SubregLO, SubregLoIdx };
01257       Result = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
01258                                       dl, ValueVT, Ops);
01259     }
01260   }
01261 
01262   ReplaceUses(N, Result);
01263   return Result;
01264 }
01265 
01266 
01267 SDNode *HexagonDAGToDAGISel::SelectFrameIndex(SDNode *N) {
01268   MachineFrameInfo *MFI = MF->getFrameInfo();
01269   const HexagonFrameLowering *HFI = HST->getFrameLowering();
01270   int FX = cast<FrameIndexSDNode>(N)->getIndex();
01271   unsigned StkA = HFI->getStackAlignment();
01272   unsigned MaxA = MFI->getMaxAlignment();
01273   SDValue FI = CurDAG->getTargetFrameIndex(FX, MVT::i32);
01274   SDLoc DL(N);
01275   SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
01276   SDNode *R = 0;
01277 
01278   // Use TFR_FI when:
01279   // - the object is fixed, or
01280   // - there are no objects with higher-than-default alignment, or
01281   // - there are no dynamically allocated objects.
01282   // Otherwise, use TFR_FIA.
01283   if (FX < 0 || MaxA <= StkA || !MFI->hasVarSizedObjects()) {
01284     R = CurDAG->getMachineNode(Hexagon::TFR_FI, DL, MVT::i32, FI, Zero);
01285   } else {
01286     auto &HMFI = *MF->getInfo<HexagonMachineFunctionInfo>();
01287     unsigned AR = HMFI.getStackAlignBaseVReg();
01288     SDValue CH = CurDAG->getEntryNode();
01289     SDValue Ops[] = { CurDAG->getCopyFromReg(CH, DL, AR, MVT::i32), FI, Zero };
01290     R = CurDAG->getMachineNode(Hexagon::TFR_FIA, DL, MVT::i32, Ops);
01291   }
01292 
01293   if (N->getHasDebugValue())
01294     CurDAG->TransferDbgValues(SDValue(N, 0), SDValue(R, 0));
01295   return R;
01296 }
01297 
01298 
01299 SDNode *HexagonDAGToDAGISel::Select(SDNode *N) {
01300   if (N->isMachineOpcode()) {
01301     N->setNodeId(-1);
01302     return nullptr;   // Already selected.
01303   }
01304 
01305   switch (N->getOpcode()) {
01306   case ISD::Constant:
01307     return SelectConstant(N);
01308 
01309   case ISD::ConstantFP:
01310     return SelectConstantFP(N);
01311 
01312   case ISD::FrameIndex:
01313     return SelectFrameIndex(N);
01314 
01315   case ISD::ADD:
01316     return SelectAdd(N);
01317 
01318   case ISD::SHL:
01319     return SelectSHL(N);
01320 
01321   case ISD::LOAD:
01322     return SelectLoad(N);
01323 
01324   case ISD::STORE:
01325     return SelectStore(N);
01326 
01327   case ISD::MUL:
01328     return SelectMul(N);
01329 
01330   case ISD::AND:
01331   case ISD::OR:
01332   case ISD::XOR:
01333   case ISD::FABS:
01334   case ISD::FNEG:
01335     return SelectBitOp(N);
01336 
01337   case ISD::ZERO_EXTEND:
01338     return SelectZeroExtend(N);
01339 
01340   case ISD::INTRINSIC_W_CHAIN:
01341     return SelectIntrinsicWChain(N);
01342 
01343   case ISD::INTRINSIC_WO_CHAIN:
01344     return SelectIntrinsicWOChain(N);
01345   }
01346 
01347   return SelectCode(N);
01348 }
01349 
01350 bool HexagonDAGToDAGISel::
01351 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
01352                              std::vector<SDValue> &OutOps) {
01353   SDValue Inp = Op, Res;
01354 
01355   switch (ConstraintID) {
01356   default:
01357     return true;
01358   case InlineAsm::Constraint_i:
01359   case InlineAsm::Constraint_o: // Offsetable.
01360   case InlineAsm::Constraint_v: // Not offsetable.
01361   case InlineAsm::Constraint_m: // Memory.
01362     if (SelectAddrFI(Inp, Res))
01363       OutOps.push_back(Res);
01364     else
01365       OutOps.push_back(Inp);
01366     break;
01367   }
01368 
01369   OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
01370   return false;
01371 }
01372 
01373 
01374 void HexagonDAGToDAGISel::PreprocessISelDAG() {
01375   SelectionDAG &DAG = *CurDAG;
01376   std::vector<SDNode*> Nodes;
01377   for (SDNode &Node : DAG.allnodes())
01378     Nodes.push_back(&Node);
01379 
01380   // Simplify: (or (select c x 0) z)  ->  (select c (or x z) z)
01381   //           (or (select c 0 y) z)  ->  (select c z (or y z))
01382   // This may not be the right thing for all targets, so do it here.
01383   for (auto I: Nodes) {
01384     if (I->getOpcode() != ISD::OR)
01385       continue;
01386 
01387     auto IsZero = [] (const SDValue &V) -> bool {
01388       if (ConstantSDNode *SC = dyn_cast<ConstantSDNode>(V.getNode()))
01389         return SC->isNullValue();
01390       return false;
01391     };
01392     auto IsSelect0 = [IsZero] (const SDValue &Op) -> bool {
01393       if (Op.getOpcode() != ISD::SELECT)
01394         return false;
01395       return IsZero(Op.getOperand(1))  || IsZero(Op.getOperand(2));
01396     };
01397 
01398     SDValue N0 = I->getOperand(0), N1 = I->getOperand(1);
01399     EVT VT = I->getValueType(0);
01400     bool SelN0 = IsSelect0(N0);
01401     SDValue SOp = SelN0 ? N0 : N1;
01402     SDValue VOp = SelN0 ? N1 : N0;
01403 
01404     if (SOp.getOpcode() == ISD::SELECT && SOp.getNode()->hasOneUse()) {
01405       SDValue SC = SOp.getOperand(0);
01406       SDValue SX = SOp.getOperand(1);
01407       SDValue SY = SOp.getOperand(2);
01408       SDLoc DLS = SOp;
01409       if (IsZero(SY)) {
01410         SDValue NewOr = DAG.getNode(ISD::OR, DLS, VT, SX, VOp);
01411         SDValue NewSel = DAG.getNode(ISD::SELECT, DLS, VT, SC, NewOr, VOp);
01412         DAG.ReplaceAllUsesWith(I, NewSel.getNode());
01413       } else if (IsZero(SX)) {
01414         SDValue NewOr = DAG.getNode(ISD::OR, DLS, VT, SY, VOp);
01415         SDValue NewSel = DAG.getNode(ISD::SELECT, DLS, VT, SC, VOp, NewOr);
01416         DAG.ReplaceAllUsesWith(I, NewSel.getNode());
01417       }
01418     }
01419   }
01420 }
01421 
01422 void HexagonDAGToDAGISel::EmitFunctionEntryCode() {
01423   auto &HST = static_cast<const HexagonSubtarget&>(MF->getSubtarget());
01424   auto &HFI = *HST.getFrameLowering();
01425   if (!HFI.needsAligna(*MF))
01426     return;
01427 
01428   MachineFrameInfo *MFI = MF->getFrameInfo();
01429   MachineBasicBlock *EntryBB = &MF->front();
01430   unsigned AR = FuncInfo->CreateReg(MVT::i32);
01431   unsigned MaxA = MFI->getMaxAlignment();
01432   BuildMI(EntryBB, DebugLoc(), HII->get(Hexagon::ALIGNA), AR)
01433       .addImm(MaxA);
01434   MF->getInfo<HexagonMachineFunctionInfo>()->setStackAlignBaseVReg(AR);
01435 }
01436 
01437 // Match a frame index that can be used in an addressing mode.
01438 bool HexagonDAGToDAGISel::SelectAddrFI(SDValue& N, SDValue &R) {
01439   if (N.getOpcode() != ISD::FrameIndex)
01440     return false;
01441   auto &HFI = *HST->getFrameLowering();
01442   MachineFrameInfo *MFI = MF->getFrameInfo();
01443   int FX = cast<FrameIndexSDNode>(N)->getIndex();
01444   if (!MFI->isFixedObjectIndex(FX) && HFI.needsAligna(*MF))
01445     return false;
01446   R = CurDAG->getTargetFrameIndex(FX, MVT::i32);
01447   return true;
01448 }
01449 
01450 inline bool HexagonDAGToDAGISel::SelectAddrGA(SDValue &N, SDValue &R) {
01451   return SelectGlobalAddress(N, R, false);
01452 }
01453 
01454 inline bool HexagonDAGToDAGISel::SelectAddrGP(SDValue &N, SDValue &R) {
01455   return SelectGlobalAddress(N, R, true);
01456 }
01457 
01458 bool HexagonDAGToDAGISel::SelectGlobalAddress(SDValue &N, SDValue &R,
01459                                               bool UseGP) {
01460   switch (N.getOpcode()) {
01461   case ISD::ADD: {
01462     SDValue N0 = N.getOperand(0);
01463     SDValue N1 = N.getOperand(1);
01464     unsigned GAOpc = N0.getOpcode();
01465     if (UseGP && GAOpc != HexagonISD::CONST32_GP)
01466       return false;
01467     if (!UseGP && GAOpc != HexagonISD::CONST32)
01468       return false;
01469     if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N1)) {
01470       SDValue Addr = N0.getOperand(0);
01471       if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Addr)) {
01472         if (GA->getOpcode() == ISD::TargetGlobalAddress) {
01473           uint64_t NewOff = GA->getOffset() + (uint64_t)Const->getSExtValue();
01474           R = CurDAG->getTargetGlobalAddress(GA->getGlobal(), SDLoc(Const),
01475                                              N.getValueType(), NewOff);
01476           return true;
01477         }
01478       }
01479     }
01480     break;
01481   }
01482   case HexagonISD::CONST32:
01483     // The operand(0) of CONST32 is TargetGlobalAddress, which is what we
01484     // want in the instruction.
01485     if (!UseGP)
01486       R = N.getOperand(0);
01487     return !UseGP;
01488   case HexagonISD::CONST32_GP:
01489     if (UseGP)
01490       R = N.getOperand(0);
01491     return UseGP;
01492   default:
01493     return false;
01494   }
01495 
01496   return false;
01497 }
01498 
01499 bool HexagonDAGToDAGISel::isValueExtension(const SDValue &Val,
01500       unsigned FromBits, SDValue &Src) {
01501   unsigned Opc = Val.getOpcode();
01502   switch (Opc) {
01503   case ISD::SIGN_EXTEND:
01504   case ISD::ZERO_EXTEND:
01505   case ISD::ANY_EXTEND: {
01506     SDValue const &Op0 = Val.getOperand(0);
01507     EVT T = Op0.getValueType();
01508     if (T.isInteger() && T.getSizeInBits() == FromBits) {
01509       Src = Op0;
01510       return true;
01511     }
01512     break;
01513   }
01514   case ISD::SIGN_EXTEND_INREG:
01515   case ISD::AssertSext:
01516   case ISD::AssertZext:
01517     if (Val.getOperand(0).getValueType().isInteger()) {
01518       VTSDNode *T = cast<VTSDNode>(Val.getOperand(1));
01519       if (T->getVT().getSizeInBits() == FromBits) {
01520         Src = Val.getOperand(0);
01521         return true;
01522       }
01523     }
01524     break;
01525   case ISD::AND: {
01526     // Check if this is an AND with "FromBits" of lower bits set to 1.
01527     uint64_t FromMask = (1 << FromBits) - 1;
01528     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(0))) {
01529       if (C->getZExtValue() == FromMask) {
01530         Src = Val.getOperand(1);
01531         return true;
01532       }
01533     }
01534     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(1))) {
01535       if (C->getZExtValue() == FromMask) {
01536         Src = Val.getOperand(0);
01537         return true;
01538       }
01539     }
01540     break;
01541   }
01542   case ISD::OR:
01543   case ISD::XOR: {
01544     // OR/XOR with the lower "FromBits" bits set to 0.
01545     uint64_t FromMask = (1 << FromBits) - 1;
01546     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(0))) {
01547       if ((C->getZExtValue() & FromMask) == 0) {
01548         Src = Val.getOperand(1);
01549         return true;
01550       }
01551     }
01552     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(1))) {
01553       if ((C->getZExtValue() & FromMask) == 0) {
01554         Src = Val.getOperand(0);
01555         return true;
01556       }
01557     }
01558   }
01559   default:
01560     break;
01561   }
01562   return false;
01563 }