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HexagonISelDAGToDAG.cpp
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00001 //===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file defines an instruction selector for the Hexagon target.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "Hexagon.h"
00015 #include "HexagonISelLowering.h"
00016 #include "HexagonMachineFunctionInfo.h"
00017 #include "HexagonTargetMachine.h"
00018 #include "llvm/ADT/DenseMap.h"
00019 #include "llvm/CodeGen/FunctionLoweringInfo.h"
00020 #include "llvm/CodeGen/MachineInstrBuilder.h"
00021 #include "llvm/CodeGen/SelectionDAGISel.h"
00022 #include "llvm/IR/Intrinsics.h"
00023 #include "llvm/Support/CommandLine.h"
00024 #include "llvm/Support/Compiler.h"
00025 #include "llvm/Support/Debug.h"
00026 using namespace llvm;
00027 
00028 #define DEBUG_TYPE "hexagon-isel"
00029 
00030 static
00031 cl::opt<unsigned>
00032 MaxNumOfUsesForConstExtenders("ga-max-num-uses-for-constant-extenders",
00033   cl::Hidden, cl::init(2),
00034   cl::desc("Maximum number of uses of a global address such that we still us a"
00035            "constant extended instruction"));
00036 
00037 //===----------------------------------------------------------------------===//
00038 // Instruction Selector Implementation
00039 //===----------------------------------------------------------------------===//
00040 
00041 namespace llvm {
00042   void initializeHexagonDAGToDAGISelPass(PassRegistry&);
00043 }
00044 
00045 //===--------------------------------------------------------------------===//
00046 /// HexagonDAGToDAGISel - Hexagon specific code to select Hexagon machine
00047 /// instructions for SelectionDAG operations.
00048 ///
00049 namespace {
00050 class HexagonDAGToDAGISel : public SelectionDAGISel {
00051   const HexagonTargetMachine& HTM;
00052   const HexagonSubtarget *HST;
00053 public:
00054   explicit HexagonDAGToDAGISel(HexagonTargetMachine &tm,
00055                                CodeGenOpt::Level OptLevel)
00056       : SelectionDAGISel(tm, OptLevel), HTM(tm) {
00057     initializeHexagonDAGToDAGISelPass(*PassRegistry::getPassRegistry());
00058   }
00059 
00060   bool runOnMachineFunction(MachineFunction &MF) override {
00061     // Reset the subtarget each time through.
00062     HST = &MF.getSubtarget<HexagonSubtarget>();
00063     SelectionDAGISel::runOnMachineFunction(MF);
00064     return true;
00065   }
00066 
00067   virtual void PreprocessISelDAG() override;
00068   virtual void EmitFunctionEntryCode() override;
00069 
00070   SDNode *Select(SDNode *N) override;
00071 
00072   // Complex Pattern Selectors.
00073   inline bool SelectAddrGA(SDValue &N, SDValue &R);
00074   inline bool SelectAddrGP(SDValue &N, SDValue &R);
00075   bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP);
00076   bool SelectAddrFI(SDValue &N, SDValue &R);
00077 
00078   const char *getPassName() const override {
00079     return "Hexagon DAG->DAG Pattern Instruction Selection";
00080   }
00081 
00082   SDNode *SelectFrameIndex(SDNode *N);
00083   /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
00084   /// inline asm expressions.
00085   bool SelectInlineAsmMemoryOperand(const SDValue &Op,
00086                                     unsigned ConstraintID,
00087                                     std::vector<SDValue> &OutOps) override;
00088   SDNode *SelectLoad(SDNode *N);
00089   SDNode *SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl);
00090   SDNode *SelectIndexedLoad(LoadSDNode *LD, SDLoc dl);
00091   SDNode *SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
00092                                         SDLoc dl);
00093   SDNode *SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode,
00094                                         SDLoc dl);
00095   SDNode *SelectBaseOffsetStore(StoreSDNode *ST, SDLoc dl);
00096   SDNode *SelectIndexedStore(StoreSDNode *ST, SDLoc dl);
00097   SDNode *SelectStore(SDNode *N);
00098   SDNode *SelectSHL(SDNode *N);
00099   SDNode *SelectMul(SDNode *N);
00100   SDNode *SelectZeroExtend(SDNode *N);
00101   SDNode *SelectIntrinsicWChain(SDNode *N);
00102   SDNode *SelectIntrinsicWOChain(SDNode *N);
00103   SDNode *SelectConstant(SDNode *N);
00104   SDNode *SelectConstantFP(SDNode *N);
00105   SDNode *SelectAdd(SDNode *N);
00106   SDNode *SelectBitOp(SDNode *N);
00107 
00108   // XformMskToBitPosU5Imm - Returns the bit position which
00109   // the single bit 32 bit mask represents.
00110   // Used in Clr and Set bit immediate memops.
00111   SDValue XformMskToBitPosU5Imm(uint32_t Imm, SDLoc DL) {
00112     int32_t bitPos;
00113     bitPos = Log2_32(Imm);
00114     assert(bitPos >= 0 && bitPos < 32 &&
00115            "Constant out of range for 32 BitPos Memops");
00116     return CurDAG->getTargetConstant(bitPos, DL, MVT::i32);
00117   }
00118 
00119   // XformMskToBitPosU4Imm - Returns the bit position which the single-bit
00120   // 16 bit mask represents. Used in Clr and Set bit immediate memops.
00121   SDValue XformMskToBitPosU4Imm(uint16_t Imm, SDLoc DL) {
00122     return XformMskToBitPosU5Imm(Imm, DL);
00123   }
00124 
00125   // XformMskToBitPosU3Imm - Returns the bit position which the single-bit
00126   // 8 bit mask represents. Used in Clr and Set bit immediate memops.
00127   SDValue XformMskToBitPosU3Imm(uint8_t Imm, SDLoc DL) {
00128     return XformMskToBitPosU5Imm(Imm, DL);
00129   }
00130 
00131   // Return true if there is exactly one bit set in V, i.e., if V is one of the
00132   // following integers: 2^0, 2^1, ..., 2^31.
00133   bool ImmIsSingleBit(uint32_t v) const {
00134     return isPowerOf2_32(v);
00135   }
00136 
00137   // XformM5ToU5Imm - Return a target constant with the specified value, of
00138   // type i32 where the negative literal is transformed into a positive literal
00139   // for use in -= memops.
00140   inline SDValue XformM5ToU5Imm(signed Imm, SDLoc DL) {
00141      assert( (Imm >= -31 && Imm <= -1)  && "Constant out of range for Memops");
00142      return CurDAG->getTargetConstant( - Imm, DL, MVT::i32);
00143   }
00144 
00145   // XformU7ToU7M1Imm - Return a target constant decremented by 1, in range
00146   // [1..128], used in cmpb.gtu instructions.
00147   inline SDValue XformU7ToU7M1Imm(signed Imm, SDLoc DL) {
00148     assert((Imm >= 1 && Imm <= 128) && "Constant out of range for cmpb op");
00149     return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i8);
00150   }
00151 
00152   // XformS8ToS8M1Imm - Return a target constant decremented by 1.
00153   inline SDValue XformSToSM1Imm(signed Imm, SDLoc DL) {
00154     return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i32);
00155   }
00156 
00157   // XformU8ToU8M1Imm - Return a target constant decremented by 1.
00158   inline SDValue XformUToUM1Imm(unsigned Imm, SDLoc DL) {
00159     assert((Imm >= 1) && "Cannot decrement unsigned int less than 1");
00160     return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i32);
00161   }
00162 
00163   // XformSToSM2Imm - Return a target constant decremented by 2.
00164   inline SDValue XformSToSM2Imm(unsigned Imm, SDLoc DL) {
00165     return CurDAG->getTargetConstant(Imm - 2, DL, MVT::i32);
00166   }
00167 
00168   // XformSToSM3Imm - Return a target constant decremented by 3.
00169   inline SDValue XformSToSM3Imm(unsigned Imm, SDLoc DL) {
00170     return CurDAG->getTargetConstant(Imm - 3, DL, MVT::i32);
00171   }
00172 
00173   // Include the pieces autogenerated from the target description.
00174   #include "HexagonGenDAGISel.inc"
00175 
00176 private:
00177   bool isValueExtension(const SDValue &Val, unsigned FromBits, SDValue &Src);
00178 }; // end HexagonDAGToDAGISel
00179 }  // end anonymous namespace
00180 
00181 
00182 /// createHexagonISelDag - This pass converts a legalized DAG into a
00183 /// Hexagon-specific DAG, ready for instruction scheduling.
00184 ///
00185 namespace llvm {
00186 FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
00187                                    CodeGenOpt::Level OptLevel) {
00188   return new HexagonDAGToDAGISel(TM, OptLevel);
00189 }
00190 }
00191 
00192 static void initializePassOnce(PassRegistry &Registry) {
00193   const char *Name = "Hexagon DAG->DAG Pattern Instruction Selection";
00194   PassInfo *PI = new PassInfo(Name, "hexagon-isel",
00195                               &SelectionDAGISel::ID, nullptr, false, false);
00196   Registry.registerPass(*PI, true);
00197 }
00198 
00199 void llvm::initializeHexagonDAGToDAGISelPass(PassRegistry &Registry) {
00200   CALL_ONCE_INITIALIZATION(initializePassOnce)
00201 }
00202 
00203 
00204 // Intrinsics that return a a predicate.
00205 static unsigned doesIntrinsicReturnPredicate(unsigned ID)
00206 {
00207   switch (ID) {
00208     default:
00209       return 0;
00210     case Intrinsic::hexagon_C2_cmpeq:
00211     case Intrinsic::hexagon_C2_cmpgt:
00212     case Intrinsic::hexagon_C2_cmpgtu:
00213     case Intrinsic::hexagon_C2_cmpgtup:
00214     case Intrinsic::hexagon_C2_cmpgtp:
00215     case Intrinsic::hexagon_C2_cmpeqp:
00216     case Intrinsic::hexagon_C2_bitsset:
00217     case Intrinsic::hexagon_C2_bitsclr:
00218     case Intrinsic::hexagon_C2_cmpeqi:
00219     case Intrinsic::hexagon_C2_cmpgti:
00220     case Intrinsic::hexagon_C2_cmpgtui:
00221     case Intrinsic::hexagon_C2_cmpgei:
00222     case Intrinsic::hexagon_C2_cmpgeui:
00223     case Intrinsic::hexagon_C2_cmplt:
00224     case Intrinsic::hexagon_C2_cmpltu:
00225     case Intrinsic::hexagon_C2_bitsclri:
00226     case Intrinsic::hexagon_C2_and:
00227     case Intrinsic::hexagon_C2_or:
00228     case Intrinsic::hexagon_C2_xor:
00229     case Intrinsic::hexagon_C2_andn:
00230     case Intrinsic::hexagon_C2_not:
00231     case Intrinsic::hexagon_C2_orn:
00232     case Intrinsic::hexagon_C2_pxfer_map:
00233     case Intrinsic::hexagon_C2_any8:
00234     case Intrinsic::hexagon_C2_all8:
00235     case Intrinsic::hexagon_A2_vcmpbeq:
00236     case Intrinsic::hexagon_A2_vcmpbgtu:
00237     case Intrinsic::hexagon_A2_vcmpheq:
00238     case Intrinsic::hexagon_A2_vcmphgt:
00239     case Intrinsic::hexagon_A2_vcmphgtu:
00240     case Intrinsic::hexagon_A2_vcmpweq:
00241     case Intrinsic::hexagon_A2_vcmpwgt:
00242     case Intrinsic::hexagon_A2_vcmpwgtu:
00243     case Intrinsic::hexagon_C2_tfrrp:
00244     case Intrinsic::hexagon_S2_tstbit_i:
00245     case Intrinsic::hexagon_S2_tstbit_r:
00246       return 1;
00247   }
00248 }
00249 
00250 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
00251                                                            unsigned Opcode,
00252                                                            SDLoc dl) {
00253   SDValue Chain = LD->getChain();
00254   EVT LoadedVT = LD->getMemoryVT();
00255   SDValue Base = LD->getBasePtr();
00256   SDValue Offset = LD->getOffset();
00257   SDNode *OffsetNode = Offset.getNode();
00258   int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
00259 
00260   const HexagonInstrInfo &TII = *HST->getInstrInfo();
00261   if (TII.isValidAutoIncImm(LoadedVT, Val)) {
00262     SDValue TargetConst = CurDAG->getTargetConstant(Val, dl, MVT::i32);
00263     SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32,
00264                                               MVT::Other, Base, TargetConst,
00265                                               Chain);
00266     SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
00267                                               SDValue(Result_1, 0));
00268     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00269     MemOp[0] = LD->getMemOperand();
00270     cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00271     const SDValue Froms[] = { SDValue(LD, 0),
00272                               SDValue(LD, 1),
00273                               SDValue(LD, 2) };
00274     const SDValue Tos[]   = { SDValue(Result_2, 0),
00275                               SDValue(Result_1, 1),
00276                               SDValue(Result_1, 2) };
00277     ReplaceUses(Froms, Tos, 3);
00278     return Result_2;
00279   }
00280 
00281   SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
00282   SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
00283   SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Other,
00284                                             Base, TargetConst0, Chain);
00285   SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
00286                                             SDValue(Result_1, 0));
00287   SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
00288                                             Base, TargetConstVal,
00289                                             SDValue(Result_1, 1));
00290   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00291   MemOp[0] = LD->getMemOperand();
00292   cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00293   const SDValue Froms[] = { SDValue(LD, 0),
00294                             SDValue(LD, 1),
00295                             SDValue(LD, 2) };
00296   const SDValue Tos[]   = { SDValue(Result_2, 0),
00297                             SDValue(Result_3, 0),
00298                             SDValue(Result_1, 1) };
00299   ReplaceUses(Froms, Tos, 3);
00300   return Result_2;
00301 }
00302 
00303 
00304 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
00305                                                            unsigned Opcode,
00306                                                            SDLoc dl) {
00307   SDValue Chain = LD->getChain();
00308   EVT LoadedVT = LD->getMemoryVT();
00309   SDValue Base = LD->getBasePtr();
00310   SDValue Offset = LD->getOffset();
00311   SDNode *OffsetNode = Offset.getNode();
00312   int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
00313 
00314   const HexagonInstrInfo &TII = *HST->getInstrInfo();
00315   if (TII.isValidAutoIncImm(LoadedVT, Val)) {
00316     SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
00317     SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
00318     SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
00319                                               MVT::i32, MVT::Other, Base,
00320                                               TargetConstVal, Chain);
00321     SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A4_combineir, dl,
00322                                               MVT::i64, MVT::Other,
00323                                               TargetConst0,
00324                                               SDValue(Result_1,0));
00325     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00326     MemOp[0] = LD->getMemOperand();
00327     cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00328     const SDValue Froms[] = { SDValue(LD, 0),
00329                               SDValue(LD, 1),
00330                               SDValue(LD, 2) };
00331     const SDValue Tos[]   = { SDValue(Result_2, 0),
00332                               SDValue(Result_1, 1),
00333                               SDValue(Result_1, 2) };
00334     ReplaceUses(Froms, Tos, 3);
00335     return Result_2;
00336   }
00337 
00338   // Generate an indirect load.
00339   SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
00340   SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
00341   SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
00342                                             MVT::Other, Base, TargetConst0,
00343                                             Chain);
00344   SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A4_combineir, dl,
00345                                             MVT::i64, MVT::Other,
00346                                             TargetConst0,
00347                                             SDValue(Result_1,0));
00348   // Add offset to base.
00349   SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
00350                                             Base, TargetConstVal,
00351                                             SDValue(Result_1, 1));
00352   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00353   MemOp[0] = LD->getMemOperand();
00354   cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00355   const SDValue Froms[] = { SDValue(LD, 0),
00356                             SDValue(LD, 1),
00357                             SDValue(LD, 2) };
00358   const SDValue Tos[]   = { SDValue(Result_2, 0), // Load value.
00359                             SDValue(Result_3, 0), // New address.
00360                             SDValue(Result_1, 1) };
00361   ReplaceUses(Froms, Tos, 3);
00362   return Result_2;
00363 }
00364 
00365 
00366 SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
00367   SDValue Chain = LD->getChain();
00368   SDValue Base = LD->getBasePtr();
00369   SDValue Offset = LD->getOffset();
00370   SDNode *OffsetNode = Offset.getNode();
00371   // Get the constant value.
00372   int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
00373   EVT LoadedVT = LD->getMemoryVT();
00374   unsigned Opcode = 0;
00375 
00376   // Check for zero extended loads. Treat any-extend loads as zero extended
00377   // loads.
00378   ISD::LoadExtType ExtType = LD->getExtensionType();
00379   bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD);
00380 
00381   // Figure out the opcode.
00382   const HexagonInstrInfo &TII = *HST->getInstrInfo();
00383   if (LoadedVT == MVT::i64) {
00384     if (TII.isValidAutoIncImm(LoadedVT, Val))
00385       Opcode = Hexagon::L2_loadrd_pi;
00386     else
00387       Opcode = Hexagon::L2_loadrd_io;
00388   } else if (LoadedVT == MVT::i32) {
00389     if (TII.isValidAutoIncImm(LoadedVT, Val))
00390       Opcode = Hexagon::L2_loadri_pi;
00391     else
00392       Opcode = Hexagon::L2_loadri_io;
00393   } else if (LoadedVT == MVT::i16) {
00394     if (TII.isValidAutoIncImm(LoadedVT, Val))
00395       Opcode = IsZeroExt ? Hexagon::L2_loadruh_pi : Hexagon::L2_loadrh_pi;
00396     else
00397       Opcode = IsZeroExt ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io;
00398   } else if (LoadedVT == MVT::i8) {
00399     if (TII.isValidAutoIncImm(LoadedVT, Val))
00400       Opcode = IsZeroExt ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrb_pi;
00401     else
00402       Opcode = IsZeroExt ? Hexagon::L2_loadrub_io : Hexagon::L2_loadrb_io;
00403   } else
00404     llvm_unreachable("unknown memory type");
00405 
00406   // For zero extended i64 loads, we need to add combine instructions.
00407   if (LD->getValueType(0) == MVT::i64 && IsZeroExt)
00408     return SelectIndexedLoadZeroExtend64(LD, Opcode, dl);
00409   // Handle sign extended i64 loads.
00410   if (LD->getValueType(0) == MVT::i64 && ExtType == ISD::SEXTLOAD)
00411     return SelectIndexedLoadSignExtend64(LD, Opcode, dl);
00412 
00413   if (TII.isValidAutoIncImm(LoadedVT, Val)) {
00414     SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
00415     SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
00416                                             LD->getValueType(0),
00417                                             MVT::i32, MVT::Other, Base,
00418                                             TargetConstVal, Chain);
00419     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00420     MemOp[0] = LD->getMemOperand();
00421     cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
00422     const SDValue Froms[] = { SDValue(LD, 0),
00423                               SDValue(LD, 1),
00424                               SDValue(LD, 2)
00425     };
00426     const SDValue Tos[]   = { SDValue(Result, 0),
00427                               SDValue(Result, 1),
00428                               SDValue(Result, 2)
00429     };
00430     ReplaceUses(Froms, Tos, 3);
00431     return Result;
00432   } else {
00433     SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
00434     SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
00435     SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl,
00436                                               LD->getValueType(0),
00437                                               MVT::Other, Base, TargetConst0,
00438                                               Chain);
00439     SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
00440                                               Base, TargetConstVal,
00441                                               SDValue(Result_1, 1));
00442     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00443     MemOp[0] = LD->getMemOperand();
00444     cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00445     const SDValue Froms[] = { SDValue(LD, 0),
00446                               SDValue(LD, 1),
00447                               SDValue(LD, 2)
00448     };
00449     const SDValue Tos[]   = { SDValue(Result_1, 0),
00450                               SDValue(Result_2, 0),
00451                               SDValue(Result_1, 1)
00452     };
00453     ReplaceUses(Froms, Tos, 3);
00454     return Result_1;
00455   }
00456 }
00457 
00458 
00459 SDNode *HexagonDAGToDAGISel::SelectLoad(SDNode *N) {
00460   SDNode *result;
00461   SDLoc dl(N);
00462   LoadSDNode *LD = cast<LoadSDNode>(N);
00463   ISD::MemIndexedMode AM = LD->getAddressingMode();
00464 
00465   // Handle indexed loads.
00466   if (AM != ISD::UNINDEXED) {
00467     result = SelectIndexedLoad(LD, dl);
00468   } else {
00469     result = SelectCode(LD);
00470   }
00471 
00472   return result;
00473 }
00474 
00475 
00476 SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) {
00477   SDValue Chain = ST->getChain();
00478   SDValue Base = ST->getBasePtr();
00479   SDValue Offset = ST->getOffset();
00480   SDValue Value = ST->getValue();
00481   SDNode *OffsetNode = Offset.getNode();
00482   // Get the constant value.
00483   int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
00484   EVT StoredVT = ST->getMemoryVT();
00485   EVT ValueVT = Value.getValueType();
00486 
00487   // Offset value must be within representable range
00488   // and must have correct alignment properties.
00489   const HexagonInstrInfo &TII = *HST->getInstrInfo();
00490   if (TII.isValidAutoIncImm(StoredVT, Val)) {
00491     unsigned Opcode = 0;
00492 
00493     // Figure out the post inc version of opcode.
00494     if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_pi;
00495     else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_pi;
00496     else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_pi;
00497     else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_pi;
00498     else llvm_unreachable("unknown memory type");
00499 
00500     if (ST->isTruncatingStore() && ValueVT.getSizeInBits() == 64) {
00501       assert(StoredVT.getSizeInBits() < 64 && "Not a truncating store");
00502       Value = CurDAG->getTargetExtractSubreg(Hexagon::subreg_loreg,
00503                                              dl, MVT::i32, Value);
00504     }
00505     SDValue Ops[] = {Base, CurDAG->getTargetConstant(Val, dl, MVT::i32), Value,
00506                      Chain};
00507     // Build post increment store.
00508     SDNode* Result = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
00509                                             MVT::Other, Ops);
00510     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00511     MemOp[0] = ST->getMemOperand();
00512     cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
00513 
00514     ReplaceUses(ST, Result);
00515     ReplaceUses(SDValue(ST,1), SDValue(Result,1));
00516     return Result;
00517   }
00518 
00519   // Note: Order of operands matches the def of instruction:
00520   // def S2_storerd_io
00521   //   : STInst<(outs), (ins IntRegs:$base, imm:$offset, DoubleRegs:$src1), ...
00522   // and it differs for POST_ST* for instance.
00523   SDValue Ops[] = { Base, CurDAG->getTargetConstant(0, dl, MVT::i32), Value,
00524                     Chain};
00525   unsigned Opcode = 0;
00526 
00527   // Figure out the opcode.
00528   if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_io;
00529   else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_io;
00530   else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_io;
00531   else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_io;
00532   else llvm_unreachable("unknown memory type");
00533 
00534   // Build regular store.
00535   SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
00536   SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
00537   // Build splitted incriment instruction.
00538   SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
00539                                             Base,
00540                                             TargetConstVal,
00541                                             SDValue(Result_1, 0));
00542   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00543   MemOp[0] = ST->getMemOperand();
00544   cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00545 
00546   ReplaceUses(SDValue(ST,0), SDValue(Result_2,0));
00547   ReplaceUses(SDValue(ST,1), SDValue(Result_1,0));
00548   return Result_2;
00549 }
00550 
00551 SDNode *HexagonDAGToDAGISel::SelectStore(SDNode *N) {
00552   SDLoc dl(N);
00553   StoreSDNode *ST = cast<StoreSDNode>(N);
00554   ISD::MemIndexedMode AM = ST->getAddressingMode();
00555 
00556   // Handle indexed stores.
00557   if (AM != ISD::UNINDEXED) {
00558     return SelectIndexedStore(ST, dl);
00559   }
00560 
00561   return SelectCode(ST);
00562 }
00563 
00564 SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
00565   SDLoc dl(N);
00566 
00567   //
00568   // %conv.i = sext i32 %tmp1 to i64
00569   // %conv2.i = sext i32 %add to i64
00570   // %mul.i = mul nsw i64 %conv2.i, %conv.i
00571   //
00572   //   --- match with the following ---
00573   //
00574   // %mul.i = mpy (%tmp1, %add)
00575   //
00576 
00577   if (N->getValueType(0) == MVT::i64) {
00578     // Shifting a i64 signed multiply.
00579     SDValue MulOp0 = N->getOperand(0);
00580     SDValue MulOp1 = N->getOperand(1);
00581 
00582     SDValue OP0;
00583     SDValue OP1;
00584 
00585     // Handle sign_extend and sextload.
00586     if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
00587       SDValue Sext0 = MulOp0.getOperand(0);
00588       if (Sext0.getNode()->getValueType(0) != MVT::i32) {
00589         return SelectCode(N);
00590       }
00591 
00592       OP0 = Sext0;
00593     } else if (MulOp0.getOpcode() == ISD::LOAD) {
00594       LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
00595       if (LD->getMemoryVT() != MVT::i32 ||
00596           LD->getExtensionType() != ISD::SEXTLOAD ||
00597           LD->getAddressingMode() != ISD::UNINDEXED) {
00598         return SelectCode(N);
00599       }
00600 
00601       SDValue Chain = LD->getChain();
00602       SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
00603       OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
00604                                             MVT::Other,
00605                                             LD->getBasePtr(), TargetConst0,
00606                                             Chain), 0);
00607     } else {
00608       return SelectCode(N);
00609     }
00610 
00611     // Same goes for the second operand.
00612     if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
00613       SDValue Sext1 = MulOp1.getOperand(0);
00614       if (Sext1.getNode()->getValueType(0) != MVT::i32) {
00615         return SelectCode(N);
00616       }
00617 
00618       OP1 = Sext1;
00619     } else if (MulOp1.getOpcode() == ISD::LOAD) {
00620       LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
00621       if (LD->getMemoryVT() != MVT::i32 ||
00622           LD->getExtensionType() != ISD::SEXTLOAD ||
00623           LD->getAddressingMode() != ISD::UNINDEXED) {
00624         return SelectCode(N);
00625       }
00626 
00627       SDValue Chain = LD->getChain();
00628       SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
00629       OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
00630                                             MVT::Other,
00631                                             LD->getBasePtr(), TargetConst0,
00632                                             Chain), 0);
00633     } else {
00634       return SelectCode(N);
00635     }
00636 
00637     // Generate a mpy instruction.
00638     SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_dpmpyss_s0, dl, MVT::i64,
00639                                             OP0, OP1);
00640     ReplaceUses(N, Result);
00641     return Result;
00642   }
00643 
00644   return SelectCode(N);
00645 }
00646 
00647 SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
00648   SDLoc dl(N);
00649   if (N->getValueType(0) == MVT::i32) {
00650     SDValue Shl_0 = N->getOperand(0);
00651     SDValue Shl_1 = N->getOperand(1);
00652     // RHS is const.
00653     if (Shl_1.getOpcode() == ISD::Constant) {
00654       if (Shl_0.getOpcode() == ISD::MUL) {
00655         SDValue Mul_0 = Shl_0.getOperand(0); // Val
00656         SDValue Mul_1 = Shl_0.getOperand(1); // Const
00657         // RHS of mul is const.
00658         if (Mul_1.getOpcode() == ISD::Constant) {
00659           int32_t ShlConst =
00660             cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
00661           int32_t MulConst =
00662             cast<ConstantSDNode>(Mul_1.getNode())->getSExtValue();
00663           int32_t ValConst = MulConst << ShlConst;
00664           SDValue Val = CurDAG->getTargetConstant(ValConst, dl,
00665                                                   MVT::i32);
00666           if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val.getNode()))
00667             if (isInt<9>(CN->getSExtValue())) {
00668               SDNode* Result =
00669                 CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl,
00670                                        MVT::i32, Mul_0, Val);
00671               ReplaceUses(N, Result);
00672               return Result;
00673             }
00674 
00675         }
00676       } else if (Shl_0.getOpcode() == ISD::SUB) {
00677         SDValue Sub_0 = Shl_0.getOperand(0); // Const 0
00678         SDValue Sub_1 = Shl_0.getOperand(1); // Val
00679         if (Sub_0.getOpcode() == ISD::Constant) {
00680           int32_t SubConst =
00681             cast<ConstantSDNode>(Sub_0.getNode())->getSExtValue();
00682           if (SubConst == 0) {
00683             if (Sub_1.getOpcode() == ISD::SHL) {
00684               SDValue Shl2_0 = Sub_1.getOperand(0); // Val
00685               SDValue Shl2_1 = Sub_1.getOperand(1); // Const
00686               if (Shl2_1.getOpcode() == ISD::Constant) {
00687                 int32_t ShlConst =
00688                   cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
00689                 int32_t Shl2Const =
00690                   cast<ConstantSDNode>(Shl2_1.getNode())->getSExtValue();
00691                 int32_t ValConst = 1 << (ShlConst+Shl2Const);
00692                 SDValue Val = CurDAG->getTargetConstant(-ValConst, dl,
00693                                                         MVT::i32);
00694                 if (ConstantSDNode *CN =
00695                     dyn_cast<ConstantSDNode>(Val.getNode()))
00696                   if (isInt<9>(CN->getSExtValue())) {
00697                     SDNode* Result =
00698                       CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl, MVT::i32,
00699                                              Shl2_0, Val);
00700                     ReplaceUses(N, Result);
00701                     return Result;
00702                   }
00703               }
00704             }
00705           }
00706         }
00707       }
00708     }
00709   }
00710   return SelectCode(N);
00711 }
00712 
00713 
00714 //
00715 // If there is an zero_extend followed an intrinsic in DAG (this means - the
00716 // result of the intrinsic is predicate); convert the zero_extend to
00717 // transfer instruction.
00718 //
00719 // Zero extend -> transfer is lowered here. Otherwise, zero_extend will be
00720 // converted into a MUX as predicate registers defined as 1 bit in the
00721 // compiler. Architecture defines them as 8-bit registers.
00722 // We want to preserve all the lower 8-bits and, not just 1 LSB bit.
00723 //
00724 SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) {
00725   SDLoc dl(N);
00726 
00727   SDValue Op0 = N->getOperand(0);
00728   EVT OpVT = Op0.getValueType();
00729   unsigned OpBW = OpVT.getSizeInBits();
00730 
00731   // Special handling for zero-extending a vector of booleans.
00732   if (OpVT.isVector() && OpVT.getVectorElementType() == MVT::i1 && OpBW <= 64) {
00733     SDNode *Mask = CurDAG->getMachineNode(Hexagon::C2_mask, dl, MVT::i64, Op0);
00734     unsigned NE = OpVT.getVectorNumElements();
00735     EVT ExVT = N->getValueType(0);
00736     unsigned ES = ExVT.getVectorElementType().getSizeInBits();
00737     uint64_t MV = 0, Bit = 1;
00738     for (unsigned i = 0; i < NE; ++i) {
00739       MV |= Bit;
00740       Bit <<= ES;
00741     }
00742     SDValue Ones = CurDAG->getTargetConstant(MV, dl, MVT::i64);
00743     SDNode *OnesReg = CurDAG->getMachineNode(Hexagon::CONST64_Int_Real, dl,
00744                                              MVT::i64, Ones);
00745     if (ExVT.getSizeInBits() == 32) {
00746       SDNode *And = CurDAG->getMachineNode(Hexagon::A2_andp, dl, MVT::i64,
00747                                            SDValue(Mask,0), SDValue(OnesReg,0));
00748       SDValue SubR = CurDAG->getTargetConstant(Hexagon::subreg_loreg, dl,
00749                                                MVT::i32);
00750       return CurDAG->getMachineNode(Hexagon::EXTRACT_SUBREG, dl, ExVT,
00751                                     SDValue(And,0), SubR);
00752     }
00753     return CurDAG->getMachineNode(Hexagon::A2_andp, dl, ExVT,
00754                                   SDValue(Mask,0), SDValue(OnesReg,0));
00755   }
00756 
00757   SDNode *IsIntrinsic = N->getOperand(0).getNode();
00758   if ((IsIntrinsic->getOpcode() == ISD::INTRINSIC_WO_CHAIN)) {
00759     unsigned ID =
00760       cast<ConstantSDNode>(IsIntrinsic->getOperand(0))->getZExtValue();
00761     if (doesIntrinsicReturnPredicate(ID)) {
00762       // Now we need to differentiate target data types.
00763       if (N->getValueType(0) == MVT::i64) {
00764         // Convert the zero_extend to Rs = Pd followed by A2_combinew(0,Rs).
00765         SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
00766         SDNode *Result_1 = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
00767                                                   MVT::i32,
00768                                                   SDValue(IsIntrinsic, 0));
00769         SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl,
00770                                                   MVT::i32,
00771                                                   TargetConst0);
00772         SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl,
00773                                                   MVT::i64, MVT::Other,
00774                                                   SDValue(Result_2, 0),
00775                                                   SDValue(Result_1, 0));
00776         ReplaceUses(N, Result_3);
00777         return Result_3;
00778       }
00779       if (N->getValueType(0) == MVT::i32) {
00780         // Convert the zero_extend to Rs = Pd
00781         SDNode* RsPd = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
00782                                               MVT::i32,
00783                                               SDValue(IsIntrinsic, 0));
00784         ReplaceUses(N, RsPd);
00785         return RsPd;
00786       }
00787       llvm_unreachable("Unexpected value type");
00788     }
00789   }
00790   return SelectCode(N);
00791 }
00792 
00793 //
00794 // Checking for intrinsics circular load/store, and bitreverse load/store
00795 // instrisics in order to select the correct lowered operation.
00796 //
00797 SDNode *HexagonDAGToDAGISel::SelectIntrinsicWChain(SDNode *N) {
00798   unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
00799   if (IntNo == Intrinsic::hexagon_circ_ldd  ||
00800       IntNo == Intrinsic::hexagon_circ_ldw  ||
00801       IntNo == Intrinsic::hexagon_circ_lduh ||
00802       IntNo == Intrinsic::hexagon_circ_ldh  ||
00803       IntNo == Intrinsic::hexagon_circ_ldub ||
00804       IntNo == Intrinsic::hexagon_circ_ldb) {
00805     SDLoc dl(N);
00806     SDValue Chain = N->getOperand(0);
00807     SDValue Base = N->getOperand(2);
00808     SDValue Load = N->getOperand(3);
00809     SDValue ModifierExpr = N->getOperand(4);
00810     SDValue Offset = N->getOperand(5);
00811 
00812     // We need to add the rerurn type for the load.  This intrinsic has
00813     // two return types, one for the load and one for the post-increment.
00814     // Only the *_ld instructions push the extra return type, and bump the
00815     // result node operand number correspondingly.
00816     std::vector<EVT> ResTys;
00817     unsigned opc;
00818     unsigned memsize, align;
00819     MVT MvtSize = MVT::i32;
00820 
00821     if (IntNo == Intrinsic::hexagon_circ_ldd) {
00822       ResTys.push_back(MVT::i32);
00823       ResTys.push_back(MVT::i64);
00824       opc = Hexagon::L2_loadrd_pci_pseudo;
00825       memsize = 8;
00826       align = 8;
00827     } else if (IntNo == Intrinsic::hexagon_circ_ldw) {
00828       ResTys.push_back(MVT::i32);
00829       ResTys.push_back(MVT::i32);
00830       opc = Hexagon::L2_loadri_pci_pseudo;
00831       memsize = 4;
00832       align = 4;
00833     } else if (IntNo == Intrinsic::hexagon_circ_ldh) {
00834       ResTys.push_back(MVT::i32);
00835       ResTys.push_back(MVT::i32);
00836       opc = Hexagon::L2_loadrh_pci_pseudo;
00837       memsize = 2;
00838       align = 2;
00839       MvtSize = MVT::i16;
00840     } else if (IntNo == Intrinsic::hexagon_circ_lduh) {
00841       ResTys.push_back(MVT::i32);
00842       ResTys.push_back(MVT::i32);
00843       opc = Hexagon::L2_loadruh_pci_pseudo;
00844       memsize = 2;
00845       align = 2;
00846       MvtSize = MVT::i16;
00847     } else if (IntNo == Intrinsic::hexagon_circ_ldb) {
00848       ResTys.push_back(MVT::i32);
00849       ResTys.push_back(MVT::i32);
00850       opc = Hexagon::L2_loadrb_pci_pseudo;
00851       memsize = 1;
00852       align = 1;
00853       MvtSize = MVT::i8;
00854     } else if (IntNo == Intrinsic::hexagon_circ_ldub) {
00855       ResTys.push_back(MVT::i32);
00856       ResTys.push_back(MVT::i32);
00857       opc = Hexagon::L2_loadrub_pci_pseudo;
00858       memsize = 1;
00859       align = 1;
00860       MvtSize = MVT::i8;
00861     } else
00862       llvm_unreachable("no opc");
00863 
00864     ResTys.push_back(MVT::Other);
00865 
00866     // Copy over the arguments, which are the same mostly.
00867     SmallVector<SDValue, 5> Ops;
00868     Ops.push_back(Base);
00869     Ops.push_back(Load);
00870     Ops.push_back(ModifierExpr);
00871     int32_t Val = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
00872     Ops.push_back(CurDAG->getTargetConstant(Val, dl, MVT::i32));
00873     Ops.push_back(Chain);
00874     SDNode* Result = CurDAG->getMachineNode(opc, dl, ResTys, Ops);
00875 
00876     SDValue ST;
00877     MachineMemOperand *Mem =
00878       MF->getMachineMemOperand(MachinePointerInfo(),
00879                                MachineMemOperand::MOStore, memsize, align);
00880     if (MvtSize != MVT::i32)
00881       ST = CurDAG->getTruncStore(Chain, dl, SDValue(Result, 1), Load,
00882                                  MvtSize, Mem);
00883     else
00884       ST = CurDAG->getStore(Chain, dl, SDValue(Result, 1), Load, Mem);
00885 
00886     SDNode* Store = SelectStore(ST.getNode());
00887 
00888     const SDValue Froms[] = { SDValue(N, 0),
00889                               SDValue(N, 1) };
00890     const SDValue Tos[]   = { SDValue(Result, 0),
00891                               SDValue(Store, 0) };
00892     ReplaceUses(Froms, Tos, 2);
00893     return Result;
00894   }
00895 
00896   if (IntNo == Intrinsic::hexagon_brev_ldd  ||
00897       IntNo == Intrinsic::hexagon_brev_ldw  ||
00898       IntNo == Intrinsic::hexagon_brev_ldh  ||
00899       IntNo == Intrinsic::hexagon_brev_lduh ||
00900       IntNo == Intrinsic::hexagon_brev_ldb  ||
00901       IntNo == Intrinsic::hexagon_brev_ldub) {
00902     SDLoc dl(N);
00903     SDValue Chain = N->getOperand(0);
00904     SDValue Base = N->getOperand(2);
00905     SDValue Load = N->getOperand(3);
00906     SDValue ModifierExpr = N->getOperand(4);
00907 
00908     // We need to add the rerurn type for the load.  This intrinsic has
00909     // two return types, one for the load and one for the post-increment.
00910     std::vector<EVT> ResTys;
00911     unsigned opc;
00912     unsigned memsize, align;
00913     MVT MvtSize = MVT::i32;
00914 
00915     if (IntNo == Intrinsic::hexagon_brev_ldd) {
00916       ResTys.push_back(MVT::i32);
00917       ResTys.push_back(MVT::i64);
00918       opc = Hexagon::L2_loadrd_pbr_pseudo;
00919       memsize = 8;
00920       align = 8;
00921     } else if (IntNo == Intrinsic::hexagon_brev_ldw) {
00922       ResTys.push_back(MVT::i32);
00923       ResTys.push_back(MVT::i32);
00924       opc = Hexagon::L2_loadri_pbr_pseudo;
00925       memsize = 4;
00926       align = 4;
00927     } else if (IntNo == Intrinsic::hexagon_brev_ldh) {
00928       ResTys.push_back(MVT::i32);
00929       ResTys.push_back(MVT::i32);
00930       opc = Hexagon::L2_loadrh_pbr_pseudo;
00931       memsize = 2;
00932       align = 2;
00933       MvtSize = MVT::i16;
00934     } else if (IntNo == Intrinsic::hexagon_brev_lduh) {
00935       ResTys.push_back(MVT::i32);
00936       ResTys.push_back(MVT::i32);
00937       opc = Hexagon::L2_loadruh_pbr_pseudo;
00938       memsize = 2;
00939       align = 2;
00940       MvtSize = MVT::i16;
00941     } else if (IntNo == Intrinsic::hexagon_brev_ldb) {
00942       ResTys.push_back(MVT::i32);
00943       ResTys.push_back(MVT::i32);
00944       opc = Hexagon::L2_loadrb_pbr_pseudo;
00945       memsize = 1;
00946       align = 1;
00947       MvtSize = MVT::i8;
00948     } else if (IntNo == Intrinsic::hexagon_brev_ldub) {
00949       ResTys.push_back(MVT::i32);
00950       ResTys.push_back(MVT::i32);
00951       opc = Hexagon::L2_loadrub_pbr_pseudo;
00952       memsize = 1;
00953       align = 1;
00954       MvtSize = MVT::i8;
00955     } else
00956       llvm_unreachable("no opc");
00957 
00958     ResTys.push_back(MVT::Other);
00959 
00960     // Copy over the arguments, which are the same mostly.
00961     SmallVector<SDValue, 4> Ops;
00962     Ops.push_back(Base);
00963     Ops.push_back(Load);
00964     Ops.push_back(ModifierExpr);
00965     Ops.push_back(Chain);
00966     SDNode* Result = CurDAG->getMachineNode(opc, dl, ResTys, Ops);
00967     SDValue ST;
00968     MachineMemOperand *Mem =
00969       MF->getMachineMemOperand(MachinePointerInfo(),
00970                                MachineMemOperand::MOStore, memsize, align);
00971     if (MvtSize != MVT::i32)
00972       ST = CurDAG->getTruncStore(Chain, dl, SDValue(Result, 1), Load,
00973                                  MvtSize, Mem);
00974     else
00975       ST = CurDAG->getStore(Chain, dl, SDValue(Result, 1), Load, Mem);
00976 
00977     SDNode* Store = SelectStore(ST.getNode());
00978 
00979     const SDValue Froms[] = { SDValue(N, 0),
00980                               SDValue(N, 1) };
00981     const SDValue Tos[]   = { SDValue(Result, 0),
00982                               SDValue(Store, 0) };
00983     ReplaceUses(Froms, Tos, 2);
00984     return Result;
00985   }
00986 
00987   return SelectCode(N);
00988 }
00989 
00990 //
00991 // Checking for intrinsics which have predicate registers as operand(s)
00992 // and lowering to the actual intrinsic.
00993 //
00994 SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
00995   unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
00996   unsigned Bits;
00997   switch (IID) {
00998   case Intrinsic::hexagon_S2_vsplatrb:
00999     Bits = 8;
01000     break;
01001   case Intrinsic::hexagon_S2_vsplatrh:
01002     Bits = 16;
01003     break;
01004   default:
01005     return SelectCode(N);
01006   }
01007 
01008   SDValue const &V = N->getOperand(1);
01009   SDValue U;
01010   if (isValueExtension(V, Bits, U)) {
01011     SDValue R = CurDAG->getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
01012       N->getOperand(0), U);
01013     return SelectCode(R.getNode());
01014   }
01015   return SelectCode(N);
01016 }
01017 
01018 //
01019 // Map floating point constant values.
01020 //
01021 SDNode *HexagonDAGToDAGISel::SelectConstantFP(SDNode *N) {
01022   SDLoc dl(N);
01023   ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
01024   APFloat APF = CN->getValueAPF();
01025   if (N->getValueType(0) == MVT::f32) {
01026     return CurDAG->getMachineNode(Hexagon::TFRI_f, dl, MVT::f32,
01027               CurDAG->getTargetConstantFP(APF.convertToFloat(), dl, MVT::f32));
01028   }
01029   else if (N->getValueType(0) == MVT::f64) {
01030     return CurDAG->getMachineNode(Hexagon::CONST64_Float_Real, dl, MVT::f64,
01031               CurDAG->getTargetConstantFP(APF.convertToDouble(), dl, MVT::f64));
01032   }
01033 
01034   return SelectCode(N);
01035 }
01036 
01037 //
01038 // Map predicate true (encoded as -1 in LLVM) to a XOR.
01039 //
01040 SDNode *HexagonDAGToDAGISel::SelectConstant(SDNode *N) {
01041   SDLoc dl(N);
01042   if (N->getValueType(0) == MVT::i1) {
01043     SDNode* Result = 0;
01044     int32_t Val = cast<ConstantSDNode>(N)->getSExtValue();
01045     if (Val == -1) {
01046       Result = CurDAG->getMachineNode(Hexagon::TFR_PdTrue, dl, MVT::i1);
01047     } else if (Val == 0) {
01048       Result = CurDAG->getMachineNode(Hexagon::TFR_PdFalse, dl, MVT::i1);
01049     }
01050     if (Result) {
01051       ReplaceUses(N, Result);
01052       return Result;
01053     }
01054   }
01055 
01056   return SelectCode(N);
01057 }
01058 
01059 
01060 //
01061 // Map add followed by a asr -> asr +=.
01062 //
01063 SDNode *HexagonDAGToDAGISel::SelectAdd(SDNode *N) {
01064   SDLoc dl(N);
01065   if (N->getValueType(0) != MVT::i32) {
01066     return SelectCode(N);
01067   }
01068   // Identify nodes of the form: add(asr(...)).
01069   SDNode* Src1 = N->getOperand(0).getNode();
01070   if (Src1->getOpcode() != ISD::SRA || !Src1->hasOneUse()
01071       || Src1->getValueType(0) != MVT::i32) {
01072     return SelectCode(N);
01073   }
01074 
01075   // Build Rd = Rd' + asr(Rs, Rt). The machine constraints will ensure that
01076   // Rd and Rd' are assigned to the same register
01077   SDNode* Result = CurDAG->getMachineNode(Hexagon::S2_asr_r_r_acc, dl, MVT::i32,
01078                                           N->getOperand(1),
01079                                           Src1->getOperand(0),
01080                                           Src1->getOperand(1));
01081   ReplaceUses(N, Result);
01082 
01083   return Result;
01084 }
01085 
01086 //
01087 // Map the following, where possible.
01088 // AND/FABS -> clrbit
01089 // OR -> setbit
01090 // XOR/FNEG ->toggle_bit.
01091 //
01092 SDNode *HexagonDAGToDAGISel::SelectBitOp(SDNode *N) {
01093   SDLoc dl(N);
01094   EVT ValueVT = N->getValueType(0);
01095 
01096   // We handle only 32 and 64-bit bit ops.
01097   if (!(ValueVT == MVT::i32 || ValueVT == MVT::i64 ||
01098         ValueVT == MVT::f32 || ValueVT == MVT::f64))
01099     return SelectCode(N);
01100 
01101   // We handly only fabs and fneg for V5.
01102   unsigned Opc = N->getOpcode();
01103   if ((Opc == ISD::FABS || Opc == ISD::FNEG) && !HST->hasV5TOps())
01104     return SelectCode(N);
01105 
01106   int64_t Val = 0;
01107   if (Opc != ISD::FABS && Opc != ISD::FNEG) {
01108     if (N->getOperand(1).getOpcode() == ISD::Constant)
01109       Val = cast<ConstantSDNode>((N)->getOperand(1))->getSExtValue();
01110     else
01111      return SelectCode(N);
01112   }
01113 
01114   if (Opc == ISD::AND) {
01115     if (((ValueVT == MVT::i32) &&
01116                   (!((Val & 0x80000000) || (Val & 0x7fffffff)))) ||
01117         ((ValueVT == MVT::i64) &&
01118                   (!((Val & 0x8000000000000000) || (Val & 0x7fffffff)))))
01119       // If it's simple AND, do the normal op.
01120       return SelectCode(N);
01121     else
01122       Val = ~Val;
01123   }
01124 
01125   // If OR or AND is being fed by shl, srl and, sra don't do this change,
01126   // because Hexagon provide |= &= on shl, srl, and sra.
01127   // Traverse the DAG to see if there is shl, srl and sra.
01128   if (Opc == ISD::OR || Opc == ISD::AND) {
01129     switch (N->getOperand(0)->getOpcode()) {
01130       default: break;
01131       case ISD::SRA:
01132       case ISD::SRL:
01133       case ISD::SHL:
01134         return SelectCode(N);
01135     }
01136   }
01137 
01138   // Make sure it's power of 2.
01139   unsigned bitpos = 0;
01140   if (Opc != ISD::FABS && Opc != ISD::FNEG) {
01141     if (((ValueVT == MVT::i32) && !isPowerOf2_32(Val)) ||
01142         ((ValueVT == MVT::i64) && !isPowerOf2_64(Val)))
01143       return SelectCode(N);
01144 
01145     // Get the bit position.
01146     bitpos = countTrailingZeros(uint64_t(Val));
01147   } else {
01148     // For fabs and fneg, it's always the 31st bit.
01149     bitpos = 31;
01150   }
01151 
01152   unsigned BitOpc = 0;
01153   // Set the right opcode for bitwise operations.
01154   switch(Opc) {
01155     default: llvm_unreachable("Only bit-wise/abs/neg operations are allowed.");
01156     case ISD::AND:
01157     case ISD::FABS:
01158       BitOpc = Hexagon::S2_clrbit_i;
01159       break;
01160     case ISD::OR:
01161       BitOpc = Hexagon::S2_setbit_i;
01162       break;
01163     case ISD::XOR:
01164     case ISD::FNEG:
01165       BitOpc = Hexagon::S2_togglebit_i;
01166       break;
01167   }
01168 
01169   SDNode *Result;
01170   // Get the right SDVal for the opcode.
01171   SDValue SDVal = CurDAG->getTargetConstant(bitpos, dl, MVT::i32);
01172 
01173   if (ValueVT == MVT::i32 || ValueVT == MVT::f32) {
01174     Result = CurDAG->getMachineNode(BitOpc, dl, ValueVT,
01175                                     N->getOperand(0), SDVal);
01176   } else {
01177     // 64-bit gymnastic to use REG_SEQUENCE. But it's worth it.
01178     EVT SubValueVT;
01179     if (ValueVT == MVT::i64)
01180       SubValueVT = MVT::i32;
01181     else
01182       SubValueVT = MVT::f32;
01183 
01184     SDNode *Reg = N->getOperand(0).getNode();
01185     SDValue RegClass = CurDAG->getTargetConstant(Hexagon::DoubleRegsRegClassID,
01186                                                  dl, MVT::i64);
01187 
01188     SDValue SubregHiIdx = CurDAG->getTargetConstant(Hexagon::subreg_hireg, dl,
01189                                                     MVT::i32);
01190     SDValue SubregLoIdx = CurDAG->getTargetConstant(Hexagon::subreg_loreg, dl,
01191                                                     MVT::i32);
01192 
01193     SDValue SubregHI = CurDAG->getTargetExtractSubreg(Hexagon::subreg_hireg, dl,
01194                                                     MVT::i32, SDValue(Reg, 0));
01195 
01196     SDValue SubregLO = CurDAG->getTargetExtractSubreg(Hexagon::subreg_loreg, dl,
01197                                                     MVT::i32, SDValue(Reg, 0));
01198 
01199     // Clear/set/toggle hi or lo registers depending on the bit position.
01200     if (SubValueVT != MVT::f32 && bitpos < 32) {
01201       SDNode *Result0 = CurDAG->getMachineNode(BitOpc, dl, SubValueVT,
01202                                                SubregLO, SDVal);
01203       const SDValue Ops[] = { RegClass, SubregHI, SubregHiIdx,
01204                               SDValue(Result0, 0), SubregLoIdx };
01205       Result = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
01206                                       dl, ValueVT, Ops);
01207     } else {
01208       if (Opc != ISD::FABS && Opc != ISD::FNEG)
01209         SDVal = CurDAG->getTargetConstant(bitpos - 32, dl, MVT::i32);
01210       SDNode *Result0 = CurDAG->getMachineNode(BitOpc, dl, SubValueVT,
01211                                                SubregHI, SDVal);
01212       const SDValue Ops[] = { RegClass, SDValue(Result0, 0), SubregHiIdx,
01213                               SubregLO, SubregLoIdx };
01214       Result = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
01215                                       dl, ValueVT, Ops);
01216     }
01217   }
01218 
01219   ReplaceUses(N, Result);
01220   return Result;
01221 }
01222 
01223 
01224 SDNode *HexagonDAGToDAGISel::SelectFrameIndex(SDNode *N) {
01225   MachineFrameInfo *MFI = MF->getFrameInfo();
01226   const HexagonFrameLowering *HFI = HST->getFrameLowering();
01227   int FX = cast<FrameIndexSDNode>(N)->getIndex();
01228   unsigned StkA = HFI->getStackAlignment();
01229   unsigned MaxA = MFI->getMaxAlignment();
01230   SDValue FI = CurDAG->getTargetFrameIndex(FX, MVT::i32);
01231   SDLoc DL(N);
01232   SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
01233   SDNode *R = 0;
01234 
01235   // Use TFR_FI when:
01236   // - the object is fixed, or
01237   // - there are no objects with higher-than-default alignment, or
01238   // - there are no dynamically allocated objects.
01239   // Otherwise, use TFR_FIA.
01240   if (FX < 0 || MaxA <= StkA || !MFI->hasVarSizedObjects()) {
01241     R = CurDAG->getMachineNode(Hexagon::TFR_FI, DL, MVT::i32, FI, Zero);
01242   } else {
01243     auto &HMFI = *MF->getInfo<HexagonMachineFunctionInfo>();
01244     unsigned AR = HMFI.getStackAlignBaseVReg();
01245     SDValue CH = CurDAG->getEntryNode();
01246     SDValue Ops[] = { CurDAG->getCopyFromReg(CH, DL, AR, MVT::i32), FI, Zero };
01247     R = CurDAG->getMachineNode(Hexagon::TFR_FIA, DL, MVT::i32, Ops);
01248   }
01249 
01250   if (N->getHasDebugValue())
01251     CurDAG->TransferDbgValues(SDValue(N, 0), SDValue(R, 0));
01252   return R;
01253 }
01254 
01255 
01256 SDNode *HexagonDAGToDAGISel::Select(SDNode *N) {
01257   if (N->isMachineOpcode()) {
01258     N->setNodeId(-1);
01259     return nullptr;   // Already selected.
01260   }
01261 
01262   switch (N->getOpcode()) {
01263   case ISD::Constant:
01264     return SelectConstant(N);
01265 
01266   case ISD::ConstantFP:
01267     return SelectConstantFP(N);
01268 
01269   case ISD::FrameIndex:
01270     return SelectFrameIndex(N);
01271 
01272   case ISD::ADD:
01273     return SelectAdd(N);
01274 
01275   case ISD::SHL:
01276     return SelectSHL(N);
01277 
01278   case ISD::LOAD:
01279     return SelectLoad(N);
01280 
01281   case ISD::STORE:
01282     return SelectStore(N);
01283 
01284   case ISD::MUL:
01285     return SelectMul(N);
01286 
01287   case ISD::AND:
01288   case ISD::OR:
01289   case ISD::XOR:
01290   case ISD::FABS:
01291   case ISD::FNEG:
01292     return SelectBitOp(N);
01293 
01294   case ISD::ZERO_EXTEND:
01295     return SelectZeroExtend(N);
01296 
01297   case ISD::INTRINSIC_W_CHAIN:
01298     return SelectIntrinsicWChain(N);
01299 
01300   case ISD::INTRINSIC_WO_CHAIN:
01301     return SelectIntrinsicWOChain(N);
01302   }
01303 
01304   return SelectCode(N);
01305 }
01306 
01307 bool HexagonDAGToDAGISel::
01308 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
01309                              std::vector<SDValue> &OutOps) {
01310   SDValue Inp = Op, Res;
01311 
01312   switch (ConstraintID) {
01313   default:
01314     return true;
01315   case InlineAsm::Constraint_i:
01316   case InlineAsm::Constraint_o: // Offsetable.
01317   case InlineAsm::Constraint_v: // Not offsetable.
01318   case InlineAsm::Constraint_m: // Memory.
01319     if (SelectAddrFI(Inp, Res))
01320       OutOps.push_back(Res);
01321     else
01322       OutOps.push_back(Inp);
01323     break;
01324   }
01325 
01326   OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
01327   return false;
01328 }
01329 
01330 void HexagonDAGToDAGISel::PreprocessISelDAG() {
01331   SelectionDAG &DAG = *CurDAG;
01332   std::vector<SDNode*> Nodes;
01333   for (auto I = DAG.allnodes_begin(), E = DAG.allnodes_end(); I != E; ++I)
01334     Nodes.push_back(I);
01335 
01336   // Simplify: (or (select c x 0) z)  ->  (select c (or x z) z)
01337   //           (or (select c 0 y) z)  ->  (select c z (or y z))
01338   // This may not be the right thing for all targets, so do it here.
01339   for (auto I: Nodes) {
01340     if (I->getOpcode() != ISD::OR)
01341       continue;
01342 
01343     auto IsZero = [] (const SDValue &V) -> bool {
01344       if (ConstantSDNode *SC = dyn_cast<ConstantSDNode>(V.getNode()))
01345         return SC->isNullValue();
01346       return false;
01347     };
01348     auto IsSelect0 = [IsZero] (const SDValue &Op) -> bool {
01349       if (Op.getOpcode() != ISD::SELECT)
01350         return false;
01351       return IsZero(Op.getOperand(1))  || IsZero(Op.getOperand(2));
01352     };
01353 
01354     SDValue N0 = I->getOperand(0), N1 = I->getOperand(1);
01355     EVT VT = I->getValueType(0);
01356     bool SelN0 = IsSelect0(N0);
01357     SDValue SOp = SelN0 ? N0 : N1;
01358     SDValue VOp = SelN0 ? N1 : N0;
01359 
01360     if (SOp.getOpcode() == ISD::SELECT && SOp.getNode()->hasOneUse()) {
01361       SDValue SC = SOp.getOperand(0);
01362       SDValue SX = SOp.getOperand(1);
01363       SDValue SY = SOp.getOperand(2);
01364       SDLoc DLS = SOp;
01365       if (IsZero(SY)) {
01366         SDValue NewOr = DAG.getNode(ISD::OR, DLS, VT, SX, VOp);
01367         SDValue NewSel = DAG.getNode(ISD::SELECT, DLS, VT, SC, NewOr, VOp);
01368         DAG.ReplaceAllUsesWith(I, NewSel.getNode());
01369       } else if (IsZero(SX)) {
01370         SDValue NewOr = DAG.getNode(ISD::OR, DLS, VT, SY, VOp);
01371         SDValue NewSel = DAG.getNode(ISD::SELECT, DLS, VT, SC, VOp, NewOr);
01372         DAG.ReplaceAllUsesWith(I, NewSel.getNode());
01373       }
01374     }
01375   }
01376 }
01377 
01378 void HexagonDAGToDAGISel::EmitFunctionEntryCode() {
01379   auto &HST = static_cast<const HexagonSubtarget&>(MF->getSubtarget());
01380   auto &HFI = *HST.getFrameLowering();
01381   if (!HFI.needsAligna(*MF))
01382     return;
01383 
01384   MachineFrameInfo *MFI = MF->getFrameInfo();
01385   MachineBasicBlock *EntryBB = MF->begin();
01386   unsigned AR = FuncInfo->CreateReg(MVT::i32);
01387   unsigned MaxA = MFI->getMaxAlignment();
01388   auto &HII = *HST.getInstrInfo();
01389   BuildMI(EntryBB, DebugLoc(), HII.get(Hexagon::ALIGNA), AR)
01390       .addImm(MaxA);
01391   MF->getInfo<HexagonMachineFunctionInfo>()->setStackAlignBaseVReg(AR);
01392 }
01393 
01394 // Match a frame index that can be used in an addressing mode.
01395 bool HexagonDAGToDAGISel::SelectAddrFI(SDValue& N, SDValue &R) {
01396   if (N.getOpcode() != ISD::FrameIndex)
01397     return false;
01398   auto &HFI = *HST->getFrameLowering();
01399   MachineFrameInfo *MFI = MF->getFrameInfo();
01400   int FX = cast<FrameIndexSDNode>(N)->getIndex();
01401   if (!MFI->isFixedObjectIndex(FX) && HFI.needsAligna(*MF))
01402     return false;
01403   R = CurDAG->getTargetFrameIndex(FX, MVT::i32);
01404   return true;
01405 }
01406 
01407 inline bool HexagonDAGToDAGISel::SelectAddrGA(SDValue &N, SDValue &R) {
01408   return SelectGlobalAddress(N, R, false);
01409 }
01410 
01411 inline bool HexagonDAGToDAGISel::SelectAddrGP(SDValue &N, SDValue &R) {
01412   return SelectGlobalAddress(N, R, true);
01413 }
01414 
01415 bool HexagonDAGToDAGISel::SelectGlobalAddress(SDValue &N, SDValue &R,
01416                                               bool UseGP) {
01417   switch (N.getOpcode()) {
01418   case ISD::ADD: {
01419     SDValue N0 = N.getOperand(0);
01420     SDValue N1 = N.getOperand(1);
01421     unsigned GAOpc = N0.getOpcode();
01422     if (UseGP && GAOpc != HexagonISD::CONST32_GP)
01423       return false;
01424     if (!UseGP && GAOpc != HexagonISD::CONST32)
01425       return false;
01426     if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N1)) {
01427       SDValue Addr = N0.getOperand(0);
01428       if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Addr)) {
01429         if (GA->getOpcode() == ISD::TargetGlobalAddress) {
01430           uint64_t NewOff = GA->getOffset() + (uint64_t)Const->getSExtValue();
01431           R = CurDAG->getTargetGlobalAddress(GA->getGlobal(), SDLoc(Const),
01432                                              N.getValueType(), NewOff);
01433           return true;
01434         }
01435       }
01436     }
01437     break;
01438   }
01439   case HexagonISD::CONST32:
01440     // The operand(0) of CONST32 is TargetGlobalAddress, which is what we
01441     // want in the instruction.
01442     if (!UseGP)
01443       R = N.getOperand(0);
01444     return !UseGP;
01445   case HexagonISD::CONST32_GP:
01446     if (UseGP)
01447       R = N.getOperand(0);
01448     return UseGP;
01449   default:
01450     return false;
01451   }
01452 
01453   return false;
01454 }
01455 
01456 bool HexagonDAGToDAGISel::isValueExtension(const SDValue &Val,
01457       unsigned FromBits, SDValue &Src) {
01458   unsigned Opc = Val.getOpcode();
01459   switch (Opc) {
01460   case ISD::SIGN_EXTEND:
01461   case ISD::ZERO_EXTEND:
01462   case ISD::ANY_EXTEND: {
01463     SDValue const &Op0 = Val.getOperand(0);
01464     EVT T = Op0.getValueType();
01465     if (T.isInteger() && T.getSizeInBits() == FromBits) {
01466       Src = Op0;
01467       return true;
01468     }
01469     break;
01470   }
01471   case ISD::SIGN_EXTEND_INREG:
01472   case ISD::AssertSext:
01473   case ISD::AssertZext:
01474     if (Val.getOperand(0).getValueType().isInteger()) {
01475       VTSDNode *T = cast<VTSDNode>(Val.getOperand(1));
01476       if (T->getVT().getSizeInBits() == FromBits) {
01477         Src = Val.getOperand(0);
01478         return true;
01479       }
01480     }
01481     break;
01482   case ISD::AND: {
01483     // Check if this is an AND with "FromBits" of lower bits set to 1.
01484     uint64_t FromMask = (1 << FromBits) - 1;
01485     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(0))) {
01486       if (C->getZExtValue() == FromMask) {
01487         Src = Val.getOperand(1);
01488         return true;
01489       }
01490     }
01491     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(1))) {
01492       if (C->getZExtValue() == FromMask) {
01493         Src = Val.getOperand(0);
01494         return true;
01495       }
01496     }
01497     break;
01498   }
01499   case ISD::OR:
01500   case ISD::XOR: {
01501     // OR/XOR with the lower "FromBits" bits set to 0.
01502     uint64_t FromMask = (1 << FromBits) - 1;
01503     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(0))) {
01504       if ((C->getZExtValue() & FromMask) == 0) {
01505         Src = Val.getOperand(1);
01506         return true;
01507       }
01508     }
01509     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(1))) {
01510       if ((C->getZExtValue() & FromMask) == 0) {
01511         Src = Val.getOperand(0);
01512         return true;
01513       }
01514     }
01515   }
01516   default:
01517     break;
01518   }
01519   return false;
01520 }