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HexagonISelDAGToDAG.cpp
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00001 //===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file defines an instruction selector for the Hexagon target.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "Hexagon.h"
00015 #include "HexagonISelLowering.h"
00016 #include "HexagonTargetMachine.h"
00017 #include "llvm/ADT/DenseMap.h"
00018 #include "llvm/CodeGen/SelectionDAGISel.h"
00019 #include "llvm/IR/Intrinsics.h"
00020 #include "llvm/Support/CommandLine.h"
00021 #include "llvm/Support/Compiler.h"
00022 #include "llvm/Support/Debug.h"
00023 using namespace llvm;
00024 
00025 #define DEBUG_TYPE "hexagon-isel"
00026 
00027 static
00028 cl::opt<unsigned>
00029 MaxNumOfUsesForConstExtenders("ga-max-num-uses-for-constant-extenders",
00030   cl::Hidden, cl::init(2),
00031   cl::desc("Maximum number of uses of a global address such that we still us a"
00032            "constant extended instruction"));
00033 
00034 //===----------------------------------------------------------------------===//
00035 // Instruction Selector Implementation
00036 //===----------------------------------------------------------------------===//
00037 
00038 namespace llvm {
00039   void initializeHexagonDAGToDAGISelPass(PassRegistry&);
00040 }
00041 
00042 //===--------------------------------------------------------------------===//
00043 /// HexagonDAGToDAGISel - Hexagon specific code to select Hexagon machine
00044 /// instructions for SelectionDAG operations.
00045 ///
00046 namespace {
00047 class HexagonDAGToDAGISel : public SelectionDAGISel {
00048   /// Subtarget - Keep a pointer to the Hexagon Subtarget around so that we can
00049   /// make the right decision when generating code for different targets.
00050   const HexagonSubtarget *Subtarget;
00051 
00052   // Keep a reference to HexagonTargetMachine.
00053   const HexagonTargetMachine& TM;
00054   DenseMap<const GlobalValue *, unsigned> GlobalAddressUseCountMap;
00055 public:
00056   explicit HexagonDAGToDAGISel(HexagonTargetMachine &targetmachine,
00057                                CodeGenOpt::Level OptLevel)
00058       : SelectionDAGISel(targetmachine, OptLevel), TM(targetmachine) {
00059     initializeHexagonDAGToDAGISelPass(*PassRegistry::getPassRegistry());
00060   }
00061   bool hasNumUsesBelowThresGA(SDNode *N) const;
00062 
00063   SDNode *Select(SDNode *N) override;
00064 
00065   // Complex Pattern Selectors.
00066   inline bool foldGlobalAddress(SDValue &N, SDValue &R);
00067   inline bool foldGlobalAddressGP(SDValue &N, SDValue &R);
00068   bool foldGlobalAddressImpl(SDValue &N, SDValue &R, bool ShouldLookForGP);
00069   bool SelectADDRri(SDValue& N, SDValue &R1, SDValue &R2);
00070   bool SelectADDRriS11_0(SDValue& N, SDValue &R1, SDValue &R2);
00071   bool SelectADDRriS11_1(SDValue& N, SDValue &R1, SDValue &R2);
00072   bool SelectADDRriS11_2(SDValue& N, SDValue &R1, SDValue &R2);
00073   bool SelectMEMriS11_2(SDValue& Addr, SDValue &Base, SDValue &Offset);
00074   bool SelectADDRriS11_3(SDValue& N, SDValue &R1, SDValue &R2);
00075   bool SelectADDRrr(SDValue &Addr, SDValue &Base, SDValue &Offset);
00076   bool SelectADDRriU6_0(SDValue& N, SDValue &R1, SDValue &R2);
00077   bool SelectADDRriU6_1(SDValue& N, SDValue &R1, SDValue &R2);
00078   bool SelectADDRriU6_2(SDValue& N, SDValue &R1, SDValue &R2);
00079 
00080   // Complex Pattern Selectors.
00081   inline bool SelectAddrGA(SDValue &N, SDValue &R);
00082   inline bool SelectAddrGP(SDValue &N, SDValue &R);
00083   bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP);
00084   bool SelectAddrFI(SDValue &N, SDValue &R);
00085 
00086   const char *getPassName() const override {
00087     return "Hexagon DAG->DAG Pattern Instruction Selection";
00088   }
00089 
00090   bool runOnMachineFunction(MachineFunction &MF) override {
00091     Subtarget = &MF.getSubtarget<HexagonSubtarget>();
00092     return SelectionDAGISel::runOnMachineFunction(MF);
00093   }
00094 
00095   /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
00096   /// inline asm expressions.
00097   bool SelectInlineAsmMemoryOperand(const SDValue &Op,
00098                                     char ConstraintCode,
00099                                     std::vector<SDValue> &OutOps) override;
00100   bool SelectAddr(SDNode *Op, SDValue Addr, SDValue &Base, SDValue &Offset);
00101 
00102   SDNode *SelectLoad(SDNode *N);
00103   SDNode *SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl);
00104   SDNode *SelectIndexedLoad(LoadSDNode *LD, SDLoc dl);
00105   SDNode *SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
00106                                         SDLoc dl);
00107   SDNode *SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode,
00108                                         SDLoc dl);
00109   SDNode *SelectBaseOffsetStore(StoreSDNode *ST, SDLoc dl);
00110   SDNode *SelectIndexedStore(StoreSDNode *ST, SDLoc dl);
00111   SDNode *SelectStore(SDNode *N);
00112   SDNode *SelectSHL(SDNode *N);
00113   SDNode *SelectSelect(SDNode *N);
00114   SDNode *SelectTruncate(SDNode *N);
00115   SDNode *SelectMul(SDNode *N);
00116   SDNode *SelectZeroExtend(SDNode *N);
00117   SDNode *SelectIntrinsicWOChain(SDNode *N);
00118   SDNode *SelectIntrinsicWChain(SDNode *N);
00119   SDNode *SelectConstant(SDNode *N);
00120   SDNode *SelectConstantFP(SDNode *N);
00121   SDNode *SelectAdd(SDNode *N);
00122   bool isConstExtProfitable(SDNode *N) const;
00123 
00124 // XformMskToBitPosU5Imm - Returns the bit position which
00125 // the single bit 32 bit mask represents.
00126 // Used in Clr and Set bit immediate memops.
00127 SDValue XformMskToBitPosU5Imm(uint32_t Imm) {
00128   int32_t bitPos;
00129   bitPos = Log2_32(Imm);
00130   assert(bitPos >= 0 && bitPos < 32 &&
00131          "Constant out of range for 32 BitPos Memops");
00132   return CurDAG->getTargetConstant(bitPos, MVT::i32);
00133 }
00134 
00135 // XformMskToBitPosU4Imm - Returns the bit position which the single bit 16 bit
00136 // mask represents. Used in Clr and Set bit immediate memops.
00137 SDValue XformMskToBitPosU4Imm(uint16_t Imm) {
00138   return XformMskToBitPosU5Imm(Imm);
00139 }
00140 
00141 // XformMskToBitPosU3Imm - Returns the bit position which the single bit 8 bit
00142 // mask represents. Used in Clr and Set bit immediate memops.
00143 SDValue XformMskToBitPosU3Imm(uint8_t Imm) {
00144   return XformMskToBitPosU5Imm(Imm);
00145 }
00146 
00147 // Return true if there is exactly one bit set in V, i.e., if V is one of the
00148 // following integers: 2^0, 2^1, ..., 2^31.
00149 bool ImmIsSingleBit(uint32_t v) const {
00150   return isPowerOf2_32(v);
00151 }
00152 
00153 // XformM5ToU5Imm - Return a target constant with the specified value, of type
00154 // i32 where the negative literal is transformed into a positive literal for
00155 // use in -= memops.
00156 inline SDValue XformM5ToU5Imm(signed Imm) {
00157    assert( (Imm >= -31 && Imm <= -1)  && "Constant out of range for Memops");
00158    return CurDAG->getTargetConstant( - Imm, MVT::i32);
00159 }
00160 
00161 
00162 // XformU7ToU7M1Imm - Return a target constant decremented by 1, in range
00163 // [1..128], used in cmpb.gtu instructions.
00164 inline SDValue XformU7ToU7M1Imm(signed Imm) {
00165   assert((Imm >= 1 && Imm <= 128) && "Constant out of range for cmpb op");
00166   return CurDAG->getTargetConstant(Imm - 1, MVT::i8);
00167 }
00168 
00169 // XformS8ToS8M1Imm - Return a target constant decremented by 1.
00170 inline SDValue XformSToSM1Imm(signed Imm) {
00171   return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
00172 }
00173 
00174 // XformU8ToU8M1Imm - Return a target constant decremented by 1.
00175 inline SDValue XformUToUM1Imm(unsigned Imm) {
00176   assert((Imm >= 1) && "Cannot decrement unsigned int less than 1");
00177   return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
00178 }
00179 
00180 // XformSToSM2Imm - Return a target constant decremented by 2.
00181 inline SDValue XformSToSM2Imm(unsigned Imm) {
00182   return CurDAG->getTargetConstant(Imm - 2, MVT::i32);
00183 }
00184 
00185 // XformSToSM3Imm - Return a target constant decremented by 3.
00186 inline SDValue XformSToSM3Imm(unsigned Imm) {
00187   return CurDAG->getTargetConstant(Imm - 3, MVT::i32);
00188 }
00189 
00190 // Include the pieces autogenerated from the target description.
00191 #include "HexagonGenDAGISel.inc"
00192 
00193 private:
00194   bool isValueExtension(SDValue const &Val, unsigned FromBits, SDValue &Src);
00195 };
00196 }  // end anonymous namespace
00197 
00198 
00199 /// createHexagonISelDag - This pass converts a legalized DAG into a
00200 /// Hexagon-specific DAG, ready for instruction scheduling.
00201 ///
00202 FunctionPass *llvm::createHexagonISelDag(HexagonTargetMachine &TM,
00203                                          CodeGenOpt::Level OptLevel) {
00204   return new HexagonDAGToDAGISel(TM, OptLevel);
00205 }
00206 
00207 static void initializePassOnce(PassRegistry &Registry) {
00208   const char *Name = "Hexagon DAG->DAG Pattern Instruction Selection";
00209   PassInfo *PI = new PassInfo(Name, "hexagon-isel",
00210                               &SelectionDAGISel::ID, nullptr, false, false);
00211   Registry.registerPass(*PI, true);
00212 }
00213 
00214 void llvm::initializeHexagonDAGToDAGISelPass(PassRegistry &Registry) {
00215   CALL_ONCE_INITIALIZATION(initializePassOnce)
00216 }
00217 
00218 
00219 static bool IsS11_0_Offset(SDNode * S) {
00220     ConstantSDNode *N = cast<ConstantSDNode>(S);
00221 
00222   // immS16 predicate - True if the immediate fits in a 16-bit sign extended
00223   // field.
00224   int64_t v = (int64_t)N->getSExtValue();
00225   return isInt<11>(v);
00226 }
00227 
00228 
00229 static bool IsS11_1_Offset(SDNode * S) {
00230     ConstantSDNode *N = cast<ConstantSDNode>(S);
00231 
00232   // immS16 predicate - True if the immediate fits in a 16-bit sign extended
00233   // field.
00234   int64_t v = (int64_t)N->getSExtValue();
00235   return isShiftedInt<11,1>(v);
00236 }
00237 
00238 
00239 static bool IsS11_2_Offset(SDNode * S) {
00240     ConstantSDNode *N = cast<ConstantSDNode>(S);
00241 
00242   // immS16 predicate - True if the immediate fits in a 16-bit sign extended
00243   // field.
00244   int64_t v = (int64_t)N->getSExtValue();
00245   return isShiftedInt<11,2>(v);
00246 }
00247 
00248 
00249 static bool IsS11_3_Offset(SDNode * S) {
00250     ConstantSDNode *N = cast<ConstantSDNode>(S);
00251 
00252   // immS16 predicate - True if the immediate fits in a 16-bit sign extended
00253   // field.
00254   int64_t v = (int64_t)N->getSExtValue();
00255   return isShiftedInt<11,3>(v);
00256 }
00257 
00258 
00259 static bool IsU6_0_Offset(SDNode * S) {
00260     ConstantSDNode *N = cast<ConstantSDNode>(S);
00261 
00262   // u6 predicate - True if the immediate fits in a 6-bit unsigned extended
00263   // field.
00264   int64_t v = (int64_t)N->getSExtValue();
00265   return isUInt<6>(v);
00266 }
00267 
00268 
00269 static bool IsU6_1_Offset(SDNode * S) {
00270     ConstantSDNode *N = cast<ConstantSDNode>(S);
00271 
00272   // u6 predicate - True if the immediate fits in a 6-bit unsigned extended
00273   // field.
00274   int64_t v = (int64_t)N->getSExtValue();
00275   return isShiftedUInt<6,1>(v);
00276 }
00277 
00278 
00279 static bool IsU6_2_Offset(SDNode * S) {
00280     ConstantSDNode *N = cast<ConstantSDNode>(S);
00281 
00282   // u6 predicate - True if the immediate fits in a 6-bit unsigned extended
00283   // field.
00284   int64_t v = (int64_t)N->getSExtValue();
00285   return isShiftedUInt<6,2>(v);
00286 }
00287 
00288 
00289 // Intrinsics that return a a predicate.
00290 static unsigned doesIntrinsicReturnPredicate(unsigned ID)
00291 {
00292   switch (ID) {
00293     default:
00294       return 0;
00295     case Intrinsic::hexagon_C2_cmpeq:
00296     case Intrinsic::hexagon_C2_cmpgt:
00297     case Intrinsic::hexagon_C2_cmpgtu:
00298     case Intrinsic::hexagon_C2_cmpgtup:
00299     case Intrinsic::hexagon_C2_cmpgtp:
00300     case Intrinsic::hexagon_C2_cmpeqp:
00301     case Intrinsic::hexagon_C2_bitsset:
00302     case Intrinsic::hexagon_C2_bitsclr:
00303     case Intrinsic::hexagon_C2_cmpeqi:
00304     case Intrinsic::hexagon_C2_cmpgti:
00305     case Intrinsic::hexagon_C2_cmpgtui:
00306     case Intrinsic::hexagon_C2_cmpgei:
00307     case Intrinsic::hexagon_C2_cmpgeui:
00308     case Intrinsic::hexagon_C2_cmplt:
00309     case Intrinsic::hexagon_C2_cmpltu:
00310     case Intrinsic::hexagon_C2_bitsclri:
00311     case Intrinsic::hexagon_C2_and:
00312     case Intrinsic::hexagon_C2_or:
00313     case Intrinsic::hexagon_C2_xor:
00314     case Intrinsic::hexagon_C2_andn:
00315     case Intrinsic::hexagon_C2_not:
00316     case Intrinsic::hexagon_C2_orn:
00317     case Intrinsic::hexagon_C2_pxfer_map:
00318     case Intrinsic::hexagon_C2_any8:
00319     case Intrinsic::hexagon_C2_all8:
00320     case Intrinsic::hexagon_A2_vcmpbeq:
00321     case Intrinsic::hexagon_A2_vcmpbgtu:
00322     case Intrinsic::hexagon_A2_vcmpheq:
00323     case Intrinsic::hexagon_A2_vcmphgt:
00324     case Intrinsic::hexagon_A2_vcmphgtu:
00325     case Intrinsic::hexagon_A2_vcmpweq:
00326     case Intrinsic::hexagon_A2_vcmpwgt:
00327     case Intrinsic::hexagon_A2_vcmpwgtu:
00328     case Intrinsic::hexagon_C2_tfrrp:
00329     case Intrinsic::hexagon_S2_tstbit_i:
00330     case Intrinsic::hexagon_S2_tstbit_r:
00331       return 1;
00332   }
00333 }
00334 
00335 static bool OffsetFitsS11(EVT MemType, int64_t Offset) {
00336   if (MemType == MVT::i64 && isShiftedInt<11,3>(Offset)) {
00337     return true;
00338   }
00339   if (MemType == MVT::i32 && isShiftedInt<11,2>(Offset)) {
00340     return true;
00341   }
00342   if (MemType == MVT::i16 && isShiftedInt<11,1>(Offset)) {
00343     return true;
00344   }
00345   if (MemType == MVT::i8 && isInt<11>(Offset)) {
00346     return true;
00347   }
00348   return false;
00349 }
00350 
00351 
00352 //
00353 // Try to lower loads of GlobalAdresses into base+offset loads.  Custom
00354 // lowering for GlobalAddress nodes has already turned it into a
00355 // CONST32.
00356 //
00357 SDNode *HexagonDAGToDAGISel::SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl) {
00358   SDValue Chain = LD->getChain();
00359   SDNode* Const32 = LD->getBasePtr().getNode();
00360   unsigned Opcode = 0;
00361 
00362   if (Const32->getOpcode() == HexagonISD::CONST32 &&
00363       ISD::isNormalLoad(LD)) {
00364     SDValue Base = Const32->getOperand(0);
00365     EVT LoadedVT = LD->getMemoryVT();
00366     int64_t Offset = cast<GlobalAddressSDNode>(Base)->getOffset();
00367     if (Offset != 0 && OffsetFitsS11(LoadedVT, Offset)) {
00368       MVT PointerTy = getTargetLowering()->getPointerTy();
00369       const GlobalValue* GV =
00370         cast<GlobalAddressSDNode>(Base)->getGlobal();
00371       SDValue TargAddr =
00372         CurDAG->getTargetGlobalAddress(GV, dl, PointerTy, 0);
00373       SDNode* NewBase = CurDAG->getMachineNode(Hexagon::CONST32_set,
00374                                                dl, PointerTy,
00375                                                TargAddr);
00376       // Figure out base + offset opcode
00377       if (LoadedVT == MVT::i64) Opcode = Hexagon::L2_loadrd_io;
00378       else if (LoadedVT == MVT::i32) Opcode = Hexagon::L2_loadri_io;
00379       else if (LoadedVT == MVT::i16) Opcode = Hexagon::L2_loadrh_io;
00380       else if (LoadedVT == MVT::i8) Opcode = Hexagon::L2_loadrb_io;
00381       else llvm_unreachable("unknown memory type");
00382 
00383       // Build indexed load.
00384       SDValue TargetConstOff = CurDAG->getTargetConstant(Offset, PointerTy);
00385       SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
00386                                               LD->getValueType(0),
00387                                               MVT::Other,
00388                                               SDValue(NewBase,0),
00389                                               TargetConstOff,
00390                                               Chain);
00391       MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00392       MemOp[0] = LD->getMemOperand();
00393       cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
00394       ReplaceUses(LD, Result);
00395       return Result;
00396     }
00397   }
00398 
00399   return SelectCode(LD);
00400 }
00401 
00402 
00403 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
00404                                                            unsigned Opcode,
00405                                                            SDLoc dl)
00406 {
00407   SDValue Chain = LD->getChain();
00408   EVT LoadedVT = LD->getMemoryVT();
00409   SDValue Base = LD->getBasePtr();
00410   SDValue Offset = LD->getOffset();
00411   SDNode *OffsetNode = Offset.getNode();
00412   int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
00413   SDValue N1 = LD->getOperand(1);
00414   SDValue CPTmpN1_0;
00415   SDValue CPTmpN1_1;
00416 
00417   if (SelectADDRriS11_2(N1, CPTmpN1_0, CPTmpN1_1) &&
00418       N1.getNode()->getValueType(0) == MVT::i32) {
00419     const HexagonInstrInfo *TII = Subtarget->getInstrInfo();
00420     if (TII->isValidAutoIncImm(LoadedVT, Val)) {
00421       SDValue TargetConst = CurDAG->getTargetConstant(Val, MVT::i32);
00422       SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32,
00423                                                 MVT::Other, Base, TargetConst,
00424                                                 Chain);
00425       SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
00426                                                 SDValue(Result_1, 0));
00427       MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00428       MemOp[0] = LD->getMemOperand();
00429       cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00430       const SDValue Froms[] = { SDValue(LD, 0),
00431                                 SDValue(LD, 1),
00432                                 SDValue(LD, 2)
00433       };
00434       const SDValue Tos[]   = { SDValue(Result_2, 0),
00435                                 SDValue(Result_1, 1),
00436                                 SDValue(Result_1, 2)
00437       };
00438       ReplaceUses(Froms, Tos, 3);
00439       return Result_2;
00440     }
00441     SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
00442     SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
00443     SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
00444                                               MVT::Other, Base, TargetConst0,
00445                                               Chain);
00446     SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl,
00447                                                 MVT::i64, SDValue(Result_1, 0));
00448     SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::A2_addi, dl,
00449                                               MVT::i32, Base, TargetConstVal,
00450                                                 SDValue(Result_1, 1));
00451     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00452     MemOp[0] = LD->getMemOperand();
00453     cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00454     const SDValue Froms[] = { SDValue(LD, 0),
00455                               SDValue(LD, 1),
00456                               SDValue(LD, 2)
00457     };
00458     const SDValue Tos[]   = { SDValue(Result_2, 0),
00459                               SDValue(Result_3, 0),
00460                               SDValue(Result_1, 1)
00461     };
00462     ReplaceUses(Froms, Tos, 3);
00463     return Result_2;
00464   }
00465   return SelectCode(LD);
00466 }
00467 
00468 
00469 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
00470                                                            unsigned Opcode,
00471                                                            SDLoc dl)
00472 {
00473   SDValue Chain = LD->getChain();
00474   EVT LoadedVT = LD->getMemoryVT();
00475   SDValue Base = LD->getBasePtr();
00476   SDValue Offset = LD->getOffset();
00477   SDNode *OffsetNode = Offset.getNode();
00478   int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
00479   SDValue N1 = LD->getOperand(1);
00480   SDValue CPTmpN1_0;
00481   SDValue CPTmpN1_1;
00482 
00483   if (SelectADDRriS11_2(N1, CPTmpN1_0, CPTmpN1_1) &&
00484       N1.getNode()->getValueType(0) == MVT::i32) {
00485     const HexagonInstrInfo *TII = Subtarget->getInstrInfo();
00486     if (TII->isValidAutoIncImm(LoadedVT, Val)) {
00487       SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
00488       SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
00489       SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
00490                                                 MVT::i32, MVT::Other, Base,
00491                                                 TargetConstVal, Chain);
00492       SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32,
00493                                                 TargetConst0);
00494       SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl,
00495                                                 MVT::i64, MVT::Other,
00496                                                 SDValue(Result_2,0),
00497                                                 SDValue(Result_1,0));
00498       MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00499       MemOp[0] = LD->getMemOperand();
00500       cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00501       const SDValue Froms[] = { SDValue(LD, 0),
00502                                 SDValue(LD, 1),
00503                                 SDValue(LD, 2)
00504       };
00505       const SDValue Tos[]   = { SDValue(Result_3, 0),
00506                                 SDValue(Result_1, 1),
00507                                 SDValue(Result_1, 2)
00508       };
00509       ReplaceUses(Froms, Tos, 3);
00510       return Result_3;
00511     }
00512 
00513     // Generate an indirect load.
00514     SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
00515     SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
00516     SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
00517                                               MVT::Other,
00518                                               Base, TargetConst0, Chain);
00519     SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32,
00520                                               TargetConst0);
00521     SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl,
00522                                               MVT::i64, MVT::Other,
00523                                               SDValue(Result_2,0),
00524                                               SDValue(Result_1,0));
00525     // Add offset to base.
00526     SDNode* Result_4 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
00527                                               Base, TargetConstVal,
00528                                               SDValue(Result_1, 1));
00529     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00530     MemOp[0] = LD->getMemOperand();
00531     cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00532     const SDValue Froms[] = { SDValue(LD, 0),
00533                               SDValue(LD, 1),
00534                               SDValue(LD, 2)
00535     };
00536     const SDValue Tos[]   = { SDValue(Result_3, 0), // Load value.
00537                               SDValue(Result_4, 0), // New address.
00538                               SDValue(Result_1, 1)
00539     };
00540     ReplaceUses(Froms, Tos, 3);
00541     return Result_3;
00542   }
00543 
00544   return SelectCode(LD);
00545 }
00546 
00547 
00548 SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
00549   SDValue Chain = LD->getChain();
00550   SDValue Base = LD->getBasePtr();
00551   SDValue Offset = LD->getOffset();
00552   SDNode *OffsetNode = Offset.getNode();
00553   // Get the constant value.
00554   int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
00555   EVT LoadedVT = LD->getMemoryVT();
00556   unsigned Opcode = 0;
00557 
00558   // Check for zero ext loads.
00559   bool zextval = (LD->getExtensionType() == ISD::ZEXTLOAD);
00560 
00561   // Figure out the opcode.
00562   const HexagonInstrInfo *TII = Subtarget->getInstrInfo();
00563   if (LoadedVT == MVT::i64) {
00564     if (TII->isValidAutoIncImm(LoadedVT, Val))
00565       Opcode = Hexagon::L2_loadrd_pi;
00566     else
00567       Opcode = Hexagon::L2_loadrd_io;
00568   } else if (LoadedVT == MVT::i32) {
00569     if (TII->isValidAutoIncImm(LoadedVT, Val))
00570       Opcode = Hexagon::L2_loadri_pi;
00571     else
00572       Opcode = Hexagon::L2_loadri_io;
00573   } else if (LoadedVT == MVT::i16) {
00574     if (TII->isValidAutoIncImm(LoadedVT, Val))
00575       Opcode = zextval ? Hexagon::L2_loadruh_pi : Hexagon::L2_loadrh_pi;
00576     else
00577       Opcode = zextval ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io;
00578   } else if (LoadedVT == MVT::i8) {
00579     if (TII->isValidAutoIncImm(LoadedVT, Val))
00580       Opcode = zextval ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrb_pi;
00581     else
00582       Opcode = zextval ? Hexagon::L2_loadrub_io : Hexagon::L2_loadrb_io;
00583   } else
00584     llvm_unreachable("unknown memory type");
00585 
00586   // For zero ext i64 loads, we need to add combine instructions.
00587   if (LD->getValueType(0) == MVT::i64 &&
00588       LD->getExtensionType() == ISD::ZEXTLOAD) {
00589     return SelectIndexedLoadZeroExtend64(LD, Opcode, dl);
00590   }
00591   if (LD->getValueType(0) == MVT::i64 &&
00592              LD->getExtensionType() == ISD::SEXTLOAD) {
00593     // Handle sign ext i64 loads.
00594     return SelectIndexedLoadSignExtend64(LD, Opcode, dl);
00595   }
00596   if (TII->isValidAutoIncImm(LoadedVT, Val)) {
00597     SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
00598     SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
00599                                             LD->getValueType(0),
00600                                             MVT::i32, MVT::Other, Base,
00601                                             TargetConstVal, Chain);
00602     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00603     MemOp[0] = LD->getMemOperand();
00604     cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
00605     const SDValue Froms[] = { SDValue(LD, 0),
00606                               SDValue(LD, 1),
00607                               SDValue(LD, 2)
00608     };
00609     const SDValue Tos[]   = { SDValue(Result, 0),
00610                               SDValue(Result, 1),
00611                               SDValue(Result, 2)
00612     };
00613     ReplaceUses(Froms, Tos, 3);
00614     return Result;
00615   } else {
00616     SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
00617     SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
00618     SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl,
00619                                               LD->getValueType(0),
00620                                               MVT::Other, Base, TargetConst0,
00621                                               Chain);
00622     SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
00623                                               Base, TargetConstVal,
00624                                               SDValue(Result_1, 1));
00625     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00626     MemOp[0] = LD->getMemOperand();
00627     cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00628     const SDValue Froms[] = { SDValue(LD, 0),
00629                               SDValue(LD, 1),
00630                               SDValue(LD, 2)
00631     };
00632     const SDValue Tos[]   = { SDValue(Result_1, 0),
00633                               SDValue(Result_2, 0),
00634                               SDValue(Result_1, 1)
00635     };
00636     ReplaceUses(Froms, Tos, 3);
00637     return Result_1;
00638   }
00639 }
00640 
00641 
00642 SDNode *HexagonDAGToDAGISel::SelectLoad(SDNode *N) {
00643   SDNode *result;
00644   SDLoc dl(N);
00645   LoadSDNode *LD = cast<LoadSDNode>(N);
00646   ISD::MemIndexedMode AM = LD->getAddressingMode();
00647 
00648   // Handle indexed loads.
00649   if (AM != ISD::UNINDEXED) {
00650     result = SelectIndexedLoad(LD, dl);
00651   } else {
00652     result = SelectBaseOffsetLoad(LD, dl);
00653   }
00654 
00655   return result;
00656 }
00657 
00658 
00659 SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) {
00660   SDValue Chain = ST->getChain();
00661   SDValue Base = ST->getBasePtr();
00662   SDValue Offset = ST->getOffset();
00663   SDValue Value = ST->getValue();
00664   SDNode *OffsetNode = Offset.getNode();
00665   // Get the constant value.
00666   int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
00667   EVT StoredVT = ST->getMemoryVT();
00668 
00669   // Offset value must be within representable range
00670   // and must have correct alignment properties.
00671   const HexagonInstrInfo *TII = Subtarget->getInstrInfo();
00672   if (TII->isValidAutoIncImm(StoredVT, Val)) {
00673     SDValue Ops[] = {Base, CurDAG->getTargetConstant(Val, MVT::i32), Value,
00674                      Chain};
00675     unsigned Opcode = 0;
00676 
00677     // Figure out the post inc version of opcode.
00678     if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_pi;
00679     else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_pi;
00680     else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_pi;
00681     else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_pi;
00682     else llvm_unreachable("unknown memory type");
00683 
00684     // Build post increment store.
00685     SDNode* Result = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
00686                                             MVT::Other, Ops);
00687     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00688     MemOp[0] = ST->getMemOperand();
00689     cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
00690 
00691     ReplaceUses(ST, Result);
00692     ReplaceUses(SDValue(ST,1), SDValue(Result,1));
00693     return Result;
00694   }
00695 
00696   // Note: Order of operands matches the def of instruction:
00697   // def STrid : STInst<(outs), (ins MEMri:$addr, DoubleRegs:$src1), ...
00698   // and it differs for POST_ST* for instance.
00699   SDValue Ops[] = { Base, CurDAG->getTargetConstant(0, MVT::i32), Value,
00700                     Chain};
00701   unsigned Opcode = 0;
00702 
00703   // Figure out the opcode.
00704   if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_io;
00705   else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_io;
00706   else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_io;
00707   else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_io;
00708   else llvm_unreachable("unknown memory type");
00709 
00710   // Build regular store.
00711   SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
00712   SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
00713   // Build splitted incriment instruction.
00714   SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
00715                                             Base,
00716                                             TargetConstVal,
00717                                             SDValue(Result_1, 0));
00718   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00719   MemOp[0] = ST->getMemOperand();
00720   cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00721 
00722   ReplaceUses(SDValue(ST,0), SDValue(Result_2,0));
00723   ReplaceUses(SDValue(ST,1), SDValue(Result_1,0));
00724   return Result_2;
00725 }
00726 
00727 
00728 SDNode *HexagonDAGToDAGISel::SelectBaseOffsetStore(StoreSDNode *ST,
00729                                                    SDLoc dl) {
00730   SDValue Chain = ST->getChain();
00731   SDNode* Const32 = ST->getBasePtr().getNode();
00732   SDValue Value = ST->getValue();
00733   unsigned Opcode = 0;
00734 
00735   // Try to lower stores of GlobalAdresses into indexed stores.  Custom
00736   // lowering for GlobalAddress nodes has already turned it into a
00737   // CONST32.  Avoid truncating stores for the moment.  Post-inc stores
00738   // do the same.  Don't think there's a reason for it, so will file a
00739   // bug to fix.
00740   if ((Const32->getOpcode() == HexagonISD::CONST32) &&
00741       !(Value.getValueType() == MVT::i64 && ST->isTruncatingStore())) {
00742     SDValue Base = Const32->getOperand(0);
00743     if (Base.getOpcode() == ISD::TargetGlobalAddress) {
00744       EVT StoredVT = ST->getMemoryVT();
00745       int64_t Offset = cast<GlobalAddressSDNode>(Base)->getOffset();
00746       if (Offset != 0 && OffsetFitsS11(StoredVT, Offset)) {
00747         MVT PointerTy = getTargetLowering()->getPointerTy();
00748         const GlobalValue* GV =
00749           cast<GlobalAddressSDNode>(Base)->getGlobal();
00750         SDValue TargAddr =
00751           CurDAG->getTargetGlobalAddress(GV, dl, PointerTy, 0);
00752         SDNode* NewBase = CurDAG->getMachineNode(Hexagon::CONST32_set,
00753                                                  dl, PointerTy,
00754                                                  TargAddr);
00755 
00756         // Figure out base + offset opcode
00757         if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_io;
00758         else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_io;
00759         else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_io;
00760         else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_io;
00761         else llvm_unreachable("unknown memory type");
00762 
00763         SDValue Ops[] = {SDValue(NewBase,0),
00764                          CurDAG->getTargetConstant(Offset,PointerTy),
00765                          Value, Chain};
00766         // build indexed store
00767         SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
00768                                                 MVT::Other, Ops);
00769         MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00770         MemOp[0] = ST->getMemOperand();
00771         cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
00772         ReplaceUses(ST, Result);
00773         return Result;
00774       }
00775     }
00776   }
00777 
00778   return SelectCode(ST);
00779 }
00780 
00781 
00782 SDNode *HexagonDAGToDAGISel::SelectStore(SDNode *N) {
00783   SDLoc dl(N);
00784   StoreSDNode *ST = cast<StoreSDNode>(N);
00785   ISD::MemIndexedMode AM = ST->getAddressingMode();
00786 
00787   // Handle indexed stores.
00788   if (AM != ISD::UNINDEXED) {
00789     return SelectIndexedStore(ST, dl);
00790   }
00791 
00792   return SelectBaseOffsetStore(ST, dl);
00793 }
00794 
00795 SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
00796   SDLoc dl(N);
00797 
00798   //
00799   // %conv.i = sext i32 %tmp1 to i64
00800   // %conv2.i = sext i32 %add to i64
00801   // %mul.i = mul nsw i64 %conv2.i, %conv.i
00802   //
00803   //   --- match with the following ---
00804   //
00805   // %mul.i = mpy (%tmp1, %add)
00806   //
00807 
00808   if (N->getValueType(0) == MVT::i64) {
00809     // Shifting a i64 signed multiply.
00810     SDValue MulOp0 = N->getOperand(0);
00811     SDValue MulOp1 = N->getOperand(1);
00812 
00813     SDValue OP0;
00814     SDValue OP1;
00815 
00816     // Handle sign_extend and sextload.
00817     if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
00818       SDValue Sext0 = MulOp0.getOperand(0);
00819       if (Sext0.getNode()->getValueType(0) != MVT::i32) {
00820         return SelectCode(N);
00821       }
00822 
00823       OP0 = Sext0;
00824     } else if (MulOp0.getOpcode() == ISD::LOAD) {
00825       LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
00826       if (LD->getMemoryVT() != MVT::i32 ||
00827           LD->getExtensionType() != ISD::SEXTLOAD ||
00828           LD->getAddressingMode() != ISD::UNINDEXED) {
00829         return SelectCode(N);
00830       }
00831 
00832       SDValue Chain = LD->getChain();
00833       SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
00834       OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
00835                                             MVT::Other,
00836                                             LD->getBasePtr(), TargetConst0,
00837                                             Chain), 0);
00838     } else {
00839       return SelectCode(N);
00840     }
00841 
00842     // Same goes for the second operand.
00843     if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
00844       SDValue Sext1 = MulOp1.getOperand(0);
00845       if (Sext1.getNode()->getValueType(0) != MVT::i32) {
00846         return SelectCode(N);
00847       }
00848 
00849       OP1 = Sext1;
00850     } else if (MulOp1.getOpcode() == ISD::LOAD) {
00851       LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
00852       if (LD->getMemoryVT() != MVT::i32 ||
00853           LD->getExtensionType() != ISD::SEXTLOAD ||
00854           LD->getAddressingMode() != ISD::UNINDEXED) {
00855         return SelectCode(N);
00856       }
00857 
00858       SDValue Chain = LD->getChain();
00859       SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
00860       OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
00861                                             MVT::Other,
00862                                             LD->getBasePtr(), TargetConst0,
00863                                             Chain), 0);
00864     } else {
00865       return SelectCode(N);
00866     }
00867 
00868     // Generate a mpy instruction.
00869     SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_dpmpyss_s0, dl, MVT::i64,
00870                                             OP0, OP1);
00871     ReplaceUses(N, Result);
00872     return Result;
00873   }
00874 
00875   return SelectCode(N);
00876 }
00877 
00878 
00879 SDNode *HexagonDAGToDAGISel::SelectSelect(SDNode *N) {
00880   SDLoc dl(N);
00881   SDValue N0 = N->getOperand(0);
00882   if (N0.getOpcode() == ISD::SETCC) {
00883     SDValue N00 = N0.getOperand(0);
00884     if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
00885       SDValue N000 = N00.getOperand(0);
00886       SDValue N001 = N00.getOperand(1);
00887       if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
00888         SDValue N01 = N0.getOperand(1);
00889         SDValue N02 = N0.getOperand(2);
00890 
00891         // Pattern: (select:i32 (setcc:i1 (sext_inreg:i32 IntRegs:i32:$src2,
00892         // i16:Other),IntRegs:i32:$src1, SETLT:Other),IntRegs:i32:$src1,
00893         // IntRegs:i32:$src2)
00894         // Emits: (MAXh_rr:i32 IntRegs:i32:$src1, IntRegs:i32:$src2)
00895         // Pattern complexity = 9  cost = 1  size = 0.
00896         if (cast<CondCodeSDNode>(N02)->get() == ISD::SETLT) {
00897           SDValue N1 = N->getOperand(1);
00898           if (N01 == N1) {
00899             SDValue N2 = N->getOperand(2);
00900             if (N000 == N2 &&
00901                 N0.getNode()->getValueType(N0.getResNo()) == MVT::i1 &&
00902                 N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) {
00903               SDNode *SextNode = CurDAG->getMachineNode(Hexagon::A2_sxth, dl,
00904                                                         MVT::i32, N000);
00905               SDNode *Result = CurDAG->getMachineNode(Hexagon::A2_max, dl,
00906                                                       MVT::i32,
00907                                                       SDValue(SextNode, 0),
00908                                                       N1);
00909               ReplaceUses(N, Result);
00910               return Result;
00911             }
00912           }
00913         }
00914 
00915         // Pattern: (select:i32 (setcc:i1 (sext_inreg:i32 IntRegs:i32:$src2,
00916         // i16:Other), IntRegs:i32:$src1, SETGT:Other), IntRegs:i32:$src1,
00917         // IntRegs:i32:$src2)
00918         // Emits: (MINh_rr:i32 IntRegs:i32:$src1, IntRegs:i32:$src2)
00919         // Pattern complexity = 9  cost = 1  size = 0.
00920         if (cast<CondCodeSDNode>(N02)->get() == ISD::SETGT) {
00921           SDValue N1 = N->getOperand(1);
00922           if (N01 == N1) {
00923             SDValue N2 = N->getOperand(2);
00924             if (N000 == N2 &&
00925                 N0.getNode()->getValueType(N0.getResNo()) == MVT::i1 &&
00926                 N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) {
00927               SDNode *SextNode = CurDAG->getMachineNode(Hexagon::A2_sxth, dl,
00928                                                         MVT::i32, N000);
00929               SDNode *Result = CurDAG->getMachineNode(Hexagon::A2_min, dl,
00930                                                       MVT::i32,
00931                                                       SDValue(SextNode, 0),
00932                                                       N1);
00933               ReplaceUses(N, Result);
00934               return Result;
00935             }
00936           }
00937         }
00938       }
00939     }
00940   }
00941 
00942   return SelectCode(N);
00943 }
00944 
00945 
00946 SDNode *HexagonDAGToDAGISel::SelectTruncate(SDNode *N) {
00947   SDLoc dl(N);
00948   SDValue Shift = N->getOperand(0);
00949 
00950   //
00951   // %conv.i = sext i32 %tmp1 to i64
00952   // %conv2.i = sext i32 %add to i64
00953   // %mul.i = mul nsw i64 %conv2.i, %conv.i
00954   // %shr5.i = lshr i64 %mul.i, 32
00955   // %conv3.i = trunc i64 %shr5.i to i32
00956   //
00957   //   --- match with the following ---
00958   //
00959   // %conv3.i = mpy (%tmp1, %add)
00960   //
00961   // Trunc to i32.
00962   if (N->getValueType(0) == MVT::i32) {
00963     // Trunc from i64.
00964     if (Shift.getNode()->getValueType(0) == MVT::i64) {
00965       // Trunc child is logical shift right.
00966       if (Shift.getOpcode() != ISD::SRL) {
00967         return SelectCode(N);
00968       }
00969 
00970       SDValue ShiftOp0 = Shift.getOperand(0);
00971       SDValue ShiftOp1 = Shift.getOperand(1);
00972 
00973       // Shift by const 32
00974       if (ShiftOp1.getOpcode() != ISD::Constant) {
00975         return SelectCode(N);
00976       }
00977 
00978       int32_t ShiftConst =
00979         cast<ConstantSDNode>(ShiftOp1.getNode())->getSExtValue();
00980       if (ShiftConst != 32) {
00981         return SelectCode(N);
00982       }
00983 
00984       // Shifting a i64 signed multiply
00985       SDValue Mul = ShiftOp0;
00986       if (Mul.getOpcode() != ISD::MUL) {
00987         return SelectCode(N);
00988       }
00989 
00990       SDValue MulOp0 = Mul.getOperand(0);
00991       SDValue MulOp1 = Mul.getOperand(1);
00992 
00993       SDValue OP0;
00994       SDValue OP1;
00995 
00996       // Handle sign_extend and sextload
00997       if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
00998         SDValue Sext0 = MulOp0.getOperand(0);
00999         if (Sext0.getNode()->getValueType(0) != MVT::i32) {
01000           return SelectCode(N);
01001         }
01002 
01003         OP0 = Sext0;
01004       } else if (MulOp0.getOpcode() == ISD::LOAD) {
01005         LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
01006         if (LD->getMemoryVT() != MVT::i32 ||
01007             LD->getExtensionType() != ISD::SEXTLOAD ||
01008             LD->getAddressingMode() != ISD::UNINDEXED) {
01009           return SelectCode(N);
01010         }
01011 
01012         SDValue Chain = LD->getChain();
01013         SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
01014         OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
01015                                               MVT::Other,
01016                                               LD->getBasePtr(),
01017                                               TargetConst0, Chain), 0);
01018       } else {
01019         return SelectCode(N);
01020       }
01021 
01022       // Same goes for the second operand.
01023       if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
01024         SDValue Sext1 = MulOp1.getOperand(0);
01025         if (Sext1.getNode()->getValueType(0) != MVT::i32)
01026           return SelectCode(N);
01027 
01028         OP1 = Sext1;
01029       } else if (MulOp1.getOpcode() == ISD::LOAD) {
01030         LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
01031         if (LD->getMemoryVT() != MVT::i32 ||
01032             LD->getExtensionType() != ISD::SEXTLOAD ||
01033             LD->getAddressingMode() != ISD::UNINDEXED) {
01034           return SelectCode(N);
01035         }
01036 
01037         SDValue Chain = LD->getChain();
01038         SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
01039         OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
01040                                               MVT::Other,
01041                                               LD->getBasePtr(),
01042                                               TargetConst0, Chain), 0);
01043       } else {
01044         return SelectCode(N);
01045       }
01046 
01047       // Generate a mpy instruction.
01048       SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_mpy_up, dl, MVT::i32,
01049                                               OP0, OP1);
01050       ReplaceUses(N, Result);
01051       return Result;
01052     }
01053   }
01054 
01055   return SelectCode(N);
01056 }
01057 
01058 
01059 SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
01060   SDLoc dl(N);
01061   if (N->getValueType(0) == MVT::i32) {
01062     SDValue Shl_0 = N->getOperand(0);
01063     SDValue Shl_1 = N->getOperand(1);
01064     // RHS is const.
01065     if (Shl_1.getOpcode() == ISD::Constant) {
01066       if (Shl_0.getOpcode() == ISD::MUL) {
01067         SDValue Mul_0 = Shl_0.getOperand(0); // Val
01068         SDValue Mul_1 = Shl_0.getOperand(1); // Const
01069         // RHS of mul is const.
01070         if (Mul_1.getOpcode() == ISD::Constant) {
01071           int32_t ShlConst =
01072             cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
01073           int32_t MulConst =
01074             cast<ConstantSDNode>(Mul_1.getNode())->getSExtValue();
01075           int32_t ValConst = MulConst << ShlConst;
01076           SDValue Val = CurDAG->getTargetConstant(ValConst,
01077                                                   MVT::i32);
01078           if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val.getNode()))
01079             if (isInt<9>(CN->getSExtValue())) {
01080               SDNode* Result =
01081                 CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl,
01082                                        MVT::i32, Mul_0, Val);
01083               ReplaceUses(N, Result);
01084               return Result;
01085             }
01086 
01087         }
01088       } else if (Shl_0.getOpcode() == ISD::SUB) {
01089         SDValue Sub_0 = Shl_0.getOperand(0); // Const 0
01090         SDValue Sub_1 = Shl_0.getOperand(1); // Val
01091         if (Sub_0.getOpcode() == ISD::Constant) {
01092           int32_t SubConst =
01093             cast<ConstantSDNode>(Sub_0.getNode())->getSExtValue();
01094           if (SubConst == 0) {
01095             if (Sub_1.getOpcode() == ISD::SHL) {
01096               SDValue Shl2_0 = Sub_1.getOperand(0); // Val
01097               SDValue Shl2_1 = Sub_1.getOperand(1); // Const
01098               if (Shl2_1.getOpcode() == ISD::Constant) {
01099                 int32_t ShlConst =
01100                   cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
01101                 int32_t Shl2Const =
01102                   cast<ConstantSDNode>(Shl2_1.getNode())->getSExtValue();
01103                 int32_t ValConst = 1 << (ShlConst+Shl2Const);
01104                 SDValue Val = CurDAG->getTargetConstant(-ValConst, MVT::i32);
01105                 if (ConstantSDNode *CN =
01106                     dyn_cast<ConstantSDNode>(Val.getNode()))
01107                   if (isInt<9>(CN->getSExtValue())) {
01108                     SDNode* Result =
01109                       CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl, MVT::i32,
01110                                              Shl2_0, Val);
01111                     ReplaceUses(N, Result);
01112                     return Result;
01113                   }
01114               }
01115             }
01116           }
01117         }
01118       }
01119     }
01120   }
01121   return SelectCode(N);
01122 }
01123 
01124 
01125 //
01126 // If there is an zero_extend followed an intrinsic in DAG (this means - the
01127 // result of the intrinsic is predicate); convert the zero_extend to
01128 // transfer instruction.
01129 //
01130 // Zero extend -> transfer is lowered here. Otherwise, zero_extend will be
01131 // converted into a MUX as predicate registers defined as 1 bit in the
01132 // compiler. Architecture defines them as 8-bit registers.
01133 // We want to preserve all the lower 8-bits and, not just 1 LSB bit.
01134 //
01135 SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) {
01136   SDLoc dl(N);
01137   SDNode *IsIntrinsic = N->getOperand(0).getNode();
01138   if ((IsIntrinsic->getOpcode() == ISD::INTRINSIC_WO_CHAIN)) {
01139     unsigned ID =
01140       cast<ConstantSDNode>(IsIntrinsic->getOperand(0))->getZExtValue();
01141     if (doesIntrinsicReturnPredicate(ID)) {
01142       // Now we need to differentiate target data types.
01143       if (N->getValueType(0) == MVT::i64) {
01144         // Convert the zero_extend to Rs = Pd followed by COMBINE_rr(0,Rs).
01145         SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
01146         SDNode *Result_1 = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
01147                                                   MVT::i32,
01148                                                   SDValue(IsIntrinsic, 0));
01149         SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl,
01150                                                   MVT::i32,
01151                                                   TargetConst0);
01152         SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl,
01153                                                   MVT::i64, MVT::Other,
01154                                                   SDValue(Result_2, 0),
01155                                                   SDValue(Result_1, 0));
01156         ReplaceUses(N, Result_3);
01157         return Result_3;
01158       }
01159       if (N->getValueType(0) == MVT::i32) {
01160         // Convert the zero_extend to Rs = Pd
01161         SDNode* RsPd = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
01162                                               MVT::i32,
01163                                               SDValue(IsIntrinsic, 0));
01164         ReplaceUses(N, RsPd);
01165         return RsPd;
01166       }
01167       llvm_unreachable("Unexpected value type");
01168     }
01169   }
01170   return SelectCode(N);
01171 }
01172 
01173 //
01174 // Checking for intrinsics which have predicate registers as operand(s)
01175 // and lowering to the actual intrinsic.
01176 //
01177 SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
01178   unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
01179   unsigned Bits;
01180   switch (IID) {
01181   case Intrinsic::hexagon_S2_vsplatrb:
01182     Bits = 8;
01183     break;
01184   case Intrinsic::hexagon_S2_vsplatrh:
01185     Bits = 16;
01186     break;
01187   default:
01188     return SelectCode(N);
01189   }
01190 
01191   SDValue const &V = N->getOperand(1);
01192   SDValue U;
01193   if (isValueExtension(V, Bits, U)) {
01194     SDValue R = CurDAG->getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
01195       N->getOperand(0), U);
01196     return SelectCode(R.getNode());
01197   }
01198   return SelectCode(N);
01199 }
01200 
01201 //
01202 // Map floating point constant values.
01203 //
01204 SDNode *HexagonDAGToDAGISel::SelectConstantFP(SDNode *N) {
01205   SDLoc dl(N);
01206   ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
01207   APFloat APF = CN->getValueAPF();
01208   if (N->getValueType(0) == MVT::f32) {
01209     return CurDAG->getMachineNode(Hexagon::TFRI_f, dl, MVT::f32,
01210               CurDAG->getTargetConstantFP(APF.convertToFloat(), MVT::f32));
01211   }
01212   else if (N->getValueType(0) == MVT::f64) {
01213     return CurDAG->getMachineNode(Hexagon::CONST64_Float_Real, dl, MVT::f64,
01214               CurDAG->getTargetConstantFP(APF.convertToDouble(), MVT::f64));
01215   }
01216 
01217   return SelectCode(N);
01218 }
01219 
01220 
01221 //
01222 // Map predicate true (encoded as -1 in LLVM) to a XOR.
01223 //
01224 SDNode *HexagonDAGToDAGISel::SelectConstant(SDNode *N) {
01225   SDLoc dl(N);
01226   if (N->getValueType(0) == MVT::i1) {
01227     SDNode* Result;
01228     int32_t Val = cast<ConstantSDNode>(N)->getSExtValue();
01229     if (Val == -1) {
01230       // Create the IntReg = 1 node.
01231       SDNode* IntRegTFR =
01232         CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32,
01233                                CurDAG->getTargetConstant(0, MVT::i32));
01234 
01235       // Pd = IntReg
01236       SDNode* Pd = CurDAG->getMachineNode(Hexagon::C2_tfrrp, dl, MVT::i1,
01237                                           SDValue(IntRegTFR, 0));
01238 
01239       // not(Pd)
01240       SDNode* NotPd = CurDAG->getMachineNode(Hexagon::C2_not, dl, MVT::i1,
01241                                              SDValue(Pd, 0));
01242 
01243       // xor(not(Pd))
01244       Result = CurDAG->getMachineNode(Hexagon::C2_xor, dl, MVT::i1,
01245                                       SDValue(Pd, 0), SDValue(NotPd, 0));
01246 
01247       // We have just built:
01248       // Rs = Pd
01249       // Pd = xor(not(Pd), Pd)
01250 
01251       ReplaceUses(N, Result);
01252       return Result;
01253     }
01254   }
01255 
01256   return SelectCode(N);
01257 }
01258 
01259 
01260 //
01261 // Map add followed by a asr -> asr +=.
01262 //
01263 SDNode *HexagonDAGToDAGISel::SelectAdd(SDNode *N) {
01264   SDLoc dl(N);
01265   if (N->getValueType(0) != MVT::i32) {
01266     return SelectCode(N);
01267   }
01268   // Identify nodes of the form: add(asr(...)).
01269   SDNode* Src1 = N->getOperand(0).getNode();
01270   if (Src1->getOpcode() != ISD::SRA || !Src1->hasOneUse()
01271       || Src1->getValueType(0) != MVT::i32) {
01272     return SelectCode(N);
01273   }
01274 
01275   // Build Rd = Rd' + asr(Rs, Rt). The machine constraints will ensure that
01276   // Rd and Rd' are assigned to the same register
01277   SDNode* Result = CurDAG->getMachineNode(Hexagon::S2_asr_r_r_acc, dl, MVT::i32,
01278                                           N->getOperand(1),
01279                                           Src1->getOperand(0),
01280                                           Src1->getOperand(1));
01281   ReplaceUses(N, Result);
01282 
01283   return Result;
01284 }
01285 
01286 
01287 SDNode *HexagonDAGToDAGISel::Select(SDNode *N) {
01288   if (N->isMachineOpcode()) {
01289     N->setNodeId(-1);
01290     return nullptr;   // Already selected.
01291   }
01292 
01293 
01294   switch (N->getOpcode()) {
01295   case ISD::Constant:
01296     return SelectConstant(N);
01297 
01298   case ISD::ConstantFP:
01299     return SelectConstantFP(N);
01300 
01301   case ISD::ADD:
01302     return SelectAdd(N);
01303 
01304   case ISD::SHL:
01305     return SelectSHL(N);
01306 
01307   case ISD::LOAD:
01308     return SelectLoad(N);
01309 
01310   case ISD::STORE:
01311     return SelectStore(N);
01312 
01313   case ISD::SELECT:
01314     return SelectSelect(N);
01315 
01316   case ISD::TRUNCATE:
01317     return SelectTruncate(N);
01318 
01319   case ISD::MUL:
01320     return SelectMul(N);
01321 
01322   case ISD::ZERO_EXTEND:
01323     return SelectZeroExtend(N);
01324 
01325   case ISD::INTRINSIC_WO_CHAIN:
01326     return SelectIntrinsicWOChain(N);
01327   }
01328 
01329   return SelectCode(N);
01330 }
01331 
01332 
01333 //
01334 // Hexagon_TODO: Five functions for ADDRri?! Surely there must be a better way
01335 // to define these instructions.
01336 //
01337 bool HexagonDAGToDAGISel::SelectADDRri(SDValue& Addr, SDValue &Base,
01338                                        SDValue &Offset) {
01339   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
01340       Addr.getOpcode() == ISD::TargetGlobalAddress)
01341     return false;  // Direct calls.
01342 
01343   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
01344     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
01345     Offset = CurDAG->getTargetConstant(0, MVT::i32);
01346     return true;
01347   }
01348   Base = Addr;
01349   Offset = CurDAG->getTargetConstant(0, MVT::i32);
01350   return true;
01351 }
01352 
01353 
01354 bool HexagonDAGToDAGISel::SelectADDRriS11_0(SDValue& Addr, SDValue &Base,
01355                                             SDValue &Offset) {
01356   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
01357       Addr.getOpcode() == ISD::TargetGlobalAddress)
01358     return false;  // Direct calls.
01359 
01360   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
01361     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
01362     Offset = CurDAG->getTargetConstant(0, MVT::i32);
01363     return (IsS11_0_Offset(Offset.getNode()));
01364   }
01365   Base = Addr;
01366   Offset = CurDAG->getTargetConstant(0, MVT::i32);
01367   return (IsS11_0_Offset(Offset.getNode()));
01368 }
01369 
01370 
01371 bool HexagonDAGToDAGISel::SelectADDRriS11_1(SDValue& Addr, SDValue &Base,
01372                                             SDValue &Offset) {
01373   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
01374       Addr.getOpcode() == ISD::TargetGlobalAddress)
01375     return false;  // Direct calls.
01376 
01377   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
01378     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
01379     Offset = CurDAG->getTargetConstant(0, MVT::i32);
01380     return (IsS11_1_Offset(Offset.getNode()));
01381   }
01382   Base = Addr;
01383   Offset = CurDAG->getTargetConstant(0, MVT::i32);
01384   return (IsS11_1_Offset(Offset.getNode()));
01385 }
01386 
01387 
01388 bool HexagonDAGToDAGISel::SelectADDRriS11_2(SDValue& Addr, SDValue &Base,
01389                                             SDValue &Offset) {
01390   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
01391       Addr.getOpcode() == ISD::TargetGlobalAddress)
01392     return false;  // Direct calls.
01393 
01394   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
01395     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
01396     Offset = CurDAG->getTargetConstant(0, MVT::i32);
01397     return (IsS11_2_Offset(Offset.getNode()));
01398   }
01399   Base = Addr;
01400   Offset = CurDAG->getTargetConstant(0, MVT::i32);
01401   return (IsS11_2_Offset(Offset.getNode()));
01402 }
01403 
01404 
01405 bool HexagonDAGToDAGISel::SelectADDRriU6_0(SDValue& Addr, SDValue &Base,
01406                                             SDValue &Offset) {
01407   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
01408       Addr.getOpcode() == ISD::TargetGlobalAddress)
01409     return false;  // Direct calls.
01410 
01411   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
01412     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
01413     Offset = CurDAG->getTargetConstant(0, MVT::i32);
01414     return (IsU6_0_Offset(Offset.getNode()));
01415   }
01416   Base = Addr;
01417   Offset = CurDAG->getTargetConstant(0, MVT::i32);
01418   return (IsU6_0_Offset(Offset.getNode()));
01419 }
01420 
01421 
01422 bool HexagonDAGToDAGISel::SelectADDRriU6_1(SDValue& Addr, SDValue &Base,
01423                                             SDValue &Offset) {
01424   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
01425       Addr.getOpcode() == ISD::TargetGlobalAddress)
01426     return false;  // Direct calls.
01427 
01428   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
01429     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
01430     Offset = CurDAG->getTargetConstant(0, MVT::i32);
01431     return (IsU6_1_Offset(Offset.getNode()));
01432   }
01433   Base = Addr;
01434   Offset = CurDAG->getTargetConstant(0, MVT::i32);
01435   return (IsU6_1_Offset(Offset.getNode()));
01436 }
01437 
01438 
01439 bool HexagonDAGToDAGISel::SelectADDRriU6_2(SDValue& Addr, SDValue &Base,
01440                                             SDValue &Offset) {
01441   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
01442       Addr.getOpcode() == ISD::TargetGlobalAddress)
01443     return false;  // Direct calls.
01444 
01445   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
01446     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
01447     Offset = CurDAG->getTargetConstant(0, MVT::i32);
01448     return (IsU6_2_Offset(Offset.getNode()));
01449   }
01450   Base = Addr;
01451   Offset = CurDAG->getTargetConstant(0, MVT::i32);
01452   return (IsU6_2_Offset(Offset.getNode()));
01453 }
01454 
01455 
01456 bool HexagonDAGToDAGISel::SelectMEMriS11_2(SDValue& Addr, SDValue &Base,
01457                                            SDValue &Offset) {
01458 
01459   if (Addr.getOpcode() != ISD::ADD) {
01460     return(SelectADDRriS11_2(Addr, Base, Offset));
01461   }
01462 
01463   return SelectADDRriS11_2(Addr, Base, Offset);
01464 }
01465 
01466 
01467 bool HexagonDAGToDAGISel::SelectADDRriS11_3(SDValue& Addr, SDValue &Base,
01468                                             SDValue &Offset) {
01469   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
01470       Addr.getOpcode() == ISD::TargetGlobalAddress)
01471     return false;  // Direct calls.
01472 
01473   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
01474     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
01475     Offset = CurDAG->getTargetConstant(0, MVT::i32);
01476     return (IsS11_3_Offset(Offset.getNode()));
01477   }
01478   Base = Addr;
01479   Offset = CurDAG->getTargetConstant(0, MVT::i32);
01480   return (IsS11_3_Offset(Offset.getNode()));
01481 }
01482 
01483 bool HexagonDAGToDAGISel::SelectADDRrr(SDValue &Addr, SDValue &R1,
01484                                        SDValue &R2) {
01485   if (Addr.getOpcode() == ISD::FrameIndex) return false;
01486   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
01487       Addr.getOpcode() == ISD::TargetGlobalAddress)
01488     return false;  // Direct calls.
01489 
01490   if (Addr.getOpcode() == ISD::ADD) {
01491     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
01492       if (isInt<13>(CN->getSExtValue()))
01493         return false;  // Let the reg+imm pattern catch this!
01494     R1 = Addr.getOperand(0);
01495     R2 = Addr.getOperand(1);
01496     return true;
01497   }
01498 
01499   R1 = Addr;
01500 
01501   return true;
01502 }
01503 
01504 
01505 // Handle generic address case. It is accessed from inlined asm =m constraints,
01506 // which could have any kind of pointer.
01507 bool HexagonDAGToDAGISel::SelectAddr(SDNode *Op, SDValue Addr,
01508                                           SDValue &Base, SDValue &Offset) {
01509   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
01510       Addr.getOpcode() == ISD::TargetGlobalAddress)
01511     return false;  // Direct calls.
01512 
01513   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
01514     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
01515     Offset = CurDAG->getTargetConstant(0, MVT::i32);
01516     return true;
01517   }
01518 
01519   if (Addr.getOpcode() == ISD::ADD) {
01520     Base = Addr.getOperand(0);
01521     Offset = Addr.getOperand(1);
01522     return true;
01523   }
01524 
01525   Base = Addr;
01526   Offset = CurDAG->getTargetConstant(0, MVT::i32);
01527   return true;
01528 }
01529 
01530 
01531 bool HexagonDAGToDAGISel::
01532 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
01533                              std::vector<SDValue> &OutOps) {
01534   SDValue Op0, Op1;
01535 
01536   switch (ConstraintCode) {
01537   case 'o':   // Offsetable.
01538   case 'v':   // Not offsetable.
01539   default: return true;
01540   case 'm':   // Memory.
01541     if (!SelectAddr(Op.getNode(), Op, Op0, Op1))
01542       return true;
01543     break;
01544   }
01545 
01546   OutOps.push_back(Op0);
01547   OutOps.push_back(Op1);
01548   return false;
01549 }
01550 
01551 bool HexagonDAGToDAGISel::isConstExtProfitable(SDNode *N) const {
01552   unsigned UseCount = 0;
01553   for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
01554     UseCount++;
01555   }
01556 
01557   return (UseCount <= 1);
01558 
01559 }
01560 
01561 //===--------------------------------------------------------------------===//
01562 // Return 'true' if use count of the global address is below threshold.
01563 //===--------------------------------------------------------------------===//
01564 bool HexagonDAGToDAGISel::hasNumUsesBelowThresGA(SDNode *N) const {
01565   assert(N->getOpcode() == ISD::TargetGlobalAddress &&
01566          "Expecting a target global address");
01567 
01568   // Always try to fold the address.
01569   if (TM.getOptLevel() == CodeGenOpt::Aggressive)
01570     return true;
01571 
01572   GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
01573   DenseMap<const GlobalValue *, unsigned>::const_iterator GI =
01574     GlobalAddressUseCountMap.find(GA->getGlobal());
01575 
01576   if (GI == GlobalAddressUseCountMap.end())
01577     return false;
01578 
01579   return GI->second <= MaxNumOfUsesForConstExtenders;
01580 }
01581 
01582 //===--------------------------------------------------------------------===//
01583 // Return true if the non-GP-relative global address can be folded.
01584 //===--------------------------------------------------------------------===//
01585 inline bool HexagonDAGToDAGISel::foldGlobalAddress(SDValue &N, SDValue &R) {
01586   return foldGlobalAddressImpl(N, R, false);
01587 }
01588 
01589 //===--------------------------------------------------------------------===//
01590 // Return true if the GP-relative global address can be folded.
01591 //===--------------------------------------------------------------------===//
01592 inline bool HexagonDAGToDAGISel::foldGlobalAddressGP(SDValue &N, SDValue &R) {
01593   return foldGlobalAddressImpl(N, R, true);
01594 }
01595 
01596 //===--------------------------------------------------------------------===//
01597 // Fold offset of the global address if number of uses are below threshold.
01598 //===--------------------------------------------------------------------===//
01599 bool HexagonDAGToDAGISel::foldGlobalAddressImpl(SDValue &N, SDValue &R,
01600                                                 bool ShouldLookForGP) {
01601   if (N.getOpcode() == ISD::ADD) {
01602     SDValue N0 = N.getOperand(0);
01603     SDValue N1 = N.getOperand(1);
01604     if ((ShouldLookForGP && (N0.getOpcode() == HexagonISD::CONST32_GP)) ||
01605         (!ShouldLookForGP && (N0.getOpcode() == HexagonISD::CONST32))) {
01606       ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N1);
01607       GlobalAddressSDNode *GA =
01608         dyn_cast<GlobalAddressSDNode>(N0.getOperand(0));
01609 
01610       if (Const && GA &&
01611           (GA->getOpcode() == ISD::TargetGlobalAddress)) {
01612         if ((N0.getOpcode() == HexagonISD::CONST32) &&
01613                 !hasNumUsesBelowThresGA(GA))
01614             return false;
01615         R = CurDAG->getTargetGlobalAddress(GA->getGlobal(),
01616                                           SDLoc(Const),
01617                                           N.getValueType(),
01618                                           GA->getOffset() +
01619                                           (uint64_t)Const->getSExtValue());
01620         return true;
01621       }
01622     }
01623   }
01624   return false;
01625 }
01626 
01627 bool HexagonDAGToDAGISel::SelectAddrFI(SDValue& N, SDValue &R) {
01628   if (N.getOpcode() != ISD::FrameIndex)
01629     return false;
01630   FrameIndexSDNode *FX = cast<FrameIndexSDNode>(N);
01631   R = CurDAG->getTargetFrameIndex(FX->getIndex(), MVT::i32);
01632   return true;
01633 }
01634 
01635 inline bool HexagonDAGToDAGISel::SelectAddrGA(SDValue &N, SDValue &R) {
01636   return SelectGlobalAddress(N, R, false);
01637 }
01638 
01639 inline bool HexagonDAGToDAGISel::SelectAddrGP(SDValue &N, SDValue &R) {
01640   return SelectGlobalAddress(N, R, true);
01641 }
01642 
01643 bool HexagonDAGToDAGISel::SelectGlobalAddress(SDValue &N, SDValue &R,
01644                                               bool UseGP) {
01645   switch (N.getOpcode()) {
01646   case ISD::ADD: {
01647     SDValue N0 = N.getOperand(0);
01648     SDValue N1 = N.getOperand(1);
01649     unsigned GAOpc = N0.getOpcode();
01650     if (UseGP && GAOpc != HexagonISD::CONST32_GP)
01651       return false;
01652     if (!UseGP && GAOpc != HexagonISD::CONST32)
01653       return false;
01654     if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N1)) {
01655       SDValue Addr = N0.getOperand(0);
01656       if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Addr)) {
01657         if (GA->getOpcode() == ISD::TargetGlobalAddress) {
01658           uint64_t NewOff = GA->getOffset() + (uint64_t)Const->getSExtValue();
01659           R = CurDAG->getTargetGlobalAddress(GA->getGlobal(), SDLoc(Const),
01660                                              N.getValueType(), NewOff);
01661           return true;
01662         }
01663       }
01664     }
01665     break;
01666   }
01667   case HexagonISD::CONST32:
01668     // The operand(0) of CONST32 is TargetGlobalAddress, which is what we
01669     // want in the instruction.
01670     if (!UseGP)
01671       R = N.getOperand(0);
01672     return !UseGP;
01673   case HexagonISD::CONST32_GP:
01674     if (UseGP)
01675       R = N.getOperand(0);
01676     return UseGP;
01677   default:
01678     return false;
01679   }
01680 
01681   return false;
01682 }
01683 
01684 bool HexagonDAGToDAGISel::isValueExtension(SDValue const &Val,
01685                                            unsigned FromBits, SDValue &Src) {
01686   unsigned Opc = Val.getOpcode();
01687   switch (Opc) {
01688   case ISD::SIGN_EXTEND:
01689   case ISD::ZERO_EXTEND:
01690   case ISD::ANY_EXTEND: {
01691     SDValue const &Op0 = Val.getOperand(0);
01692     EVT T = Op0.getValueType();
01693     if (T.isInteger() && T.getSizeInBits() == FromBits) {
01694       Src = Op0;
01695       return true;
01696     }
01697     break;
01698   }
01699   case ISD::SIGN_EXTEND_INREG:
01700   case ISD::AssertSext:
01701   case ISD::AssertZext:
01702     if (Val.getOperand(0).getValueType().isInteger()) {
01703       VTSDNode *T = cast<VTSDNode>(Val.getOperand(1));
01704       if (T->getVT().getSizeInBits() == FromBits) {
01705         Src = Val.getOperand(0);
01706         return true;
01707       }
01708     }
01709     break;
01710   case ISD::AND: {
01711     // Check if this is an AND with "FromBits" of lower bits set to 1.
01712     uint64_t FromMask = (1 << FromBits) - 1;
01713     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(0))) {
01714       if (C->getZExtValue() == FromMask) {
01715         Src = Val.getOperand(1);
01716         return true;
01717       }
01718     }
01719     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(1))) {
01720       if (C->getZExtValue() == FromMask) {
01721         Src = Val.getOperand(0);
01722         return true;
01723       }
01724     }
01725     break;
01726   }
01727   case ISD::OR:
01728   case ISD::XOR: {
01729     // OR/XOR with the lower "FromBits" bits set to 0.
01730     uint64_t FromMask = (1 << FromBits) - 1;
01731     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(0))) {
01732       if ((C->getZExtValue() & FromMask) == 0) {
01733         Src = Val.getOperand(1);
01734         return true;
01735       }
01736     }
01737     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(1))) {
01738       if ((C->getZExtValue() & FromMask) == 0) {
01739         Src = Val.getOperand(0);
01740         return true;
01741       }
01742     }
01743   }
01744   default:
01745     break;
01746   }
01747   return false;
01748 }