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HexagonISelDAGToDAG.cpp
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00001 //===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file defines an instruction selector for the Hexagon target.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #define DEBUG_TYPE "hexagon-isel"
00015 #include "Hexagon.h"
00016 #include "HexagonISelLowering.h"
00017 #include "HexagonTargetMachine.h"
00018 #include "llvm/ADT/DenseMap.h"
00019 #include "llvm/CodeGen/SelectionDAGISel.h"
00020 #include "llvm/IR/Intrinsics.h"
00021 #include "llvm/Support/CommandLine.h"
00022 #include "llvm/Support/Compiler.h"
00023 #include "llvm/Support/Debug.h"
00024 using namespace llvm;
00025 
00026 static
00027 cl::opt<unsigned>
00028 MaxNumOfUsesForConstExtenders("ga-max-num-uses-for-constant-extenders",
00029   cl::Hidden, cl::init(2),
00030   cl::desc("Maximum number of uses of a global address such that we still us a"
00031            "constant extended instruction"));
00032 
00033 //===----------------------------------------------------------------------===//
00034 // Instruction Selector Implementation
00035 //===----------------------------------------------------------------------===//
00036 
00037 namespace llvm {
00038   void initializeHexagonDAGToDAGISelPass(PassRegistry&);
00039 }
00040 
00041 //===--------------------------------------------------------------------===//
00042 /// HexagonDAGToDAGISel - Hexagon specific code to select Hexagon machine
00043 /// instructions for SelectionDAG operations.
00044 ///
00045 namespace {
00046 class HexagonDAGToDAGISel : public SelectionDAGISel {
00047   /// Subtarget - Keep a pointer to the Hexagon Subtarget around so that we can
00048   /// make the right decision when generating code for different targets.
00049   const HexagonSubtarget &Subtarget;
00050 
00051   // Keep a reference to HexagonTargetMachine.
00052   const HexagonTargetMachine& TM;
00053   DenseMap<const GlobalValue *, unsigned> GlobalAddressUseCountMap;
00054 public:
00055   explicit HexagonDAGToDAGISel(HexagonTargetMachine &targetmachine,
00056                                CodeGenOpt::Level OptLevel)
00057     : SelectionDAGISel(targetmachine, OptLevel),
00058       Subtarget(targetmachine.getSubtarget<HexagonSubtarget>()),
00059       TM(targetmachine) {
00060     initializeHexagonDAGToDAGISelPass(*PassRegistry::getPassRegistry());
00061   }
00062   bool hasNumUsesBelowThresGA(SDNode *N) const;
00063 
00064   SDNode *Select(SDNode *N);
00065 
00066   // Complex Pattern Selectors.
00067   inline bool foldGlobalAddress(SDValue &N, SDValue &R);
00068   inline bool foldGlobalAddressGP(SDValue &N, SDValue &R);
00069   bool foldGlobalAddressImpl(SDValue &N, SDValue &R, bool ShouldLookForGP);
00070   bool SelectADDRri(SDValue& N, SDValue &R1, SDValue &R2);
00071   bool SelectADDRriS11_0(SDValue& N, SDValue &R1, SDValue &R2);
00072   bool SelectADDRriS11_1(SDValue& N, SDValue &R1, SDValue &R2);
00073   bool SelectADDRriS11_2(SDValue& N, SDValue &R1, SDValue &R2);
00074   bool SelectMEMriS11_2(SDValue& Addr, SDValue &Base, SDValue &Offset);
00075   bool SelectADDRriS11_3(SDValue& N, SDValue &R1, SDValue &R2);
00076   bool SelectADDRrr(SDValue &Addr, SDValue &Base, SDValue &Offset);
00077   bool SelectADDRriU6_0(SDValue& N, SDValue &R1, SDValue &R2);
00078   bool SelectADDRriU6_1(SDValue& N, SDValue &R1, SDValue &R2);
00079   bool SelectADDRriU6_2(SDValue& N, SDValue &R1, SDValue &R2);
00080 
00081   virtual const char *getPassName() const {
00082     return "Hexagon DAG->DAG Pattern Instruction Selection";
00083   }
00084 
00085   /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
00086   /// inline asm expressions.
00087   virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
00088                                             char ConstraintCode,
00089                                             std::vector<SDValue> &OutOps);
00090   bool SelectAddr(SDNode *Op, SDValue Addr, SDValue &Base, SDValue &Offset);
00091 
00092   SDNode *SelectLoad(SDNode *N);
00093   SDNode *SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl);
00094   SDNode *SelectIndexedLoad(LoadSDNode *LD, SDLoc dl);
00095   SDNode *SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
00096                                         SDLoc dl);
00097   SDNode *SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode,
00098                                         SDLoc dl);
00099   SDNode *SelectBaseOffsetStore(StoreSDNode *ST, SDLoc dl);
00100   SDNode *SelectIndexedStore(StoreSDNode *ST, SDLoc dl);
00101   SDNode *SelectStore(SDNode *N);
00102   SDNode *SelectSHL(SDNode *N);
00103   SDNode *SelectSelect(SDNode *N);
00104   SDNode *SelectTruncate(SDNode *N);
00105   SDNode *SelectMul(SDNode *N);
00106   SDNode *SelectZeroExtend(SDNode *N);
00107   SDNode *SelectIntrinsicWOChain(SDNode *N);
00108   SDNode *SelectIntrinsicWChain(SDNode *N);
00109   SDNode *SelectConstant(SDNode *N);
00110   SDNode *SelectConstantFP(SDNode *N);
00111   SDNode *SelectAdd(SDNode *N);
00112   bool isConstExtProfitable(SDNode *N) const;
00113 
00114 // XformMskToBitPosU5Imm - Returns the bit position which
00115 // the single bit 32 bit mask represents.
00116 // Used in Clr and Set bit immediate memops.
00117 SDValue XformMskToBitPosU5Imm(uint32_t Imm) {
00118   int32_t bitPos;
00119   bitPos = Log2_32(Imm);
00120   assert(bitPos >= 0 && bitPos < 32 &&
00121          "Constant out of range for 32 BitPos Memops");
00122   return CurDAG->getTargetConstant(bitPos, MVT::i32);
00123 }
00124 
00125 // XformMskToBitPosU4Imm - Returns the bit position which the single bit 16 bit
00126 // mask represents. Used in Clr and Set bit immediate memops.
00127 SDValue XformMskToBitPosU4Imm(uint16_t Imm) {
00128   return XformMskToBitPosU5Imm(Imm);
00129 }
00130 
00131 // XformMskToBitPosU3Imm - Returns the bit position which the single bit 8 bit
00132 // mask represents. Used in Clr and Set bit immediate memops.
00133 SDValue XformMskToBitPosU3Imm(uint8_t Imm) {
00134   return XformMskToBitPosU5Imm(Imm);
00135 }
00136 
00137 // Return true if there is exactly one bit set in V, i.e., if V is one of the
00138 // following integers: 2^0, 2^1, ..., 2^31.
00139 bool ImmIsSingleBit(uint32_t v) const {
00140   uint32_t c = CountPopulation_64(v);
00141   // Only return true if we counted 1 bit.
00142   return c == 1;
00143 }
00144 
00145 // XformM5ToU5Imm - Return a target constant with the specified value, of type
00146 // i32 where the negative literal is transformed into a positive literal for
00147 // use in -= memops.
00148 inline SDValue XformM5ToU5Imm(signed Imm) {
00149    assert( (Imm >= -31 && Imm <= -1)  && "Constant out of range for Memops");
00150    return CurDAG->getTargetConstant( - Imm, MVT::i32);
00151 }
00152 
00153 
00154 // XformU7ToU7M1Imm - Return a target constant decremented by 1, in range
00155 // [1..128], used in cmpb.gtu instructions.
00156 inline SDValue XformU7ToU7M1Imm(signed Imm) {
00157   assert((Imm >= 1 && Imm <= 128) && "Constant out of range for cmpb op");
00158   return CurDAG->getTargetConstant(Imm - 1, MVT::i8);
00159 }
00160 
00161 // XformS8ToS8M1Imm - Return a target constant decremented by 1.
00162 inline SDValue XformSToSM1Imm(signed Imm) {
00163   return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
00164 }
00165 
00166 // XformU8ToU8M1Imm - Return a target constant decremented by 1.
00167 inline SDValue XformUToUM1Imm(unsigned Imm) {
00168   assert((Imm >= 1) && "Cannot decrement unsigned int less than 1");
00169   return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
00170 }
00171 
00172 // Include the pieces autogenerated from the target description.
00173 #include "HexagonGenDAGISel.inc"
00174 };
00175 }  // end anonymous namespace
00176 
00177 
00178 /// createHexagonISelDag - This pass converts a legalized DAG into a
00179 /// Hexagon-specific DAG, ready for instruction scheduling.
00180 ///
00181 FunctionPass *llvm::createHexagonISelDag(HexagonTargetMachine &TM,
00182                                          CodeGenOpt::Level OptLevel) {
00183   return new HexagonDAGToDAGISel(TM, OptLevel);
00184 }
00185 
00186 static void initializePassOnce(PassRegistry &Registry) {
00187   const char *Name = "Hexagon DAG->DAG Pattern Instruction Selection";
00188   PassInfo *PI = new PassInfo(Name, "hexagon-isel",
00189                               &SelectionDAGISel::ID, 0, false, false);
00190   Registry.registerPass(*PI, true);
00191 }
00192 
00193 void llvm::initializeHexagonDAGToDAGISelPass(PassRegistry &Registry) {
00194   CALL_ONCE_INITIALIZATION(initializePassOnce)
00195 }
00196 
00197 
00198 static bool IsS11_0_Offset(SDNode * S) {
00199     ConstantSDNode *N = cast<ConstantSDNode>(S);
00200 
00201   // immS16 predicate - True if the immediate fits in a 16-bit sign extended
00202   // field.
00203   int64_t v = (int64_t)N->getSExtValue();
00204   return isInt<11>(v);
00205 }
00206 
00207 
00208 static bool IsS11_1_Offset(SDNode * S) {
00209     ConstantSDNode *N = cast<ConstantSDNode>(S);
00210 
00211   // immS16 predicate - True if the immediate fits in a 16-bit sign extended
00212   // field.
00213   int64_t v = (int64_t)N->getSExtValue();
00214   return isShiftedInt<11,1>(v);
00215 }
00216 
00217 
00218 static bool IsS11_2_Offset(SDNode * S) {
00219     ConstantSDNode *N = cast<ConstantSDNode>(S);
00220 
00221   // immS16 predicate - True if the immediate fits in a 16-bit sign extended
00222   // field.
00223   int64_t v = (int64_t)N->getSExtValue();
00224   return isShiftedInt<11,2>(v);
00225 }
00226 
00227 
00228 static bool IsS11_3_Offset(SDNode * S) {
00229     ConstantSDNode *N = cast<ConstantSDNode>(S);
00230 
00231   // immS16 predicate - True if the immediate fits in a 16-bit sign extended
00232   // field.
00233   int64_t v = (int64_t)N->getSExtValue();
00234   return isShiftedInt<11,3>(v);
00235 }
00236 
00237 
00238 static bool IsU6_0_Offset(SDNode * S) {
00239     ConstantSDNode *N = cast<ConstantSDNode>(S);
00240 
00241   // u6 predicate - True if the immediate fits in a 6-bit unsigned extended
00242   // field.
00243   int64_t v = (int64_t)N->getSExtValue();
00244   return isUInt<6>(v);
00245 }
00246 
00247 
00248 static bool IsU6_1_Offset(SDNode * S) {
00249     ConstantSDNode *N = cast<ConstantSDNode>(S);
00250 
00251   // u6 predicate - True if the immediate fits in a 6-bit unsigned extended
00252   // field.
00253   int64_t v = (int64_t)N->getSExtValue();
00254   return isShiftedUInt<6,1>(v);
00255 }
00256 
00257 
00258 static bool IsU6_2_Offset(SDNode * S) {
00259     ConstantSDNode *N = cast<ConstantSDNode>(S);
00260 
00261   // u6 predicate - True if the immediate fits in a 6-bit unsigned extended
00262   // field.
00263   int64_t v = (int64_t)N->getSExtValue();
00264   return isShiftedUInt<6,2>(v);
00265 }
00266 
00267 
00268 // Intrinsics that return a a predicate.
00269 static unsigned doesIntrinsicReturnPredicate(unsigned ID)
00270 {
00271   switch (ID) {
00272     default:
00273       return 0;
00274     case Intrinsic::hexagon_C2_cmpeq:
00275     case Intrinsic::hexagon_C2_cmpgt:
00276     case Intrinsic::hexagon_C2_cmpgtu:
00277     case Intrinsic::hexagon_C2_cmpgtup:
00278     case Intrinsic::hexagon_C2_cmpgtp:
00279     case Intrinsic::hexagon_C2_cmpeqp:
00280     case Intrinsic::hexagon_C2_bitsset:
00281     case Intrinsic::hexagon_C2_bitsclr:
00282     case Intrinsic::hexagon_C2_cmpeqi:
00283     case Intrinsic::hexagon_C2_cmpgti:
00284     case Intrinsic::hexagon_C2_cmpgtui:
00285     case Intrinsic::hexagon_C2_cmpgei:
00286     case Intrinsic::hexagon_C2_cmpgeui:
00287     case Intrinsic::hexagon_C2_cmplt:
00288     case Intrinsic::hexagon_C2_cmpltu:
00289     case Intrinsic::hexagon_C2_bitsclri:
00290     case Intrinsic::hexagon_C2_and:
00291     case Intrinsic::hexagon_C2_or:
00292     case Intrinsic::hexagon_C2_xor:
00293     case Intrinsic::hexagon_C2_andn:
00294     case Intrinsic::hexagon_C2_not:
00295     case Intrinsic::hexagon_C2_orn:
00296     case Intrinsic::hexagon_C2_pxfer_map:
00297     case Intrinsic::hexagon_C2_any8:
00298     case Intrinsic::hexagon_C2_all8:
00299     case Intrinsic::hexagon_A2_vcmpbeq:
00300     case Intrinsic::hexagon_A2_vcmpbgtu:
00301     case Intrinsic::hexagon_A2_vcmpheq:
00302     case Intrinsic::hexagon_A2_vcmphgt:
00303     case Intrinsic::hexagon_A2_vcmphgtu:
00304     case Intrinsic::hexagon_A2_vcmpweq:
00305     case Intrinsic::hexagon_A2_vcmpwgt:
00306     case Intrinsic::hexagon_A2_vcmpwgtu:
00307     case Intrinsic::hexagon_C2_tfrrp:
00308     case Intrinsic::hexagon_S2_tstbit_i:
00309     case Intrinsic::hexagon_S2_tstbit_r:
00310       return 1;
00311   }
00312 }
00313 
00314 
00315 // Intrinsics that have predicate operands.
00316 static unsigned doesIntrinsicContainPredicate(unsigned ID)
00317 {
00318   switch (ID) {
00319     default:
00320       return 0;
00321     case Intrinsic::hexagon_C2_tfrpr:
00322       return Hexagon::TFR_RsPd;
00323     case Intrinsic::hexagon_C2_and:
00324       return Hexagon::AND_pp;
00325     case Intrinsic::hexagon_C2_xor:
00326       return Hexagon::XOR_pp;
00327     case Intrinsic::hexagon_C2_or:
00328       return Hexagon::OR_pp;
00329     case Intrinsic::hexagon_C2_not:
00330       return Hexagon::NOT_p;
00331     case Intrinsic::hexagon_C2_any8:
00332       return Hexagon::ANY_pp;
00333     case Intrinsic::hexagon_C2_all8:
00334       return Hexagon::ALL_pp;
00335     case Intrinsic::hexagon_C2_vitpack:
00336       return Hexagon::VITPACK_pp;
00337     case Intrinsic::hexagon_C2_mask:
00338       return Hexagon::MASK_p;
00339     case Intrinsic::hexagon_C2_mux:
00340       return Hexagon::MUX_rr;
00341 
00342       // Mapping hexagon_C2_muxir to MUX_pri.  This is pretty weird - but
00343       // that's how it's mapped in q6protos.h.
00344     case Intrinsic::hexagon_C2_muxir:
00345       return Hexagon::MUX_ri;
00346 
00347       // Mapping hexagon_C2_muxri to MUX_pir.  This is pretty weird - but
00348       // that's how it's mapped in q6protos.h.
00349     case Intrinsic::hexagon_C2_muxri:
00350       return Hexagon::MUX_ir;
00351 
00352     case Intrinsic::hexagon_C2_muxii:
00353       return Hexagon::MUX_ii;
00354     case Intrinsic::hexagon_C2_vmux:
00355       return Hexagon::VMUX_prr64;
00356     case Intrinsic::hexagon_S2_valignrb:
00357       return Hexagon::VALIGN_rrp;
00358     case Intrinsic::hexagon_S2_vsplicerb:
00359       return Hexagon::VSPLICE_rrp;
00360   }
00361 }
00362 
00363 
00364 static bool OffsetFitsS11(EVT MemType, int64_t Offset) {
00365   if (MemType == MVT::i64 && isShiftedInt<11,3>(Offset)) {
00366     return true;
00367   }
00368   if (MemType == MVT::i32 && isShiftedInt<11,2>(Offset)) {
00369     return true;
00370   }
00371   if (MemType == MVT::i16 && isShiftedInt<11,1>(Offset)) {
00372     return true;
00373   }
00374   if (MemType == MVT::i8 && isInt<11>(Offset)) {
00375     return true;
00376   }
00377   return false;
00378 }
00379 
00380 
00381 //
00382 // Try to lower loads of GlobalAdresses into base+offset loads.  Custom
00383 // lowering for GlobalAddress nodes has already turned it into a
00384 // CONST32.
00385 //
00386 SDNode *HexagonDAGToDAGISel::SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl) {
00387   SDValue Chain = LD->getChain();
00388   SDNode* Const32 = LD->getBasePtr().getNode();
00389   unsigned Opcode = 0;
00390 
00391   if (Const32->getOpcode() == HexagonISD::CONST32 &&
00392       ISD::isNormalLoad(LD)) {
00393     SDValue Base = Const32->getOperand(0);
00394     EVT LoadedVT = LD->getMemoryVT();
00395     int64_t Offset = cast<GlobalAddressSDNode>(Base)->getOffset();
00396     if (Offset != 0 && OffsetFitsS11(LoadedVT, Offset)) {
00397       MVT PointerTy = getTargetLowering()->getPointerTy();
00398       const GlobalValue* GV =
00399         cast<GlobalAddressSDNode>(Base)->getGlobal();
00400       SDValue TargAddr =
00401         CurDAG->getTargetGlobalAddress(GV, dl, PointerTy, 0);
00402       SDNode* NewBase = CurDAG->getMachineNode(Hexagon::CONST32_set,
00403                                                dl, PointerTy,
00404                                                TargAddr);
00405       // Figure out base + offset opcode
00406       if (LoadedVT == MVT::i64) Opcode = Hexagon::LDrid_indexed;
00407       else if (LoadedVT == MVT::i32) Opcode = Hexagon::LDriw_indexed;
00408       else if (LoadedVT == MVT::i16) Opcode = Hexagon::LDrih_indexed;
00409       else if (LoadedVT == MVT::i8) Opcode = Hexagon::LDrib_indexed;
00410       else llvm_unreachable("unknown memory type");
00411 
00412       // Build indexed load.
00413       SDValue TargetConstOff = CurDAG->getTargetConstant(Offset, PointerTy);
00414       SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
00415                                               LD->getValueType(0),
00416                                               MVT::Other,
00417                                               SDValue(NewBase,0),
00418                                               TargetConstOff,
00419                                               Chain);
00420       MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00421       MemOp[0] = LD->getMemOperand();
00422       cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
00423       ReplaceUses(LD, Result);
00424       return Result;
00425     }
00426   }
00427 
00428   return SelectCode(LD);
00429 }
00430 
00431 
00432 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
00433                                                            unsigned Opcode,
00434                                                            SDLoc dl)
00435 {
00436   SDValue Chain = LD->getChain();
00437   EVT LoadedVT = LD->getMemoryVT();
00438   SDValue Base = LD->getBasePtr();
00439   SDValue Offset = LD->getOffset();
00440   SDNode *OffsetNode = Offset.getNode();
00441   int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
00442   SDValue N1 = LD->getOperand(1);
00443   SDValue CPTmpN1_0;
00444   SDValue CPTmpN1_1;
00445 
00446   if (SelectADDRriS11_2(N1, CPTmpN1_0, CPTmpN1_1) &&
00447       N1.getNode()->getValueType(0) == MVT::i32) {
00448     const HexagonInstrInfo *TII =
00449       static_cast<const HexagonInstrInfo*>(TM.getInstrInfo());
00450     if (TII->isValidAutoIncImm(LoadedVT, Val)) {
00451       SDValue TargetConst = CurDAG->getTargetConstant(Val, MVT::i32);
00452       SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32,
00453                                                 MVT::Other, Base, TargetConst,
00454                                                 Chain);
00455       SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::SXTW, dl, MVT::i64,
00456                                                 SDValue(Result_1, 0));
00457       MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00458       MemOp[0] = LD->getMemOperand();
00459       cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00460       const SDValue Froms[] = { SDValue(LD, 0),
00461                                 SDValue(LD, 1),
00462                                 SDValue(LD, 2)
00463       };
00464       const SDValue Tos[]   = { SDValue(Result_2, 0),
00465                                 SDValue(Result_1, 1),
00466                                 SDValue(Result_1, 2)
00467       };
00468       ReplaceUses(Froms, Tos, 3);
00469       return Result_2;
00470     }
00471     SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
00472     SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
00473     SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
00474                                               MVT::Other, Base, TargetConst0,
00475                                               Chain);
00476     SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::SXTW, dl,
00477                                                 MVT::i64, SDValue(Result_1, 0));
00478     SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::ADD_ri, dl,
00479                                               MVT::i32, Base, TargetConstVal,
00480                                                 SDValue(Result_1, 1));
00481     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00482     MemOp[0] = LD->getMemOperand();
00483     cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00484     const SDValue Froms[] = { SDValue(LD, 0),
00485                               SDValue(LD, 1),
00486                               SDValue(LD, 2)
00487     };
00488     const SDValue Tos[]   = { SDValue(Result_2, 0),
00489                               SDValue(Result_3, 0),
00490                               SDValue(Result_1, 1)
00491     };
00492     ReplaceUses(Froms, Tos, 3);
00493     return Result_2;
00494   }
00495   return SelectCode(LD);
00496 }
00497 
00498 
00499 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
00500                                                            unsigned Opcode,
00501                                                            SDLoc dl)
00502 {
00503   SDValue Chain = LD->getChain();
00504   EVT LoadedVT = LD->getMemoryVT();
00505   SDValue Base = LD->getBasePtr();
00506   SDValue Offset = LD->getOffset();
00507   SDNode *OffsetNode = Offset.getNode();
00508   int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
00509   SDValue N1 = LD->getOperand(1);
00510   SDValue CPTmpN1_0;
00511   SDValue CPTmpN1_1;
00512 
00513   if (SelectADDRriS11_2(N1, CPTmpN1_0, CPTmpN1_1) &&
00514       N1.getNode()->getValueType(0) == MVT::i32) {
00515     const HexagonInstrInfo *TII =
00516       static_cast<const HexagonInstrInfo*>(TM.getInstrInfo());
00517     if (TII->isValidAutoIncImm(LoadedVT, Val)) {
00518       SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
00519       SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
00520       SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
00521                                                 MVT::i32, MVT::Other, Base,
00522                                                 TargetConstVal, Chain);
00523       SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::TFRI, dl, MVT::i32,
00524                                                 TargetConst0);
00525       SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::COMBINE_rr, dl,
00526                                                 MVT::i64, MVT::Other,
00527                                                 SDValue(Result_2,0),
00528                                                 SDValue(Result_1,0));
00529       MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00530       MemOp[0] = LD->getMemOperand();
00531       cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00532       const SDValue Froms[] = { SDValue(LD, 0),
00533                                 SDValue(LD, 1),
00534                                 SDValue(LD, 2)
00535       };
00536       const SDValue Tos[]   = { SDValue(Result_3, 0),
00537                                 SDValue(Result_1, 1),
00538                                 SDValue(Result_1, 2)
00539       };
00540       ReplaceUses(Froms, Tos, 3);
00541       return Result_3;
00542     }
00543 
00544     // Generate an indirect load.
00545     SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
00546     SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
00547     SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
00548                                               MVT::Other,
00549                                               Base, TargetConst0, Chain);
00550     SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::TFRI, dl, MVT::i32,
00551                                               TargetConst0);
00552     SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::COMBINE_rr, dl,
00553                                               MVT::i64, MVT::Other,
00554                                               SDValue(Result_2,0),
00555                                               SDValue(Result_1,0));
00556     // Add offset to base.
00557     SDNode* Result_4 = CurDAG->getMachineNode(Hexagon::ADD_ri, dl, MVT::i32,
00558                                               Base, TargetConstVal,
00559                                               SDValue(Result_1, 1));
00560     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00561     MemOp[0] = LD->getMemOperand();
00562     cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00563     const SDValue Froms[] = { SDValue(LD, 0),
00564                               SDValue(LD, 1),
00565                               SDValue(LD, 2)
00566     };
00567     const SDValue Tos[]   = { SDValue(Result_3, 0), // Load value.
00568                               SDValue(Result_4, 0), // New address.
00569                               SDValue(Result_1, 1)
00570     };
00571     ReplaceUses(Froms, Tos, 3);
00572     return Result_3;
00573   }
00574 
00575   return SelectCode(LD);
00576 }
00577 
00578 
00579 SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
00580   SDValue Chain = LD->getChain();
00581   SDValue Base = LD->getBasePtr();
00582   SDValue Offset = LD->getOffset();
00583   SDNode *OffsetNode = Offset.getNode();
00584   // Get the constant value.
00585   int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
00586   EVT LoadedVT = LD->getMemoryVT();
00587   unsigned Opcode = 0;
00588 
00589   // Check for zero ext loads.
00590   bool zextval = (LD->getExtensionType() == ISD::ZEXTLOAD);
00591 
00592   // Figure out the opcode.
00593   const HexagonInstrInfo *TII =
00594     static_cast<const HexagonInstrInfo*>(TM.getInstrInfo());
00595   if (LoadedVT == MVT::i64) {
00596     if (TII->isValidAutoIncImm(LoadedVT, Val))
00597       Opcode = Hexagon::POST_LDrid;
00598     else
00599       Opcode = Hexagon::LDrid;
00600   } else if (LoadedVT == MVT::i32) {
00601     if (TII->isValidAutoIncImm(LoadedVT, Val))
00602       Opcode = Hexagon::POST_LDriw;
00603     else
00604       Opcode = Hexagon::LDriw;
00605   } else if (LoadedVT == MVT::i16) {
00606     if (TII->isValidAutoIncImm(LoadedVT, Val))
00607       Opcode = zextval ? Hexagon::POST_LDriuh : Hexagon::POST_LDrih;
00608     else
00609       Opcode = zextval ? Hexagon::LDriuh : Hexagon::LDrih;
00610   } else if (LoadedVT == MVT::i8) {
00611     if (TII->isValidAutoIncImm(LoadedVT, Val))
00612       Opcode = zextval ? Hexagon::POST_LDriub : Hexagon::POST_LDrib;
00613     else
00614       Opcode = zextval ? Hexagon::LDriub : Hexagon::LDrib;
00615   } else
00616     llvm_unreachable("unknown memory type");
00617 
00618   // For zero ext i64 loads, we need to add combine instructions.
00619   if (LD->getValueType(0) == MVT::i64 &&
00620       LD->getExtensionType() == ISD::ZEXTLOAD) {
00621     return SelectIndexedLoadZeroExtend64(LD, Opcode, dl);
00622   }
00623   if (LD->getValueType(0) == MVT::i64 &&
00624              LD->getExtensionType() == ISD::SEXTLOAD) {
00625     // Handle sign ext i64 loads.
00626     return SelectIndexedLoadSignExtend64(LD, Opcode, dl);
00627   }
00628   if (TII->isValidAutoIncImm(LoadedVT, Val)) {
00629     SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
00630     SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
00631                                             LD->getValueType(0),
00632                                             MVT::i32, MVT::Other, Base,
00633                                             TargetConstVal, Chain);
00634     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00635     MemOp[0] = LD->getMemOperand();
00636     cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
00637     const SDValue Froms[] = { SDValue(LD, 0),
00638                               SDValue(LD, 1),
00639                               SDValue(LD, 2)
00640     };
00641     const SDValue Tos[]   = { SDValue(Result, 0),
00642                               SDValue(Result, 1),
00643                               SDValue(Result, 2)
00644     };
00645     ReplaceUses(Froms, Tos, 3);
00646     return Result;
00647   } else {
00648     SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
00649     SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
00650     SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl,
00651                                               LD->getValueType(0),
00652                                               MVT::Other, Base, TargetConst0,
00653                                               Chain);
00654     SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::ADD_ri, dl, MVT::i32,
00655                                               Base, TargetConstVal,
00656                                               SDValue(Result_1, 1));
00657     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00658     MemOp[0] = LD->getMemOperand();
00659     cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00660     const SDValue Froms[] = { SDValue(LD, 0),
00661                               SDValue(LD, 1),
00662                               SDValue(LD, 2)
00663     };
00664     const SDValue Tos[]   = { SDValue(Result_1, 0),
00665                               SDValue(Result_2, 0),
00666                               SDValue(Result_1, 1)
00667     };
00668     ReplaceUses(Froms, Tos, 3);
00669     return Result_1;
00670   }
00671 }
00672 
00673 
00674 SDNode *HexagonDAGToDAGISel::SelectLoad(SDNode *N) {
00675   SDNode *result;
00676   SDLoc dl(N);
00677   LoadSDNode *LD = cast<LoadSDNode>(N);
00678   ISD::MemIndexedMode AM = LD->getAddressingMode();
00679 
00680   // Handle indexed loads.
00681   if (AM != ISD::UNINDEXED) {
00682     result = SelectIndexedLoad(LD, dl);
00683   } else {
00684     result = SelectBaseOffsetLoad(LD, dl);
00685   }
00686 
00687   return result;
00688 }
00689 
00690 
00691 SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) {
00692   SDValue Chain = ST->getChain();
00693   SDValue Base = ST->getBasePtr();
00694   SDValue Offset = ST->getOffset();
00695   SDValue Value = ST->getValue();
00696   SDNode *OffsetNode = Offset.getNode();
00697   // Get the constant value.
00698   int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
00699   EVT StoredVT = ST->getMemoryVT();
00700 
00701   // Offset value must be within representable range
00702   // and must have correct alignment properties.
00703   const HexagonInstrInfo *TII =
00704     static_cast<const HexagonInstrInfo*>(TM.getInstrInfo());
00705   if (TII->isValidAutoIncImm(StoredVT, Val)) {
00706     SDValue Ops[] = {Base, CurDAG->getTargetConstant(Val, MVT::i32), Value,
00707                      Chain};
00708     unsigned Opcode = 0;
00709 
00710     // Figure out the post inc version of opcode.
00711     if (StoredVT == MVT::i64) Opcode = Hexagon::POST_STdri;
00712     else if (StoredVT == MVT::i32) Opcode = Hexagon::POST_STwri;
00713     else if (StoredVT == MVT::i16) Opcode = Hexagon::POST_SThri;
00714     else if (StoredVT == MVT::i8) Opcode = Hexagon::POST_STbri;
00715     else llvm_unreachable("unknown memory type");
00716 
00717     // Build post increment store.
00718     SDNode* Result = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
00719                                             MVT::Other, Ops);
00720     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00721     MemOp[0] = ST->getMemOperand();
00722     cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
00723 
00724     ReplaceUses(ST, Result);
00725     ReplaceUses(SDValue(ST,1), SDValue(Result,1));
00726     return Result;
00727   }
00728 
00729   // Note: Order of operands matches the def of instruction:
00730   // def STrid : STInst<(outs), (ins MEMri:$addr, DoubleRegs:$src1), ...
00731   // and it differs for POST_ST* for instance.
00732   SDValue Ops[] = { Base, CurDAG->getTargetConstant(0, MVT::i32), Value,
00733                     Chain};
00734   unsigned Opcode = 0;
00735 
00736   // Figure out the opcode.
00737   if (StoredVT == MVT::i64) Opcode = Hexagon::STrid;
00738   else if (StoredVT == MVT::i32) Opcode = Hexagon::STriw_indexed;
00739   else if (StoredVT == MVT::i16) Opcode = Hexagon::STrih;
00740   else if (StoredVT == MVT::i8) Opcode = Hexagon::STrib;
00741   else llvm_unreachable("unknown memory type");
00742 
00743   // Build regular store.
00744   SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
00745   SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
00746   // Build splitted incriment instruction.
00747   SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::ADD_ri, dl, MVT::i32,
00748                                             Base,
00749                                             TargetConstVal,
00750                                             SDValue(Result_1, 0));
00751   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00752   MemOp[0] = ST->getMemOperand();
00753   cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00754 
00755   ReplaceUses(SDValue(ST,0), SDValue(Result_2,0));
00756   ReplaceUses(SDValue(ST,1), SDValue(Result_1,0));
00757   return Result_2;
00758 }
00759 
00760 
00761 SDNode *HexagonDAGToDAGISel::SelectBaseOffsetStore(StoreSDNode *ST,
00762                                                    SDLoc dl) {
00763   SDValue Chain = ST->getChain();
00764   SDNode* Const32 = ST->getBasePtr().getNode();
00765   SDValue Value = ST->getValue();
00766   unsigned Opcode = 0;
00767 
00768   // Try to lower stores of GlobalAdresses into indexed stores.  Custom
00769   // lowering for GlobalAddress nodes has already turned it into a
00770   // CONST32.  Avoid truncating stores for the moment.  Post-inc stores
00771   // do the same.  Don't think there's a reason for it, so will file a
00772   // bug to fix.
00773   if ((Const32->getOpcode() == HexagonISD::CONST32) &&
00774       !(Value.getValueType() == MVT::i64 && ST->isTruncatingStore())) {
00775     SDValue Base = Const32->getOperand(0);
00776     if (Base.getOpcode() == ISD::TargetGlobalAddress) {
00777       EVT StoredVT = ST->getMemoryVT();
00778       int64_t Offset = cast<GlobalAddressSDNode>(Base)->getOffset();
00779       if (Offset != 0 && OffsetFitsS11(StoredVT, Offset)) {
00780         MVT PointerTy = getTargetLowering()->getPointerTy();
00781         const GlobalValue* GV =
00782           cast<GlobalAddressSDNode>(Base)->getGlobal();
00783         SDValue TargAddr =
00784           CurDAG->getTargetGlobalAddress(GV, dl, PointerTy, 0);
00785         SDNode* NewBase = CurDAG->getMachineNode(Hexagon::CONST32_set,
00786                                                  dl, PointerTy,
00787                                                  TargAddr);
00788 
00789         // Figure out base + offset opcode
00790         if (StoredVT == MVT::i64) Opcode = Hexagon::STrid_indexed;
00791         else if (StoredVT == MVT::i32) Opcode = Hexagon::STriw_indexed;
00792         else if (StoredVT == MVT::i16) Opcode = Hexagon::STrih_indexed;
00793         else if (StoredVT == MVT::i8) Opcode = Hexagon::STrib_indexed;
00794         else llvm_unreachable("unknown memory type");
00795 
00796         SDValue Ops[] = {SDValue(NewBase,0),
00797                          CurDAG->getTargetConstant(Offset,PointerTy),
00798                          Value, Chain};
00799         // build indexed store
00800         SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
00801                                                 MVT::Other, Ops);
00802         MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00803         MemOp[0] = ST->getMemOperand();
00804         cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
00805         ReplaceUses(ST, Result);
00806         return Result;
00807       }
00808     }
00809   }
00810 
00811   return SelectCode(ST);
00812 }
00813 
00814 
00815 SDNode *HexagonDAGToDAGISel::SelectStore(SDNode *N) {
00816   SDLoc dl(N);
00817   StoreSDNode *ST = cast<StoreSDNode>(N);
00818   ISD::MemIndexedMode AM = ST->getAddressingMode();
00819 
00820   // Handle indexed stores.
00821   if (AM != ISD::UNINDEXED) {
00822     return SelectIndexedStore(ST, dl);
00823   }
00824 
00825   return SelectBaseOffsetStore(ST, dl);
00826 }
00827 
00828 SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
00829   SDLoc dl(N);
00830 
00831   //
00832   // %conv.i = sext i32 %tmp1 to i64
00833   // %conv2.i = sext i32 %add to i64
00834   // %mul.i = mul nsw i64 %conv2.i, %conv.i
00835   //
00836   //   --- match with the following ---
00837   //
00838   // %mul.i = mpy (%tmp1, %add)
00839   //
00840 
00841   if (N->getValueType(0) == MVT::i64) {
00842     // Shifting a i64 signed multiply.
00843     SDValue MulOp0 = N->getOperand(0);
00844     SDValue MulOp1 = N->getOperand(1);
00845 
00846     SDValue OP0;
00847     SDValue OP1;
00848 
00849     // Handle sign_extend and sextload.
00850     if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
00851       SDValue Sext0 = MulOp0.getOperand(0);
00852       if (Sext0.getNode()->getValueType(0) != MVT::i32) {
00853         return SelectCode(N);
00854       }
00855 
00856       OP0 = Sext0;
00857     } else if (MulOp0.getOpcode() == ISD::LOAD) {
00858       LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
00859       if (LD->getMemoryVT() != MVT::i32 ||
00860           LD->getExtensionType() != ISD::SEXTLOAD ||
00861           LD->getAddressingMode() != ISD::UNINDEXED) {
00862         return SelectCode(N);
00863       }
00864 
00865       SDValue Chain = LD->getChain();
00866       SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
00867       OP0 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32,
00868                                             MVT::Other,
00869                                             LD->getBasePtr(), TargetConst0,
00870                                             Chain), 0);
00871     } else {
00872       return SelectCode(N);
00873     }
00874 
00875     // Same goes for the second operand.
00876     if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
00877       SDValue Sext1 = MulOp1.getOperand(0);
00878       if (Sext1.getNode()->getValueType(0) != MVT::i32) {
00879         return SelectCode(N);
00880       }
00881 
00882       OP1 = Sext1;
00883     } else if (MulOp1.getOpcode() == ISD::LOAD) {
00884       LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
00885       if (LD->getMemoryVT() != MVT::i32 ||
00886           LD->getExtensionType() != ISD::SEXTLOAD ||
00887           LD->getAddressingMode() != ISD::UNINDEXED) {
00888         return SelectCode(N);
00889       }
00890 
00891       SDValue Chain = LD->getChain();
00892       SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
00893       OP1 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32,
00894                                             MVT::Other,
00895                                             LD->getBasePtr(), TargetConst0,
00896                                             Chain), 0);
00897     } else {
00898       return SelectCode(N);
00899     }
00900 
00901     // Generate a mpy instruction.
00902     SDNode *Result = CurDAG->getMachineNode(Hexagon::MPY64, dl, MVT::i64,
00903                                             OP0, OP1);
00904     ReplaceUses(N, Result);
00905     return Result;
00906   }
00907 
00908   return SelectCode(N);
00909 }
00910 
00911 
00912 SDNode *HexagonDAGToDAGISel::SelectSelect(SDNode *N) {
00913   SDLoc dl(N);
00914   SDValue N0 = N->getOperand(0);
00915   if (N0.getOpcode() == ISD::SETCC) {
00916     SDValue N00 = N0.getOperand(0);
00917     if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
00918       SDValue N000 = N00.getOperand(0);
00919       SDValue N001 = N00.getOperand(1);
00920       if (cast<VTSDNode>(N001)->getVT() == MVT::i16) {
00921         SDValue N01 = N0.getOperand(1);
00922         SDValue N02 = N0.getOperand(2);
00923 
00924         // Pattern: (select:i32 (setcc:i1 (sext_inreg:i32 IntRegs:i32:$src2,
00925         // i16:Other),IntRegs:i32:$src1, SETLT:Other),IntRegs:i32:$src1,
00926         // IntRegs:i32:$src2)
00927         // Emits: (MAXh_rr:i32 IntRegs:i32:$src1, IntRegs:i32:$src2)
00928         // Pattern complexity = 9  cost = 1  size = 0.
00929         if (cast<CondCodeSDNode>(N02)->get() == ISD::SETLT) {
00930           SDValue N1 = N->getOperand(1);
00931           if (N01 == N1) {
00932             SDValue N2 = N->getOperand(2);
00933             if (N000 == N2 &&
00934                 N0.getNode()->getValueType(N0.getResNo()) == MVT::i1 &&
00935                 N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) {
00936               SDNode *SextNode = CurDAG->getMachineNode(Hexagon::SXTH, dl,
00937                                                         MVT::i32, N000);
00938               SDNode *Result = CurDAG->getMachineNode(Hexagon::MAXw_rr, dl,
00939                                                       MVT::i32,
00940                                                       SDValue(SextNode, 0),
00941                                                       N1);
00942               ReplaceUses(N, Result);
00943               return Result;
00944             }
00945           }
00946         }
00947 
00948         // Pattern: (select:i32 (setcc:i1 (sext_inreg:i32 IntRegs:i32:$src2,
00949         // i16:Other), IntRegs:i32:$src1, SETGT:Other), IntRegs:i32:$src1,
00950         // IntRegs:i32:$src2)
00951         // Emits: (MINh_rr:i32 IntRegs:i32:$src1, IntRegs:i32:$src2)
00952         // Pattern complexity = 9  cost = 1  size = 0.
00953         if (cast<CondCodeSDNode>(N02)->get() == ISD::SETGT) {
00954           SDValue N1 = N->getOperand(1);
00955           if (N01 == N1) {
00956             SDValue N2 = N->getOperand(2);
00957             if (N000 == N2 &&
00958                 N0.getNode()->getValueType(N0.getResNo()) == MVT::i1 &&
00959                 N00.getNode()->getValueType(N00.getResNo()) == MVT::i32) {
00960               SDNode *SextNode = CurDAG->getMachineNode(Hexagon::SXTH, dl,
00961                                                         MVT::i32, N000);
00962               SDNode *Result = CurDAG->getMachineNode(Hexagon::MINw_rr, dl,
00963                                                       MVT::i32,
00964                                                       SDValue(SextNode, 0),
00965                                                       N1);
00966               ReplaceUses(N, Result);
00967               return Result;
00968             }
00969           }
00970         }
00971       }
00972     }
00973   }
00974 
00975   return SelectCode(N);
00976 }
00977 
00978 
00979 SDNode *HexagonDAGToDAGISel::SelectTruncate(SDNode *N) {
00980   SDLoc dl(N);
00981   SDValue Shift = N->getOperand(0);
00982 
00983   //
00984   // %conv.i = sext i32 %tmp1 to i64
00985   // %conv2.i = sext i32 %add to i64
00986   // %mul.i = mul nsw i64 %conv2.i, %conv.i
00987   // %shr5.i = lshr i64 %mul.i, 32
00988   // %conv3.i = trunc i64 %shr5.i to i32
00989   //
00990   //   --- match with the following ---
00991   //
00992   // %conv3.i = mpy (%tmp1, %add)
00993   //
00994   // Trunc to i32.
00995   if (N->getValueType(0) == MVT::i32) {
00996     // Trunc from i64.
00997     if (Shift.getNode()->getValueType(0) == MVT::i64) {
00998       // Trunc child is logical shift right.
00999       if (Shift.getOpcode() != ISD::SRL) {
01000         return SelectCode(N);
01001       }
01002 
01003       SDValue ShiftOp0 = Shift.getOperand(0);
01004       SDValue ShiftOp1 = Shift.getOperand(1);
01005 
01006       // Shift by const 32
01007       if (ShiftOp1.getOpcode() != ISD::Constant) {
01008         return SelectCode(N);
01009       }
01010 
01011       int32_t ShiftConst =
01012         cast<ConstantSDNode>(ShiftOp1.getNode())->getSExtValue();
01013       if (ShiftConst != 32) {
01014         return SelectCode(N);
01015       }
01016 
01017       // Shifting a i64 signed multiply
01018       SDValue Mul = ShiftOp0;
01019       if (Mul.getOpcode() != ISD::MUL) {
01020         return SelectCode(N);
01021       }
01022 
01023       SDValue MulOp0 = Mul.getOperand(0);
01024       SDValue MulOp1 = Mul.getOperand(1);
01025 
01026       SDValue OP0;
01027       SDValue OP1;
01028 
01029       // Handle sign_extend and sextload
01030       if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
01031         SDValue Sext0 = MulOp0.getOperand(0);
01032         if (Sext0.getNode()->getValueType(0) != MVT::i32) {
01033           return SelectCode(N);
01034         }
01035 
01036         OP0 = Sext0;
01037       } else if (MulOp0.getOpcode() == ISD::LOAD) {
01038         LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
01039         if (LD->getMemoryVT() != MVT::i32 ||
01040             LD->getExtensionType() != ISD::SEXTLOAD ||
01041             LD->getAddressingMode() != ISD::UNINDEXED) {
01042           return SelectCode(N);
01043         }
01044 
01045         SDValue Chain = LD->getChain();
01046         SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
01047         OP0 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32,
01048                                               MVT::Other,
01049                                               LD->getBasePtr(),
01050                                               TargetConst0, Chain), 0);
01051       } else {
01052         return SelectCode(N);
01053       }
01054 
01055       // Same goes for the second operand.
01056       if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
01057         SDValue Sext1 = MulOp1.getOperand(0);
01058         if (Sext1.getNode()->getValueType(0) != MVT::i32)
01059           return SelectCode(N);
01060 
01061         OP1 = Sext1;
01062       } else if (MulOp1.getOpcode() == ISD::LOAD) {
01063         LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
01064         if (LD->getMemoryVT() != MVT::i32 ||
01065             LD->getExtensionType() != ISD::SEXTLOAD ||
01066             LD->getAddressingMode() != ISD::UNINDEXED) {
01067           return SelectCode(N);
01068         }
01069 
01070         SDValue Chain = LD->getChain();
01071         SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
01072         OP1 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32,
01073                                               MVT::Other,
01074                                               LD->getBasePtr(),
01075                                               TargetConst0, Chain), 0);
01076       } else {
01077         return SelectCode(N);
01078       }
01079 
01080       // Generate a mpy instruction.
01081       SDNode *Result = CurDAG->getMachineNode(Hexagon::MPY, dl, MVT::i32,
01082                                               OP0, OP1);
01083       ReplaceUses(N, Result);
01084       return Result;
01085     }
01086   }
01087 
01088   return SelectCode(N);
01089 }
01090 
01091 
01092 SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
01093   SDLoc dl(N);
01094   if (N->getValueType(0) == MVT::i32) {
01095     SDValue Shl_0 = N->getOperand(0);
01096     SDValue Shl_1 = N->getOperand(1);
01097     // RHS is const.
01098     if (Shl_1.getOpcode() == ISD::Constant) {
01099       if (Shl_0.getOpcode() == ISD::MUL) {
01100         SDValue Mul_0 = Shl_0.getOperand(0); // Val
01101         SDValue Mul_1 = Shl_0.getOperand(1); // Const
01102         // RHS of mul is const.
01103         if (Mul_1.getOpcode() == ISD::Constant) {
01104           int32_t ShlConst =
01105             cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
01106           int32_t MulConst =
01107             cast<ConstantSDNode>(Mul_1.getNode())->getSExtValue();
01108           int32_t ValConst = MulConst << ShlConst;
01109           SDValue Val = CurDAG->getTargetConstant(ValConst,
01110                                                   MVT::i32);
01111           if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val.getNode()))
01112             if (isInt<9>(CN->getSExtValue())) {
01113               SDNode* Result =
01114                 CurDAG->getMachineNode(Hexagon::MPYI_ri, dl,
01115                                        MVT::i32, Mul_0, Val);
01116               ReplaceUses(N, Result);
01117               return Result;
01118             }
01119 
01120         }
01121       } else if (Shl_0.getOpcode() == ISD::SUB) {
01122         SDValue Sub_0 = Shl_0.getOperand(0); // Const 0
01123         SDValue Sub_1 = Shl_0.getOperand(1); // Val
01124         if (Sub_0.getOpcode() == ISD::Constant) {
01125           int32_t SubConst =
01126             cast<ConstantSDNode>(Sub_0.getNode())->getSExtValue();
01127           if (SubConst == 0) {
01128             if (Sub_1.getOpcode() == ISD::SHL) {
01129               SDValue Shl2_0 = Sub_1.getOperand(0); // Val
01130               SDValue Shl2_1 = Sub_1.getOperand(1); // Const
01131               if (Shl2_1.getOpcode() == ISD::Constant) {
01132                 int32_t ShlConst =
01133                   cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
01134                 int32_t Shl2Const =
01135                   cast<ConstantSDNode>(Shl2_1.getNode())->getSExtValue();
01136                 int32_t ValConst = 1 << (ShlConst+Shl2Const);
01137                 SDValue Val = CurDAG->getTargetConstant(-ValConst, MVT::i32);
01138                 if (ConstantSDNode *CN =
01139                     dyn_cast<ConstantSDNode>(Val.getNode()))
01140                   if (isInt<9>(CN->getSExtValue())) {
01141                     SDNode* Result =
01142                       CurDAG->getMachineNode(Hexagon::MPYI_ri, dl, MVT::i32,
01143                                              Shl2_0, Val);
01144                     ReplaceUses(N, Result);
01145                     return Result;
01146                   }
01147               }
01148             }
01149           }
01150         }
01151       }
01152     }
01153   }
01154   return SelectCode(N);
01155 }
01156 
01157 
01158 //
01159 // If there is an zero_extend followed an intrinsic in DAG (this means - the
01160 // result of the intrinsic is predicate); convert the zero_extend to
01161 // transfer instruction.
01162 //
01163 // Zero extend -> transfer is lowered here. Otherwise, zero_extend will be
01164 // converted into a MUX as predicate registers defined as 1 bit in the
01165 // compiler. Architecture defines them as 8-bit registers.
01166 // We want to preserve all the lower 8-bits and, not just 1 LSB bit.
01167 //
01168 SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) {
01169   SDLoc dl(N);
01170   SDNode *IsIntrinsic = N->getOperand(0).getNode();
01171   if ((IsIntrinsic->getOpcode() == ISD::INTRINSIC_WO_CHAIN)) {
01172     unsigned ID =
01173       cast<ConstantSDNode>(IsIntrinsic->getOperand(0))->getZExtValue();
01174     if (doesIntrinsicReturnPredicate(ID)) {
01175       // Now we need to differentiate target data types.
01176       if (N->getValueType(0) == MVT::i64) {
01177         // Convert the zero_extend to Rs = Pd followed by COMBINE_rr(0,Rs).
01178         SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
01179         SDNode *Result_1 = CurDAG->getMachineNode(Hexagon::TFR_RsPd, dl,
01180                                                   MVT::i32,
01181                                                   SDValue(IsIntrinsic, 0));
01182         SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::TFRI, dl,
01183                                                   MVT::i32,
01184                                                   TargetConst0);
01185         SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::COMBINE_rr, dl,
01186                                                   MVT::i64, MVT::Other,
01187                                                   SDValue(Result_2, 0),
01188                                                   SDValue(Result_1, 0));
01189         ReplaceUses(N, Result_3);
01190         return Result_3;
01191       }
01192       if (N->getValueType(0) == MVT::i32) {
01193         // Convert the zero_extend to Rs = Pd
01194         SDNode* RsPd = CurDAG->getMachineNode(Hexagon::TFR_RsPd, dl,
01195                                               MVT::i32,
01196                                               SDValue(IsIntrinsic, 0));
01197         ReplaceUses(N, RsPd);
01198         return RsPd;
01199       }
01200       llvm_unreachable("Unexpected value type");
01201     }
01202   }
01203   return SelectCode(N);
01204 }
01205 
01206 
01207 //
01208 // Checking for intrinsics which have predicate registers as operand(s)
01209 // and lowering to the actual intrinsic.
01210 //
01211 SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
01212   SDLoc dl(N);
01213   unsigned ID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
01214   unsigned IntrinsicWithPred = doesIntrinsicContainPredicate(ID);
01215 
01216   // We are concerned with only those intrinsics that have predicate registers
01217   // as at least one of the operands.
01218   if (IntrinsicWithPred) {
01219     SmallVector<SDValue, 8> Ops;
01220     const HexagonInstrInfo *TII =
01221       static_cast<const HexagonInstrInfo*>(TM.getInstrInfo());
01222     const MCInstrDesc &MCID = TII->get(IntrinsicWithPred);
01223     const TargetRegisterInfo *TRI = TM.getRegisterInfo();
01224 
01225     // Iterate over all the operands of the intrinsics.
01226     // For PredRegs, do the transfer.
01227     // For Double/Int Regs, just preserve the value
01228     // For immediates, lower it.
01229     for (unsigned i = 1; i < N->getNumOperands(); ++i) {
01230       SDNode *Arg = N->getOperand(i).getNode();
01231       const TargetRegisterClass *RC = TII->getRegClass(MCID, i, TRI, *MF);
01232 
01233       if (RC == &Hexagon::IntRegsRegClass ||
01234           RC == &Hexagon::DoubleRegsRegClass) {
01235         Ops.push_back(SDValue(Arg, 0));
01236       } else if (RC == &Hexagon::PredRegsRegClass) {
01237         // Do the transfer.
01238         SDNode *PdRs = CurDAG->getMachineNode(Hexagon::TFR_PdRs, dl, MVT::i1,
01239                                               SDValue(Arg, 0));
01240         Ops.push_back(SDValue(PdRs,0));
01241       } else if (RC == NULL && (dyn_cast<ConstantSDNode>(Arg) != NULL)) {
01242         // This is immediate operand. Lower it here making sure that we DO have
01243         // const SDNode for immediate value.
01244         int32_t Val = cast<ConstantSDNode>(Arg)->getSExtValue();
01245         SDValue SDVal = CurDAG->getTargetConstant(Val, MVT::i32);
01246         Ops.push_back(SDVal);
01247       } else {
01248         llvm_unreachable("Unimplemented");
01249       }
01250     }
01251     EVT ReturnValueVT = N->getValueType(0);
01252     SDNode *Result = CurDAG->getMachineNode(IntrinsicWithPred, dl,
01253                                             ReturnValueVT, Ops);
01254     ReplaceUses(N, Result);
01255     return Result;
01256   }
01257   return SelectCode(N);
01258 }
01259 
01260 //
01261 // Map floating point constant values.
01262 //
01263 SDNode *HexagonDAGToDAGISel::SelectConstantFP(SDNode *N) {
01264   SDLoc dl(N);
01265   ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
01266   APFloat APF = CN->getValueAPF();
01267   if (N->getValueType(0) == MVT::f32) {
01268     return CurDAG->getMachineNode(Hexagon::TFRI_f, dl, MVT::f32,
01269               CurDAG->getTargetConstantFP(APF.convertToFloat(), MVT::f32));
01270   }
01271   else if (N->getValueType(0) == MVT::f64) {
01272     return CurDAG->getMachineNode(Hexagon::CONST64_Float_Real, dl, MVT::f64,
01273               CurDAG->getTargetConstantFP(APF.convertToDouble(), MVT::f64));
01274   }
01275 
01276   return SelectCode(N);
01277 }
01278 
01279 
01280 //
01281 // Map predicate true (encoded as -1 in LLVM) to a XOR.
01282 //
01283 SDNode *HexagonDAGToDAGISel::SelectConstant(SDNode *N) {
01284   SDLoc dl(N);
01285   if (N->getValueType(0) == MVT::i1) {
01286     SDNode* Result;
01287     int32_t Val = cast<ConstantSDNode>(N)->getSExtValue();
01288     if (Val == -1) {
01289       // Create the IntReg = 1 node.
01290       SDNode* IntRegTFR =
01291         CurDAG->getMachineNode(Hexagon::TFRI, dl, MVT::i32,
01292                                CurDAG->getTargetConstant(0, MVT::i32));
01293 
01294       // Pd = IntReg
01295       SDNode* Pd = CurDAG->getMachineNode(Hexagon::TFR_PdRs, dl, MVT::i1,
01296                                           SDValue(IntRegTFR, 0));
01297 
01298       // not(Pd)
01299       SDNode* NotPd = CurDAG->getMachineNode(Hexagon::NOT_p, dl, MVT::i1,
01300                                              SDValue(Pd, 0));
01301 
01302       // xor(not(Pd))
01303       Result = CurDAG->getMachineNode(Hexagon::XOR_pp, dl, MVT::i1,
01304                                       SDValue(Pd, 0), SDValue(NotPd, 0));
01305 
01306       // We have just built:
01307       // Rs = Pd
01308       // Pd = xor(not(Pd), Pd)
01309 
01310       ReplaceUses(N, Result);
01311       return Result;
01312     }
01313   }
01314 
01315   return SelectCode(N);
01316 }
01317 
01318 
01319 //
01320 // Map add followed by a asr -> asr +=.
01321 //
01322 SDNode *HexagonDAGToDAGISel::SelectAdd(SDNode *N) {
01323   SDLoc dl(N);
01324   if (N->getValueType(0) != MVT::i32) {
01325     return SelectCode(N);
01326   }
01327   // Identify nodes of the form: add(asr(...)).
01328   SDNode* Src1 = N->getOperand(0).getNode();
01329   if (Src1->getOpcode() != ISD::SRA || !Src1->hasOneUse()
01330       || Src1->getValueType(0) != MVT::i32) {
01331     return SelectCode(N);
01332   }
01333 
01334   // Build Rd = Rd' + asr(Rs, Rt). The machine constraints will ensure that
01335   // Rd and Rd' are assigned to the same register
01336   SDNode* Result = CurDAG->getMachineNode(Hexagon::ASR_ADD_rr, dl, MVT::i32,
01337                                           N->getOperand(1),
01338                                           Src1->getOperand(0),
01339                                           Src1->getOperand(1));
01340   ReplaceUses(N, Result);
01341 
01342   return Result;
01343 }
01344 
01345 
01346 SDNode *HexagonDAGToDAGISel::Select(SDNode *N) {
01347   if (N->isMachineOpcode()) {
01348     N->setNodeId(-1);
01349     return NULL;   // Already selected.
01350   }
01351 
01352 
01353   switch (N->getOpcode()) {
01354   case ISD::Constant:
01355     return SelectConstant(N);
01356 
01357   case ISD::ConstantFP:
01358     return SelectConstantFP(N);
01359 
01360   case ISD::ADD:
01361     return SelectAdd(N);
01362 
01363   case ISD::SHL:
01364     return SelectSHL(N);
01365 
01366   case ISD::LOAD:
01367     return SelectLoad(N);
01368 
01369   case ISD::STORE:
01370     return SelectStore(N);
01371 
01372   case ISD::SELECT:
01373     return SelectSelect(N);
01374 
01375   case ISD::TRUNCATE:
01376     return SelectTruncate(N);
01377 
01378   case ISD::MUL:
01379     return SelectMul(N);
01380 
01381   case ISD::ZERO_EXTEND:
01382     return SelectZeroExtend(N);
01383 
01384   case ISD::INTRINSIC_WO_CHAIN:
01385     return SelectIntrinsicWOChain(N);
01386   }
01387 
01388   return SelectCode(N);
01389 }
01390 
01391 
01392 //
01393 // Hexagon_TODO: Five functions for ADDRri?! Surely there must be a better way
01394 // to define these instructions.
01395 //
01396 bool HexagonDAGToDAGISel::SelectADDRri(SDValue& Addr, SDValue &Base,
01397                                        SDValue &Offset) {
01398   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
01399       Addr.getOpcode() == ISD::TargetGlobalAddress)
01400     return false;  // Direct calls.
01401 
01402   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
01403     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
01404     Offset = CurDAG->getTargetConstant(0, MVT::i32);
01405     return true;
01406   }
01407   Base = Addr;
01408   Offset = CurDAG->getTargetConstant(0, MVT::i32);
01409   return true;
01410 }
01411 
01412 
01413 bool HexagonDAGToDAGISel::SelectADDRriS11_0(SDValue& Addr, SDValue &Base,
01414                                             SDValue &Offset) {
01415   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
01416       Addr.getOpcode() == ISD::TargetGlobalAddress)
01417     return false;  // Direct calls.
01418 
01419   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
01420     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
01421     Offset = CurDAG->getTargetConstant(0, MVT::i32);
01422     return (IsS11_0_Offset(Offset.getNode()));
01423   }
01424   Base = Addr;
01425   Offset = CurDAG->getTargetConstant(0, MVT::i32);
01426   return (IsS11_0_Offset(Offset.getNode()));
01427 }
01428 
01429 
01430 bool HexagonDAGToDAGISel::SelectADDRriS11_1(SDValue& Addr, SDValue &Base,
01431                                             SDValue &Offset) {
01432   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
01433       Addr.getOpcode() == ISD::TargetGlobalAddress)
01434     return false;  // Direct calls.
01435 
01436   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
01437     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
01438     Offset = CurDAG->getTargetConstant(0, MVT::i32);
01439     return (IsS11_1_Offset(Offset.getNode()));
01440   }
01441   Base = Addr;
01442   Offset = CurDAG->getTargetConstant(0, MVT::i32);
01443   return (IsS11_1_Offset(Offset.getNode()));
01444 }
01445 
01446 
01447 bool HexagonDAGToDAGISel::SelectADDRriS11_2(SDValue& Addr, SDValue &Base,
01448                                             SDValue &Offset) {
01449   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
01450       Addr.getOpcode() == ISD::TargetGlobalAddress)
01451     return false;  // Direct calls.
01452 
01453   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
01454     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
01455     Offset = CurDAG->getTargetConstant(0, MVT::i32);
01456     return (IsS11_2_Offset(Offset.getNode()));
01457   }
01458   Base = Addr;
01459   Offset = CurDAG->getTargetConstant(0, MVT::i32);
01460   return (IsS11_2_Offset(Offset.getNode()));
01461 }
01462 
01463 
01464 bool HexagonDAGToDAGISel::SelectADDRriU6_0(SDValue& Addr, SDValue &Base,
01465                                             SDValue &Offset) {
01466   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
01467       Addr.getOpcode() == ISD::TargetGlobalAddress)
01468     return false;  // Direct calls.
01469 
01470   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
01471     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
01472     Offset = CurDAG->getTargetConstant(0, MVT::i32);
01473     return (IsU6_0_Offset(Offset.getNode()));
01474   }
01475   Base = Addr;
01476   Offset = CurDAG->getTargetConstant(0, MVT::i32);
01477   return (IsU6_0_Offset(Offset.getNode()));
01478 }
01479 
01480 
01481 bool HexagonDAGToDAGISel::SelectADDRriU6_1(SDValue& Addr, SDValue &Base,
01482                                             SDValue &Offset) {
01483   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
01484       Addr.getOpcode() == ISD::TargetGlobalAddress)
01485     return false;  // Direct calls.
01486 
01487   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
01488     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
01489     Offset = CurDAG->getTargetConstant(0, MVT::i32);
01490     return (IsU6_1_Offset(Offset.getNode()));
01491   }
01492   Base = Addr;
01493   Offset = CurDAG->getTargetConstant(0, MVT::i32);
01494   return (IsU6_1_Offset(Offset.getNode()));
01495 }
01496 
01497 
01498 bool HexagonDAGToDAGISel::SelectADDRriU6_2(SDValue& Addr, SDValue &Base,
01499                                             SDValue &Offset) {
01500   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
01501       Addr.getOpcode() == ISD::TargetGlobalAddress)
01502     return false;  // Direct calls.
01503 
01504   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
01505     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
01506     Offset = CurDAG->getTargetConstant(0, MVT::i32);
01507     return (IsU6_2_Offset(Offset.getNode()));
01508   }
01509   Base = Addr;
01510   Offset = CurDAG->getTargetConstant(0, MVT::i32);
01511   return (IsU6_2_Offset(Offset.getNode()));
01512 }
01513 
01514 
01515 bool HexagonDAGToDAGISel::SelectMEMriS11_2(SDValue& Addr, SDValue &Base,
01516                                            SDValue &Offset) {
01517 
01518   if (Addr.getOpcode() != ISD::ADD) {
01519     return(SelectADDRriS11_2(Addr, Base, Offset));
01520   }
01521 
01522   return SelectADDRriS11_2(Addr, Base, Offset);
01523 }
01524 
01525 
01526 bool HexagonDAGToDAGISel::SelectADDRriS11_3(SDValue& Addr, SDValue &Base,
01527                                             SDValue &Offset) {
01528   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
01529       Addr.getOpcode() == ISD::TargetGlobalAddress)
01530     return false;  // Direct calls.
01531 
01532   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
01533     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
01534     Offset = CurDAG->getTargetConstant(0, MVT::i32);
01535     return (IsS11_3_Offset(Offset.getNode()));
01536   }
01537   Base = Addr;
01538   Offset = CurDAG->getTargetConstant(0, MVT::i32);
01539   return (IsS11_3_Offset(Offset.getNode()));
01540 }
01541 
01542 bool HexagonDAGToDAGISel::SelectADDRrr(SDValue &Addr, SDValue &R1,
01543                                        SDValue &R2) {
01544   if (Addr.getOpcode() == ISD::FrameIndex) return false;
01545   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
01546       Addr.getOpcode() == ISD::TargetGlobalAddress)
01547     return false;  // Direct calls.
01548 
01549   if (Addr.getOpcode() == ISD::ADD) {
01550     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
01551       if (isInt<13>(CN->getSExtValue()))
01552         return false;  // Let the reg+imm pattern catch this!
01553     R1 = Addr.getOperand(0);
01554     R2 = Addr.getOperand(1);
01555     return true;
01556   }
01557 
01558   R1 = Addr;
01559 
01560   return true;
01561 }
01562 
01563 
01564 // Handle generic address case. It is accessed from inlined asm =m constraints,
01565 // which could have any kind of pointer.
01566 bool HexagonDAGToDAGISel::SelectAddr(SDNode *Op, SDValue Addr,
01567                                           SDValue &Base, SDValue &Offset) {
01568   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
01569       Addr.getOpcode() == ISD::TargetGlobalAddress)
01570     return false;  // Direct calls.
01571 
01572   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
01573     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
01574     Offset = CurDAG->getTargetConstant(0, MVT::i32);
01575     return true;
01576   }
01577 
01578   if (Addr.getOpcode() == ISD::ADD) {
01579     Base = Addr.getOperand(0);
01580     Offset = Addr.getOperand(1);
01581     return true;
01582   }
01583 
01584   Base = Addr;
01585   Offset = CurDAG->getTargetConstant(0, MVT::i32);
01586   return true;
01587 }
01588 
01589 
01590 bool HexagonDAGToDAGISel::
01591 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
01592                              std::vector<SDValue> &OutOps) {
01593   SDValue Op0, Op1;
01594 
01595   switch (ConstraintCode) {
01596   case 'o':   // Offsetable.
01597   case 'v':   // Not offsetable.
01598   default: return true;
01599   case 'm':   // Memory.
01600     if (!SelectAddr(Op.getNode(), Op, Op0, Op1))
01601       return true;
01602     break;
01603   }
01604 
01605   OutOps.push_back(Op0);
01606   OutOps.push_back(Op1);
01607   return false;
01608 }
01609 
01610 bool HexagonDAGToDAGISel::isConstExtProfitable(SDNode *N) const {
01611   unsigned UseCount = 0;
01612   for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
01613     UseCount++;
01614   }
01615 
01616   return (UseCount <= 1);
01617 
01618 }
01619 
01620 //===--------------------------------------------------------------------===//
01621 // Return 'true' if use count of the global address is below threshold.
01622 //===--------------------------------------------------------------------===//
01623 bool HexagonDAGToDAGISel::hasNumUsesBelowThresGA(SDNode *N) const {
01624   assert(N->getOpcode() == ISD::TargetGlobalAddress &&
01625          "Expecting a target global address");
01626 
01627   // Always try to fold the address.
01628   if (TM.getOptLevel() == CodeGenOpt::Aggressive)
01629     return true;
01630 
01631   GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
01632   DenseMap<const GlobalValue *, unsigned>::const_iterator GI =
01633     GlobalAddressUseCountMap.find(GA->getGlobal());
01634 
01635   if (GI == GlobalAddressUseCountMap.end())
01636     return false;
01637 
01638   return GI->second <= MaxNumOfUsesForConstExtenders;
01639 }
01640 
01641 //===--------------------------------------------------------------------===//
01642 // Return true if the non-GP-relative global address can be folded.
01643 //===--------------------------------------------------------------------===//
01644 inline bool HexagonDAGToDAGISel::foldGlobalAddress(SDValue &N, SDValue &R) {
01645   return foldGlobalAddressImpl(N, R, false);
01646 }
01647 
01648 //===--------------------------------------------------------------------===//
01649 // Return true if the GP-relative global address can be folded.
01650 //===--------------------------------------------------------------------===//
01651 inline bool HexagonDAGToDAGISel::foldGlobalAddressGP(SDValue &N, SDValue &R) {
01652   return foldGlobalAddressImpl(N, R, true);
01653 }
01654 
01655 //===--------------------------------------------------------------------===//
01656 // Fold offset of the global address if number of uses are below threshold.
01657 //===--------------------------------------------------------------------===//
01658 bool HexagonDAGToDAGISel::foldGlobalAddressImpl(SDValue &N, SDValue &R,
01659                                                 bool ShouldLookForGP) {
01660   if (N.getOpcode() == ISD::ADD) {
01661     SDValue N0 = N.getOperand(0);
01662     SDValue N1 = N.getOperand(1);
01663     if ((ShouldLookForGP && (N0.getOpcode() == HexagonISD::CONST32_GP)) ||
01664         (!ShouldLookForGP && (N0.getOpcode() == HexagonISD::CONST32))) {
01665       ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N1);
01666       GlobalAddressSDNode *GA =
01667         dyn_cast<GlobalAddressSDNode>(N0.getOperand(0));
01668 
01669       if (Const && GA &&
01670           (GA->getOpcode() == ISD::TargetGlobalAddress)) {
01671         if ((N0.getOpcode() == HexagonISD::CONST32) &&
01672                 !hasNumUsesBelowThresGA(GA))
01673             return false;
01674         R = CurDAG->getTargetGlobalAddress(GA->getGlobal(),
01675                                           SDLoc(Const),
01676                                           N.getValueType(),
01677                                           GA->getOffset() +
01678                                           (uint64_t)Const->getSExtValue());
01679         return true;
01680       }
01681     }
01682   }
01683   return false;
01684 }