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HexagonISelDAGToDAG.cpp
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00001 //===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file defines an instruction selector for the Hexagon target.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "Hexagon.h"
00015 #include "HexagonISelLowering.h"
00016 #include "HexagonMachineFunctionInfo.h"
00017 #include "HexagonTargetMachine.h"
00018 #include "llvm/ADT/DenseMap.h"
00019 #include "llvm/CodeGen/FunctionLoweringInfo.h"
00020 #include "llvm/CodeGen/MachineInstrBuilder.h"
00021 #include "llvm/CodeGen/SelectionDAGISel.h"
00022 #include "llvm/IR/Intrinsics.h"
00023 #include "llvm/Support/CommandLine.h"
00024 #include "llvm/Support/Compiler.h"
00025 #include "llvm/Support/Debug.h"
00026 using namespace llvm;
00027 
00028 #define DEBUG_TYPE "hexagon-isel"
00029 
00030 static
00031 cl::opt<unsigned>
00032 MaxNumOfUsesForConstExtenders("ga-max-num-uses-for-constant-extenders",
00033   cl::Hidden, cl::init(2),
00034   cl::desc("Maximum number of uses of a global address such that we still us a"
00035            "constant extended instruction"));
00036 
00037 //===----------------------------------------------------------------------===//
00038 // Instruction Selector Implementation
00039 //===----------------------------------------------------------------------===//
00040 
00041 namespace llvm {
00042   void initializeHexagonDAGToDAGISelPass(PassRegistry&);
00043 }
00044 
00045 //===--------------------------------------------------------------------===//
00046 /// HexagonDAGToDAGISel - Hexagon specific code to select Hexagon machine
00047 /// instructions for SelectionDAG operations.
00048 ///
00049 namespace {
00050 class HexagonDAGToDAGISel : public SelectionDAGISel {
00051   const HexagonTargetMachine& HTM;
00052   const HexagonSubtarget *HST;
00053 public:
00054   explicit HexagonDAGToDAGISel(HexagonTargetMachine &tm,
00055                                CodeGenOpt::Level OptLevel)
00056       : SelectionDAGISel(tm, OptLevel), HTM(tm) {
00057     initializeHexagonDAGToDAGISelPass(*PassRegistry::getPassRegistry());
00058   }
00059 
00060   bool runOnMachineFunction(MachineFunction &MF) override {
00061     // Reset the subtarget each time through.
00062     HST = &MF.getSubtarget<HexagonSubtarget>();
00063     SelectionDAGISel::runOnMachineFunction(MF);
00064     return true;
00065   }
00066 
00067   virtual void PreprocessISelDAG() override;
00068   virtual void EmitFunctionEntryCode() override;
00069 
00070   SDNode *Select(SDNode *N) override;
00071 
00072   // Complex Pattern Selectors.
00073   inline bool SelectAddrGA(SDValue &N, SDValue &R);
00074   inline bool SelectAddrGP(SDValue &N, SDValue &R);
00075   bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP);
00076   bool SelectAddrFI(SDValue &N, SDValue &R);
00077 
00078   const char *getPassName() const override {
00079     return "Hexagon DAG->DAG Pattern Instruction Selection";
00080   }
00081 
00082   SDNode *SelectFrameIndex(SDNode *N);
00083   /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
00084   /// inline asm expressions.
00085   bool SelectInlineAsmMemoryOperand(const SDValue &Op,
00086                                     unsigned ConstraintID,
00087                                     std::vector<SDValue> &OutOps) override;
00088   SDNode *SelectLoad(SDNode *N);
00089   SDNode *SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl);
00090   SDNode *SelectIndexedLoad(LoadSDNode *LD, SDLoc dl);
00091   SDNode *SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
00092                                         SDLoc dl);
00093   SDNode *SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode,
00094                                         SDLoc dl);
00095   SDNode *SelectBaseOffsetStore(StoreSDNode *ST, SDLoc dl);
00096   SDNode *SelectIndexedStore(StoreSDNode *ST, SDLoc dl);
00097   SDNode *SelectStore(SDNode *N);
00098   SDNode *SelectSHL(SDNode *N);
00099   SDNode *SelectMul(SDNode *N);
00100   SDNode *SelectZeroExtend(SDNode *N);
00101   SDNode *SelectIntrinsicWChain(SDNode *N);
00102   SDNode *SelectIntrinsicWOChain(SDNode *N);
00103   SDNode *SelectConstant(SDNode *N);
00104   SDNode *SelectConstantFP(SDNode *N);
00105   SDNode *SelectAdd(SDNode *N);
00106   SDNode *SelectBitOp(SDNode *N);
00107   bool isConstExtProfitable(SDNode *N) const;
00108 
00109   // XformMskToBitPosU5Imm - Returns the bit position which
00110   // the single bit 32 bit mask represents.
00111   // Used in Clr and Set bit immediate memops.
00112   SDValue XformMskToBitPosU5Imm(uint32_t Imm, SDLoc DL) {
00113     int32_t bitPos;
00114     bitPos = Log2_32(Imm);
00115     assert(bitPos >= 0 && bitPos < 32 &&
00116            "Constant out of range for 32 BitPos Memops");
00117     return CurDAG->getTargetConstant(bitPos, DL, MVT::i32);
00118   }
00119 
00120   // XformMskToBitPosU4Imm - Returns the bit position which the single-bit
00121   // 16 bit mask represents. Used in Clr and Set bit immediate memops.
00122   SDValue XformMskToBitPosU4Imm(uint16_t Imm, SDLoc DL) {
00123     return XformMskToBitPosU5Imm(Imm, DL);
00124   }
00125 
00126   // XformMskToBitPosU3Imm - Returns the bit position which the single-bit
00127   // 8 bit mask represents. Used in Clr and Set bit immediate memops.
00128   SDValue XformMskToBitPosU3Imm(uint8_t Imm, SDLoc DL) {
00129     return XformMskToBitPosU5Imm(Imm, DL);
00130   }
00131 
00132   // Return true if there is exactly one bit set in V, i.e., if V is one of the
00133   // following integers: 2^0, 2^1, ..., 2^31.
00134   bool ImmIsSingleBit(uint32_t v) const {
00135     return isPowerOf2_32(v);
00136   }
00137 
00138   // XformM5ToU5Imm - Return a target constant with the specified value, of
00139   // type i32 where the negative literal is transformed into a positive literal
00140   // for use in -= memops.
00141   inline SDValue XformM5ToU5Imm(signed Imm, SDLoc DL) {
00142      assert( (Imm >= -31 && Imm <= -1)  && "Constant out of range for Memops");
00143      return CurDAG->getTargetConstant( - Imm, DL, MVT::i32);
00144   }
00145 
00146   // XformU7ToU7M1Imm - Return a target constant decremented by 1, in range
00147   // [1..128], used in cmpb.gtu instructions.
00148   inline SDValue XformU7ToU7M1Imm(signed Imm, SDLoc DL) {
00149     assert((Imm >= 1 && Imm <= 128) && "Constant out of range for cmpb op");
00150     return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i8);
00151   }
00152 
00153   // XformS8ToS8M1Imm - Return a target constant decremented by 1.
00154   inline SDValue XformSToSM1Imm(signed Imm, SDLoc DL) {
00155     return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i32);
00156   }
00157 
00158   // XformU8ToU8M1Imm - Return a target constant decremented by 1.
00159   inline SDValue XformUToUM1Imm(unsigned Imm, SDLoc DL) {
00160     assert((Imm >= 1) && "Cannot decrement unsigned int less than 1");
00161     return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i32);
00162   }
00163 
00164   // XformSToSM2Imm - Return a target constant decremented by 2.
00165   inline SDValue XformSToSM2Imm(unsigned Imm, SDLoc DL) {
00166     return CurDAG->getTargetConstant(Imm - 2, DL, MVT::i32);
00167   }
00168 
00169   // XformSToSM3Imm - Return a target constant decremented by 3.
00170   inline SDValue XformSToSM3Imm(unsigned Imm, SDLoc DL) {
00171     return CurDAG->getTargetConstant(Imm - 3, DL, MVT::i32);
00172   }
00173 
00174   // Include the pieces autogenerated from the target description.
00175   #include "HexagonGenDAGISel.inc"
00176 
00177 private:
00178   bool isValueExtension(const SDValue &Val, unsigned FromBits, SDValue &Src);
00179 }; // end HexagonDAGToDAGISel
00180 }  // end anonymous namespace
00181 
00182 
00183 /// createHexagonISelDag - This pass converts a legalized DAG into a
00184 /// Hexagon-specific DAG, ready for instruction scheduling.
00185 ///
00186 namespace llvm {
00187 FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
00188                                    CodeGenOpt::Level OptLevel) {
00189   return new HexagonDAGToDAGISel(TM, OptLevel);
00190 }
00191 }
00192 
00193 static void initializePassOnce(PassRegistry &Registry) {
00194   const char *Name = "Hexagon DAG->DAG Pattern Instruction Selection";
00195   PassInfo *PI = new PassInfo(Name, "hexagon-isel",
00196                               &SelectionDAGISel::ID, nullptr, false, false);
00197   Registry.registerPass(*PI, true);
00198 }
00199 
00200 void llvm::initializeHexagonDAGToDAGISelPass(PassRegistry &Registry) {
00201   CALL_ONCE_INITIALIZATION(initializePassOnce)
00202 }
00203 
00204 
00205 // Intrinsics that return a a predicate.
00206 static unsigned doesIntrinsicReturnPredicate(unsigned ID)
00207 {
00208   switch (ID) {
00209     default:
00210       return 0;
00211     case Intrinsic::hexagon_C2_cmpeq:
00212     case Intrinsic::hexagon_C2_cmpgt:
00213     case Intrinsic::hexagon_C2_cmpgtu:
00214     case Intrinsic::hexagon_C2_cmpgtup:
00215     case Intrinsic::hexagon_C2_cmpgtp:
00216     case Intrinsic::hexagon_C2_cmpeqp:
00217     case Intrinsic::hexagon_C2_bitsset:
00218     case Intrinsic::hexagon_C2_bitsclr:
00219     case Intrinsic::hexagon_C2_cmpeqi:
00220     case Intrinsic::hexagon_C2_cmpgti:
00221     case Intrinsic::hexagon_C2_cmpgtui:
00222     case Intrinsic::hexagon_C2_cmpgei:
00223     case Intrinsic::hexagon_C2_cmpgeui:
00224     case Intrinsic::hexagon_C2_cmplt:
00225     case Intrinsic::hexagon_C2_cmpltu:
00226     case Intrinsic::hexagon_C2_bitsclri:
00227     case Intrinsic::hexagon_C2_and:
00228     case Intrinsic::hexagon_C2_or:
00229     case Intrinsic::hexagon_C2_xor:
00230     case Intrinsic::hexagon_C2_andn:
00231     case Intrinsic::hexagon_C2_not:
00232     case Intrinsic::hexagon_C2_orn:
00233     case Intrinsic::hexagon_C2_pxfer_map:
00234     case Intrinsic::hexagon_C2_any8:
00235     case Intrinsic::hexagon_C2_all8:
00236     case Intrinsic::hexagon_A2_vcmpbeq:
00237     case Intrinsic::hexagon_A2_vcmpbgtu:
00238     case Intrinsic::hexagon_A2_vcmpheq:
00239     case Intrinsic::hexagon_A2_vcmphgt:
00240     case Intrinsic::hexagon_A2_vcmphgtu:
00241     case Intrinsic::hexagon_A2_vcmpweq:
00242     case Intrinsic::hexagon_A2_vcmpwgt:
00243     case Intrinsic::hexagon_A2_vcmpwgtu:
00244     case Intrinsic::hexagon_C2_tfrrp:
00245     case Intrinsic::hexagon_S2_tstbit_i:
00246     case Intrinsic::hexagon_S2_tstbit_r:
00247       return 1;
00248   }
00249 }
00250 
00251 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
00252                                                            unsigned Opcode,
00253                                                            SDLoc dl) {
00254   SDValue Chain = LD->getChain();
00255   EVT LoadedVT = LD->getMemoryVT();
00256   SDValue Base = LD->getBasePtr();
00257   SDValue Offset = LD->getOffset();
00258   SDNode *OffsetNode = Offset.getNode();
00259   int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
00260 
00261   const HexagonInstrInfo &TII = *HST->getInstrInfo();
00262   if (TII.isValidAutoIncImm(LoadedVT, Val)) {
00263     SDValue TargetConst = CurDAG->getTargetConstant(Val, dl, MVT::i32);
00264     SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32,
00265                                               MVT::Other, Base, TargetConst,
00266                                               Chain);
00267     SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
00268                                               SDValue(Result_1, 0));
00269     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00270     MemOp[0] = LD->getMemOperand();
00271     cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00272     const SDValue Froms[] = { SDValue(LD, 0),
00273                               SDValue(LD, 1),
00274                               SDValue(LD, 2) };
00275     const SDValue Tos[]   = { SDValue(Result_2, 0),
00276                               SDValue(Result_1, 1),
00277                               SDValue(Result_1, 2) };
00278     ReplaceUses(Froms, Tos, 3);
00279     return Result_2;
00280   }
00281 
00282   SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
00283   SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
00284   SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Other,
00285                                             Base, TargetConst0, Chain);
00286   SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
00287                                             SDValue(Result_1, 0));
00288   SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
00289                                             Base, TargetConstVal,
00290                                             SDValue(Result_1, 1));
00291   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00292   MemOp[0] = LD->getMemOperand();
00293   cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00294   const SDValue Froms[] = { SDValue(LD, 0),
00295                             SDValue(LD, 1),
00296                             SDValue(LD, 2) };
00297   const SDValue Tos[]   = { SDValue(Result_2, 0),
00298                             SDValue(Result_3, 0),
00299                             SDValue(Result_1, 1) };
00300   ReplaceUses(Froms, Tos, 3);
00301   return Result_2;
00302 }
00303 
00304 
00305 SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
00306                                                            unsigned Opcode,
00307                                                            SDLoc dl) {
00308   SDValue Chain = LD->getChain();
00309   EVT LoadedVT = LD->getMemoryVT();
00310   SDValue Base = LD->getBasePtr();
00311   SDValue Offset = LD->getOffset();
00312   SDNode *OffsetNode = Offset.getNode();
00313   int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
00314 
00315   const HexagonInstrInfo &TII = *HST->getInstrInfo();
00316   if (TII.isValidAutoIncImm(LoadedVT, Val)) {
00317     SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
00318     SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
00319     SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
00320                                               MVT::i32, MVT::Other, Base,
00321                                               TargetConstVal, Chain);
00322     SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A4_combineir, dl,
00323                                               MVT::i64, MVT::Other,
00324                                               TargetConst0,
00325                                               SDValue(Result_1,0));
00326     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00327     MemOp[0] = LD->getMemOperand();
00328     cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00329     const SDValue Froms[] = { SDValue(LD, 0),
00330                               SDValue(LD, 1),
00331                               SDValue(LD, 2) };
00332     const SDValue Tos[]   = { SDValue(Result_2, 0),
00333                               SDValue(Result_1, 1),
00334                               SDValue(Result_1, 2) };
00335     ReplaceUses(Froms, Tos, 3);
00336     return Result_2;
00337   }
00338 
00339   // Generate an indirect load.
00340   SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
00341   SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
00342   SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
00343                                             MVT::Other, Base, TargetConst0,
00344                                             Chain);
00345   SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A4_combineir, dl,
00346                                             MVT::i64, MVT::Other,
00347                                             TargetConst0,
00348                                             SDValue(Result_1,0));
00349   // Add offset to base.
00350   SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
00351                                             Base, TargetConstVal,
00352                                             SDValue(Result_1, 1));
00353   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00354   MemOp[0] = LD->getMemOperand();
00355   cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00356   const SDValue Froms[] = { SDValue(LD, 0),
00357                             SDValue(LD, 1),
00358                             SDValue(LD, 2) };
00359   const SDValue Tos[]   = { SDValue(Result_2, 0), // Load value.
00360                             SDValue(Result_3, 0), // New address.
00361                             SDValue(Result_1, 1) };
00362   ReplaceUses(Froms, Tos, 3);
00363   return Result_2;
00364 }
00365 
00366 
00367 SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
00368   SDValue Chain = LD->getChain();
00369   SDValue Base = LD->getBasePtr();
00370   SDValue Offset = LD->getOffset();
00371   SDNode *OffsetNode = Offset.getNode();
00372   // Get the constant value.
00373   int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
00374   EVT LoadedVT = LD->getMemoryVT();
00375   unsigned Opcode = 0;
00376 
00377   // Check for zero extended loads. Treat any-extend loads as zero extended
00378   // loads.
00379   ISD::LoadExtType ExtType = LD->getExtensionType();
00380   bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD);
00381 
00382   // Figure out the opcode.
00383   const HexagonInstrInfo &TII = *HST->getInstrInfo();
00384   if (LoadedVT == MVT::i64) {
00385     if (TII.isValidAutoIncImm(LoadedVT, Val))
00386       Opcode = Hexagon::L2_loadrd_pi;
00387     else
00388       Opcode = Hexagon::L2_loadrd_io;
00389   } else if (LoadedVT == MVT::i32) {
00390     if (TII.isValidAutoIncImm(LoadedVT, Val))
00391       Opcode = Hexagon::L2_loadri_pi;
00392     else
00393       Opcode = Hexagon::L2_loadri_io;
00394   } else if (LoadedVT == MVT::i16) {
00395     if (TII.isValidAutoIncImm(LoadedVT, Val))
00396       Opcode = IsZeroExt ? Hexagon::L2_loadruh_pi : Hexagon::L2_loadrh_pi;
00397     else
00398       Opcode = IsZeroExt ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io;
00399   } else if (LoadedVT == MVT::i8) {
00400     if (TII.isValidAutoIncImm(LoadedVT, Val))
00401       Opcode = IsZeroExt ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrb_pi;
00402     else
00403       Opcode = IsZeroExt ? Hexagon::L2_loadrub_io : Hexagon::L2_loadrb_io;
00404   } else
00405     llvm_unreachable("unknown memory type");
00406 
00407   // For zero extended i64 loads, we need to add combine instructions.
00408   if (LD->getValueType(0) == MVT::i64 && IsZeroExt)
00409     return SelectIndexedLoadZeroExtend64(LD, Opcode, dl);
00410   // Handle sign extended i64 loads.
00411   if (LD->getValueType(0) == MVT::i64 && ExtType == ISD::SEXTLOAD)
00412     return SelectIndexedLoadSignExtend64(LD, Opcode, dl);
00413 
00414   if (TII.isValidAutoIncImm(LoadedVT, Val)) {
00415     SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
00416     SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
00417                                             LD->getValueType(0),
00418                                             MVT::i32, MVT::Other, Base,
00419                                             TargetConstVal, Chain);
00420     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00421     MemOp[0] = LD->getMemOperand();
00422     cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
00423     const SDValue Froms[] = { SDValue(LD, 0),
00424                               SDValue(LD, 1),
00425                               SDValue(LD, 2)
00426     };
00427     const SDValue Tos[]   = { SDValue(Result, 0),
00428                               SDValue(Result, 1),
00429                               SDValue(Result, 2)
00430     };
00431     ReplaceUses(Froms, Tos, 3);
00432     return Result;
00433   } else {
00434     SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
00435     SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
00436     SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl,
00437                                               LD->getValueType(0),
00438                                               MVT::Other, Base, TargetConst0,
00439                                               Chain);
00440     SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
00441                                               Base, TargetConstVal,
00442                                               SDValue(Result_1, 1));
00443     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00444     MemOp[0] = LD->getMemOperand();
00445     cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00446     const SDValue Froms[] = { SDValue(LD, 0),
00447                               SDValue(LD, 1),
00448                               SDValue(LD, 2)
00449     };
00450     const SDValue Tos[]   = { SDValue(Result_1, 0),
00451                               SDValue(Result_2, 0),
00452                               SDValue(Result_1, 1)
00453     };
00454     ReplaceUses(Froms, Tos, 3);
00455     return Result_1;
00456   }
00457 }
00458 
00459 
00460 SDNode *HexagonDAGToDAGISel::SelectLoad(SDNode *N) {
00461   SDNode *result;
00462   SDLoc dl(N);
00463   LoadSDNode *LD = cast<LoadSDNode>(N);
00464   ISD::MemIndexedMode AM = LD->getAddressingMode();
00465 
00466   // Handle indexed loads.
00467   if (AM != ISD::UNINDEXED) {
00468     result = SelectIndexedLoad(LD, dl);
00469   } else {
00470     result = SelectCode(LD);
00471   }
00472 
00473   return result;
00474 }
00475 
00476 
00477 SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) {
00478   SDValue Chain = ST->getChain();
00479   SDValue Base = ST->getBasePtr();
00480   SDValue Offset = ST->getOffset();
00481   SDValue Value = ST->getValue();
00482   SDNode *OffsetNode = Offset.getNode();
00483   // Get the constant value.
00484   int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
00485   EVT StoredVT = ST->getMemoryVT();
00486   EVT ValueVT = Value.getValueType();
00487 
00488   // Offset value must be within representable range
00489   // and must have correct alignment properties.
00490   const HexagonInstrInfo &TII = *HST->getInstrInfo();
00491   if (TII.isValidAutoIncImm(StoredVT, Val)) {
00492     unsigned Opcode = 0;
00493 
00494     // Figure out the post inc version of opcode.
00495     if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_pi;
00496     else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_pi;
00497     else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_pi;
00498     else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_pi;
00499     else llvm_unreachable("unknown memory type");
00500 
00501     if (ST->isTruncatingStore() && ValueVT.getSizeInBits() == 64) {
00502       assert(StoredVT.getSizeInBits() < 64 && "Not a truncating store");
00503       Value = CurDAG->getTargetExtractSubreg(Hexagon::subreg_loreg,
00504                                              dl, MVT::i32, Value);
00505     }
00506     SDValue Ops[] = {Base, CurDAG->getTargetConstant(Val, dl, MVT::i32), Value,
00507                      Chain};
00508     // Build post increment store.
00509     SDNode* Result = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
00510                                             MVT::Other, Ops);
00511     MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00512     MemOp[0] = ST->getMemOperand();
00513     cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
00514 
00515     ReplaceUses(ST, Result);
00516     ReplaceUses(SDValue(ST,1), SDValue(Result,1));
00517     return Result;
00518   }
00519 
00520   // Note: Order of operands matches the def of instruction:
00521   // def S2_storerd_io
00522   //   : STInst<(outs), (ins IntRegs:$base, imm:$offset, DoubleRegs:$src1), ...
00523   // and it differs for POST_ST* for instance.
00524   SDValue Ops[] = { Base, CurDAG->getTargetConstant(0, dl, MVT::i32), Value,
00525                     Chain};
00526   unsigned Opcode = 0;
00527 
00528   // Figure out the opcode.
00529   if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_io;
00530   else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_io;
00531   else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_io;
00532   else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_io;
00533   else llvm_unreachable("unknown memory type");
00534 
00535   // Build regular store.
00536   SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
00537   SDNode* Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops);
00538   // Build splitted incriment instruction.
00539   SDNode* Result_2 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
00540                                             Base,
00541                                             TargetConstVal,
00542                                             SDValue(Result_1, 0));
00543   MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
00544   MemOp[0] = ST->getMemOperand();
00545   cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
00546 
00547   ReplaceUses(SDValue(ST,0), SDValue(Result_2,0));
00548   ReplaceUses(SDValue(ST,1), SDValue(Result_1,0));
00549   return Result_2;
00550 }
00551 
00552 SDNode *HexagonDAGToDAGISel::SelectStore(SDNode *N) {
00553   SDLoc dl(N);
00554   StoreSDNode *ST = cast<StoreSDNode>(N);
00555   ISD::MemIndexedMode AM = ST->getAddressingMode();
00556 
00557   // Handle indexed stores.
00558   if (AM != ISD::UNINDEXED) {
00559     return SelectIndexedStore(ST, dl);
00560   }
00561 
00562   return SelectCode(ST);
00563 }
00564 
00565 SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
00566   SDLoc dl(N);
00567 
00568   //
00569   // %conv.i = sext i32 %tmp1 to i64
00570   // %conv2.i = sext i32 %add to i64
00571   // %mul.i = mul nsw i64 %conv2.i, %conv.i
00572   //
00573   //   --- match with the following ---
00574   //
00575   // %mul.i = mpy (%tmp1, %add)
00576   //
00577 
00578   if (N->getValueType(0) == MVT::i64) {
00579     // Shifting a i64 signed multiply.
00580     SDValue MulOp0 = N->getOperand(0);
00581     SDValue MulOp1 = N->getOperand(1);
00582 
00583     SDValue OP0;
00584     SDValue OP1;
00585 
00586     // Handle sign_extend and sextload.
00587     if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
00588       SDValue Sext0 = MulOp0.getOperand(0);
00589       if (Sext0.getNode()->getValueType(0) != MVT::i32) {
00590         return SelectCode(N);
00591       }
00592 
00593       OP0 = Sext0;
00594     } else if (MulOp0.getOpcode() == ISD::LOAD) {
00595       LoadSDNode *LD = cast<LoadSDNode>(MulOp0.getNode());
00596       if (LD->getMemoryVT() != MVT::i32 ||
00597           LD->getExtensionType() != ISD::SEXTLOAD ||
00598           LD->getAddressingMode() != ISD::UNINDEXED) {
00599         return SelectCode(N);
00600       }
00601 
00602       SDValue Chain = LD->getChain();
00603       SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
00604       OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
00605                                             MVT::Other,
00606                                             LD->getBasePtr(), TargetConst0,
00607                                             Chain), 0);
00608     } else {
00609       return SelectCode(N);
00610     }
00611 
00612     // Same goes for the second operand.
00613     if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
00614       SDValue Sext1 = MulOp1.getOperand(0);
00615       if (Sext1.getNode()->getValueType(0) != MVT::i32) {
00616         return SelectCode(N);
00617       }
00618 
00619       OP1 = Sext1;
00620     } else if (MulOp1.getOpcode() == ISD::LOAD) {
00621       LoadSDNode *LD = cast<LoadSDNode>(MulOp1.getNode());
00622       if (LD->getMemoryVT() != MVT::i32 ||
00623           LD->getExtensionType() != ISD::SEXTLOAD ||
00624           LD->getAddressingMode() != ISD::UNINDEXED) {
00625         return SelectCode(N);
00626       }
00627 
00628       SDValue Chain = LD->getChain();
00629       SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
00630       OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
00631                                             MVT::Other,
00632                                             LD->getBasePtr(), TargetConst0,
00633                                             Chain), 0);
00634     } else {
00635       return SelectCode(N);
00636     }
00637 
00638     // Generate a mpy instruction.
00639     SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_dpmpyss_s0, dl, MVT::i64,
00640                                             OP0, OP1);
00641     ReplaceUses(N, Result);
00642     return Result;
00643   }
00644 
00645   return SelectCode(N);
00646 }
00647 
00648 SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
00649   SDLoc dl(N);
00650   if (N->getValueType(0) == MVT::i32) {
00651     SDValue Shl_0 = N->getOperand(0);
00652     SDValue Shl_1 = N->getOperand(1);
00653     // RHS is const.
00654     if (Shl_1.getOpcode() == ISD::Constant) {
00655       if (Shl_0.getOpcode() == ISD::MUL) {
00656         SDValue Mul_0 = Shl_0.getOperand(0); // Val
00657         SDValue Mul_1 = Shl_0.getOperand(1); // Const
00658         // RHS of mul is const.
00659         if (Mul_1.getOpcode() == ISD::Constant) {
00660           int32_t ShlConst =
00661             cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
00662           int32_t MulConst =
00663             cast<ConstantSDNode>(Mul_1.getNode())->getSExtValue();
00664           int32_t ValConst = MulConst << ShlConst;
00665           SDValue Val = CurDAG->getTargetConstant(ValConst, dl,
00666                                                   MVT::i32);
00667           if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val.getNode()))
00668             if (isInt<9>(CN->getSExtValue())) {
00669               SDNode* Result =
00670                 CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl,
00671                                        MVT::i32, Mul_0, Val);
00672               ReplaceUses(N, Result);
00673               return Result;
00674             }
00675 
00676         }
00677       } else if (Shl_0.getOpcode() == ISD::SUB) {
00678         SDValue Sub_0 = Shl_0.getOperand(0); // Const 0
00679         SDValue Sub_1 = Shl_0.getOperand(1); // Val
00680         if (Sub_0.getOpcode() == ISD::Constant) {
00681           int32_t SubConst =
00682             cast<ConstantSDNode>(Sub_0.getNode())->getSExtValue();
00683           if (SubConst == 0) {
00684             if (Sub_1.getOpcode() == ISD::SHL) {
00685               SDValue Shl2_0 = Sub_1.getOperand(0); // Val
00686               SDValue Shl2_1 = Sub_1.getOperand(1); // Const
00687               if (Shl2_1.getOpcode() == ISD::Constant) {
00688                 int32_t ShlConst =
00689                   cast<ConstantSDNode>(Shl_1.getNode())->getSExtValue();
00690                 int32_t Shl2Const =
00691                   cast<ConstantSDNode>(Shl2_1.getNode())->getSExtValue();
00692                 int32_t ValConst = 1 << (ShlConst+Shl2Const);
00693                 SDValue Val = CurDAG->getTargetConstant(-ValConst, dl,
00694                                                         MVT::i32);
00695                 if (ConstantSDNode *CN =
00696                     dyn_cast<ConstantSDNode>(Val.getNode()))
00697                   if (isInt<9>(CN->getSExtValue())) {
00698                     SDNode* Result =
00699                       CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl, MVT::i32,
00700                                              Shl2_0, Val);
00701                     ReplaceUses(N, Result);
00702                     return Result;
00703                   }
00704               }
00705             }
00706           }
00707         }
00708       }
00709     }
00710   }
00711   return SelectCode(N);
00712 }
00713 
00714 
00715 //
00716 // If there is an zero_extend followed an intrinsic in DAG (this means - the
00717 // result of the intrinsic is predicate); convert the zero_extend to
00718 // transfer instruction.
00719 //
00720 // Zero extend -> transfer is lowered here. Otherwise, zero_extend will be
00721 // converted into a MUX as predicate registers defined as 1 bit in the
00722 // compiler. Architecture defines them as 8-bit registers.
00723 // We want to preserve all the lower 8-bits and, not just 1 LSB bit.
00724 //
00725 SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) {
00726   SDLoc dl(N);
00727 
00728   SDValue Op0 = N->getOperand(0);
00729   EVT OpVT = Op0.getValueType();
00730   unsigned OpBW = OpVT.getSizeInBits();
00731 
00732   // Special handling for zero-extending a vector of booleans.
00733   if (OpVT.isVector() && OpVT.getVectorElementType() == MVT::i1 && OpBW <= 64) {
00734     SDNode *Mask = CurDAG->getMachineNode(Hexagon::C2_mask, dl, MVT::i64, Op0);
00735     unsigned NE = OpVT.getVectorNumElements();
00736     EVT ExVT = N->getValueType(0);
00737     unsigned ES = ExVT.getVectorElementType().getSizeInBits();
00738     uint64_t MV = 0, Bit = 1;
00739     for (unsigned i = 0; i < NE; ++i) {
00740       MV |= Bit;
00741       Bit <<= ES;
00742     }
00743     SDValue Ones = CurDAG->getTargetConstant(MV, dl, MVT::i64);
00744     SDNode *OnesReg = CurDAG->getMachineNode(Hexagon::CONST64_Int_Real, dl,
00745                                              MVT::i64, Ones);
00746     if (ExVT.getSizeInBits() == 32) {
00747       SDNode *And = CurDAG->getMachineNode(Hexagon::A2_andp, dl, MVT::i64,
00748                                            SDValue(Mask,0), SDValue(OnesReg,0));
00749       SDValue SubR = CurDAG->getTargetConstant(Hexagon::subreg_loreg, dl,
00750                                                MVT::i32);
00751       return CurDAG->getMachineNode(Hexagon::EXTRACT_SUBREG, dl, ExVT,
00752                                     SDValue(And,0), SubR);
00753     }
00754     return CurDAG->getMachineNode(Hexagon::A2_andp, dl, ExVT,
00755                                   SDValue(Mask,0), SDValue(OnesReg,0));
00756   }
00757 
00758   SDNode *IsIntrinsic = N->getOperand(0).getNode();
00759   if ((IsIntrinsic->getOpcode() == ISD::INTRINSIC_WO_CHAIN)) {
00760     unsigned ID =
00761       cast<ConstantSDNode>(IsIntrinsic->getOperand(0))->getZExtValue();
00762     if (doesIntrinsicReturnPredicate(ID)) {
00763       // Now we need to differentiate target data types.
00764       if (N->getValueType(0) == MVT::i64) {
00765         // Convert the zero_extend to Rs = Pd followed by A2_combinew(0,Rs).
00766         SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
00767         SDNode *Result_1 = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
00768                                                   MVT::i32,
00769                                                   SDValue(IsIntrinsic, 0));
00770         SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl,
00771                                                   MVT::i32,
00772                                                   TargetConst0);
00773         SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl,
00774                                                   MVT::i64, MVT::Other,
00775                                                   SDValue(Result_2, 0),
00776                                                   SDValue(Result_1, 0));
00777         ReplaceUses(N, Result_3);
00778         return Result_3;
00779       }
00780       if (N->getValueType(0) == MVT::i32) {
00781         // Convert the zero_extend to Rs = Pd
00782         SDNode* RsPd = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
00783                                               MVT::i32,
00784                                               SDValue(IsIntrinsic, 0));
00785         ReplaceUses(N, RsPd);
00786         return RsPd;
00787       }
00788       llvm_unreachable("Unexpected value type");
00789     }
00790   }
00791   return SelectCode(N);
00792 }
00793 
00794 //
00795 // Checking for intrinsics circular load/store, and bitreverse load/store
00796 // instrisics in order to select the correct lowered operation.
00797 //
00798 SDNode *HexagonDAGToDAGISel::SelectIntrinsicWChain(SDNode *N) {
00799   unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
00800   if (IntNo == Intrinsic::hexagon_circ_ldd  ||
00801       IntNo == Intrinsic::hexagon_circ_ldw  ||
00802       IntNo == Intrinsic::hexagon_circ_lduh ||
00803       IntNo == Intrinsic::hexagon_circ_ldh  ||
00804       IntNo == Intrinsic::hexagon_circ_ldub ||
00805       IntNo == Intrinsic::hexagon_circ_ldb) {
00806     SDLoc dl(N);
00807     SDValue Chain = N->getOperand(0);
00808     SDValue Base = N->getOperand(2);
00809     SDValue Load = N->getOperand(3);
00810     SDValue ModifierExpr = N->getOperand(4);
00811     SDValue Offset = N->getOperand(5);
00812 
00813     // We need to add the rerurn type for the load.  This intrinsic has
00814     // two return types, one for the load and one for the post-increment.
00815     // Only the *_ld instructions push the extra return type, and bump the
00816     // result node operand number correspondingly.
00817     std::vector<EVT> ResTys;
00818     unsigned opc;
00819     unsigned memsize, align;
00820     MVT MvtSize = MVT::i32;
00821 
00822     if (IntNo == Intrinsic::hexagon_circ_ldd) {
00823       ResTys.push_back(MVT::i32);
00824       ResTys.push_back(MVT::i64);
00825       opc = Hexagon::L2_loadrd_pci_pseudo;
00826       memsize = 8;
00827       align = 8;
00828     } else if (IntNo == Intrinsic::hexagon_circ_ldw) {
00829       ResTys.push_back(MVT::i32);
00830       ResTys.push_back(MVT::i32);
00831       opc = Hexagon::L2_loadri_pci_pseudo;
00832       memsize = 4;
00833       align = 4;
00834     } else if (IntNo == Intrinsic::hexagon_circ_ldh) {
00835       ResTys.push_back(MVT::i32);
00836       ResTys.push_back(MVT::i32);
00837       opc = Hexagon::L2_loadrh_pci_pseudo;
00838       memsize = 2;
00839       align = 2;
00840       MvtSize = MVT::i16;
00841     } else if (IntNo == Intrinsic::hexagon_circ_lduh) {
00842       ResTys.push_back(MVT::i32);
00843       ResTys.push_back(MVT::i32);
00844       opc = Hexagon::L2_loadruh_pci_pseudo;
00845       memsize = 2;
00846       align = 2;
00847       MvtSize = MVT::i16;
00848     } else if (IntNo == Intrinsic::hexagon_circ_ldb) {
00849       ResTys.push_back(MVT::i32);
00850       ResTys.push_back(MVT::i32);
00851       opc = Hexagon::L2_loadrb_pci_pseudo;
00852       memsize = 1;
00853       align = 1;
00854       MvtSize = MVT::i8;
00855     } else if (IntNo == Intrinsic::hexagon_circ_ldub) {
00856       ResTys.push_back(MVT::i32);
00857       ResTys.push_back(MVT::i32);
00858       opc = Hexagon::L2_loadrub_pci_pseudo;
00859       memsize = 1;
00860       align = 1;
00861       MvtSize = MVT::i8;
00862     } else
00863       llvm_unreachable("no opc");
00864 
00865     ResTys.push_back(MVT::Other);
00866 
00867     // Copy over the arguments, which are the same mostly.
00868     SmallVector<SDValue, 5> Ops;
00869     Ops.push_back(Base);
00870     Ops.push_back(Load);
00871     Ops.push_back(ModifierExpr);
00872     int32_t Val = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
00873     Ops.push_back(CurDAG->getTargetConstant(Val, dl, MVT::i32));
00874     Ops.push_back(Chain);
00875     SDNode* Result = CurDAG->getMachineNode(opc, dl, ResTys, Ops);
00876 
00877     SDValue ST;
00878     MachineMemOperand *Mem =
00879       MF->getMachineMemOperand(MachinePointerInfo(),
00880                                MachineMemOperand::MOStore, memsize, align);
00881     if (MvtSize != MVT::i32)
00882       ST = CurDAG->getTruncStore(Chain, dl, SDValue(Result, 1), Load,
00883                                  MvtSize, Mem);
00884     else
00885       ST = CurDAG->getStore(Chain, dl, SDValue(Result, 1), Load, Mem);
00886 
00887     SDNode* Store = SelectStore(ST.getNode());
00888 
00889     const SDValue Froms[] = { SDValue(N, 0),
00890                               SDValue(N, 1) };
00891     const SDValue Tos[]   = { SDValue(Result, 0),
00892                               SDValue(Store, 0) };
00893     ReplaceUses(Froms, Tos, 2);
00894     return Result;
00895   }
00896 
00897   if (IntNo == Intrinsic::hexagon_brev_ldd  ||
00898       IntNo == Intrinsic::hexagon_brev_ldw  ||
00899       IntNo == Intrinsic::hexagon_brev_ldh  ||
00900       IntNo == Intrinsic::hexagon_brev_lduh ||
00901       IntNo == Intrinsic::hexagon_brev_ldb  ||
00902       IntNo == Intrinsic::hexagon_brev_ldub) {
00903     SDLoc dl(N);
00904     SDValue Chain = N->getOperand(0);
00905     SDValue Base = N->getOperand(2);
00906     SDValue Load = N->getOperand(3);
00907     SDValue ModifierExpr = N->getOperand(4);
00908 
00909     // We need to add the rerurn type for the load.  This intrinsic has
00910     // two return types, one for the load and one for the post-increment.
00911     std::vector<EVT> ResTys;
00912     unsigned opc;
00913     unsigned memsize, align;
00914     MVT MvtSize = MVT::i32;
00915 
00916     if (IntNo == Intrinsic::hexagon_brev_ldd) {
00917       ResTys.push_back(MVT::i32);
00918       ResTys.push_back(MVT::i64);
00919       opc = Hexagon::L2_loadrd_pbr_pseudo;
00920       memsize = 8;
00921       align = 8;
00922     } else if (IntNo == Intrinsic::hexagon_brev_ldw) {
00923       ResTys.push_back(MVT::i32);
00924       ResTys.push_back(MVT::i32);
00925       opc = Hexagon::L2_loadri_pbr_pseudo;
00926       memsize = 4;
00927       align = 4;
00928     } else if (IntNo == Intrinsic::hexagon_brev_ldh) {
00929       ResTys.push_back(MVT::i32);
00930       ResTys.push_back(MVT::i32);
00931       opc = Hexagon::L2_loadrh_pbr_pseudo;
00932       memsize = 2;
00933       align = 2;
00934       MvtSize = MVT::i16;
00935     } else if (IntNo == Intrinsic::hexagon_brev_lduh) {
00936       ResTys.push_back(MVT::i32);
00937       ResTys.push_back(MVT::i32);
00938       opc = Hexagon::L2_loadruh_pbr_pseudo;
00939       memsize = 2;
00940       align = 2;
00941       MvtSize = MVT::i16;
00942     } else if (IntNo == Intrinsic::hexagon_brev_ldb) {
00943       ResTys.push_back(MVT::i32);
00944       ResTys.push_back(MVT::i32);
00945       opc = Hexagon::L2_loadrb_pbr_pseudo;
00946       memsize = 1;
00947       align = 1;
00948       MvtSize = MVT::i8;
00949     } else if (IntNo == Intrinsic::hexagon_brev_ldub) {
00950       ResTys.push_back(MVT::i32);
00951       ResTys.push_back(MVT::i32);
00952       opc = Hexagon::L2_loadrub_pbr_pseudo;
00953       memsize = 1;
00954       align = 1;
00955       MvtSize = MVT::i8;
00956     } else
00957       llvm_unreachable("no opc");
00958 
00959     ResTys.push_back(MVT::Other);
00960 
00961     // Copy over the arguments, which are the same mostly.
00962     SmallVector<SDValue, 4> Ops;
00963     Ops.push_back(Base);
00964     Ops.push_back(Load);
00965     Ops.push_back(ModifierExpr);
00966     Ops.push_back(Chain);
00967     SDNode* Result = CurDAG->getMachineNode(opc, dl, ResTys, Ops);
00968     SDValue ST;
00969     MachineMemOperand *Mem =
00970       MF->getMachineMemOperand(MachinePointerInfo(),
00971                                MachineMemOperand::MOStore, memsize, align);
00972     if (MvtSize != MVT::i32)
00973       ST = CurDAG->getTruncStore(Chain, dl, SDValue(Result, 1), Load,
00974                                  MvtSize, Mem);
00975     else
00976       ST = CurDAG->getStore(Chain, dl, SDValue(Result, 1), Load, Mem);
00977 
00978     SDNode* Store = SelectStore(ST.getNode());
00979 
00980     const SDValue Froms[] = { SDValue(N, 0),
00981                               SDValue(N, 1) };
00982     const SDValue Tos[]   = { SDValue(Result, 0),
00983                               SDValue(Store, 0) };
00984     ReplaceUses(Froms, Tos, 2);
00985     return Result;
00986   }
00987 
00988   return SelectCode(N);
00989 }
00990 
00991 //
00992 // Checking for intrinsics which have predicate registers as operand(s)
00993 // and lowering to the actual intrinsic.
00994 //
00995 SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
00996   unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
00997   unsigned Bits;
00998   switch (IID) {
00999   case Intrinsic::hexagon_S2_vsplatrb:
01000     Bits = 8;
01001     break;
01002   case Intrinsic::hexagon_S2_vsplatrh:
01003     Bits = 16;
01004     break;
01005   default:
01006     return SelectCode(N);
01007   }
01008 
01009   SDValue const &V = N->getOperand(1);
01010   SDValue U;
01011   if (isValueExtension(V, Bits, U)) {
01012     SDValue R = CurDAG->getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
01013       N->getOperand(0), U);
01014     return SelectCode(R.getNode());
01015   }
01016   return SelectCode(N);
01017 }
01018 
01019 //
01020 // Map floating point constant values.
01021 //
01022 SDNode *HexagonDAGToDAGISel::SelectConstantFP(SDNode *N) {
01023   SDLoc dl(N);
01024   ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
01025   APFloat APF = CN->getValueAPF();
01026   if (N->getValueType(0) == MVT::f32) {
01027     return CurDAG->getMachineNode(Hexagon::TFRI_f, dl, MVT::f32,
01028               CurDAG->getTargetConstantFP(APF.convertToFloat(), dl, MVT::f32));
01029   }
01030   else if (N->getValueType(0) == MVT::f64) {
01031     return CurDAG->getMachineNode(Hexagon::CONST64_Float_Real, dl, MVT::f64,
01032               CurDAG->getTargetConstantFP(APF.convertToDouble(), dl, MVT::f64));
01033   }
01034 
01035   return SelectCode(N);
01036 }
01037 
01038 //
01039 // Map predicate true (encoded as -1 in LLVM) to a XOR.
01040 //
01041 SDNode *HexagonDAGToDAGISel::SelectConstant(SDNode *N) {
01042   SDLoc dl(N);
01043   if (N->getValueType(0) == MVT::i1) {
01044     SDNode* Result = 0;
01045     int32_t Val = cast<ConstantSDNode>(N)->getSExtValue();
01046     if (Val == -1) {
01047       Result = CurDAG->getMachineNode(Hexagon::TFR_PdTrue, dl, MVT::i1);
01048     } else if (Val == 0) {
01049       Result = CurDAG->getMachineNode(Hexagon::TFR_PdFalse, dl, MVT::i1);
01050     }
01051     if (Result) {
01052       ReplaceUses(N, Result);
01053       return Result;
01054     }
01055   }
01056 
01057   return SelectCode(N);
01058 }
01059 
01060 
01061 //
01062 // Map add followed by a asr -> asr +=.
01063 //
01064 SDNode *HexagonDAGToDAGISel::SelectAdd(SDNode *N) {
01065   SDLoc dl(N);
01066   if (N->getValueType(0) != MVT::i32) {
01067     return SelectCode(N);
01068   }
01069   // Identify nodes of the form: add(asr(...)).
01070   SDNode* Src1 = N->getOperand(0).getNode();
01071   if (Src1->getOpcode() != ISD::SRA || !Src1->hasOneUse()
01072       || Src1->getValueType(0) != MVT::i32) {
01073     return SelectCode(N);
01074   }
01075 
01076   // Build Rd = Rd' + asr(Rs, Rt). The machine constraints will ensure that
01077   // Rd and Rd' are assigned to the same register
01078   SDNode* Result = CurDAG->getMachineNode(Hexagon::S2_asr_r_r_acc, dl, MVT::i32,
01079                                           N->getOperand(1),
01080                                           Src1->getOperand(0),
01081                                           Src1->getOperand(1));
01082   ReplaceUses(N, Result);
01083 
01084   return Result;
01085 }
01086 
01087 //
01088 // Map the following, where possible.
01089 // AND/FABS -> clrbit
01090 // OR -> setbit
01091 // XOR/FNEG ->toggle_bit.
01092 //
01093 SDNode *HexagonDAGToDAGISel::SelectBitOp(SDNode *N) {
01094   SDLoc dl(N);
01095   EVT ValueVT = N->getValueType(0);
01096 
01097   // We handle only 32 and 64-bit bit ops.
01098   if (!(ValueVT == MVT::i32 || ValueVT == MVT::i64 ||
01099         ValueVT == MVT::f32 || ValueVT == MVT::f64))
01100     return SelectCode(N);
01101 
01102   // We handly only fabs and fneg for V5.
01103   unsigned Opc = N->getOpcode();
01104   if ((Opc == ISD::FABS || Opc == ISD::FNEG) && !HST->hasV5TOps())
01105     return SelectCode(N);
01106 
01107   int64_t Val = 0;
01108   if (Opc != ISD::FABS && Opc != ISD::FNEG) {
01109     if (N->getOperand(1).getOpcode() == ISD::Constant)
01110       Val = cast<ConstantSDNode>((N)->getOperand(1))->getSExtValue();
01111     else
01112      return SelectCode(N);
01113   }
01114 
01115   if (Opc == ISD::AND) {
01116     if (((ValueVT == MVT::i32) &&
01117                   (!((Val & 0x80000000) || (Val & 0x7fffffff)))) ||
01118         ((ValueVT == MVT::i64) &&
01119                   (!((Val & 0x8000000000000000) || (Val & 0x7fffffff)))))
01120       // If it's simple AND, do the normal op.
01121       return SelectCode(N);
01122     else
01123       Val = ~Val;
01124   }
01125 
01126   // If OR or AND is being fed by shl, srl and, sra don't do this change,
01127   // because Hexagon provide |= &= on shl, srl, and sra.
01128   // Traverse the DAG to see if there is shl, srl and sra.
01129   if (Opc == ISD::OR || Opc == ISD::AND) {
01130     switch (N->getOperand(0)->getOpcode()) {
01131       default: break;
01132       case ISD::SRA:
01133       case ISD::SRL:
01134       case ISD::SHL:
01135         return SelectCode(N);
01136     }
01137   }
01138 
01139   // Make sure it's power of 2.
01140   unsigned bitpos = 0;
01141   if (Opc != ISD::FABS && Opc != ISD::FNEG) {
01142     if (((ValueVT == MVT::i32) && !isPowerOf2_32(Val)) ||
01143         ((ValueVT == MVT::i64) && !isPowerOf2_64(Val)))
01144       return SelectCode(N);
01145 
01146     // Get the bit position.
01147     bitpos = countTrailingZeros(uint64_t(Val));
01148   } else {
01149     // For fabs and fneg, it's always the 31st bit.
01150     bitpos = 31;
01151   }
01152 
01153   unsigned BitOpc = 0;
01154   // Set the right opcode for bitwise operations.
01155   switch(Opc) {
01156     default: llvm_unreachable("Only bit-wise/abs/neg operations are allowed.");
01157     case ISD::AND:
01158     case ISD::FABS:
01159       BitOpc = Hexagon::S2_clrbit_i;
01160       break;
01161     case ISD::OR:
01162       BitOpc = Hexagon::S2_setbit_i;
01163       break;
01164     case ISD::XOR:
01165     case ISD::FNEG:
01166       BitOpc = Hexagon::S2_togglebit_i;
01167       break;
01168   }
01169 
01170   SDNode *Result;
01171   // Get the right SDVal for the opcode.
01172   SDValue SDVal = CurDAG->getTargetConstant(bitpos, dl, MVT::i32);
01173 
01174   if (ValueVT == MVT::i32 || ValueVT == MVT::f32) {
01175     Result = CurDAG->getMachineNode(BitOpc, dl, ValueVT,
01176                                     N->getOperand(0), SDVal);
01177   } else {
01178     // 64-bit gymnastic to use REG_SEQUENCE. But it's worth it.
01179     EVT SubValueVT;
01180     if (ValueVT == MVT::i64)
01181       SubValueVT = MVT::i32;
01182     else
01183       SubValueVT = MVT::f32;
01184 
01185     SDNode *Reg = N->getOperand(0).getNode();
01186     SDValue RegClass = CurDAG->getTargetConstant(Hexagon::DoubleRegsRegClassID,
01187                                                  dl, MVT::i64);
01188 
01189     SDValue SubregHiIdx = CurDAG->getTargetConstant(Hexagon::subreg_hireg, dl,
01190                                                     MVT::i32);
01191     SDValue SubregLoIdx = CurDAG->getTargetConstant(Hexagon::subreg_loreg, dl,
01192                                                     MVT::i32);
01193 
01194     SDValue SubregHI = CurDAG->getTargetExtractSubreg(Hexagon::subreg_hireg, dl,
01195                                                     MVT::i32, SDValue(Reg, 0));
01196 
01197     SDValue SubregLO = CurDAG->getTargetExtractSubreg(Hexagon::subreg_loreg, dl,
01198                                                     MVT::i32, SDValue(Reg, 0));
01199 
01200     // Clear/set/toggle hi or lo registers depending on the bit position.
01201     if (SubValueVT != MVT::f32 && bitpos < 32) {
01202       SDNode *Result0 = CurDAG->getMachineNode(BitOpc, dl, SubValueVT,
01203                                                SubregLO, SDVal);
01204       const SDValue Ops[] = { RegClass, SubregHI, SubregHiIdx,
01205                               SDValue(Result0, 0), SubregLoIdx };
01206       Result = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
01207                                       dl, ValueVT, Ops);
01208     } else {
01209       if (Opc != ISD::FABS && Opc != ISD::FNEG)
01210         SDVal = CurDAG->getTargetConstant(bitpos - 32, dl, MVT::i32);
01211       SDNode *Result0 = CurDAG->getMachineNode(BitOpc, dl, SubValueVT,
01212                                                SubregHI, SDVal);
01213       const SDValue Ops[] = { RegClass, SDValue(Result0, 0), SubregHiIdx,
01214                               SubregLO, SubregLoIdx };
01215       Result = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
01216                                       dl, ValueVT, Ops);
01217     }
01218   }
01219 
01220   ReplaceUses(N, Result);
01221   return Result;
01222 }
01223 
01224 
01225 SDNode *HexagonDAGToDAGISel::SelectFrameIndex(SDNode *N) {
01226   MachineFrameInfo *MFI = MF->getFrameInfo();
01227   const HexagonFrameLowering *HFI = HST->getFrameLowering();
01228   int FX = cast<FrameIndexSDNode>(N)->getIndex();
01229   unsigned StkA = HFI->getStackAlignment();
01230   unsigned MaxA = MFI->getMaxAlignment();
01231   SDValue FI = CurDAG->getTargetFrameIndex(FX, MVT::i32);
01232   SDLoc DL(N);
01233   SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
01234   SDNode *R = 0;
01235 
01236   // Use TFR_FI when:
01237   // - the object is fixed, or
01238   // - there are no objects with higher-than-default alignment, or
01239   // - there are no dynamically allocated objects.
01240   // Otherwise, use TFR_FIA.
01241   if (FX < 0 || MaxA <= StkA || !MFI->hasVarSizedObjects()) {
01242     R = CurDAG->getMachineNode(Hexagon::TFR_FI, DL, MVT::i32, FI, Zero);
01243   } else {
01244     auto &HMFI = *MF->getInfo<HexagonMachineFunctionInfo>();
01245     unsigned AR = HMFI.getStackAlignBaseVReg();
01246     SDValue CH = CurDAG->getEntryNode();
01247     SDValue Ops[] = { CurDAG->getCopyFromReg(CH, DL, AR, MVT::i32), FI, Zero };
01248     R = CurDAG->getMachineNode(Hexagon::TFR_FIA, DL, MVT::i32, Ops);
01249   }
01250 
01251   if (N->getHasDebugValue())
01252     CurDAG->TransferDbgValues(SDValue(N, 0), SDValue(R, 0));
01253   return R;
01254 }
01255 
01256 
01257 SDNode *HexagonDAGToDAGISel::Select(SDNode *N) {
01258   if (N->isMachineOpcode()) {
01259     N->setNodeId(-1);
01260     return nullptr;   // Already selected.
01261   }
01262 
01263   switch (N->getOpcode()) {
01264   case ISD::Constant:
01265     return SelectConstant(N);
01266 
01267   case ISD::ConstantFP:
01268     return SelectConstantFP(N);
01269 
01270   case ISD::FrameIndex:
01271     return SelectFrameIndex(N);
01272 
01273   case ISD::ADD:
01274     return SelectAdd(N);
01275 
01276   case ISD::SHL:
01277     return SelectSHL(N);
01278 
01279   case ISD::LOAD:
01280     return SelectLoad(N);
01281 
01282   case ISD::STORE:
01283     return SelectStore(N);
01284 
01285   case ISD::MUL:
01286     return SelectMul(N);
01287 
01288   case ISD::AND:
01289   case ISD::OR:
01290   case ISD::XOR:
01291   case ISD::FABS:
01292   case ISD::FNEG:
01293     return SelectBitOp(N);
01294 
01295   case ISD::ZERO_EXTEND:
01296     return SelectZeroExtend(N);
01297 
01298   case ISD::INTRINSIC_W_CHAIN:
01299     return SelectIntrinsicWChain(N);
01300 
01301   case ISD::INTRINSIC_WO_CHAIN:
01302     return SelectIntrinsicWOChain(N);
01303   }
01304 
01305   return SelectCode(N);
01306 }
01307 
01308 bool HexagonDAGToDAGISel::
01309 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
01310                              std::vector<SDValue> &OutOps) {
01311   SDValue Inp = Op, Res;
01312 
01313   switch (ConstraintID) {
01314   default:
01315     return true;
01316   case InlineAsm::Constraint_i:
01317   case InlineAsm::Constraint_o: // Offsetable.
01318   case InlineAsm::Constraint_v: // Not offsetable.
01319   case InlineAsm::Constraint_m: // Memory.
01320     if (SelectAddrFI(Inp, Res))
01321       OutOps.push_back(Res);
01322     else
01323       OutOps.push_back(Inp);
01324     break;
01325   }
01326 
01327   OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
01328   return false;
01329 }
01330 
01331 bool HexagonDAGToDAGISel::isConstExtProfitable(SDNode *N) const {
01332   unsigned UseCount = 0;
01333   unsigned CallCount = 0;
01334   for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
01335     // Ignore call instructions.
01336     if (I->getOpcode() == ISD::CopyToReg)
01337       ++CallCount;
01338     UseCount++;
01339   }
01340 
01341   return (UseCount <= 1) || (CallCount > 1);
01342 
01343 }
01344 
01345 void HexagonDAGToDAGISel::PreprocessISelDAG() {
01346   SelectionDAG &DAG = *CurDAG;
01347   std::vector<SDNode*> Nodes;
01348   for (auto I = DAG.allnodes_begin(), E = DAG.allnodes_end(); I != E; ++I)
01349     Nodes.push_back(I);
01350 
01351   // Simplify: (or (select c x 0) z)  ->  (select c (or x z) z)
01352   //           (or (select c 0 y) z)  ->  (select c z (or y z))
01353   // This may not be the right thing for all targets, so do it here.
01354   for (auto I: Nodes) {
01355     if (I->getOpcode() != ISD::OR)
01356       continue;
01357 
01358     auto IsZero = [] (const SDValue &V) -> bool {
01359       if (ConstantSDNode *SC = dyn_cast<ConstantSDNode>(V.getNode()))
01360         return SC->isNullValue();
01361       return false;
01362     };
01363     auto IsSelect0 = [IsZero] (const SDValue &Op) -> bool {
01364       if (Op.getOpcode() != ISD::SELECT)
01365         return false;
01366       return IsZero(Op.getOperand(1))  || IsZero(Op.getOperand(2));
01367     };
01368 
01369     SDValue N0 = I->getOperand(0), N1 = I->getOperand(1);
01370     EVT VT = I->getValueType(0);
01371     bool SelN0 = IsSelect0(N0);
01372     SDValue SOp = SelN0 ? N0 : N1;
01373     SDValue VOp = SelN0 ? N1 : N0;
01374 
01375     if (SOp.getOpcode() == ISD::SELECT && SOp.getNode()->hasOneUse()) {
01376       SDValue SC = SOp.getOperand(0);
01377       SDValue SX = SOp.getOperand(1);
01378       SDValue SY = SOp.getOperand(2);
01379       SDLoc DLS = SOp;
01380       if (IsZero(SY)) {
01381         SDValue NewOr = DAG.getNode(ISD::OR, DLS, VT, SX, VOp);
01382         SDValue NewSel = DAG.getNode(ISD::SELECT, DLS, VT, SC, NewOr, VOp);
01383         DAG.ReplaceAllUsesWith(I, NewSel.getNode());
01384       } else if (IsZero(SX)) {
01385         SDValue NewOr = DAG.getNode(ISD::OR, DLS, VT, SY, VOp);
01386         SDValue NewSel = DAG.getNode(ISD::SELECT, DLS, VT, SC, VOp, NewOr);
01387         DAG.ReplaceAllUsesWith(I, NewSel.getNode());
01388       }
01389     }
01390   }
01391 }
01392 
01393 void HexagonDAGToDAGISel::EmitFunctionEntryCode() {
01394   auto &HST = static_cast<const HexagonSubtarget&>(MF->getSubtarget());
01395   auto &HFI = *HST.getFrameLowering();
01396   if (!HFI.needsAligna(*MF))
01397     return;
01398 
01399   MachineFrameInfo *MFI = MF->getFrameInfo();
01400   MachineBasicBlock *EntryBB = MF->begin();
01401   unsigned AR = FuncInfo->CreateReg(MVT::i32);
01402   unsigned MaxA = MFI->getMaxAlignment();
01403   auto &HII = *HST.getInstrInfo();
01404   BuildMI(EntryBB, DebugLoc(), HII.get(Hexagon::ALIGNA), AR)
01405       .addImm(MaxA);
01406   MF->getInfo<HexagonMachineFunctionInfo>()->setStackAlignBaseVReg(AR);
01407 }
01408 
01409 // Match a frame index that can be used in an addressing mode.
01410 bool HexagonDAGToDAGISel::SelectAddrFI(SDValue& N, SDValue &R) {
01411   if (N.getOpcode() != ISD::FrameIndex)
01412     return false;
01413   auto &HFI = *HST->getFrameLowering();
01414   MachineFrameInfo *MFI = MF->getFrameInfo();
01415   int FX = cast<FrameIndexSDNode>(N)->getIndex();
01416   if (!MFI->isFixedObjectIndex(FX) && HFI.needsAligna(*MF))
01417     return false;
01418   R = CurDAG->getTargetFrameIndex(FX, MVT::i32);
01419   return true;
01420 }
01421 
01422 inline bool HexagonDAGToDAGISel::SelectAddrGA(SDValue &N, SDValue &R) {
01423   return SelectGlobalAddress(N, R, false);
01424 }
01425 
01426 inline bool HexagonDAGToDAGISel::SelectAddrGP(SDValue &N, SDValue &R) {
01427   return SelectGlobalAddress(N, R, true);
01428 }
01429 
01430 bool HexagonDAGToDAGISel::SelectGlobalAddress(SDValue &N, SDValue &R,
01431                                               bool UseGP) {
01432   switch (N.getOpcode()) {
01433   case ISD::ADD: {
01434     SDValue N0 = N.getOperand(0);
01435     SDValue N1 = N.getOperand(1);
01436     unsigned GAOpc = N0.getOpcode();
01437     if (UseGP && GAOpc != HexagonISD::CONST32_GP)
01438       return false;
01439     if (!UseGP && GAOpc != HexagonISD::CONST32)
01440       return false;
01441     if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N1)) {
01442       SDValue Addr = N0.getOperand(0);
01443       if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Addr)) {
01444         if (GA->getOpcode() == ISD::TargetGlobalAddress) {
01445           uint64_t NewOff = GA->getOffset() + (uint64_t)Const->getSExtValue();
01446           R = CurDAG->getTargetGlobalAddress(GA->getGlobal(), SDLoc(Const),
01447                                              N.getValueType(), NewOff);
01448           return true;
01449         }
01450       }
01451     }
01452     break;
01453   }
01454   case HexagonISD::CONST32:
01455     // The operand(0) of CONST32 is TargetGlobalAddress, which is what we
01456     // want in the instruction.
01457     if (!UseGP)
01458       R = N.getOperand(0);
01459     return !UseGP;
01460   case HexagonISD::CONST32_GP:
01461     if (UseGP)
01462       R = N.getOperand(0);
01463     return UseGP;
01464   default:
01465     return false;
01466   }
01467 
01468   return false;
01469 }
01470 
01471 bool HexagonDAGToDAGISel::isValueExtension(const SDValue &Val,
01472       unsigned FromBits, SDValue &Src) {
01473   unsigned Opc = Val.getOpcode();
01474   switch (Opc) {
01475   case ISD::SIGN_EXTEND:
01476   case ISD::ZERO_EXTEND:
01477   case ISD::ANY_EXTEND: {
01478     SDValue const &Op0 = Val.getOperand(0);
01479     EVT T = Op0.getValueType();
01480     if (T.isInteger() && T.getSizeInBits() == FromBits) {
01481       Src = Op0;
01482       return true;
01483     }
01484     break;
01485   }
01486   case ISD::SIGN_EXTEND_INREG:
01487   case ISD::AssertSext:
01488   case ISD::AssertZext:
01489     if (Val.getOperand(0).getValueType().isInteger()) {
01490       VTSDNode *T = cast<VTSDNode>(Val.getOperand(1));
01491       if (T->getVT().getSizeInBits() == FromBits) {
01492         Src = Val.getOperand(0);
01493         return true;
01494       }
01495     }
01496     break;
01497   case ISD::AND: {
01498     // Check if this is an AND with "FromBits" of lower bits set to 1.
01499     uint64_t FromMask = (1 << FromBits) - 1;
01500     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(0))) {
01501       if (C->getZExtValue() == FromMask) {
01502         Src = Val.getOperand(1);
01503         return true;
01504       }
01505     }
01506     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(1))) {
01507       if (C->getZExtValue() == FromMask) {
01508         Src = Val.getOperand(0);
01509         return true;
01510       }
01511     }
01512     break;
01513   }
01514   case ISD::OR:
01515   case ISD::XOR: {
01516     // OR/XOR with the lower "FromBits" bits set to 0.
01517     uint64_t FromMask = (1 << FromBits) - 1;
01518     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(0))) {
01519       if ((C->getZExtValue() & FromMask) == 0) {
01520         Src = Val.getOperand(1);
01521         return true;
01522       }
01523     }
01524     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(1))) {
01525       if ((C->getZExtValue() & FromMask) == 0) {
01526         Src = Val.getOperand(0);
01527         return true;
01528       }
01529     }
01530   }
01531   default:
01532     break;
01533   }
01534   return false;
01535 }