LLVM  6.0.0svn
Macros | Functions | Variables
SIRegisterInfo.cpp File Reference

SI implementation of the TargetRegisterInfo class. More...

#include "SIRegisterInfo.h"
#include "AMDGPUSubtarget.h"
#include "SIInstrInfo.h"
#include "SIMachineFunctionInfo.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/LLVMContext.h"
#include "AMDGPURegAsmNames.inc.cpp"
Include dependency graph for SIRegisterInfo.cpp:

Go to the source code of this file.

Macros

#define AMDGPU_REG_ASM_NAMES
 
#define REG_RANGE(BeginReg, EndReg, RegTable)
 

Functions

static bool hasPressureSet (const int *PSets, unsigned PSetID)
 
static unsigned findPrivateSegmentWaveByteOffsetRegIndex (unsigned RegCount)
 
static unsigned getNumSubRegsForSpillOp (unsigned Op)
 
static int getOffsetMUBUFStore (unsigned Opc)
 
static int getOffsetMUBUFLoad (unsigned Opc)
 
static bool buildMUBUFOffsetLoadStore (const SIInstrInfo *TII, MachineFrameInfo &MFI, MachineBasicBlock::iterator MI, int Index, int64_t Offset)
 
static std::pair< unsigned, unsignedgetSpillEltSize (unsigned SuperRegSize, bool Store)
 

Variables

static cl::opt< boolEnableSpillSGPRToSMEM ("amdgpu-spill-sgpr-to-smem", cl::desc("Use scalar stores to spill SGPRs if supported by subtarget"), cl::init(false))
 
static cl::opt< boolEnableSpillSGPRToVGPR ("amdgpu-spill-sgpr-to-vgpr", cl::desc("Enable spilling VGPRs to SGPRs"), cl::ReallyHidden, cl::init(true))
 

Detailed Description

SI implementation of the TargetRegisterInfo class.

Definition in file SIRegisterInfo.cpp.

Macro Definition Documentation

◆ AMDGPU_REG_ASM_NAMES

#define AMDGPU_REG_ASM_NAMES

◆ REG_RANGE

#define REG_RANGE (   BeginReg,
  EndReg,
  RegTable 
)
Value:
if (Reg >= BeginReg && Reg <= EndReg) { \
unsigned Index = Reg - BeginReg; \
assert(Index < array_lengthof(RegTable)); \
return RegTable[Index]; \
}
Reg
All possible values of the reg field in the ModR/M byte.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:720

Referenced by llvm::SIRegisterInfo::getRegAsmName().

Function Documentation

◆ buildMUBUFOffsetLoadStore()

static bool buildMUBUFOffsetLoadStore ( const SIInstrInfo TII,
MachineFrameInfo MFI,
MachineBasicBlock::iterator  MI,
int  Index,
int64_t  Offset 
)
static

◆ findPrivateSegmentWaveByteOffsetRegIndex()

static unsigned findPrivateSegmentWaveByteOffsetRegIndex ( unsigned  RegCount)
static

◆ getNumSubRegsForSpillOp()

static unsigned getNumSubRegsForSpillOp ( unsigned  Op)
static

Definition at line 391 of file SIRegisterInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().

◆ getOffsetMUBUFLoad()

static int getOffsetMUBUFLoad ( unsigned  Opc)
static

Definition at line 447 of file SIRegisterInfo.cpp.

Referenced by buildMUBUFOffsetLoadStore().

◆ getOffsetMUBUFStore()

static int getOffsetMUBUFStore ( unsigned  Opc)
static

Definition at line 426 of file SIRegisterInfo.cpp.

Referenced by buildMUBUFOffsetLoadStore().

◆ getSpillEltSize()

static std::pair<unsigned, unsigned> getSpillEltSize ( unsigned  SuperRegSize,
bool  Store 
)
static

◆ hasPressureSet()

static bool hasPressureSet ( const int *  PSets,
unsigned  PSetID 
)
static

Variable Documentation

◆ EnableSpillSGPRToSMEM

cl::opt<bool> EnableSpillSGPRToSMEM("amdgpu-spill-sgpr-to-smem", cl::desc("Use scalar stores to spill SGPRs if supported by subtarget"), cl::init(false))
static

Referenced by hasPressureSet().

◆ EnableSpillSGPRToVGPR

cl::opt<bool> EnableSpillSGPRToVGPR("amdgpu-spill-sgpr-to-vgpr", cl::desc("Enable spilling VGPRs to SGPRs"), cl::ReallyHidden, cl::init(true))
static

Referenced by hasPressureSet().