LLVM 22.0.0git
AVRISelLowering.h
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1//===-- AVRISelLowering.h - AVR DAG Lowering Interface ----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that AVR uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_AVR_ISEL_LOWERING_H
15#define LLVM_AVR_ISEL_LOWERING_H
16
19
20namespace llvm {
21
22class AVRSubtarget;
24
25/// Performs target lowering for the AVR.
27public:
28 explicit AVRTargetLowering(const AVRTargetMachine &TM,
29 const AVRSubtarget &STI);
30
31public:
32 MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override {
33 return MVT::i8;
34 }
35
37 return MVT::i8;
38 }
39
40 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
41
43 SelectionDAG &DAG) const override;
44
45 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
46 unsigned AS,
47 Instruction *I = nullptr) const override;
48
51 SelectionDAG &DAG) const override;
52
55 SelectionDAG &DAG) const override;
56
57 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
58
60 EVT VT) const override;
61
64 MachineBasicBlock *MBB) const override;
65
66 ConstraintType getConstraintType(StringRef Constraint) const override;
67
70 const char *constraint) const override;
71
72 std::pair<unsigned, const TargetRegisterClass *>
74 StringRef Constraint, MVT VT) const override;
75
77 getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
78
80 std::vector<SDValue> &Ops,
81 SelectionDAG &DAG) const override;
82
83 Register getRegisterByName(const char *RegName, LLT VT,
84 const MachineFunction &MF) const override;
85
87 const DataLayout &DL) const override {
88 return false;
89 }
90
93 unsigned ExpansionFactor) const override {
95 }
96
97 bool softPromoteHalfType() const override { return true; }
98
99private:
100 SDValue getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AVRcc,
101 SelectionDAG &DAG, SDLoc dl) const;
102 SDValue getAVRCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
103 SDLoc dl) const;
104 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
105 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
106 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
107 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
109 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
111 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
113
114 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
115 bool isVarArg,
117 LLVMContext &Context, const Type *RetTy) const override;
118
119 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
121 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
122 SelectionDAG &DAG) const override;
123 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
124 bool isVarArg,
126 const SDLoc &dl, SelectionDAG &DAG,
127 SmallVectorImpl<SDValue> &InVals) const override;
129 SmallVectorImpl<SDValue> &InVals) const override;
131 CallingConv::ID CallConv, bool isVarArg,
133 const SDLoc &dl, SelectionDAG &DAG,
134 SmallVectorImpl<SDValue> &InVals) const;
135
136protected:
138
139private:
141 bool Tiny) const;
142 MachineBasicBlock *insertWideShift(MachineInstr &MI,
143 MachineBasicBlock *BB) const;
144 MachineBasicBlock *insertMul(MachineInstr &MI, MachineBasicBlock *BB) const;
145 MachineBasicBlock *insertCopyZero(MachineInstr &MI,
146 MachineBasicBlock *BB) const;
147 MachineBasicBlock *insertAtomicArithmeticOp(MachineInstr &MI,
149 unsigned Opcode, int Width) const;
150};
151
152} // end namespace llvm
153
154#endif // LLVM_AVR_ISEL_LOWERING_H
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
IRTranslator LLVM IR MI
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
#define RegName(no)
lazy value info
#define I(x, y, z)
Definition MD5.cpp:58
Register const TargetRegisterInfo * TRI
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad, bool isV9, bool is64Bit)
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad, bool isV9, bool is64Bit)
This file describes how to lower LLVM code to machine code.
Value * RHS
Value * LHS
static SDValue LowerCallResult(SDValue Chain, SDValue InGlue, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
A specific AVR target MCU.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
Replace a node with an illegal result type with a new node built out of custom code.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
bool shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL) const override
For most targets, an LLVM type must be broken down into multiple smaller types.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
const AVRSubtarget & Subtarget
ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const override
InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
bool softPromoteHalfType() const override
MVT::SimpleValueType getCmpLibcallReturnType() const override
Return the ValueType for comparison libcalls.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
AVRTargetLowering(const AVRTargetMachine &TM, const AVRSubtarget &STI)
void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
A generic AVR implementation.
A parsed version of the target data layout string in and methods for querying it.
Definition DataLayout.h:63
This is an important class for using LLVM in a threaded context.
Definition LLVMContext.h:68
Machine Value Type.
Representation of each machine instruction.
Wrapper class representing virtual and physical registers.
Definition Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
StringRef - Represent a constant reference to a string, i.e.
Definition StringRef.h:55
ShiftLegalizationStrategy
Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recu...
TargetLowering(const TargetLowering &)=delete
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition Type.h:45
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition CallingConv.h:24
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
This is an optimization pass for GlobalISel generic memory operations.
@ Offset
Definition DWP.cpp:477
DWARFExpression::Operation Op
#define N
Extended Value Type.
Definition ValueTypes.h:35
This structure contains all information that is necessary for lowering calls.