9#ifndef LLVM_MC_MCPARSER_MCTARGETASMPARSER_H
10#define LLVM_MC_MCPARSER_MCTARGETASMPARSER_H
31template <
typename T>
class SmallVectorImpl;
76 StringRef offsetName, int64_t imm,
bool needBracs)
90 return (
Scale == 1) ||
107 bool Restricted =
false)
136#if __cplusplus >= 202002L
139 static constexpr StatusTy
Success = StatusTy::Success;
140 static constexpr StatusTy
Failure = StatusTy::Failure;
141 static constexpr StatusTy
NoMatch = StatusTy::NoMatch;
243 Result.Features = MissingFeatures;
253 Result.PredicateError = FailureCode;
263 unsigned OperandClass,
unsigned Opcode,
264 unsigned OperandIndex) {
267 Result.MissedOperand.Error = OperandError;
268 Result.MissedOperand.Class = OperandClass;
269 Result.MissedOperand.Opcode = Opcode;
270 Result.MissedOperand.Index = OperandIndex;
281 Result.TooFewOperands.Class = OperandClass;
282 Result.TooFewOperands.Opcode = Opcode;
329 struct MissedOpInfo {
336 struct TooFewOperandsInfo {
483 bool MatchingInlineAsm) = 0;
static uint64_t scale(uint64_t Num, uint32_t N, uint32_t D)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
#define LLVM_DEPRECATED(MSG, FIX)
mir Rename Register Operands
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Target independent representation for an assembler token.
This class represents an Operation in the Expression.
Base class for user error types.
Lightweight error class with error context and mandatory checking.
Container class for subtarget features.
Generic interface for extending the MCAsmParser, which is implemented by target and object file assem...
MCAsmParser & getParser()
Generic Sema callback for assembly parser.
virtual bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc, AsmTypeInfo *TypeInfo)=0
Parse a primary expression.
Context object for machine code objects.
Base class for the full range of assembler expressions which are needed for parsing.
Instances of this class represent a single low-level machine instruction.
Interface to description of machine instruction set.
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand.
Wrapper class representing physical registers. Should be passed by value.
Streaming machine code generation interface.
Generic base class for all target subtargets.
static VariantKind getVariantKindForName(StringRef Name)
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
MCTargetAsmParser - Generic interface to target specific assembly parsers.
virtual ParseStatus parseDirective(AsmToken DirectiveID)
Parses a target-specific assembler directive.
virtual void onLabelParsed(MCSymbol *Symbol)
const FeatureBitset & getAvailableFeatures() const
virtual void convertToMapAndConstraints(unsigned Kind, const OperandVector &Operands)=0
MCTargetOptions MCOptions
Set of options which affects instrumentation of inline assembly.
MCSubtargetInfo & copySTI()
Create a copy of STI and return a non-const reference to it.
bool ParsingMSInlineAsm
ParsingMSInlineAsm - Are we parsing ms-style inline assembly?
virtual bool equalIsAsmAssignment()
@ FIRST_TARGET_MATCH_RESULT_TY
@ Match_InvalidTiedOperand
virtual bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc)=0
virtual bool ParseDirective(AsmToken DirectiveID)
ParseDirective - Parse a target specific assembler directive This method is deprecated,...
MCAsmParserSemaCallback * SemaCallback
SemaCallback - The Sema callback implementation.
void setParsingMSInlineAsm(bool Value)
virtual void onBeginOfFile()
virtual bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc)
virtual unsigned checkEarlyTargetMatchPredicate(MCInst &Inst, const OperandVector &Operands)
Validate the instruction match against any complex target predicates before rendering any operands to...
virtual ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc)=0
tryParseRegister - parse one register if possible
virtual bool starIsStartOfStatement()
virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, AsmToken Token, OperandVector &Operands)
virtual bool areEqualRegs(const MCParsedAsmOperand &Op1, const MCParsedAsmOperand &Op2) const
Returns whether two operands are registers and are equal.
virtual void flushPendingInstructions(MCStreamer &Out)
Ensure that all previously parsed instructions have been emitted to the output streamer,...
bool isParsingMSInlineAsm()
virtual void onEndOfFile()
virtual bool isLabel(AsmToken &Token)
void setAvailableFeatures(const FeatureBitset &Value)
virtual MCSymbolRefExpr::VariantKind getVariantKindForName(StringRef Name) const
const MCSubtargetInfo & getSTI() const
virtual void doBeforeLabelEmit(MCSymbol *Symbol, SMLoc IDLoc)
FeatureBitset AvailableFeatures
AvailableFeatures - The current set of available features.
virtual const MCExpr * applyModifierToExpr(const MCExpr *E, MCSymbolRefExpr::VariantKind, MCContext &Ctx)
void setSemaCallback(MCAsmParserSemaCallback *Callback)
virtual const MCExpr * createTargetUnaryExpr(const MCExpr *E, AsmToken::TokenKind OperatorToken, MCContext &Ctx)
MCTargetAsmParser(const MCTargetAsmParser &)=delete
virtual bool OmitRegisterFromClobberLists(unsigned RegNo)
Allows targets to let registers opt out of clobber lists.
virtual unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind)
Allow a target to add special case operand matching for things that tblgen doesn't/can't handle effec...
~MCTargetAsmParser() override
MCTargetAsmParser & operator=(const MCTargetAsmParser &)=delete
virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands)=0
ParseInstruction - Parse one assembly instruction.
virtual unsigned checkTargetMatchPredicate(MCInst &Inst)
checkTargetMatchPredicate - Validate the instruction match against any complex target predicates not ...
MCTargetOptions getTargetOptions() const
virtual bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm)=0
MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst ...
const MCSubtargetInfo * STI
Current STI.
static NearMissInfo getMissedPredicate(unsigned FailureCode)
unsigned getOperandClass() const
static NearMissInfo getTooFewOperands(unsigned OperandClass, unsigned Opcode)
static NearMissInfo getMissedOperand(unsigned OperandError, unsigned OperandClass, unsigned Opcode, unsigned OperandIndex)
unsigned getOperandIndex() const
const FeatureBitset & getFeatures() const
NearMissKind getKind() const
static NearMissInfo getMissedFeature(const FeatureBitset &MissingFeatures)
TooFewOperandsInfo TooFewOperands
unsigned getOperandError() const
static NearMissInfo getSuccess()
unsigned getOpcode() const
unsigned getPredicateError() const
MissedOpInfo MissedOperand
Ternary parse status returned by various parse* methods.
constexpr bool isFailure() const
static constexpr StatusTy Failure
constexpr ParseStatus(bool Error)
constexpr ParseStatus(StatusTy Status)
constexpr bool isSuccess() const
static constexpr StatusTy Success
static constexpr StatusTy NoMatch
constexpr bool isNoMatch() const
constexpr ParseStatus(T)=delete
Represents a location in source code.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
This is an optimization pass for GlobalISel generic memory operations.
const char AsmRewritePrecedence[]
AsmRewrite(AsmRewriteKind kind, SMLoc loc, unsigned len=0, int64_t val=0, bool Restricted=false)
AsmRewrite(SMLoc loc, unsigned len, IntelExpr exp)
AsmRewrite(AsmRewriteKind kind, SMLoc loc, unsigned len, StringRef label)
DiagnosticPredicate(const DiagnosticPredicate &)=default
DiagnosticPredicate & operator=(const DiagnosticPredicate &)=default
DiagnosticPredicateTy Type
DiagnosticPredicate(bool Match)
DiagnosticPredicate(DiagnosticPredicateTy T)
IntelExpr(StringRef baseReg, StringRef indexReg, unsigned scale, StringRef offsetName, int64_t imm, bool needBracs)
ParseInstructionInfo(SmallVectorImpl< AsmRewrite > *rewrites)
ParseInstructionInfo()=default
SmallVectorImpl< AsmRewrite > * AsmRewrites