PPCISelDAGToDAG.cpp File Reference

#include "MCTargetDesc/PPCMCTargetDesc.h"
#include "MCTargetDesc/PPCPredicates.h"
#include "PPC.h"
#include "PPCISelLowering.h"
#include "PPCMachineFunctionInfo.h"
#include "PPCSelectionDAGInfo.h"
#include "PPCSubtarget.h"
#include "PPCTargetMachine.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/BranchProbabilityInfo.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/CodeGenTypes/MachineValueType.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/InstrTypes.h"
#include "llvm/IR/IntrinsicsPowerPC.h"
#include "llvm/IR/Module.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <iterator>
#include <limits>
#include <memory>
#include <new>
#include <tuple>
#include <utility>
#include "PPCGenDAGISel.inc"

Go to the source code of this file.

Macros
#define	DEBUG_TYPE   "ppc-isel"
#define	PASS_NAME   "PowerPC DAG->DAG Pattern Instruction Selection"

Enumerations
enum	ICmpInGPRType {   ICGPR_All , ICGPR_None , ICGPR_I32 , ICGPR_I64 ,   ICGPR_NonExtIn , ICGPR_Zext , ICGPR_Sext , ICGPR_ZextI32 ,   ICGPR_SextI32 , ICGPR_ZextI64 , ICGPR_SextI64 }

Functions
	STATISTIC (NumSextSetcc, "Number of (sext(setcc)) nodes expanded into GPR sequence.")
	STATISTIC (NumZextSetcc, "Number of (zext(setcc)) nodes expanded into GPR sequence.")
	STATISTIC (SignExtensionsAdded, "Number of sign extensions for compare inputs added.")
	STATISTIC (ZeroExtensionsAdded, "Number of zero extensions for compare inputs added.")
	STATISTIC (NumLogicOpsOnComparison, "Number of logical ops on i1 values calculated in GPR.")
	STATISTIC (OmittedForNonExtendUses, "Number of compares not eliminated as they have non-extending uses.")
	STATISTIC (NumP9Setb, "Number of compares lowered to setb.")
static bool	hasTocDataAttr (SDValue Val)
static CodeModel::Model	getCodeModel (const PPCSubtarget &Subtarget, const TargetMachine &TM, const SDNode *Node)
static bool	isInt32Immediate (SDNode *N, unsigned &Imm)
	isInt32Immediate - This method tests to see if the node is a 32-bit constant operand.
static bool	isInt64Immediate (SDNode *N, uint64_t &Imm)
	isInt64Immediate - This method tests to see if the node is a 64-bit constant operand.
static bool	isInt32Immediate (SDValue N, unsigned &Imm)
static bool	isInt64Immediate (SDValue N, uint64_t &Imm)
	isInt64Immediate - This method tests to see if the value is a 64-bit constant operand.
static unsigned	getBranchHint (unsigned PCC, const FunctionLoweringInfo &FuncInfo, const SDValue &DestMBB)
static bool	isOpcWithIntImmediate (SDNode *N, unsigned Opc, unsigned &Imm)
static bool	isThreadPointerAcquisitionNode (SDValue Base, SelectionDAG *CurDAG)
static bool	canOptimizeTLSDFormToXForm (SelectionDAG *CurDAG, SDValue Base)
static unsigned	allUsesTruncate (SelectionDAG *CurDAG, SDNode *N)
static int	findContiguousZerosAtLeast (uint64_t Imm, unsigned Num)
static SDNode *	selectI64ImmDirect (SelectionDAG *CurDAG, const SDLoc &dl, uint64_t Imm, unsigned &InstCnt)
static SDNode *	selectI64ImmDirectPrefix (SelectionDAG *CurDAG, const SDLoc &dl, uint64_t Imm, unsigned &InstCnt)
static SDNode *	selectI64Imm (SelectionDAG *CurDAG, const SDLoc &dl, uint64_t Imm, unsigned *InstCnt=nullptr)
static SDNode *	selectI64Imm (SelectionDAG *CurDAG, SDNode *N)
static PPC::Predicate	getPredicateForSetCC (ISD::CondCode CC, const EVT &VT, const PPCSubtarget *Subtarget)
static unsigned	getCRIdxForSetCC (ISD::CondCode CC, bool &Invert)
	getCRIdxForSetCC - Return the index of the condition register field associated with the SetCC condition, and whether or not the field is treated as inverted.
static unsigned int	getVCmpInst (MVT VecVT, ISD::CondCode CC, bool HasVSX, bool &Swap, bool &Negate)
static bool	mayUseP9Setb (SDNode *N, const ISD::CondCode &CC, SelectionDAG *DAG, bool &NeedSwapOps, bool &IsUnCmp)
static bool	isSWTestOp (SDValue N)
static bool	PeepholePPC64ZExtGather (SDValue Op32, SmallPtrSetImpl< SDNode * > &ToPromote)
static bool	isVSXSwap (SDValue N)
static bool	isLaneInsensitive (SDValue N)
static void	reduceVSXSwap (SDNode *N, SelectionDAG *DAG)
static bool	hasAIXSmallTLSAttr (SDValue Val)
static bool	isEligibleToFoldADDIForFasterLocalAccesses (SelectionDAG *DAG, SDValue ADDIToFold)
static void	foldADDIForFasterLocalAccesses (SDNode *N, SelectionDAG *DAG)

Variables
cl::opt< bool >	ANDIGlueBug ("expose-ppc-andi-glue-bug", cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden)
static cl::opt< bool >	UseBitPermRewriter ("ppc-use-bit-perm-rewriter", cl::init(true), cl::desc("use aggressive ppc isel for bit permutations"), cl::Hidden)
static cl::opt< bool >	BPermRewriterNoMasking ("ppc-bit-perm-rewriter-stress-rotates", cl::desc("stress rotate selection in aggressive ppc isel for " "bit permutations"), cl::Hidden)
static cl::opt< bool >	EnableBranchHint ("ppc-use-branch-hint", cl::init(true), cl::desc("Enable static hinting of branches on ppc"), cl::Hidden)
static cl::opt< bool >	EnableTLSOpt ("ppc-tls-opt", cl::init(true), cl::desc("Enable tls optimization peephole"), cl::Hidden)
static cl::opt< ICmpInGPRType >	CmpInGPR ("ppc-gpr-icmps", cl::Hidden, cl::init(ICGPR_All), cl::desc("Specify the types of comparisons to emit GPR-only code for."), cl::values(clEnumValN(ICGPR_None, "none", "Do not modify integer comparisons."), clEnumValN(ICGPR_All, "all", "All possible int comparisons in GPRs."), clEnumValN(ICGPR_I32, "i32", "Only i32 comparisons in GPRs."), clEnumValN(ICGPR_I64, "i64", "Only i64 comparisons in GPRs."), clEnumValN(ICGPR_NonExtIn, "nonextin", "Only comparisons where inputs don't need [sz]ext."), clEnumValN(ICGPR_Zext, "zext", "Only comparisons with zext result."), clEnumValN(ICGPR_ZextI32, "zexti32", "Only i32 comparisons with zext result."), clEnumValN(ICGPR_ZextI64, "zexti64", "Only i64 comparisons with zext result."), clEnumValN(ICGPR_Sext, "sext", "Only comparisons with sext result."), clEnumValN(ICGPR_SextI32, "sexti32", "Only i32 comparisons with sext result."), clEnumValN(ICGPR_SextI64, "sexti64", "Only i64 comparisons with sext result.")))

Macro Definition Documentation

DEBUG_TYPE

#define DEBUG_TYPE   "ppc-isel"

Definition at line 72 of file PPCISelDAGToDAG.cpp.

PASS_NAME

#define PASS_NAME   "PowerPC DAG->DAG Pattern Instruction Selection"

Definition at line 73 of file PPCISelDAGToDAG.cpp.

Enumeration Type Documentation

ICmpInGPRType

enum ICmpInGPRType

Enumerator
ICGPR_All
ICGPR_None
ICGPR_I32
ICGPR_I64
ICGPR_NonExtIn
ICGPR_Zext
ICGPR_Sext
ICGPR_ZextI32
ICGPR_SextI32
ICGPR_ZextI64
ICGPR_SextI64

Definition at line 114 of file PPCISelDAGToDAG.cpp.

Function Documentation

allUsesTruncate()

unsigned allUsesTruncate ( SelectionDAG * CurDAG, SDNode * N )

static

Definition at line 958 of file PPCISelDAGToDAG.cpp.

References llvm::cast(), llvm::MemSDNode::getMemoryVT(), llvm::Use::getOperandNo(), llvm::EVT::getSizeInBits(), llvm::Use::getUser(), N, Opc, llvm::ISD::STORE, and llvm::ISD::TRUNCATE.

Referenced by selectI64Imm().

canOptimizeTLSDFormToXForm()

bool canOptimizeTLSDFormToXForm ( SelectionDAG * CurDAG, SDValue Base )

static

Definition at line 743 of file PPCISelDAGToDAG.cpp.

References llvm::sampleprof::Base, llvm::dyn_cast(), llvm::TargetMachine::getOptLevel(), llvm::SelectionDAG::getTarget(), isThreadPointerAcquisitionNode(), and llvm::None.

findContiguousZerosAtLeast()

int findContiguousZerosAtLeast ( uint64_t Imm, unsigned Num )

static

Definition at line 1016 of file PPCISelDAGToDAG.cpp.

References llvm::countl_zero(), llvm::countr_zero(), llvm::Hi_32(), Imm, llvm::Lo_32(), and uint64_t.

foldADDIForFasterLocalAccesses()

void foldADDIForFasterLocalAccesses ( SDNode * N, SelectionDAG * DAG )

static

Definition at line 7688 of file PPCISelDAGToDAG.cpp.

References assert(), llvm::dyn_cast(), llvm::GlobalAddressSDNode::getGlobal(), llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::GlobalAddressSDNode::getTargetFlags(), llvm::SelectionDAG::getTargetGlobalAddress(), isEligibleToFoldADDIForFasterLocalAccesses(), N, llvm::Offset, llvm::SelectionDAG::RemoveDeadNode(), llvm::SelectionDAG::UpdateNodeOperands(), and llvm::SDNode::use_empty().

getBranchHint()

unsigned getBranchHint ( unsigned PCC, const FunctionLoweringInfo & FuncInfo, const SDValue & DestMBB )

static

Definition at line 583 of file PPCISelDAGToDAG.cpp.

References assert(), llvm::FunctionLoweringInfo::BPI, llvm::PPC::BR_NO_HINT, llvm::PPC::BR_NONTAKEN_HINT, llvm::PPC::BR_TAKEN_HINT, llvm::cast(), llvm::dbgs(), llvm::FunctionLoweringInfo::Fn, llvm::BasicBlockSDNode::getBasicBlock(), llvm::MachineBasicBlock::getBasicBlock(), llvm::BranchProbabilityInfo::getEdgeProbability(), llvm::Value::getName(), llvm::Instruction::getNumSuccessors(), llvm::Instruction::getSuccessor(), llvm::BasicBlock::getTerminator(), llvm::isa(), LLVM_DEBUG, llvm::FunctionLoweringInfo::MBB, std::swap(), and TBB.

getCodeModel()

CodeModel::Model getCodeModel ( const PPCSubtarget & Subtarget, const TargetMachine & TM, const SDNode * Node )

static

Definition at line 533 of file PPCISelDAGToDAG.cpp.

References llvm::dyn_cast(), llvm::PPCSubtarget::getCodeModel(), llvm::TargetMachine::getCodeModel(), and llvm::GlobalAddressSDNode::getGlobal().

getCRIdxForSetCC()

unsigned getCRIdxForSetCC ( ISD::CondCode CC, bool & Invert )

static

getCRIdxForSetCC - Return the index of the condition register field associated with the SetCC condition, and whether or not the field is treated as inverted.

That is, lt = 0; ge = 0 inverted.

Definition at line 4329 of file PPCISelDAGToDAG.cpp.

References llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, and llvm::ISD::SETUO.

getPredicateForSetCC()

PPC::Predicate getPredicateForSetCC ( ISD::CondCode CC, const EVT & VT, const PPCSubtarget * Subtarget )

static

Definition at line 4288 of file PPCISelDAGToDAG.cpp.

References llvm::EVT::isFloatingPoint(), llvm_unreachable, llvm::PPC::PRED_EQ, llvm::PPC::PRED_GE, llvm::PPC::PRED_GT, llvm::PPC::PRED_LE, llvm::PPC::PRED_LT, llvm::PPC::PRED_NE, llvm::PPC::PRED_NU, llvm::PPC::PRED_UN, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, and llvm::ISD::SETUO.

getVCmpInst()

unsigned int getVCmpInst ( MVT VecVT, ISD::CondCode CC, bool HasVSX, bool & Swap, bool & Negate )

static

Definition at line 4362 of file PPCISelDAGToDAG.cpp.

References llvm::MVT::isFloatingPoint(), llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, and llvm::ISD::SETUNE.

hasAIXSmallTLSAttr()

bool hasAIXSmallTLSAttr ( SDValue Val )

static

Definition at line 7624 of file PPCISelDAGToDAG.cpp.

References llvm::dyn_cast().

Referenced by isEligibleToFoldADDIForFasterLocalAccesses().

hasTocDataAttr()

bool hasTocDataAttr ( SDValue Val )

static

Definition at line 519 of file PPCISelDAGToDAG.cpp.

References llvm::dyn_cast(), llvm::dyn_cast_or_null(), llvm::GlobalAddressSDNode::getGlobal(), and llvm::GlobalVariable::hasAttribute().

isEligibleToFoldADDIForFasterLocalAccesses()

bool isEligibleToFoldADDIForFasterLocalAccesses ( SelectionDAG * DAG, SDValue ADDIToFold )

static

Definition at line 7635 of file PPCISelDAGToDAG.cpp.

References llvm::dyn_cast(), llvm::GlobalAddressSDNode::getGlobal(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getMachineOpcode(), llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::RegisterSDNode::getReg(), llvm::MachineFunction::getSubtarget(), llvm::SelectionDAG::getTarget(), llvm::GlobalAddressSDNode::getTargetFlags(), llvm::PPCSubtarget::getThreadPointerRegister(), llvm::TargetMachine::getTLSModel(), hasAIXSmallTLSAttr(), llvm::SDValue::isMachineOpcode(), llvm::TLSModel::LocalExec, llvm::PPCII::MO_TLSLD_FLAG, and llvm::PPCII::MO_TPREL_FLAG.

Referenced by foldADDIForFasterLocalAccesses().

isInt32Immediate() [1/2]

bool isInt32Immediate ( SDNode * N, unsigned & Imm )

static

isInt32Immediate - This method tests to see if the node is a 32-bit constant operand.

If so Imm will receive the 32-bit value.

Definition at line 553 of file PPCISelDAGToDAG.cpp.

References llvm::ISD::Constant, Imm, and N.

Referenced by isInt32Immediate(), and isOpcWithIntImmediate().

isInt32Immediate() [2/2]

bool isInt32Immediate ( SDValue N, unsigned & Imm )

static

Definition at line 573 of file PPCISelDAGToDAG.cpp.

References Imm, isInt32Immediate(), and N.

isInt64Immediate() [1/2]

bool isInt64Immediate ( SDNode * N, uint64_t & Imm )

static

isInt64Immediate - This method tests to see if the node is a 64-bit constant operand.

If so Imm will receive the 64-bit value.

Definition at line 563 of file PPCISelDAGToDAG.cpp.

References llvm::ISD::Constant, Imm, N, and uint64_t.

Referenced by isInt64Immediate().

isInt64Immediate() [2/2]

bool isInt64Immediate ( SDValue N, uint64_t & Imm )

static

isInt64Immediate - This method tests to see if the value is a 64-bit constant operand.

If so Imm will receive the 64-bit value.

Definition at line 579 of file PPCISelDAGToDAG.cpp.

References Imm, isInt64Immediate(), N, and uint64_t.

isLaneInsensitive()

bool isLaneInsensitive ( SDValue N )

static

Definition at line 7544 of file PPCISelDAGToDAG.cpp.

References N, and Opc.

Referenced by reduceVSXSwap().

isOpcWithIntImmediate()

bool isOpcWithIntImmediate ( SDNode * N, unsigned Opc, unsigned & Imm )

static

Definition at line 637 of file PPCISelDAGToDAG.cpp.

References Imm, isInt32Immediate(), N, and Opc.

isSWTestOp()

bool isSWTestOp ( SDValue N )

static

Definition at line 4836 of file PPCISelDAGToDAG.cpp.

References llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isa(), and N.

isThreadPointerAcquisitionNode()

bool isThreadPointerAcquisitionNode ( SDValue Base, SelectionDAG * CurDAG )

static

Definition at line 699 of file PPCISelDAGToDAG.cpp.

References assert(), llvm::sampleprof::Base, llvm::dyn_cast(), llvm::dyn_cast_or_null(), llvm::SelectionDAG::getMachineFunction(), llvm::RegisterSDNode::getReg(), llvm::MachineFunction::getSubtarget(), and llvm::PPCSubtarget::getThreadPointerRegister().

Referenced by canOptimizeTLSDFormToXForm().

isVSXSwap()

bool isVSXSwap ( SDValue N )

static

Definition at line 7524 of file PPCISelDAGToDAG.cpp.

References llvm::isa(), N, and Opc.

Referenced by reduceVSXSwap().

mayUseP9Setb()

bool mayUseP9Setb ( SDNode * N, const ISD::CondCode & CC, SelectionDAG * DAG, bool & NeedSwapOps, bool & IsUnCmp )

static

Definition at line 4696 of file PPCISelDAGToDAG.cpp.

References assert(), llvm::cast(), llvm::dbgs(), llvm::dyn_cast(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getSExtValue(), llvm::SDValue::hasOneUse(), LHS, LLVM_DEBUG, N, RHS, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGT, llvm::ISD::SETULT, llvm::ISD::SIGN_EXTEND, std::swap(), and llvm::ISD::ZERO_EXTEND.

PeepholePPC64ZExtGather()

bool PeepholePPC64ZExtGather ( SDValue Op32, SmallPtrSetImpl< SDNode * > & ToPromote )

static

Definition at line 7212 of file PPCISelDAGToDAG.cpp.

References B(), llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getMachineOpcode(), llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::SmallPtrSetImpl< PtrType >::insert_range(), llvm::SDValue::isMachineOpcode(), llvm::isUInt(), and PeepholePPC64ZExtGather().

Referenced by PeepholePPC64ZExtGather().

reduceVSXSwap()

void reduceVSXSwap ( SDNode * N, SelectionDAG * DAG )

static

Definition at line 7593 of file PPCISelDAGToDAG.cpp.

References llvm::SDValue::getOperand(), isLaneInsensitive(), isVSXSwap(), LHS, N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), RHS, and SDValue().

selectI64Imm() [1/2]

SDNode * selectI64Imm ( SelectionDAG * CurDAG, const SDLoc & dl, uint64_t Imm, unsigned * InstCnt = nullptr )

static

Definition at line 1386 of file PPCISelDAGToDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMachineNode(), llvm::MachineFunction::getSubtarget(), llvm::SelectionDAG::getTargetConstant(), llvm::Hi_32(), Imm, llvm::Lo_32(), SDValue(), selectI64ImmDirect(), selectI64ImmDirectPrefix(), and uint64_t.

Referenced by selectI64Imm().

selectI64Imm() [2/2]

SDNode * selectI64Imm ( SelectionDAG * CurDAG, SDNode * N )

static

Definition at line 1492 of file PPCISelDAGToDAG.cpp.

References allUsesTruncate(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), Imm, llvm::isInt(), N, selectI64Imm(), llvm::SignExtend64(), and uint64_t.

selectI64ImmDirect()

SDNode * selectI64ImmDirect ( SelectionDAG * CurDAG, const SDLoc & dl, uint64_t Imm, unsigned & InstCnt )

static

Definition at line 1025 of file PPCISelDAGToDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, assert(), llvm::countl_one(), llvm::countl_zero(), llvm::countr_one(), llvm::countr_zero(), findContiguousZerosAtLeast(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::APInt::getZExtValue(), llvm::Hi_32(), Imm, llvm::isInt(), llvm::Lo_32(), llvm::APInt::rotr(), SDValue(), and uint64_t.

Referenced by selectI64Imm().

selectI64ImmDirectPrefix()

SDNode * selectI64ImmDirectPrefix ( SelectionDAG * CurDAG, const SDLoc & dl, uint64_t Imm, unsigned & InstCnt )

static

Definition at line 1266 of file PPCISelDAGToDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::countl_one(), llvm::countl_zero(), llvm::countr_one(), llvm::countr_zero(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::APInt::getZExtValue(), llvm::Hi_32(), Imm, llvm::isInt(), llvm::Lo_32(), llvm::APInt::rotr(), SDValue(), llvm::APInt::sext(), and uint64_t.

Referenced by selectI64Imm().

STATISTIC() [1/7]

STATISTIC	(	NumLogicOpsOnComparison	,
		"Number of logical ops on i1 values calculated in GPR."	)

STATISTIC() [2/7]

STATISTIC	(	NumP9Setb	,
		"Number of compares lowered to setb."	)

STATISTIC() [3/7]

STATISTIC	(	NumSextSetcc	,
		"Number of (sext(setcc)) nodes expanded into GPR sequence."	)

STATISTIC() [4/7]

STATISTIC	(	NumZextSetcc	,
		"Number of (zext(setcc)) nodes expanded into GPR sequence."	)

STATISTIC() [5/7]

STATISTIC	(	OmittedForNonExtendUses	,
		"Number of compares not eliminated as they have non-extending uses."	)

STATISTIC() [6/7]

STATISTIC	(	SignExtensionsAdded	,
		"Number of sign extensions for compare inputs added."	)

STATISTIC() [7/7]

STATISTIC	(	ZeroExtensionsAdded	,
		"Number of zero extensions for compare inputs added."	)

Variable Documentation

ANDIGlueBug

cl::opt< bool > ANDIGlueBug("expose-ppc-andi-glue-bug", cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden)	(	"expose-ppc-andi-glue-bug"	,
		cl::desc("expose the ANDI glue bug on PPC")	,
		cl::Hidden	)

Referenced by llvm::PPCTargetLowering::PPCTargetLowering().

BPermRewriterNoMasking

cl::opt< bool > BPermRewriterNoMasking("ppc-bit-perm-rewriter-stress-rotates", cl::desc("stress rotate selection in aggressive ppc isel for " "bit permutations"), cl::Hidden) ( "ppc-bit-perm-rewriter-stress-rotates" , cl::desc("stress rotate selection in aggressive ppc isel for " "bit permutations") , cl::Hidden  )

static

CmpInGPR

cl::opt< ICmpInGPRType > CmpInGPR("ppc-gpr-icmps", cl::Hidden, cl::init(ICGPR_All), cl::desc("Specify the types of comparisons to emit GPR-only code for."), cl::values(clEnumValN(ICGPR_None, "none", "Do not modify integer comparisons."), clEnumValN(ICGPR_All, "all", "All possible int comparisons in GPRs."), clEnumValN(ICGPR_I32, "i32", "Only i32 comparisons in GPRs."), clEnumValN(ICGPR_I64, "i64", "Only i64 comparisons in GPRs."), clEnumValN(ICGPR_NonExtIn, "nonextin", "Only comparisons where inputs don't need [sz]ext."), clEnumValN(ICGPR_Zext, "zext", "Only comparisons with zext result."), clEnumValN(ICGPR_ZextI32, "zexti32", "Only i32 comparisons with zext result."), clEnumValN(ICGPR_ZextI64, "zexti64", "Only i64 comparisons with zext result."), clEnumValN(ICGPR_Sext, "sext", "Only comparisons with sext result."), clEnumValN(ICGPR_SextI32, "sexti32", "Only i32 comparisons with sext result."), clEnumValN(ICGPR_SextI64, "sexti64", "Only i64 comparisons with sext result."))) ( "ppc-gpr-icmps" , cl::Hidden , cl::init(ICGPR_All) , cl::desc("Specify the types of comparisons to emit GPR-only code for.") , cl::values(clEnumValN(ICGPR_None, "none", "Do not modify integer comparisons."), clEnumValN(ICGPR_All, "all", "All possible int comparisons in GPRs."), clEnumValN(ICGPR_I32, "i32", "Only i32 comparisons in GPRs."), clEnumValN(ICGPR_I64, "i64", "Only i64 comparisons in GPRs."), clEnumValN(ICGPR_NonExtIn, "nonextin", "Only comparisons where inputs don't need [sz]ext."), clEnumValN(ICGPR_Zext, "zext", "Only comparisons with zext result."), clEnumValN(ICGPR_ZextI32, "zexti32", "Only i32 comparisons with zext result."), clEnumValN(ICGPR_ZextI64, "zexti64", "Only i64 comparisons with zext result."), clEnumValN(ICGPR_Sext, "sext", "Only comparisons with sext result."), clEnumValN(ICGPR_SextI32, "sexti32", "Only i32 comparisons with sext result."), clEnumValN(ICGPR_SextI64, "sexti64", "Only i64 comparisons with sext result."))  )

static

EnableBranchHint

cl::opt< bool > EnableBranchHint("ppc-use-branch-hint", cl::init(true), cl::desc("Enable static hinting of branches on ppc"), cl::Hidden) ( "ppc-use-branch-hint" , cl::init(true) , cl::desc("Enable static hinting of branches on ppc") , cl::Hidden  )

static

Referenced by llvm::X86AsmPrinter::emitInstruction().

EnableTLSOpt

cl::opt< bool > EnableTLSOpt("ppc-tls-opt", cl::init(true), cl::desc("Enable tls optimization peephole"), cl::Hidden) ( "ppc-tls-opt" , cl::init(true) , cl::desc("Enable tls optimization peephole") , cl::Hidden  )

static

UseBitPermRewriter

cl::opt< bool > UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true), cl::desc("use aggressive ppc isel for bit permutations"), cl::Hidden) ( "ppc-use-bit-perm-rewriter" , cl::init(true) , cl::desc("use aggressive ppc isel for bit permutations") , cl::Hidden  )

static