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19 void SPIRVGeneralDuplicatesTracker::prebuildReg2Entry(
22 for (
auto &RegPair : TPair.second) {
28 Reg2Entry[&
MI->getOperand(0)] = &TPair.second;
34 std::vector<SPIRV::DTSortableEntry *> &Graph,
37 prebuildReg2Entry(TT, Reg2Entry);
38 prebuildReg2Entry(CT, Reg2Entry);
39 prebuildReg2Entry(GT, Reg2Entry);
40 prebuildReg2Entry(FT, Reg2Entry);
41 prebuildReg2Entry(AT, Reg2Entry);
42 prebuildReg2Entry(ST, Reg2Entry);
44 for (
auto &Op2E : Reg2Entry) {
52 assert(
MI &&
MI->getParent() &&
"No MachineInstr created yet");
53 for (
auto i =
MI->getNumDefs(); i < MI->getNumOperands();
i++) {
58 assert((
MI->getOpcode() == SPIRV::OpVariable &&
i == 3) ||
59 Reg2Entry.count(RegOp));
60 if (Reg2Entry.count(RegOp))
61 E->addDep(Reg2Entry[RegOp]);
66 if (Next && (Next->
getOpcode() == SPIRV::OpFunction ||
67 Next->
getOpcode() == SPIRV::OpFunctionParameter)) {
74 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
76 const Module *
M = MMI->getModule();
77 for (
auto F =
M->begin(),
E =
M->end();
F !=
E; ++
F) {
85 if (
MI.getNumExplicitDefs() > 0 &&
86 Reg2Entry.count(&
MI.getOperand(0))) {
89 Reg2Entry.lookup(&
MI.getOperand(0))->getDeps())
This is an optimization pass for GlobalISel generic memory operations.
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
void buildDepsGraph(std::vector< SPIRV::DTSortableEntry * > &Graph, MachineModuleInfo *MMI)
This class implements a map that also provides access to all stored values in a deterministic order.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
This class contains meta information specific to a module.
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
const StorageTy & getAllUses() const
Representation of each machine instruction.
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A Module instance is used to store all the information related to an LLVM module.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.