LLVM  6.0.0svn
PPCVSXCopy.cpp
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1 //===-------------- PPCVSXCopy.cpp - VSX Copy Legalization ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // A pass which deals with the complexity of generating legal VSX register
11 // copies to/from register classes which partially overlap with the VSX
12 // register file.
13 //
14 //===----------------------------------------------------------------------===//
15 
17 #include "PPC.h"
18 #include "PPCHazardRecognizers.h"
19 #include "PPCInstrBuilder.h"
20 #include "PPCInstrInfo.h"
21 #include "PPCMachineFunctionInfo.h"
22 #include "PPCTargetMachine.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/Statistic.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/Support/Debug.h"
35 
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "ppc-vsx-copy"
39 
40 namespace llvm {
42 }
43 
44 namespace {
45  // PPCVSXCopy pass - For copies between VSX registers and non-VSX registers
46  // (Altivec and scalar floating-point registers), we need to transform the
47  // copies into subregister copies with other restrictions.
48  struct PPCVSXCopy : public MachineFunctionPass {
49  static char ID;
50  PPCVSXCopy() : MachineFunctionPass(ID) {
52  }
53 
54  const TargetInstrInfo *TII;
55 
56  bool IsRegInClass(unsigned Reg, const TargetRegisterClass *RC,
59  return RC->hasSubClassEq(MRI.getRegClass(Reg));
60  } else if (RC->contains(Reg)) {
61  return true;
62  }
63 
64  return false;
65  }
66 
67  bool IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) {
68  return IsRegInClass(Reg, &PPC::VSRCRegClass, MRI);
69  }
70 
71  bool IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) {
72  return IsRegInClass(Reg, &PPC::VRRCRegClass, MRI);
73  }
74 
75  bool IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) {
76  return IsRegInClass(Reg, &PPC::F8RCRegClass, MRI);
77  }
78 
79  bool IsVSFReg(unsigned Reg, MachineRegisterInfo &MRI) {
80  return IsRegInClass(Reg, &PPC::VSFRCRegClass, MRI);
81  }
82 
83  bool IsVSSReg(unsigned Reg, MachineRegisterInfo &MRI) {
84  return IsRegInClass(Reg, &PPC::VSSRCRegClass, MRI);
85  }
86 
87 protected:
88  bool processBlock(MachineBasicBlock &MBB) {
89  bool Changed = false;
90 
92  for (MachineInstr &MI : MBB) {
93  if (!MI.isFullCopy())
94  continue;
95 
96  MachineOperand &DstMO = MI.getOperand(0);
97  MachineOperand &SrcMO = MI.getOperand(1);
98 
99  if ( IsVSReg(DstMO.getReg(), MRI) &&
100  !IsVSReg(SrcMO.getReg(), MRI)) {
101  // This is a copy *to* a VSX register from a non-VSX register.
102  Changed = true;
103 
104  const TargetRegisterClass *SrcRC = &PPC::VSLRCRegClass;
105  assert((IsF8Reg(SrcMO.getReg(), MRI) ||
106  IsVSSReg(SrcMO.getReg(), MRI) ||
107  IsVSFReg(SrcMO.getReg(), MRI)) &&
108  "Unknown source for a VSX copy");
109 
110  unsigned NewVReg = MRI.createVirtualRegister(SrcRC);
111  BuildMI(MBB, MI, MI.getDebugLoc(),
112  TII->get(TargetOpcode::SUBREG_TO_REG), NewVReg)
113  .addImm(1) // add 1, not 0, because there is no implicit clearing
114  // of the high bits.
115  .add(SrcMO)
116  .addImm(PPC::sub_64);
117 
118  // The source of the original copy is now the new virtual register.
119  SrcMO.setReg(NewVReg);
120  } else if (!IsVSReg(DstMO.getReg(), MRI) &&
121  IsVSReg(SrcMO.getReg(), MRI)) {
122  // This is a copy *from* a VSX register to a non-VSX register.
123  Changed = true;
124 
125  const TargetRegisterClass *DstRC = &PPC::VSLRCRegClass;
126  assert((IsF8Reg(DstMO.getReg(), MRI) ||
127  IsVSFReg(DstMO.getReg(), MRI) ||
128  IsVSSReg(DstMO.getReg(), MRI)) &&
129  "Unknown destination for a VSX copy");
130 
131  // Copy the VSX value into a new VSX register of the correct subclass.
132  unsigned NewVReg = MRI.createVirtualRegister(DstRC);
133  BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(TargetOpcode::COPY),
134  NewVReg)
135  .add(SrcMO);
136 
137  // Transform the original copy into a subregister extraction copy.
138  SrcMO.setReg(NewVReg);
139  SrcMO.setSubReg(PPC::sub_64);
140  }
141  }
142 
143  return Changed;
144  }
145 
146 public:
147  bool runOnMachineFunction(MachineFunction &MF) override {
148  // If we don't have VSX on the subtarget, don't do anything.
149  const PPCSubtarget &STI = MF.getSubtarget<PPCSubtarget>();
150  if (!STI.hasVSX())
151  return false;
152  TII = STI.getInstrInfo();
153 
154  bool Changed = false;
155 
156  for (MachineFunction::iterator I = MF.begin(); I != MF.end();) {
157  MachineBasicBlock &B = *I++;
158  if (processBlock(B))
159  Changed = true;
160  }
161 
162  return Changed;
163  }
164 
165  void getAnalysisUsage(AnalysisUsage &AU) const override {
167  }
168  };
169 }
170 
171 INITIALIZE_PASS(PPCVSXCopy, DEBUG_TYPE,
172  "PowerPC VSX Copy Legalization", false, false)
173 
174 char PPCVSXCopy::ID = 0;
176 llvm::createPPCVSXCopyPass() { return new PPCVSXCopy(); }
177 
void initializePPCVSXCopyPass(PassRegistry &)
const MachineInstrBuilder & add(const MachineOperand &MO) const
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
bool contains(unsigned Reg) const
Return true if the specified register is included in this register class.
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
unsigned getReg() const
getReg - Returns the register number.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
bool hasVSX() const
Definition: PPCSubtarget.h:242
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
Reg
All possible values of the reg field in the ModR/M byte.
TargetInstrInfo - Interface to description of machine instruction set.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Represent the analysis usage information of a pass.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
#define DEBUG_TYPE
Definition: PPCVSXCopy.cpp:38
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
FunctionPass * createPPCVSXCopyPass()
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:34
Iterator for intrusive lists based on ilist_node.
const PPCInstrInfo * getInstrInfo() const override
Definition: PPCSubtarget.h:179
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:59
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
void setReg(unsigned Reg)
Change the register this operand corresponds to.
#define I(x, y, z)
Definition: MD5.cpp:58
void setSubReg(unsigned subReg)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
IRTranslator LLVM IR MI
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:39