43class X86AlignBranchKind {
45 uint8_t AlignBranchKind = 0;
48 void operator=(
const std::string &Val) {
53 for (
auto BranchType : BranchTypes) {
54 if (BranchType ==
"fused")
56 else if (BranchType ==
"jcc")
58 else if (BranchType ==
"jmp")
60 else if (BranchType ==
"call")
62 else if (BranchType ==
"ret")
64 else if (BranchType ==
"indirect")
68 <<
" to -x86-align-branch=; each element must be one of: fused, "
69 "jcc, jmp, call, ret, indirect.(plus separated)\n";
74 operator uint8_t()
const {
return AlignBranchKind; }
78X86AlignBranchKind X86AlignBranchKindLoc;
81 "x86-align-branch-boundary",
cl::init(0),
83 "Control how the assembler should align branches with NOP. If the "
84 "boundary's size is not 0, it should be a power of 2 and no less "
85 "than 32. Branches will be aligned to prevent from being across or "
86 "against the boundary of specified size. The default value 0 does not "
92 "Specify types of branches to align (plus separated list of types):"
93 "\njcc indicates conditional jumps"
94 "\nfused indicates fused conditional jumps"
95 "\njmp indicates direct unconditional jumps"
96 "\ncall indicates direct and indirect calls"
97 "\nret indicates rets"
98 "\nindirect indicates indirect unconditional jumps"),
102 "x86-branches-within-32B-boundaries",
cl::init(
false),
104 "Align selected instructions to mitigate negative performance impact "
105 "of Intel's micro code update for errata skx102. May break "
106 "assumptions about labels corresponding to particular instructions, "
107 "and should be used with caution."));
110 "x86-pad-max-prefix-size",
cl::init(0),
111 cl::desc(
"Maximum number of prefixes to use for padding"));
115 cl::desc(
"Pad previous instructions to implement align directives"));
119 cl::desc(
"Pad previous instructions to implement branch alignment"));
123 std::unique_ptr<const MCInstrInfo> MCII;
124 X86AlignBranchKind AlignBranchType;
126 unsigned TargetPrefixMax = 0;
129 unsigned PrevInstOpcode = 0;
131 std::pair<MCFragment *, size_t> PrevInstPosition;
132 bool IsRightAfterData =
false;
134 uint8_t determinePaddingPrefix(
const MCInst &Inst)
const;
136 bool needAlign(
const MCInst &Inst)
const;
144 if (X86AlignBranchWithin32BBoundaries) {
155 if (X86AlignBranchBoundary.getNumOccurrences())
157 if (X86AlignBranch.getNumOccurrences())
158 AlignBranchType = X86AlignBranchKindLoc;
159 if (X86PadMaxPrefixSize.getNumOccurrences())
160 TargetPrefixMax = X86PadMaxPrefixSize;
198 unsigned &RemainingSize)
const;
201 unsigned &RemainingSize)
const;
204 unsigned &RemainingSize)
const;
216 return Opcode == X86::JCC_1 || Opcode == X86::JMP_1;
220 bool Is16BitMode =
false) {
225 return (Is16BitMode) ? X86::JCC_2 : X86::JCC_4;
227 return (Is16BitMode) ? X86::JMP_2 : X86::JMP_4;
232 unsigned Opcode =
MI.getOpcode();
239 unsigned Opcode =
MI.getOpcode();
246 MI.getOperand(
Desc.getNumOperands() - 1).getImm());
254 return classifySecondCondCodeInMacroFusion(
CC);
259 unsigned Opcode =
MI.getOpcode();
264 if (MemoryOperand < 0)
267 unsigned BaseReg =
MI.getOperand(BaseRegNum).getReg();
268 return (BaseReg == X86::RIP);
284 return FIK != X86::FirstMacroFusionInstKind::Invalid;
296uint8_t X86AsmBackend::determinePaddingPrefix(
const MCInst &Inst)
const {
298 "Prefixes can be added only in 32-bit or 64-bit mode.");
304 if (MemoryOperand != -1)
307 unsigned SegmentReg = 0;
308 if (MemoryOperand >= 0) {
341 if (MemoryOperand >= 0) {
344 if (BaseReg == X86::ESP || BaseReg == X86::EBP)
351bool X86AsmBackend::isMacroFused(
const MCInst &Cmp,
const MCInst &Jcc)
const {
366 for (
auto &Operand :
MI) {
367 if (!Operand.isExpr())
369 const MCExpr &Expr = *Operand.getExpr();
377bool X86AsmBackend::allowAutoPadding()
const {
381bool X86AsmBackend::allowEnhancedRelaxation()
const {
382 return allowAutoPadding() && TargetPrefixMax != 0 && X86PadForBranchAlign;
389 switch (InstOpcode) {
409 const std::pair<MCFragment *, size_t> &PrevInstPosition) {
422 if (
auto *
DF = dyn_cast_or_null<MCDataFragment>(
F))
423 return DF->getContents().size() &&
424 (
DF != PrevInstPosition.first ||
425 DF->getContents().size() != PrevInstPosition.second);
432 if (!
F || !
F->hasInstructions())
435 switch (
F->getKind()) {
439 return cast<MCDataFragment>(*F).getContents().size();
441 return cast<MCRelaxableFragment>(*F).getContents().size();
443 return cast<MCCompactEncodedInstFragment>(*F).getContents().size();
460 if (
isPrefix(PrevInstOpcode, *MCII))
470 if (IsRightAfterData)
479 if (!
OS.getAllowAutoPadding())
481 assert(allowAutoPadding() &&
"incorrect initialization!");
484 if (!
OS.getCurrentSectionOnly()->isText())
488 if (
OS.getAssembler().isBundlingEnabled())
499bool X86AsmBackend::needAlign(
const MCInst &Inst)
const {
501 return (
Desc.isConditionalBranch() &&
503 (
Desc.isUnconditionalBranch() &&
507 (
Desc.isIndirectBranch() &&
519 if (!canPadBranches(
OS))
531 if (!canPadInst(Inst,
OS))
534 if (PendingBA && PendingBA->
getNext() ==
OS.getCurrentFragment()) {
562 OS.insert(PendingBA);
570 if (
auto *
F = dyn_cast_or_null<MCRelaxableFragment>(CF))
571 F->setAllowAutoPadding(canPadInst(Inst,
OS));
577 if (!canPadBranches(
OS))
583 if (!needAlign(Inst) || !PendingBA)
594 if (isa_and_nonnull<MCDataFragment>(CF))
602std::optional<MCFixupKind> X86AsmBackend::getFixupKind(
StringRef Name)
const {
607#define ELF_RELOC(X, Y) .Case(#X, Y)
608#include "llvm/BinaryFormat/ELFRelocs/x86_64.def"
610 .
Case(
"BFD_RELOC_NONE", ELF::R_X86_64_NONE)
611 .
Case(
"BFD_RELOC_8", ELF::R_X86_64_8)
612 .
Case(
"BFD_RELOC_16", ELF::R_X86_64_16)
613 .
Case(
"BFD_RELOC_32", ELF::R_X86_64_32)
614 .
Case(
"BFD_RELOC_64", ELF::R_X86_64_64)
618#define ELF_RELOC(X, Y) .Case(#X, Y)
619#include "llvm/BinaryFormat/ELFRelocs/i386.def"
621 .
Case(
"BFD_RELOC_NONE", ELF::R_386_NONE)
622 .
Case(
"BFD_RELOC_8", ELF::R_386_8)
623 .
Case(
"BFD_RELOC_16", ELF::R_386_16)
624 .
Case(
"BFD_RELOC_32", ELF::R_386_32)
640 {
"reloc_signed_4byte", 0, 32, 0},
641 {
"reloc_signed_4byte_relax", 0, 32, 0},
642 {
"reloc_global_offset_table", 0, 32, 0},
643 {
"reloc_global_offset_table8", 0, 64, 0},
661bool X86AsmBackend::shouldForceRelocation(
const MCAssembler &,
711 assert(
Fixup.getOffset() +
Size <= Data.size() &&
"Invalid fixup offset!");
713 int64_t SignedValue =
static_cast<int64_t
>(
Value);
714 if ((
Target.isAbsolute() || IsResolved) &&
715 getFixupKindInfo(
Fixup.getKind()).Flags &
719 Asm.getContext().reportError(
720 Fixup.getLoc(),
"value of " +
Twine(SignedValue) +
721 " is too large for field of " +
Twine(
Size) +
722 ((
Size == 1) ?
" byte." :
" bytes."));
729 "Value does not fit in the Fixup field");
732 for (
unsigned i = 0; i !=
Size; ++i)
733 Data[
Fixup.getOffset() + i] = uint8_t(
Value >> (i * 8));
736bool X86AsmBackend::mayNeedRelaxation(
const MCInst &
MI,
738 unsigned Opcode =
MI.getOpcode();
739 unsigned SkipOperands = X86::isCCMPCC(Opcode) ? 2 : 0;
742 MI.getOperand(
MI.getNumOperands() - 1 - SkipOperands).isExpr());
745bool X86AsmBackend::fixupNeedsRelaxation(
const MCFixup &
Fixup,
750 return !isInt<8>(
Value);
755void X86AsmBackend::relaxInstruction(
MCInst &Inst,
758 bool Is16BitMode = STI.
hasFeature(X86::Is16Bit);
774 unsigned &RemainingSize)
const {
788 const unsigned MaxPossiblePad = std::min(15 - OldSize, RemainingSize);
789 const unsigned RemainingPrefixSize = [&]() ->
unsigned {
792 assert(
Code.size() < 15 &&
"The number of prefixes must be less than 15.");
799 unsigned ExistingPrefixSize =
Code.size();
800 if (TargetPrefixMax <= ExistingPrefixSize)
802 return TargetPrefixMax - ExistingPrefixSize;
804 const unsigned PrefixBytesToAdd =
805 std::min(MaxPossiblePad, RemainingPrefixSize);
806 if (PrefixBytesToAdd == 0)
812 Code.append(PrefixBytesToAdd, Prefix);
818 F.setOffset(
F.getOffset() + PrefixBytesToAdd);
821 RemainingSize -= PrefixBytesToAdd;
827 unsigned &RemainingSize)
const {
840 const unsigned NewSize =
Code.size();
841 assert(NewSize >= OldSize &&
"size decrease during relaxation?");
842 unsigned Delta = NewSize - OldSize;
843 if (Delta > RemainingSize)
848 RemainingSize -= Delta;
854 unsigned &RemainingSize)
const {
855 bool Changed =
false;
856 if (RemainingSize != 0)
857 Changed |= padInstructionViaRelaxation(RF,
Emitter, RemainingSize);
858 if (RemainingSize != 0)
859 Changed |= padInstructionViaPrefix(RF,
Emitter, RemainingSize);
863void X86AsmBackend::finishLayout(
MCAssembler const &Asm,
871 if (!X86PadForAlign && !X86PadForBranchAlign)
879 LabeledFragments.
insert(S.getFragment(
false));
889 if (LabeledFragments.
count(&
F))
898 auto &RF = cast<MCRelaxableFragment>(*
I);
904 switch (
F.getKind()) {
908 return X86PadForAlign;
910 return X86PadForBranchAlign;
928 unsigned RemainingSize = OrigSize;
929 while (!Relaxable.
empty() && RemainingSize != 0) {
934 if (padInstructionEncoding(RF,
Asm.getEmitter(), RemainingSize))
950 cast<MCBoundaryAlignFragment>(
F).setSize(RemainingSize);
955 assert(OrigOffset + OrigSize == FinalOffset + FinalSize &&
956 "can't move start of next fragment!");
957 assert(FinalSize == RemainingSize &&
"inconsistent size computation?");
963 if (
auto *BF = dyn_cast<MCBoundaryAlignFragment>(&
F)) {
964 const MCFragment *LastFragment = BF->getLastFragment();
967 while (&*
I != LastFragment)
974 for (
unsigned int i = 0, n = Layout.
getSectionOrder().size(); i != n; ++i) {
976 Asm.getFragmentOffset(*
Section.curFragList()->Tail);
977 Asm.computeFragmentSize(*
Section.curFragList()->Tail);
981unsigned X86AsmBackend::getMaximumNopSize(
const MCSubtargetInfo &STI)
const {
1003 static const char Nops32Bit[10][11] = {
1013 "\x0f\x1f\x44\x00\x00",
1015 "\x66\x0f\x1f\x44\x00\x00",
1017 "\x0f\x1f\x80\x00\x00\x00\x00",
1019 "\x0f\x1f\x84\x00\x00\x00\x00\x00",
1021 "\x66\x0f\x1f\x84\x00\x00\x00\x00\x00",
1023 "\x66\x2e\x0f\x1f\x84\x00\x00\x00\x00\x00",
1027 static const char Nops16Bit[4][11] = {
1038 const char(*Nops)[11] =
1039 STI->
hasFeature(X86::Is16Bit) ? Nops16Bit : Nops32Bit;
1046 const uint8_t ThisNopLength = (uint8_t) std::min(Count, MaxNopLength);
1047 const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10;
1048 for (uint8_t i = 0; i < Prefixes; i++)
1050 const uint8_t Rest = ThisNopLength - Prefixes;
1052 OS.
write(Nops[Rest - 1], Rest);
1053 Count -= ThisNopLength;
1054 }
while (Count != 0);
1063class ELFX86AsmBackend :
public X86AsmBackend {
1067 : X86AsmBackend(
T, STI), OSABI(OSABI) {}
1070class ELFX86_32AsmBackend :
public ELFX86AsmBackend {
1072 ELFX86_32AsmBackend(
const Target &
T, uint8_t OSABI,
1074 : ELFX86AsmBackend(
T, OSABI, STI) {}
1076 std::unique_ptr<MCObjectTargetWriter>
1077 createObjectTargetWriter()
const override {
1082class ELFX86_X32AsmBackend :
public ELFX86AsmBackend {
1084 ELFX86_X32AsmBackend(
const Target &
T, uint8_t OSABI,
1086 : ELFX86AsmBackend(
T, OSABI, STI) {}
1088 std::unique_ptr<MCObjectTargetWriter>
1089 createObjectTargetWriter()
const override {
1095class ELFX86_IAMCUAsmBackend :
public ELFX86AsmBackend {
1097 ELFX86_IAMCUAsmBackend(
const Target &
T, uint8_t OSABI,
1099 : ELFX86AsmBackend(
T, OSABI, STI) {}
1101 std::unique_ptr<MCObjectTargetWriter>
1102 createObjectTargetWriter()
const override {
1108class ELFX86_64AsmBackend :
public ELFX86AsmBackend {
1110 ELFX86_64AsmBackend(
const Target &
T, uint8_t OSABI,
1112 : ELFX86AsmBackend(
T, OSABI, STI) {}
1114 std::unique_ptr<MCObjectTargetWriter>
1115 createObjectTargetWriter()
const override {
1120class WindowsX86AsmBackend :
public X86AsmBackend {
1126 : X86AsmBackend(
T, STI)
1130 std::optional<MCFixupKind> getFixupKind(
StringRef Name)
const override {
1138 std::unique_ptr<MCObjectTargetWriter>
1139 createObjectTargetWriter()
const override {
1150 UNWIND_MODE_BP_FRAME = 0x01000000,
1153 UNWIND_MODE_STACK_IMMD = 0x02000000,
1156 UNWIND_MODE_STACK_IND = 0x03000000,
1159 UNWIND_MODE_DWARF = 0x04000000,
1162 UNWIND_BP_FRAME_REGISTERS = 0x00007FFF,
1165 UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF
1170class DarwinX86AsmBackend :
public X86AsmBackend {
1174 enum { CU_NUM_SAVED_REGS = 6 };
1176 mutable unsigned SavedRegs[CU_NUM_SAVED_REGS];
1180 unsigned OffsetSize;
1181 unsigned MoveInstrSize;
1182 unsigned StackDivide;
1185 unsigned PushInstrSize(
unsigned Reg)
const {
1208 int getCompactUnwindRegNum(
unsigned Reg)
const {
1209 static const MCPhysReg CU32BitRegs[7] = {
1210 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
1212 static const MCPhysReg CU64BitRegs[] = {
1213 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
1215 const MCPhysReg *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs;
1216 for (
int Idx = 1; *CURegs; ++CURegs, ++
Idx)
1225 uint32_t encodeCompactUnwindRegistersWithFrame()
const {
1230 for (
int i = 0,
Idx = 0; i != CU_NUM_SAVED_REGS; ++i) {
1231 unsigned Reg = SavedRegs[i];
1232 if (Reg == 0)
break;
1234 int CURegNum = getCompactUnwindRegNum(Reg);
1235 if (CURegNum == -1)
return ~0
U;
1239 RegEnc |= (CURegNum & 0x7) << (
Idx++ * 3);
1242 assert((RegEnc & 0x3FFFF) == RegEnc &&
1243 "Invalid compact register encoding!");
1250 uint32_t encodeCompactUnwindRegistersWithoutFrame(
unsigned RegCount)
const {
1264 for (
unsigned i = 0; i < RegCount; ++i) {
1265 int CUReg = getCompactUnwindRegNum(SavedRegs[i]);
1266 if (CUReg == -1)
return ~0
U;
1267 SavedRegs[i] = CUReg;
1271 std::reverse(&SavedRegs[0], &SavedRegs[CU_NUM_SAVED_REGS]);
1273 uint32_t RenumRegs[CU_NUM_SAVED_REGS];
1274 for (
unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i){
1275 unsigned Countless = 0;
1276 for (
unsigned j = CU_NUM_SAVED_REGS - RegCount;
j < i; ++
j)
1277 if (SavedRegs[j] < SavedRegs[i])
1280 RenumRegs[i] = SavedRegs[i] - Countless - 1;
1287 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
1288 + 6 * RenumRegs[2] + 2 * RenumRegs[3]
1292 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
1293 + 6 * RenumRegs[3] + 2 * RenumRegs[4]
1297 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
1298 + 3 * RenumRegs[4] + RenumRegs[5];
1301 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
1305 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
1308 permutationEncoding |= RenumRegs[5];
1312 assert((permutationEncoding & 0x3FF) == permutationEncoding &&
1313 "Invalid compact register encoding!");
1314 return permutationEncoding;
1320 : X86AsmBackend(
T, STI),
MRI(
MRI),
TT(STI.getTargetTriple()),
1321 Is64Bit(
TT.isArch64Bit()) {
1322 memset(SavedRegs, 0,
sizeof(SavedRegs));
1323 OffsetSize = Is64Bit ? 8 : 4;
1324 MoveInstrSize = Is64Bit ? 3 : 2;
1325 StackDivide = Is64Bit ? 8 : 4;
1328 std::unique_ptr<MCObjectTargetWriter>
1329 createObjectTargetWriter()
const override {
1340 if (Instrs.
empty())
return 0;
1341 if (!isDarwinCanonicalPersonality(FI->
Personality) &&
1343 return CU::UNWIND_MODE_DWARF;
1346 unsigned SavedRegIdx = 0;
1347 memset(SavedRegs, 0,
sizeof(SavedRegs));
1352 uint32_t CompactUnwindEncoding = 0;
1354 unsigned SubtractInstrIdx = Is64Bit ? 3 : 2;
1355 unsigned InstrOffset = 0;
1356 unsigned StackAdjust = 0;
1357 unsigned StackSize = 0;
1358 int MinAbsOffset = std::numeric_limits<int>::max();
1361 switch (Inst.getOperation()) {
1365 return CU::UNWIND_MODE_DWARF;
1377 if (*
MRI.getLLVMRegNum(Inst.getRegister(),
true) !=
1378 (Is64Bit ? X86::RBP : X86::EBP))
1379 return CU::UNWIND_MODE_DWARF;
1382 memset(SavedRegs, 0,
sizeof(SavedRegs));
1385 MinAbsOffset = std::numeric_limits<int>::max();
1386 InstrOffset += MoveInstrSize;
1404 StackSize = Inst.getOffset() / StackDivide;
1420 if (SavedRegIdx == CU_NUM_SAVED_REGS)
1423 return CU::UNWIND_MODE_DWARF;
1425 unsigned Reg = *
MRI.getLLVMRegNum(Inst.getRegister(),
true);
1426 SavedRegs[SavedRegIdx++] =
Reg;
1427 StackAdjust += OffsetSize;
1428 MinAbsOffset = std::min(MinAbsOffset,
abs(Inst.getOffset()));
1429 InstrOffset += PushInstrSize(Reg);
1435 StackAdjust /= StackDivide;
1438 if ((StackAdjust & 0xFF) != StackAdjust)
1440 return CU::UNWIND_MODE_DWARF;
1444 if (SavedRegIdx != 0 && MinAbsOffset != 3 * (
int)OffsetSize)
1445 return CU::UNWIND_MODE_DWARF;
1448 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame();
1449 if (RegEnc == ~0U)
return CU::UNWIND_MODE_DWARF;
1451 CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME;
1452 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
1453 CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;
1455 SubtractInstrIdx += InstrOffset;
1458 if ((StackSize & 0xFF) == StackSize) {
1460 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD;
1463 CompactUnwindEncoding |= (StackSize & 0xFF) << 16;
1465 if ((StackAdjust & 0x7) != StackAdjust)
1467 return CU::UNWIND_MODE_DWARF;
1470 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND;
1474 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
1477 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
1481 std::reverse(&SavedRegs[0], &SavedRegs[SavedRegIdx]);
1482 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
1486 uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegIdx);
1487 if (RegEnc == ~0U)
return CU::UNWIND_MODE_DWARF;
1490 CompactUnwindEncoding |=
1491 RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION;
1494 return CompactUnwindEncoding;
1506 return new DarwinX86AsmBackend(
T,
MRI, STI);
1509 return new WindowsX86AsmBackend(
T,
false, STI);
1514 return new ELFX86_IAMCUAsmBackend(
T, OSABI, STI);
1516 return new ELFX86_32AsmBackend(
T, OSABI, STI);
1525 return new DarwinX86AsmBackend(
T,
MRI, STI);
1528 return new WindowsX86AsmBackend(
T,
true, STI);
1530 if (TheTriple.
isUEFI()) {
1532 "Only COFF format is supported in UEFI environment.");
1533 return new WindowsX86AsmBackend(
T,
true, STI);
1538 if (TheTriple.
isX32())
1539 return new ELFX86_X32AsmBackend(
T, OSABI, STI);
1540 return new ELFX86_64AsmBackend(
T, OSABI, STI);
1546 X86ELFStreamer(
MCContext &Context, std::unique_ptr<MCAsmBackend> TAB,
1547 std::unique_ptr<MCObjectWriter> OW,
1548 std::unique_ptr<MCCodeEmitter>
Emitter)
1559 Backend.emitInstructionBegin(S, Inst, STI);
1560 S.MCObjectStreamer::emitInstruction(Inst, STI);
1561 Backend.emitInstructionEnd(S, Inst);
1564void X86ELFStreamer::emitInstruction(
const MCInst &Inst,
1570 std::unique_ptr<MCAsmBackend> &&MAB,
1571 std::unique_ptr<MCObjectWriter> &&MOW,
1572 std::unique_ptr<MCCodeEmitter> &&MCE) {
1573 return new X86ELFStreamer(Context, std::move(MAB), std::move(MOW),
unsigned const MachineRegisterInfo * MRI
dxil DXContainer Global Emitter
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static MCInstrInfo * createMCInstrInfo()
static unsigned getRelaxedOpcodeBranch(unsigned Opcode, bool Is16BitMode=false)
static X86::SecondMacroFusionInstKind classifySecondInstInMacroFusion(const MCInst &MI, const MCInstrInfo &MCII)
static size_t getSizeForInstFragment(const MCFragment *F)
static bool isRIPRelative(const MCInst &MI, const MCInstrInfo &MCII)
Check if the instruction uses RIP relative addressing.
static bool isRightAfterData(MCFragment *CurrentFragment, const std::pair< MCFragment *, size_t > &PrevInstPosition)
Check if the instruction to be emitted is right after any data.
static bool mayHaveInterruptDelaySlot(unsigned InstOpcode)
X86 has certain instructions which enable interrupts exactly one instruction after the instruction wh...
static bool isFirstMacroFusibleInst(const MCInst &Inst, const MCInstrInfo &MCII)
Check if the instruction is valid as the first instruction in macro fusion.
static X86::CondCode getCondFromBranch(const MCInst &MI, const MCInstrInfo &MCII)
static unsigned getRelaxedOpcode(const MCInst &MI, bool Is16BitMode)
static unsigned getFixupKindSize(unsigned Kind)
static bool isRelaxableBranch(unsigned Opcode)
static bool isPrefix(unsigned Opcode, const MCInstrInfo &MCII)
Check if the instruction is a prefix.
static bool hasVariantSymbol(const MCInst &MI)
Check if the instruction has a variant symbol operand.
static bool is64Bit(const char *name)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool empty() const
empty - Check if the array is empty.
Implements a dense probed hash-table based set.
Generic interface to target specific assembler backends.
virtual bool allowEnhancedRelaxation() const
Return true if this target allows an unrelaxable instruction to be emitted into RelaxableFragment and...
virtual unsigned getMaximumNopSize(const MCSubtargetInfo &STI) const
Returns the maximum size of a nop in bytes on this target.
virtual bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const =0
Write an (optimal) nop sequence of Count bytes to the given output.
virtual void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const
Relax the instruction in the given fragment to the next wider instruction.
virtual bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const
Check whether the given instruction may need relaxation.
virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const =0
Simple predicate for targets where !Resolved implies requiring relaxation.
virtual void finishLayout(MCAssembler const &Asm, MCAsmLayout &Layout) const
Give backend an opportunity to finish layout after relaxation.
virtual bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, const MCSubtargetInfo *STI)
Hook to check if a relocation is needed for some target specific reason.
virtual unsigned getNumFixupKinds() const =0
Get the number of target specific fixup kinds.
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
virtual std::optional< MCFixupKind > getFixupKind(StringRef Name) const
Map a relocation name used in .reloc to a fixup kind.
virtual void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const =0
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
virtual bool allowAutoPadding() const
Return true if this target might automatically pad instructions and thus need to emit padding enable/...
Encapsulates the layout of an assembly file at a particular point in time.
llvm::SmallVectorImpl< MCSection * > & getSectionOrder()
MCAsmBackend & getBackend() const
Represents required padding such that a particular other set of fragments does not cross a particular...
void setLastFragment(const MCFragment *F)
MCCodeEmitter - Generic instruction encoding interface.
Context object for machine code objects.
bool emitCompactUnwindNonCanonical() const
Fragment for data and encoded instructions.
SmallVectorImpl< char > & getContents()
SmallVectorImpl< MCFixup > & getFixups()
const MCSubtargetInfo * getSubtargetInfo() const
Retrieve the MCSubTargetInfo in effect when the instruction was encoded.
Base class for the full range of assembler expressions which are needed for parsing.
@ SymbolRef
References to labels and assigned expressions.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
MCFragment * getNext() const
Instances of this class represent a single low-level machine instruction.
void dump_pretty(raw_ostream &OS, const MCInstPrinter *Printer=nullptr, StringRef Separator=" ", const MCRegisterInfo *RegInfo=nullptr) const
Dump the MCInst as prettily as possible using the additional MC structures, if given.
unsigned getOpcode() const
void setOpcode(unsigned Op)
const MCOperand & getOperand(unsigned i) const
Describe properties that are true of each instruction in the target description file.
bool isConditionalBranch() const
Return true if this is a branch which may fall through to the next instruction or may transfer contro...
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Streaming object file generation interface.
MCAssembler & getAssembler()
void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override
Emit the given Instruction into the current section.
unsigned getReg() const
Returns the register number.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
bool getAllowAutoPadding() const
const MCInst & getInst() const
void setInst(const MCInst &Value)
Instances of this class represent a uniqued identifier for a section in the current translation unit.
void ensureMinAlignment(Align MinAlignment)
Makes sure that Alignment is at least MinAlignment.
void setHasLayout(bool Value)
Streaming machine code generation interface.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
This represents an "assembler immediate".
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
bool isX32() const
Tests whether the target is X32.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
OSType getOS() const
Get the parsed operating system type of this triple.
ArchType getArch() const
Get the parsed architecture type of this triple.
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
bool isUEFI() const
Tests whether the OS is UEFI.
bool isOSWindows() const
Tests whether the OS is Windows.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
std::pair< iterator, bool > insert(const ValueT &V)
size_type count(const_arg_type_t< ValueT > V) const
Return 1 if the specified key is in the set, 0 otherwise.
This class implements an extremely fast bulk output stream that can only output to a stream.
raw_ostream & write(unsigned char C)
A raw_ostream that writes to an SmallVector or SmallString.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
CompactUnwindEncodings
Compact unwind encoding values.
Expected< uint32_t > getCPUSubType(const Triple &T)
Expected< uint32_t > getCPUType(const Triple &T)
Reg
All possible values of the reg field in the ModR/M byte.
bool isPrefix(uint64_t TSFlags)
int getMemoryOperandNo(uint64_t TSFlags)
unsigned getOperandBias(const MCInstrDesc &Desc)
Compute whether all of the def operands are repeated in the uses and therefore should be skipped.
@ RawFrmDstSrc
RawFrmDstSrc - This form is for instructions that use the source index register SI/ESI/RSI with a pos...
@ RawFrmSrc
RawFrmSrc - This form is for instructions that use the source index register SI/ESI/RSI with a possib...
@ RawFrmMemOffs
RawFrmMemOffs - This form is for instructions that store an absolute memory offset as an immediate wi...
void emitPrefix(MCCodeEmitter &MCE, const MCInst &MI, SmallVectorImpl< char > &CB, const MCSubtargetInfo &STI)
void emitInstruction(MCObjectStreamer &, const MCInst &Inst, const MCSubtargetInfo &STI)
FirstMacroFusionInstKind classifyFirstOpcodeInMacroFusion(unsigned Opcode)
AlignBranchBoundaryKind
Defines the possible values of the branch boundary alignment mask.
SecondMacroFusionInstKind
unsigned getOpcodeForLongImmediateForm(unsigned Opcode)
EncodingOfSegmentOverridePrefix getSegmentOverridePrefixForReg(unsigned Reg)
Given a segment register, return the encoding of the segment override prefix for it.
bool isMacroFused(FirstMacroFusionInstKind FirstKind, SecondMacroFusionInstKind SecondKind)
@ reloc_global_offset_table8
@ reloc_signed_4byte_relax
@ reloc_branch_4byte_pcrel
@ reloc_riprel_4byte_relax
@ reloc_riprel_4byte_relax_rex
@ reloc_global_offset_table
@ reloc_riprel_4byte_movq_load
initializer< Ty > init(const Ty &Val)
LocationClass< Ty > location(Ty &L)
NodeAddr< CodeNode * > Code
This is an optimization pass for GlobalISel generic memory operations.
APFloat abs(APFloat X)
Returns the absolute value of the argument.
MCAsmBackend * createX86_64AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter > createX86WinCOFFObjectWriter(bool Is64Bit)
Construct an X86 Win COFF object writer.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
MCStreamer * createX86ELFStreamer(const Triple &T, MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&MOW, std::unique_ptr< MCCodeEmitter > &&MCE)
MCFixupKind
Extensible enumeration to represent the type of a fixup.
@ FK_PCRel_4
A four-byte pc relative fixup.
@ FK_PCRel_2
A two-byte pc relative fixup.
@ FK_SecRel_2
A two-byte section relative fixup.
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
@ FK_Data_8
A eight-byte fixup.
@ FK_Data_1
A one-byte fixup.
@ FK_Data_4
A four-byte fixup.
@ FK_SecRel_8
A eight-byte section relative fixup.
@ FK_PCRel_8
A eight-byte pc relative fixup.
@ FK_SecRel_4
A four-byte section relative fixup.
@ FK_PCRel_1
A one-byte pc relative fixup.
@ FK_SecRel_1
A one-byte section relative fixup.
@ FK_Data_2
A two-byte fixup.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
void cantFail(Error Err, const char *Msg=nullptr)
Report a fatal error if Err is a failure value.
std::unique_ptr< MCObjectTargetWriter > createX86MachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)
Construct an X86 Mach-O object writer.
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
std::unique_ptr< MCObjectTargetWriter > createX86ELFObjectWriter(bool IsELF64, uint8_t OSABI, uint16_t EMachine)
Construct an X86 ELF object writer.
Align assumeAligned(uint64_t Value)
Treats the value 0 as a 1, so Align is always at least 1.
MCAsmBackend * createX86_32AsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Implement std::hash so that hash_code can be used in STL containers.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Description of the encoding of one expression Op.
const MCSymbol * Personality
std::vector< MCCFIInstruction > Instructions
Target independent information on a fixup kind.
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...