94#define DEBUG_TYPE "x86-disassembler"
96#define debug(s) LLVM_DEBUG(dbgs() << __LINE__ << ": " << s);
121#include "X86GenDisassemblerTables.inc"
124 uint8_t opcode, uint8_t modRM) {
129 dec = &
ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
132 dec = &
TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
135 dec = &
THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
138 dec = &
THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
141 dec = &
XOP8_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
144 dec = &
XOP9_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
147 dec = &
XOPA_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
154 dec = &
MAP4_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
157 dec = &
MAP5_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
160 dec = &
MAP6_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
163 dec = &
MAP7_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
179 return modRMTable[dec->
instructionIDs + ((modRM & 0x38) >> 3) + 8];
181 case MODRM_SPLITMISC:
194 byte = insn->
bytes[offset];
199 auto r = insn->
bytes;
201 if (offset +
sizeof(
T) > r.size())
209 return insn->
mode ==
MODE_64BIT && prefix >= 0x40 && prefix <= 0x4f;
239 if ((
byte == 0xf2 ||
byte == 0xf3) && !
peek(insn,
nextByte)) {
248 if (!(
byte == 0xf3 &&
nextByte == 0x90))
266 if (
peek(insn, nnextByte))
339 uint8_t byte1, byte2;
345 if (
peek(insn, byte2)) {
386 "Found EVEX prefix 0x%hhx 0x%hhx 0x%hhx 0x%hhx",
390 }
else if (
byte == 0xc4) {
392 if (
peek(insn, byte1)) {
421 }
else if (
byte == 0xc5) {
423 if (
peek(insn, byte1)) {
453 }
else if (
byte == 0x8f) {
455 if (
peek(insn, byte1)) {
460 if ((byte1 & 0x38) != 0x0)
492 }
else if (
isREX2(insn,
byte)) {
494 if (
peek(insn, byte1)) {
509 }
else if (
isREX(insn,
byte)) {
556 sibBaseBase = SIB_BASE_EAX;
560 sibBaseBase = SIB_BASE_RAX;
641 uint8_t
mod, rm, reg;
685 EABase eaBaseBase = EA_BASE_BX_SI;
754 insn->
eaBase = EA_BASE_sib;
777#define GENERIC_FIXUP_FUNC(name, base, prefix) \
778 static uint16_t name(struct InternalInstruction *insn, OperandType type, \
779 uint8_t index, uint8_t *valid) { \
783 debug("Unhandled register type"); \
787 return base + index; \
789 if (insn->rexPrefix && index >= 4 && index <= 7) \
790 return prefix##_SPL + (index - 4); \
792 return prefix##_AL + index; \
794 return prefix##_AX + index; \
796 return prefix##_EAX + index; \
798 return prefix##_RAX + index; \
800 return prefix##_ZMM0 + index; \
802 return prefix##_YMM0 + index; \
804 return prefix##_XMM0 + index; \
808 return prefix##_TMM0 + index; \
813 return prefix##_K0 + index; \
817 return prefix##_K0_K1 + (index / 2); \
819 return prefix##_MM0 + (index & 0x7); \
820 case TYPE_SEGMENTREG: \
821 if ((index & 7) > 5) \
823 return prefix##_ES + (index & 7); \
824 case TYPE_DEBUGREG: \
827 return prefix##_DR0 + index; \
828 case TYPE_CONTROLREG: \
831 return prefix##_CR0 + index; \
833 return prefix##_XMM0 + index; \
835 return prefix##_YMM0 + index; \
837 return prefix##_ZMM0 + index; \
868 debug(
"Expected a REG or R/M encoding in fixupReg");
878 insn->reg - insn->regBase, &valid);
907 if (insn->eaBase >= insn->eaRegBase) {
908 insn->eaBase = (
EABase)fixupRMValue(
909 insn, (
OperandType)
op->type, insn->eaBase - insn->eaRegBase, &valid);
930 dbgs() <<
format(
"Unhandled mmm field for instruction (0x%hhx)",
959 dbgs() <<
format(
"Unhandled m-mmmm field for instruction (0x%hhx)",
988 dbgs() <<
format(
"Unhandled m-mmmm field for instruction (0x%hhx)",
1010 if (current == 0x0f) {
1012 dbgs() <<
format(
"Found a two-byte escape prefix (0x%hhx)", current));
1016 if (current == 0x38) {
1023 }
else if (current == 0x3a) {
1030 }
else if (current == 0x0f) {
1032 dbgs() <<
format(
"Found a 3dnow escape prefix (0x%hhx)", current));
1060 for (
int i = 0;; i++) {
1061 if (orig[i] ==
'\0' && equiv[i] ==
'\0')
1063 if (orig[i] ==
'\0' || equiv[i] ==
'\0')
1065 if (orig[i] != equiv[i]) {
1066 if ((orig[i] ==
'Q' || orig[i] ==
'L') && equiv[i] ==
'W')
1068 if ((orig[i] ==
'6' || orig[i] ==
'3') && equiv[i] ==
'1')
1070 if ((orig[i] ==
'4' || orig[i] ==
'2') && equiv[i] ==
'6')
1079 for (
int i = 0;; ++i) {
1080 if (
name[i] ==
'\0')
1082 if (
name[i] ==
'6' &&
name[i + 1] ==
'4')
1152 switch (insn->
opcode & 0xfe) {
1325 attrMask &= ~ATTR_ADSIZE;
1330 (insn->
opcode == 0xA1 || (insn->
opcode & 0xf0) == 0x50))
1375 auto SpecName = mii->
getName(instructionIDWithREXW);
1377 if (!
is64Bit(SpecName.data())) {
1439 specName = mii->
getName(instructionID);
1440 specWithOpSizeName = mii->
getName(instructionIDWithOpsize);
1458 uint16_t instructionIDWithNewOpcode;
1481 insn->
spec = specWithNewOpcode;
1506 auto setOpcodeRegister = [&](
unsigned base) {
1515 setOpcodeRegister(MODRM_REG_AL);
1524 setOpcodeRegister(MODRM_REG_AX);
1527 setOpcodeRegister(MODRM_REG_EAX);
1530 setOpcodeRegister(MODRM_REG_RAX);
1607 insn->
vvvv =
static_cast<Reg>(vvvv);
1629 int hasVVVV, needVVVV;
1636 needVVVV = hasVVVV && (insn->
vvvv != 0);
1639 switch (
Op.encoding) {
1647 needVVVV = hasVVVV & ((insn->
vvvv & 0xf) != 0);
1652 if (insn->
eaBase != EA_BASE_sib && insn->
eaBase != EA_BASE_sib64)
1667 debug(
"Unhandled VSIB index type");
1689 if (insn->
eaBase != EA_BASE_sib && insn->
eaBase != EA_BASE_sib64)
1717 if (
Op.type == TYPE_XMM ||
Op.type == TYPE_YMM)
1785 case ENCODING_WRITEMASK:
1792 LLVM_DEBUG(
dbgs() <<
"Encountered an operand with an unknown encoding.");
1832 std::unique_ptr<const MCInstrInfo> MII;
1835 std::unique_ptr<const MCInstrInfo> MII);
1847X86GenericDisassembler::X86GenericDisassembler(
1850 std::unique_ptr<const MCInstrInfo> MII)
1853 if (FB[X86::Is16Bit]) {
1856 }
else if (FB[X86::Is32Bit]) {
1859 }
else if (FB[X86::Is64Bit]) {
1870 CommentStream = &CStream;
1886 Insn.operands = x86OperandSets[
Insn.spec->operands];
1897 if (!
Insn.mandatoryPrefix) {
1900 if (
Insn.repeatPrefix == 0xf2)
1902 else if (
Insn.repeatPrefix == 0xf3 &&
1904 Insn.opcode != 0x90)
1906 if (
Insn.hasLockPrefix)
1909 Instr.setFlags(Flags);
1924#define ENTRY(x) X86::x,
1928 MCPhysReg llvmRegnum = llvmRegnums[reg];
1950 baseRegNo = insn.
hasAdSize ? X86::ESI : X86::RSI;
1952 baseRegNo = insn.
hasAdSize ? X86::SI : X86::ESI;
1955 baseRegNo = insn.
hasAdSize ? X86::ESI : X86::SI;
1975 baseRegNo = insn.
hasAdSize ? X86::EDI : X86::RDI;
1977 baseRegNo = insn.
hasAdSize ? X86::DI : X86::EDI;
1980 baseRegNo = insn.
hasAdSize ? X86::EDI : X86::DI;
2003 if (type == TYPE_REL) {
2014 if(immediate & 0x80)
2015 immediate |= ~(0xffull);
2018 if(immediate & 0x8000)
2019 immediate |= ~(0xffffull);
2022 if(immediate & 0x80000000)
2023 immediate |= ~(0xffffffffull);
2030 if(immediate & 0x80)
2031 immediate |= ~(0xffull);
2034 if(immediate & 0x8000)
2035 immediate |= ~(0xffffull);
2038 if(immediate & 0x80000000)
2039 immediate |= ~(0xffffffffull);
2044 else if (type == TYPE_IMM) {
2049 if(immediate & 0x80)
2050 immediate |= ~(0xffull);
2053 if(immediate & 0x8000)
2054 immediate |= ~(0xffffull);
2057 if(immediate & 0x80000000)
2058 immediate |= ~(0xffffffffull);
2085 if (type == TYPE_MOFFS) {
2100 if (insn.
eaBase == EA_BASE_sib || insn.
eaBase == EA_BASE_sib64) {
2101 debug(
"A R/M register operand may not have a SIB byte");
2107 debug(
"Unexpected EA base register");
2110 debug(
"EA_BASE_NONE for ModR/M base");
2112#define ENTRY(x) case EA_BASE_##x:
2115 debug(
"A R/M register operand may not have a base; "
2116 "the operand must be a register.");
2120 mcInst.addOperand(MCOperand::createReg(X86::x)); break;
2139 bool ForceSIB =
false) {
2159 if (insn.
eaBase == EA_BASE_sib || insn.
eaBase == EA_BASE_sib64) {
2163 debug(
"Unexpected sibBase");
2166 case SIB_BASE_##x: \
2167 baseReg = MCOperand::createReg(X86::x); break;
2178 debug(
"Unexpected sibIndex");
2181 case SIB_INDEX_##x: \
2182 indexReg = MCOperand::createReg(X86::x); break;
2203 insn.
sibBase != SIB_BASE_R12D && insn.
sibBase != SIB_BASE_R12))) {
2215 debug(
"EA_BASE_NONE and EA_DISP_NONE for ModR/M base");
2252 debug(
"Unexpected eaBase");
2260 baseReg = MCOperand::createReg(X86::x); break;
2263#define ENTRY(x) case EA_REG_##x:
2266 debug(
"A R/M memory operand may not be a register; "
2267 "the base field must be a base.");
2283 const uint8_t dispSize =
2304 switch (operand.
type) {
2306 debug(
"Unexpected type for a R/M operand");
2321 case TYPE_CONTROLREG:
2351 uint8_t maskRegNum) {
2352 if (maskRegNum >= 8) {
2353 debug(
"Invalid mask register number");
2373 debug(
"Unhandled operand encoding during translation");
2378 case ENCODING_WRITEMASK:
2441 debug(
"Instruction has no specification");
2451 if(mcInst.
getOpcode() == X86::REP_PREFIX)
2453 else if(mcInst.
getOpcode() == X86::REPNE_PREFIX)
2460 if (
Op.encoding != ENCODING_NONE) {
2473 std::unique_ptr<const MCInstrInfo> MII(
T.createMCInstrInfo());
2474 return new X86GenericDisassembler(STI, Ctx, std::move(MII));
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
#define LLVM_EXTERNAL_VISIBILITY
static bool isBranch(unsigned Opcode)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static uint8_t readOpcode(WasmObjectFile::ReadContext &Ctx)
static int nextByte(ArrayRef< uint8_t > Bytes, uint64_t &Size)
static bool isPrefix(unsigned Opcode, const MCInstrInfo &MCII)
Check if the instruction is a prefix.
#define CASE_ENCODING_VSIB
#define THREEDNOW_MAP_SYM
#define rFromEVEX2of4(evex)
#define lFromEVEX4of4(evex)
#define l2FromEVEX4of4(evex)
#define rFromVEX2of3(vex)
#define zFromEVEX4of4(evex)
#define bFromXOP2of3(xop)
#define xFromVEX2of3(vex)
#define mmmmmFromVEX2of3(vex)
#define rmFromModRM(modRM)
#define bFromEVEX4of4(evex)
#define rFromVEX2of2(vex)
#define ppFromEVEX3of4(evex)
#define v2FromEVEX4of4(evex)
#define modFromModRM(modRM)
#define rFromXOP2of3(xop)
#define lFromXOP3of3(xop)
#define lFromVEX2of2(vex)
#define scFromEVEX4of4(evex)
#define scaleFromSIB(sib)
#define regFromModRM(modRM)
#define b2FromEVEX2of4(evex)
#define vvvvFromVEX2of2(vex)
#define nfFromEVEX4of4(evex)
#define ppFromXOP3of3(xop)
#define vvvvFromVEX3of3(vex)
#define r2FromEVEX2of4(evex)
#define uFromEVEX3of4(evex)
#define xFromXOP2of3(xop)
#define wFromEVEX3of4(evex)
#define bFromVEX2of3(vex)
#define wFromVEX3of3(vex)
#define mmmmmFromXOP2of3(xop)
#define aaaFromEVEX4of4(evex)
#define lFromVEX3of3(vex)
#define mmmFromEVEX2of4(evex)
#define ppFromVEX3of3(vex)
#define bFromEVEX2of4(evex)
#define xFromEVEX2of4(evex)
#define ppFromVEX2of2(vex)
#define indexFromSIB(sib)
#define vvvvFromXOP3of3(xop)
#define wFromXOP3of3(xop)
#define oszcFromEVEX3of4(evex)
#define vvvvFromEVEX3of4(evex)
static void translateRegister(MCInst &mcInst, Reg reg)
translateRegister - Translates an internal register to the appropriate LLVM register,...
static bool isREX2(struct InternalInstruction *insn, uint8_t prefix)
static int getInstructionID(struct InternalInstruction *insn, const MCInstrInfo *mii)
static bool readOpcode(struct InternalInstruction *insn)
static MCDisassembler * createX86Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static bool translateMaskRegister(MCInst &mcInst, uint8_t maskRegNum)
translateMaskRegister - Translates a 3-bit mask register number to LLVM form, and appends it to an MC...
static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn)
translateDstIndex - Appends a destination index operand to an MCInst.
static void translateImmediate(MCInst &mcInst, uint64_t immediate, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateImmediate - Appends an immediate operand to an MCInst.
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Disassembler()
static int readOperands(struct InternalInstruction *insn)
static void translateFPRegister(MCInst &mcInst, uint8_t stackPos)
translateFPRegister - Translates a stack position on the FPU stack to its LLVM form,...
static bool is64Bit(const char *name)
static const uint8_t segmentRegnums[SEG_OVERRIDE_max]
static int readImmediate(struct InternalInstruction *insn, uint8_t size)
static int getInstructionIDWithAttrMask(uint16_t *instructionID, struct InternalInstruction *insn, uint16_t attrMask)
static int readSIB(struct InternalInstruction *insn)
static bool isREX(struct InternalInstruction *insn, uint8_t prefix)
static int readVVVV(struct InternalInstruction *insn)
static bool isNF(InternalInstruction *insn)
static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn)
translateSrcIndex - Appends a source index operand to an MCInst.
#define GENERIC_FIXUP_FUNC(name, base, prefix)
static int readMaskRegister(struct InternalInstruction *insn)
static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateRM - Translates an operand stored in the R/M (and possibly SIB) byte of an instruction to LL...
static InstrUID decode(OpcodeType type, InstructionContext insnContext, uint8_t opcode, uint8_t modRM)
static int readOpcodeRegister(struct InternalInstruction *insn, uint8_t size)
static int readDisplacement(struct InternalInstruction *insn)
static bool isCCMPOrCTEST(InternalInstruction *insn)
static int fixupReg(struct InternalInstruction *insn, const struct OperandSpecifier *op)
static int readModRM(struct InternalInstruction *insn)
static bool is16BitEquivalent(const char *orig, const char *equiv)
static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn, const MCDisassembler *Dis, bool ForceSIB=false)
translateRMMemory - Translates a memory operand stored in the Mod and R/M fields of an internal instr...
static bool translateInstruction(MCInst &target, InternalInstruction &source, const MCDisassembler *Dis)
translateInstruction - Translates an internal instruction and all its operands to an MCInst.
static bool translateRMRegister(MCInst &mcInst, InternalInstruction &insn)
translateRMRegister - Translates a register stored in the R/M field of the ModR/M byte to its LLVM eq...
static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateOperand - Translates an operand stored in an internal instruction to LLVM's format and appen...
static int readPrefixes(struct InternalInstruction *insn)
static bool peek(struct InternalInstruction *insn, uint8_t &byte)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
This class represents an Operation in the Expression.
Container class for subtarget features.
Context object for machine code objects.
Superclass for all disassemblers.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
void tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) const
DecodeStatus
Ternary decode status.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
Instances of this class represent a single low-level machine instruction.
unsigned getOpcode() const
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
Interface to description of machine instruction set.
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(unsigned Reg)
static MCOperand createImm(int64_t Val)
Generic base class for all target subtargets.
const FeatureBitset & getFeatureBits() const
StringRef - Represent a constant reference to a string, i.e.
constexpr const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ X86
Windows x64, Windows Itanium (IA-64)
EABase
All possible values of the base field for effective-address computations, a.k.a.
Reg
All possible values of the reg field in the ModR/M byte.
DisassemblerMode
Decoding mode for the Intel disassembler.
SIBBase
All possible values of the SIB base field.
SIBIndex
All possible values of the SIB index field.
NodeAddr< InstrNode * > Instr
This is an optimization pass for GlobalISel generic memory operations.
LLVM_ATTRIBUTE_ALWAYS_INLINE DynamicAPInt mod(const DynamicAPInt &LHS, const DynamicAPInt &RHS)
is always non-negative.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Target & getTheX86_32Target()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Target & getTheX86_64Target()
Implement std::hash so that hash_code can be used in STL containers.
OpcodeDecision opcodeDecisions[IC_max]
ModRMDecision modRMDecisions[256]
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
The specification for how to extract and interpret a full instruction and its operands.
The x86 internal instruction, which is produced by the decoder.
ArrayRef< OperandSpecifier > operands
EADisplacement eaDisplacement
uint8_t rex2ExtensionPrefix[2]
uint8_t vectorExtensionPrefix[4]
SegmentOverride segmentOverride
uint8_t numImmediatesConsumed
llvm::ArrayRef< uint8_t > bytes
uint8_t numImmediatesTranslated
const InstructionSpecifier * spec
VectorExtensionType vectorExtensionType
uint8_t displacementOffset
The specification for how to extract and interpret one operand.