LLVM 20.0.0git
X86Disassembler.cpp
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1//===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file is part of the X86 Disassembler.
10// It contains code to translate the data produced by the decoder into
11// MCInsts.
12//
13//
14// The X86 disassembler is a table-driven disassembler for the 16-, 32-, and
15// 64-bit X86 instruction sets. The main decode sequence for an assembly
16// instruction in this disassembler is:
17//
18// 1. Read the prefix bytes and determine the attributes of the instruction.
19// These attributes, recorded in enum attributeBits
20// (X86DisassemblerDecoderCommon.h), form a bitmask. The table CONTEXTS_SYM
21// provides a mapping from bitmasks to contexts, which are represented by
22// enum InstructionContext (ibid.).
23//
24// 2. Read the opcode, and determine what kind of opcode it is. The
25// disassembler distinguishes four kinds of opcodes, which are enumerated in
26// OpcodeType (X86DisassemblerDecoderCommon.h): one-byte (0xnn), two-byte
27// (0x0f 0xnn), three-byte-38 (0x0f 0x38 0xnn), or three-byte-3a
28// (0x0f 0x3a 0xnn). Mandatory prefixes are treated as part of the context.
29//
30// 3. Depending on the opcode type, look in one of four ClassDecision structures
31// (X86DisassemblerDecoderCommon.h). Use the opcode class to determine which
32// OpcodeDecision (ibid.) to look the opcode in. Look up the opcode, to get
33// a ModRMDecision (ibid.).
34//
35// 4. Some instructions, such as escape opcodes or extended opcodes, or even
36// instructions that have ModRM*Reg / ModRM*Mem forms in LLVM, need the
37// ModR/M byte to complete decode. The ModRMDecision's type is an entry from
38// ModRMDecisionType (X86DisassemblerDecoderCommon.h) that indicates if the
39// ModR/M byte is required and how to interpret it.
40//
41// 5. After resolving the ModRMDecision, the disassembler has a unique ID
42// of type InstrUID (X86DisassemblerDecoderCommon.h). Looking this ID up in
43// INSTRUCTIONS_SYM yields the name of the instruction and the encodings and
44// meanings of its operands.
45//
46// 6. For each operand, its encoding is an entry from OperandEncoding
47// (X86DisassemblerDecoderCommon.h) and its type is an entry from
48// OperandType (ibid.). The encoding indicates how to read it from the
49// instruction; the type indicates how to interpret the value once it has
50// been read. For example, a register operand could be stored in the R/M
51// field of the ModR/M byte, the REG field of the ModR/M byte, or added to
52// the main opcode. This is orthogonal from its meaning (an GPR or an XMM
53// register, for instance). Given this information, the operands can be
54// extracted and interpreted.
55//
56// 7. As the last step, the disassembler translates the instruction information
57// and operands into a format understandable by the client - in this case, an
58// MCInst for use by the MC infrastructure.
59//
60// The disassembler is broken broadly into two parts: the table emitter that
61// emits the instruction decode tables discussed above during compilation, and
62// the disassembler itself. The table emitter is documented in more detail in
63// utils/TableGen/X86DisassemblerEmitter.h.
64//
65// X86Disassembler.cpp contains the code responsible for step 7, and for
66// invoking the decoder to execute steps 1-6.
67// X86DisassemblerDecoderCommon.h contains the definitions needed by both the
68// table emitter and the disassembler.
69// X86DisassemblerDecoder.h contains the public interface of the decoder,
70// factored out into C for possible use by other projects.
71// X86DisassemblerDecoder.c contains the source code of the decoder, which is
72// responsible for steps 1-6.
73//
74//===----------------------------------------------------------------------===//
75
80#include "llvm/MC/MCContext.h"
82#include "llvm/MC/MCExpr.h"
83#include "llvm/MC/MCInst.h"
84#include "llvm/MC/MCInstrInfo.h"
87#include "llvm/Support/Debug.h"
88#include "llvm/Support/Format.h"
90
91using namespace llvm;
92using namespace llvm::X86Disassembler;
93
94#define DEBUG_TYPE "x86-disassembler"
95
96#define debug(s) LLVM_DEBUG(dbgs() << __LINE__ << ": " << s);
97
98// Specifies whether a ModR/M byte is needed and (if so) which
99// instruction each possible value of the ModR/M byte corresponds to. Once
100// this information is known, we have narrowed down to a single instruction.
102 uint8_t modrm_type;
104};
105
106// Specifies which set of ModR/M->instruction tables to look at
107// given a particular opcode.
110};
111
112// Specifies which opcode->instruction tables to look at given
113// a particular context (set of attributes). Since there are many possible
114// contexts, the decoder first uses CONTEXTS_SYM to determine which context
115// applies given a specific set of attributes. Hence there are only IC_max
116// entries in this table, rather than 2^(ATTR_max).
119};
120
121#include "X86GenDisassemblerTables.inc"
122
124 uint8_t opcode, uint8_t modRM) {
125 const struct ModRMDecision *dec;
126
127 switch (type) {
128 case ONEBYTE:
129 dec = &ONEBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
130 break;
131 case TWOBYTE:
132 dec = &TWOBYTE_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
133 break;
134 case THREEBYTE_38:
135 dec = &THREEBYTE38_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
136 break;
137 case THREEBYTE_3A:
138 dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
139 break;
140 case XOP8_MAP:
141 dec = &XOP8_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
142 break;
143 case XOP9_MAP:
144 dec = &XOP9_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
145 break;
146 case XOPA_MAP:
147 dec = &XOPA_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
148 break;
149 case THREEDNOW_MAP:
150 dec =
151 &THREEDNOW_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
152 break;
153 case MAP4:
154 dec = &MAP4_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
155 break;
156 case MAP5:
157 dec = &MAP5_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
158 break;
159 case MAP6:
160 dec = &MAP6_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
161 break;
162 case MAP7:
163 dec = &MAP7_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
164 break;
165 }
166
167 switch (dec->modrm_type) {
168 default:
169 llvm_unreachable("Corrupt table! Unknown modrm_type");
170 return 0;
171 case MODRM_ONEENTRY:
172 return modRMTable[dec->instructionIDs];
173 case MODRM_SPLITRM:
174 if (modFromModRM(modRM) == 0x3)
175 return modRMTable[dec->instructionIDs + 1];
176 return modRMTable[dec->instructionIDs];
177 case MODRM_SPLITREG:
178 if (modFromModRM(modRM) == 0x3)
179 return modRMTable[dec->instructionIDs + ((modRM & 0x38) >> 3) + 8];
180 return modRMTable[dec->instructionIDs + ((modRM & 0x38) >> 3)];
181 case MODRM_SPLITMISC:
182 if (modFromModRM(modRM) == 0x3)
183 return modRMTable[dec->instructionIDs + (modRM & 0x3f) + 8];
184 return modRMTable[dec->instructionIDs + ((modRM & 0x38) >> 3)];
185 case MODRM_FULL:
186 return modRMTable[dec->instructionIDs + modRM];
187 }
188}
189
190static bool peek(struct InternalInstruction *insn, uint8_t &byte) {
191 uint64_t offset = insn->readerCursor - insn->startLocation;
192 if (offset >= insn->bytes.size())
193 return true;
194 byte = insn->bytes[offset];
195 return false;
196}
197
198template <typename T> static bool consume(InternalInstruction *insn, T &ptr) {
199 auto r = insn->bytes;
200 uint64_t offset = insn->readerCursor - insn->startLocation;
201 if (offset + sizeof(T) > r.size())
202 return true;
203 ptr = support::endian::read<T>(&r[offset], llvm::endianness::little);
204 insn->readerCursor += sizeof(T);
205 return false;
206}
207
208static bool isREX(struct InternalInstruction *insn, uint8_t prefix) {
209 return insn->mode == MODE_64BIT && prefix >= 0x40 && prefix <= 0x4f;
210}
211
212static bool isREX2(struct InternalInstruction *insn, uint8_t prefix) {
213 return insn->mode == MODE_64BIT && prefix == 0xd5;
214}
215
216// Consumes all of an instruction's prefix bytes, and marks the
217// instruction as having them. Also sets the instruction's default operand,
218// address, and other relevant data sizes to report operands correctly.
219//
220// insn must not be empty.
221static int readPrefixes(struct InternalInstruction *insn) {
222 bool isPrefix = true;
223 uint8_t byte = 0;
224 uint8_t nextByte;
225
226 LLVM_DEBUG(dbgs() << "readPrefixes()");
227
228 while (isPrefix) {
229 // If we fail reading prefixes, just stop here and let the opcode reader
230 // deal with it.
231 if (consume(insn, byte))
232 break;
233
234 // If the byte is a LOCK/REP/REPNE prefix and not a part of the opcode, then
235 // break and let it be disassembled as a normal "instruction".
236 if (insn->readerCursor - 1 == insn->startLocation && byte == 0xf0) // LOCK
237 break;
238
239 if ((byte == 0xf2 || byte == 0xf3) && !peek(insn, nextByte)) {
240 // If the byte is 0xf2 or 0xf3, and any of the following conditions are
241 // met:
242 // - it is followed by a LOCK (0xf0) prefix
243 // - it is followed by an xchg instruction
244 // then it should be disassembled as a xacquire/xrelease not repne/rep.
245 if (((nextByte == 0xf0) ||
246 ((nextByte & 0xfe) == 0x86 || (nextByte & 0xf8) == 0x90))) {
247 insn->xAcquireRelease = true;
248 if (!(byte == 0xf3 && nextByte == 0x90)) // PAUSE instruction support
249 break;
250 }
251 // Also if the byte is 0xf3, and the following condition is met:
252 // - it is followed by a "mov mem, reg" (opcode 0x88/0x89) or
253 // "mov mem, imm" (opcode 0xc6/0xc7) instructions.
254 // then it should be disassembled as an xrelease not rep.
255 if (byte == 0xf3 && (nextByte == 0x88 || nextByte == 0x89 ||
256 nextByte == 0xc6 || nextByte == 0xc7)) {
257 insn->xAcquireRelease = true;
258 break;
259 }
260 if (isREX(insn, nextByte)) {
261 uint8_t nnextByte;
262 // Go to REX prefix after the current one
263 if (consume(insn, nnextByte))
264 return -1;
265 // We should be able to read next byte after REX prefix
266 if (peek(insn, nnextByte))
267 return -1;
268 --insn->readerCursor;
269 }
270 }
271
272 switch (byte) {
273 case 0xf0: // LOCK
274 insn->hasLockPrefix = true;
275 break;
276 case 0xf2: // REPNE/REPNZ
277 case 0xf3: { // REP or REPE/REPZ
278 uint8_t nextByte;
279 if (peek(insn, nextByte))
280 break;
281 // TODO:
282 // 1. There could be several 0x66
283 // 2. if (nextByte == 0x66) and nextNextByte != 0x0f then
284 // it's not mandatory prefix
285 // 3. if (nextByte >= 0x40 && nextByte <= 0x4f) it's REX and we need
286 // 0x0f exactly after it to be mandatory prefix
287 // 4. if (nextByte == 0xd5) it's REX2 and we need
288 // 0x0f exactly after it to be mandatory prefix
289 if (isREX(insn, nextByte) || isREX2(insn, nextByte) || nextByte == 0x0f ||
290 nextByte == 0x66)
291 // The last of 0xf2 /0xf3 is mandatory prefix
292 insn->mandatoryPrefix = byte;
293 insn->repeatPrefix = byte;
294 break;
295 }
296 case 0x2e: // CS segment override -OR- Branch not taken
298 break;
299 case 0x36: // SS segment override -OR- Branch taken
301 break;
302 case 0x3e: // DS segment override
304 break;
305 case 0x26: // ES segment override
307 break;
308 case 0x64: // FS segment override
310 break;
311 case 0x65: // GS segment override
313 break;
314 case 0x66: { // Operand-size override {
315 uint8_t nextByte;
316 insn->hasOpSize = true;
317 if (peek(insn, nextByte))
318 break;
319 // 0x66 can't overwrite existing mandatory prefix and should be ignored
320 if (!insn->mandatoryPrefix && (nextByte == 0x0f || isREX(insn, nextByte)))
321 insn->mandatoryPrefix = byte;
322 break;
323 }
324 case 0x67: // Address-size override
325 insn->hasAdSize = true;
326 break;
327 default: // Not a prefix byte
328 isPrefix = false;
329 break;
330 }
331
332 if (isPrefix)
333 LLVM_DEBUG(dbgs() << format("Found prefix 0x%hhx", byte));
334 }
335
337
338 if (byte == 0x62) {
339 uint8_t byte1, byte2;
340 if (consume(insn, byte1)) {
341 LLVM_DEBUG(dbgs() << "Couldn't read second byte of EVEX prefix");
342 return -1;
343 }
344
345 if (peek(insn, byte2)) {
346 LLVM_DEBUG(dbgs() << "Couldn't read third byte of EVEX prefix");
347 return -1;
348 }
349
350 if ((insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0)) {
352 } else {
353 --insn->readerCursor; // unconsume byte1
354 --insn->readerCursor; // unconsume byte
355 }
356
357 if (insn->vectorExtensionType == TYPE_EVEX) {
358 insn->vectorExtensionPrefix[0] = byte;
359 insn->vectorExtensionPrefix[1] = byte1;
360 if (consume(insn, insn->vectorExtensionPrefix[2])) {
361 LLVM_DEBUG(dbgs() << "Couldn't read third byte of EVEX prefix");
362 return -1;
363 }
364 if (consume(insn, insn->vectorExtensionPrefix[3])) {
365 LLVM_DEBUG(dbgs() << "Couldn't read fourth byte of EVEX prefix");
366 return -1;
367 }
368
369 if (insn->mode == MODE_64BIT) {
370 // We simulate the REX prefix for simplicity's sake
371 insn->rexPrefix = 0x40 |
372 (wFromEVEX3of4(insn->vectorExtensionPrefix[2]) << 3) |
373 (rFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 2) |
374 (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 1) |
375 (bFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 0);
376
377 // We simulate the REX2 prefix for simplicity's sake
378 insn->rex2ExtensionPrefix[1] =
379 (r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 6) |
380 (uFromEVEX3of4(insn->vectorExtensionPrefix[2]) << 5) |
381 (b2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4);
382 }
383
385 dbgs() << format(
386 "Found EVEX prefix 0x%hhx 0x%hhx 0x%hhx 0x%hhx",
388 insn->vectorExtensionPrefix[2], insn->vectorExtensionPrefix[3]));
389 }
390 } else if (byte == 0xc4) {
391 uint8_t byte1;
392 if (peek(insn, byte1)) {
393 LLVM_DEBUG(dbgs() << "Couldn't read second byte of VEX");
394 return -1;
395 }
396
397 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0)
399 else
400 --insn->readerCursor;
401
402 if (insn->vectorExtensionType == TYPE_VEX_3B) {
403 insn->vectorExtensionPrefix[0] = byte;
404 consume(insn, insn->vectorExtensionPrefix[1]);
405 consume(insn, insn->vectorExtensionPrefix[2]);
406
407 // We simulate the REX prefix for simplicity's sake
408
409 if (insn->mode == MODE_64BIT)
410 insn->rexPrefix = 0x40 |
411 (wFromVEX3of3(insn->vectorExtensionPrefix[2]) << 3) |
412 (rFromVEX2of3(insn->vectorExtensionPrefix[1]) << 2) |
413 (xFromVEX2of3(insn->vectorExtensionPrefix[1]) << 1) |
414 (bFromVEX2of3(insn->vectorExtensionPrefix[1]) << 0);
415
416 LLVM_DEBUG(dbgs() << format("Found VEX prefix 0x%hhx 0x%hhx 0x%hhx",
417 insn->vectorExtensionPrefix[0],
418 insn->vectorExtensionPrefix[1],
419 insn->vectorExtensionPrefix[2]));
420 }
421 } else if (byte == 0xc5) {
422 uint8_t byte1;
423 if (peek(insn, byte1)) {
424 LLVM_DEBUG(dbgs() << "Couldn't read second byte of VEX");
425 return -1;
426 }
427
428 if (insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0)
430 else
431 --insn->readerCursor;
432
433 if (insn->vectorExtensionType == TYPE_VEX_2B) {
434 insn->vectorExtensionPrefix[0] = byte;
435 consume(insn, insn->vectorExtensionPrefix[1]);
436
437 if (insn->mode == MODE_64BIT)
438 insn->rexPrefix =
439 0x40 | (rFromVEX2of2(insn->vectorExtensionPrefix[1]) << 2);
440
441 switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) {
442 default:
443 break;
444 case VEX_PREFIX_66:
445 insn->hasOpSize = true;
446 break;
447 }
448
449 LLVM_DEBUG(dbgs() << format("Found VEX prefix 0x%hhx 0x%hhx",
450 insn->vectorExtensionPrefix[0],
451 insn->vectorExtensionPrefix[1]));
452 }
453 } else if (byte == 0x8f) {
454 uint8_t byte1;
455 if (peek(insn, byte1)) {
456 LLVM_DEBUG(dbgs() << "Couldn't read second byte of XOP");
457 return -1;
458 }
459
460 if ((byte1 & 0x38) != 0x0) // 0 in these 3 bits is a POP instruction.
462 else
463 --insn->readerCursor;
464
465 if (insn->vectorExtensionType == TYPE_XOP) {
466 insn->vectorExtensionPrefix[0] = byte;
467 consume(insn, insn->vectorExtensionPrefix[1]);
468 consume(insn, insn->vectorExtensionPrefix[2]);
469
470 // We simulate the REX prefix for simplicity's sake
471
472 if (insn->mode == MODE_64BIT)
473 insn->rexPrefix = 0x40 |
474 (wFromXOP3of3(insn->vectorExtensionPrefix[2]) << 3) |
475 (rFromXOP2of3(insn->vectorExtensionPrefix[1]) << 2) |
476 (xFromXOP2of3(insn->vectorExtensionPrefix[1]) << 1) |
477 (bFromXOP2of3(insn->vectorExtensionPrefix[1]) << 0);
478
479 switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) {
480 default:
481 break;
482 case VEX_PREFIX_66:
483 insn->hasOpSize = true;
484 break;
485 }
486
487 LLVM_DEBUG(dbgs() << format("Found XOP prefix 0x%hhx 0x%hhx 0x%hhx",
488 insn->vectorExtensionPrefix[0],
489 insn->vectorExtensionPrefix[1],
490 insn->vectorExtensionPrefix[2]));
491 }
492 } else if (isREX2(insn, byte)) {
493 uint8_t byte1;
494 if (peek(insn, byte1)) {
495 LLVM_DEBUG(dbgs() << "Couldn't read second byte of REX2");
496 return -1;
497 }
498 insn->rex2ExtensionPrefix[0] = byte;
499 consume(insn, insn->rex2ExtensionPrefix[1]);
500
501 // We simulate the REX prefix for simplicity's sake
502 insn->rexPrefix = 0x40 | (wFromREX2(insn->rex2ExtensionPrefix[1]) << 3) |
503 (rFromREX2(insn->rex2ExtensionPrefix[1]) << 2) |
504 (xFromREX2(insn->rex2ExtensionPrefix[1]) << 1) |
505 (bFromREX2(insn->rex2ExtensionPrefix[1]) << 0);
506 LLVM_DEBUG(dbgs() << format("Found REX2 prefix 0x%hhx 0x%hhx",
507 insn->rex2ExtensionPrefix[0],
508 insn->rex2ExtensionPrefix[1]));
509 } else if (isREX(insn, byte)) {
510 if (peek(insn, nextByte))
511 return -1;
512 insn->rexPrefix = byte;
513 LLVM_DEBUG(dbgs() << format("Found REX prefix 0x%hhx", byte));
514 } else
515 --insn->readerCursor;
516
517 if (insn->mode == MODE_16BIT) {
518 insn->registerSize = (insn->hasOpSize ? 4 : 2);
519 insn->addressSize = (insn->hasAdSize ? 4 : 2);
520 insn->displacementSize = (insn->hasAdSize ? 4 : 2);
521 insn->immediateSize = (insn->hasOpSize ? 4 : 2);
522 } else if (insn->mode == MODE_32BIT) {
523 insn->registerSize = (insn->hasOpSize ? 2 : 4);
524 insn->addressSize = (insn->hasAdSize ? 2 : 4);
525 insn->displacementSize = (insn->hasAdSize ? 2 : 4);
526 insn->immediateSize = (insn->hasOpSize ? 2 : 4);
527 } else if (insn->mode == MODE_64BIT) {
528 insn->displacementSize = 4;
529 if (insn->rexPrefix && wFromREX(insn->rexPrefix)) {
530 insn->registerSize = 8;
531 insn->addressSize = (insn->hasAdSize ? 4 : 8);
532 insn->immediateSize = 4;
533 insn->hasOpSize = false;
534 } else {
535 insn->registerSize = (insn->hasOpSize ? 2 : 4);
536 insn->addressSize = (insn->hasAdSize ? 4 : 8);
537 insn->immediateSize = (insn->hasOpSize ? 2 : 4);
538 }
539 }
540
541 return 0;
542}
543
544// Consumes the SIB byte to determine addressing information.
545static int readSIB(struct InternalInstruction *insn) {
546 SIBBase sibBaseBase = SIB_BASE_NONE;
547 uint8_t index, base;
548
549 LLVM_DEBUG(dbgs() << "readSIB()");
550 switch (insn->addressSize) {
551 case 2:
552 default:
553 llvm_unreachable("SIB-based addressing doesn't work in 16-bit mode");
554 case 4:
555 insn->sibIndexBase = SIB_INDEX_EAX;
556 sibBaseBase = SIB_BASE_EAX;
557 break;
558 case 8:
559 insn->sibIndexBase = SIB_INDEX_RAX;
560 sibBaseBase = SIB_BASE_RAX;
561 break;
562 }
563
564 if (consume(insn, insn->sib))
565 return -1;
566
567 index = indexFromSIB(insn->sib) | (xFromREX(insn->rexPrefix) << 3) |
568 (x2FromREX2(insn->rex2ExtensionPrefix[1]) << 4);
569
570 if (index == 0x4) {
571 insn->sibIndex = SIB_INDEX_NONE;
572 } else {
573 insn->sibIndex = (SIBIndex)(insn->sibIndexBase + index);
574 }
575
576 insn->sibScale = 1 << scaleFromSIB(insn->sib);
577
578 base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3) |
579 (b2FromREX2(insn->rex2ExtensionPrefix[1]) << 4);
580
581 switch (base) {
582 case 0x5:
583 case 0xd:
584 switch (modFromModRM(insn->modRM)) {
585 case 0x0:
587 insn->sibBase = SIB_BASE_NONE;
588 break;
589 case 0x1:
591 insn->sibBase = (SIBBase)(sibBaseBase + base);
592 break;
593 case 0x2:
595 insn->sibBase = (SIBBase)(sibBaseBase + base);
596 break;
597 default:
598 llvm_unreachable("Cannot have Mod = 0b11 and a SIB byte");
599 }
600 break;
601 default:
602 insn->sibBase = (SIBBase)(sibBaseBase + base);
603 break;
604 }
605
606 return 0;
607}
608
609static int readDisplacement(struct InternalInstruction *insn) {
610 int8_t d8;
611 int16_t d16;
612 int32_t d32;
613 LLVM_DEBUG(dbgs() << "readDisplacement()");
614
615 insn->displacementOffset = insn->readerCursor - insn->startLocation;
616 switch (insn->eaDisplacement) {
617 case EA_DISP_NONE:
618 break;
619 case EA_DISP_8:
620 if (consume(insn, d8))
621 return -1;
622 insn->displacement = d8;
623 break;
624 case EA_DISP_16:
625 if (consume(insn, d16))
626 return -1;
627 insn->displacement = d16;
628 break;
629 case EA_DISP_32:
630 if (consume(insn, d32))
631 return -1;
632 insn->displacement = d32;
633 break;
634 }
635
636 return 0;
637}
638
639// Consumes all addressing information (ModR/M byte, SIB byte, and displacement.
640static int readModRM(struct InternalInstruction *insn) {
641 uint8_t mod, rm, reg;
642 LLVM_DEBUG(dbgs() << "readModRM()");
643
644 if (insn->consumedModRM)
645 return 0;
646
647 if (consume(insn, insn->modRM))
648 return -1;
649 insn->consumedModRM = true;
650
651 mod = modFromModRM(insn->modRM);
652 rm = rmFromModRM(insn->modRM);
653 reg = regFromModRM(insn->modRM);
654
655 // This goes by insn->registerSize to pick the correct register, which messes
656 // up if we're using (say) XMM or 8-bit register operands. That gets fixed in
657 // fixupReg().
658 switch (insn->registerSize) {
659 case 2:
660 insn->regBase = MODRM_REG_AX;
661 insn->eaRegBase = EA_REG_AX;
662 break;
663 case 4:
664 insn->regBase = MODRM_REG_EAX;
665 insn->eaRegBase = EA_REG_EAX;
666 break;
667 case 8:
668 insn->regBase = MODRM_REG_RAX;
669 insn->eaRegBase = EA_REG_RAX;
670 break;
671 }
672
673 reg |= (rFromREX(insn->rexPrefix) << 3) |
674 (r2FromREX2(insn->rex2ExtensionPrefix[1]) << 4);
675 rm |= (bFromREX(insn->rexPrefix) << 3) |
676 (b2FromREX2(insn->rex2ExtensionPrefix[1]) << 4);
677
678 if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT)
679 reg |= r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4;
680
681 insn->reg = (Reg)(insn->regBase + reg);
682
683 switch (insn->addressSize) {
684 case 2: {
685 EABase eaBaseBase = EA_BASE_BX_SI;
686
687 switch (mod) {
688 case 0x0:
689 if (rm == 0x6) {
690 insn->eaBase = EA_BASE_NONE;
692 if (readDisplacement(insn))
693 return -1;
694 } else {
695 insn->eaBase = (EABase)(eaBaseBase + rm);
697 }
698 break;
699 case 0x1:
700 insn->eaBase = (EABase)(eaBaseBase + rm);
702 insn->displacementSize = 1;
703 if (readDisplacement(insn))
704 return -1;
705 break;
706 case 0x2:
707 insn->eaBase = (EABase)(eaBaseBase + rm);
709 if (readDisplacement(insn))
710 return -1;
711 break;
712 case 0x3:
713 insn->eaBase = (EABase)(insn->eaRegBase + rm);
714 if (readDisplacement(insn))
715 return -1;
716 break;
717 }
718 break;
719 }
720 case 4:
721 case 8: {
722 EABase eaBaseBase = (insn->addressSize == 4 ? EA_BASE_EAX : EA_BASE_RAX);
723
724 switch (mod) {
725 case 0x0:
726 insn->eaDisplacement = EA_DISP_NONE; // readSIB may override this
727 // In determining whether RIP-relative mode is used (rm=5),
728 // or whether a SIB byte is present (rm=4),
729 // the extension bits (REX.b and EVEX.x) are ignored.
730 switch (rm & 7) {
731 case 0x4: // SIB byte is present
732 insn->eaBase = (insn->addressSize == 4 ? EA_BASE_sib : EA_BASE_sib64);
733 if (readSIB(insn) || readDisplacement(insn))
734 return -1;
735 break;
736 case 0x5: // RIP-relative
737 insn->eaBase = EA_BASE_NONE;
739 if (readDisplacement(insn))
740 return -1;
741 break;
742 default:
743 insn->eaBase = (EABase)(eaBaseBase + rm);
744 break;
745 }
746 break;
747 case 0x1:
748 insn->displacementSize = 1;
749 [[fallthrough]];
750 case 0x2:
751 insn->eaDisplacement = (mod == 0x1 ? EA_DISP_8 : EA_DISP_32);
752 switch (rm & 7) {
753 case 0x4: // SIB byte is present
754 insn->eaBase = EA_BASE_sib;
755 if (readSIB(insn) || readDisplacement(insn))
756 return -1;
757 break;
758 default:
759 insn->eaBase = (EABase)(eaBaseBase + rm);
760 if (readDisplacement(insn))
761 return -1;
762 break;
763 }
764 break;
765 case 0x3:
767 insn->eaBase = (EABase)(insn->eaRegBase + rm);
768 break;
769 }
770 break;
771 }
772 } // switch (insn->addressSize)
773
774 return 0;
775}
776
777#define GENERIC_FIXUP_FUNC(name, base, prefix) \
778 static uint16_t name(struct InternalInstruction *insn, OperandType type, \
779 uint8_t index, uint8_t *valid) { \
780 *valid = 1; \
781 switch (type) { \
782 default: \
783 debug("Unhandled register type"); \
784 *valid = 0; \
785 return 0; \
786 case TYPE_Rv: \
787 return base + index; \
788 case TYPE_R8: \
789 if (insn->rexPrefix && index >= 4 && index <= 7) \
790 return prefix##_SPL + (index - 4); \
791 else \
792 return prefix##_AL + index; \
793 case TYPE_R16: \
794 return prefix##_AX + index; \
795 case TYPE_R32: \
796 return prefix##_EAX + index; \
797 case TYPE_R64: \
798 return prefix##_RAX + index; \
799 case TYPE_ZMM: \
800 return prefix##_ZMM0 + index; \
801 case TYPE_YMM: \
802 return prefix##_YMM0 + index; \
803 case TYPE_XMM: \
804 return prefix##_XMM0 + index; \
805 case TYPE_TMM: \
806 if (index > 7) \
807 *valid = 0; \
808 return prefix##_TMM0 + index; \
809 case TYPE_VK: \
810 index &= 0xf; \
811 if (index > 7) \
812 *valid = 0; \
813 return prefix##_K0 + index; \
814 case TYPE_VK_PAIR: \
815 if (index > 7) \
816 *valid = 0; \
817 return prefix##_K0_K1 + (index / 2); \
818 case TYPE_MM64: \
819 return prefix##_MM0 + (index & 0x7); \
820 case TYPE_SEGMENTREG: \
821 if ((index & 7) > 5) \
822 *valid = 0; \
823 return prefix##_ES + (index & 7); \
824 case TYPE_DEBUGREG: \
825 if (index > 15) \
826 *valid = 0; \
827 return prefix##_DR0 + index; \
828 case TYPE_CONTROLREG: \
829 if (index > 15) \
830 *valid = 0; \
831 return prefix##_CR0 + index; \
832 case TYPE_MVSIBX: \
833 return prefix##_XMM0 + index; \
834 case TYPE_MVSIBY: \
835 return prefix##_YMM0 + index; \
836 case TYPE_MVSIBZ: \
837 return prefix##_ZMM0 + index; \
838 } \
839 }
840
841// Consult an operand type to determine the meaning of the reg or R/M field. If
842// the operand is an XMM operand, for example, an operand would be XMM0 instead
843// of AX, which readModRM() would otherwise misinterpret it as.
844//
845// @param insn - The instruction containing the operand.
846// @param type - The operand type.
847// @param index - The existing value of the field as reported by readModRM().
848// @param valid - The address of a uint8_t. The target is set to 1 if the
849// field is valid for the register class; 0 if not.
850// @return - The proper value.
851GENERIC_FIXUP_FUNC(fixupRegValue, insn->regBase, MODRM_REG)
852GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG)
853
854// Consult an operand specifier to determine which of the fixup*Value functions
855// to use in correcting readModRM()'ss interpretation.
856//
857// @param insn - See fixup*Value().
858// @param op - The operand specifier.
859// @return - 0 if fixup was successful; -1 if the register returned was
860// invalid for its class.
861static int fixupReg(struct InternalInstruction *insn,
862 const struct OperandSpecifier *op) {
863 uint8_t valid;
864 LLVM_DEBUG(dbgs() << "fixupReg()");
865
866 switch ((OperandEncoding)op->encoding) {
867 default:
868 debug("Expected a REG or R/M encoding in fixupReg");
869 return -1;
870 case ENCODING_VVVV:
871 insn->vvvv =
872 (Reg)fixupRegValue(insn, (OperandType)op->type, insn->vvvv, &valid);
873 if (!valid)
874 return -1;
875 break;
876 case ENCODING_REG:
877 insn->reg = (Reg)fixupRegValue(insn, (OperandType)op->type,
878 insn->reg - insn->regBase, &valid);
879 if (!valid)
880 return -1;
881 break;
883 if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT &&
884 modFromModRM(insn->modRM) == 3) {
885 // EVEX_X can extend the register id to 32 for a non-GPR register that is
886 // encoded in RM.
887 // mode : MODE_64_BIT
888 // Only 8 vector registers are available in 32 bit mode
889 // mod : 3
890 // RM encodes a register
891 switch (op->type) {
892 case TYPE_Rv:
893 case TYPE_R8:
894 case TYPE_R16:
895 case TYPE_R32:
896 case TYPE_R64:
897 break;
898 default:
899 insn->eaBase =
900 (EABase)(insn->eaBase +
901 (xFromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4));
902 break;
903 }
904 }
905 [[fallthrough]];
906 case ENCODING_SIB:
907 if (insn->eaBase >= insn->eaRegBase) {
908 insn->eaBase = (EABase)fixupRMValue(
909 insn, (OperandType)op->type, insn->eaBase - insn->eaRegBase, &valid);
910 if (!valid)
911 return -1;
912 }
913 break;
914 }
915
916 return 0;
917}
918
919// Read the opcode (except the ModR/M byte in the case of extended or escape
920// opcodes).
921static bool readOpcode(struct InternalInstruction *insn) {
922 uint8_t current;
923 LLVM_DEBUG(dbgs() << "readOpcode()");
924
925 insn->opcodeType = ONEBYTE;
926 if (insn->vectorExtensionType == TYPE_EVEX) {
927 switch (mmmFromEVEX2of4(insn->vectorExtensionPrefix[1])) {
928 default:
930 dbgs() << format("Unhandled mmm field for instruction (0x%hhx)",
932 return true;
933 case VEX_LOB_0F:
934 insn->opcodeType = TWOBYTE;
935 return consume(insn, insn->opcode);
936 case VEX_LOB_0F38:
937 insn->opcodeType = THREEBYTE_38;
938 return consume(insn, insn->opcode);
939 case VEX_LOB_0F3A:
940 insn->opcodeType = THREEBYTE_3A;
941 return consume(insn, insn->opcode);
942 case VEX_LOB_MAP4:
943 insn->opcodeType = MAP4;
944 return consume(insn, insn->opcode);
945 case VEX_LOB_MAP5:
946 insn->opcodeType = MAP5;
947 return consume(insn, insn->opcode);
948 case VEX_LOB_MAP6:
949 insn->opcodeType = MAP6;
950 return consume(insn, insn->opcode);
951 case VEX_LOB_MAP7:
952 insn->opcodeType = MAP7;
953 return consume(insn, insn->opcode);
954 }
955 } else if (insn->vectorExtensionType == TYPE_VEX_3B) {
956 switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) {
957 default:
959 dbgs() << format("Unhandled m-mmmm field for instruction (0x%hhx)",
961 return true;
962 case VEX_LOB_0F:
963 insn->opcodeType = TWOBYTE;
964 return consume(insn, insn->opcode);
965 case VEX_LOB_0F38:
966 insn->opcodeType = THREEBYTE_38;
967 return consume(insn, insn->opcode);
968 case VEX_LOB_0F3A:
969 insn->opcodeType = THREEBYTE_3A;
970 return consume(insn, insn->opcode);
971 case VEX_LOB_MAP5:
972 insn->opcodeType = MAP5;
973 return consume(insn, insn->opcode);
974 case VEX_LOB_MAP6:
975 insn->opcodeType = MAP6;
976 return consume(insn, insn->opcode);
977 case VEX_LOB_MAP7:
978 insn->opcodeType = MAP7;
979 return consume(insn, insn->opcode);
980 }
981 } else if (insn->vectorExtensionType == TYPE_VEX_2B) {
982 insn->opcodeType = TWOBYTE;
983 return consume(insn, insn->opcode);
984 } else if (insn->vectorExtensionType == TYPE_XOP) {
985 switch (mmmmmFromXOP2of3(insn->vectorExtensionPrefix[1])) {
986 default:
988 dbgs() << format("Unhandled m-mmmm field for instruction (0x%hhx)",
990 return true;
991 case XOP_MAP_SELECT_8:
992 insn->opcodeType = XOP8_MAP;
993 return consume(insn, insn->opcode);
994 case XOP_MAP_SELECT_9:
995 insn->opcodeType = XOP9_MAP;
996 return consume(insn, insn->opcode);
997 case XOP_MAP_SELECT_A:
998 insn->opcodeType = XOPA_MAP;
999 return consume(insn, insn->opcode);
1000 }
1001 } else if (mFromREX2(insn->rex2ExtensionPrefix[1])) {
1002 // m bit indicates opcode map 1
1003 insn->opcodeType = TWOBYTE;
1004 return consume(insn, insn->opcode);
1005 }
1006
1007 if (consume(insn, current))
1008 return true;
1009
1010 if (current == 0x0f) {
1011 LLVM_DEBUG(
1012 dbgs() << format("Found a two-byte escape prefix (0x%hhx)", current));
1013 if (consume(insn, current))
1014 return true;
1015
1016 if (current == 0x38) {
1017 LLVM_DEBUG(dbgs() << format("Found a three-byte escape prefix (0x%hhx)",
1018 current));
1019 if (consume(insn, current))
1020 return true;
1021
1022 insn->opcodeType = THREEBYTE_38;
1023 } else if (current == 0x3a) {
1024 LLVM_DEBUG(dbgs() << format("Found a three-byte escape prefix (0x%hhx)",
1025 current));
1026 if (consume(insn, current))
1027 return true;
1028
1029 insn->opcodeType = THREEBYTE_3A;
1030 } else if (current == 0x0f) {
1031 LLVM_DEBUG(
1032 dbgs() << format("Found a 3dnow escape prefix (0x%hhx)", current));
1033
1034 // Consume operands before the opcode to comply with the 3DNow encoding
1035 if (readModRM(insn))
1036 return true;
1037
1038 if (consume(insn, current))
1039 return true;
1040
1041 insn->opcodeType = THREEDNOW_MAP;
1042 } else {
1043 LLVM_DEBUG(dbgs() << "Didn't find a three-byte escape prefix");
1044 insn->opcodeType = TWOBYTE;
1045 }
1046 } else if (insn->mandatoryPrefix)
1047 // The opcode with mandatory prefix must start with opcode escape.
1048 // If not it's legacy repeat prefix
1049 insn->mandatoryPrefix = 0;
1050
1051 // At this point we have consumed the full opcode.
1052 // Anything we consume from here on must be unconsumed.
1053 insn->opcode = current;
1054
1055 return false;
1056}
1057
1058// Determine whether equiv is the 16-bit equivalent of orig (32-bit or 64-bit).
1059static bool is16BitEquivalent(const char *orig, const char *equiv) {
1060 for (int i = 0;; i++) {
1061 if (orig[i] == '\0' && equiv[i] == '\0')
1062 return true;
1063 if (orig[i] == '\0' || equiv[i] == '\0')
1064 return false;
1065 if (orig[i] != equiv[i]) {
1066 if ((orig[i] == 'Q' || orig[i] == 'L') && equiv[i] == 'W')
1067 continue;
1068 if ((orig[i] == '6' || orig[i] == '3') && equiv[i] == '1')
1069 continue;
1070 if ((orig[i] == '4' || orig[i] == '2') && equiv[i] == '6')
1071 continue;
1072 return false;
1073 }
1074 }
1075}
1076
1077// Determine whether this instruction is a 64-bit instruction.
1078static bool is64Bit(const char *name) {
1079 for (int i = 0;; ++i) {
1080 if (name[i] == '\0')
1081 return false;
1082 if (name[i] == '6' && name[i + 1] == '4')
1083 return true;
1084 }
1085}
1086
1087// Determine the ID of an instruction, consuming the ModR/M byte as appropriate
1088// for extended and escape opcodes, and using a supplied attribute mask.
1089static int getInstructionIDWithAttrMask(uint16_t *instructionID,
1090 struct InternalInstruction *insn,
1091 uint16_t attrMask) {
1092 auto insnCtx = InstructionContext(x86DisassemblerContexts[attrMask]);
1093 const ContextDecision *decision;
1094 switch (insn->opcodeType) {
1095 case ONEBYTE:
1096 decision = &ONEBYTE_SYM;
1097 break;
1098 case TWOBYTE:
1099 decision = &TWOBYTE_SYM;
1100 break;
1101 case THREEBYTE_38:
1102 decision = &THREEBYTE38_SYM;
1103 break;
1104 case THREEBYTE_3A:
1105 decision = &THREEBYTE3A_SYM;
1106 break;
1107 case XOP8_MAP:
1108 decision = &XOP8_MAP_SYM;
1109 break;
1110 case XOP9_MAP:
1111 decision = &XOP9_MAP_SYM;
1112 break;
1113 case XOPA_MAP:
1114 decision = &XOPA_MAP_SYM;
1115 break;
1116 case THREEDNOW_MAP:
1117 decision = &THREEDNOW_MAP_SYM;
1118 break;
1119 case MAP4:
1120 decision = &MAP4_SYM;
1121 break;
1122 case MAP5:
1123 decision = &MAP5_SYM;
1124 break;
1125 case MAP6:
1126 decision = &MAP6_SYM;
1127 break;
1128 case MAP7:
1129 decision = &MAP7_SYM;
1130 break;
1131 }
1132
1133 if (decision->opcodeDecisions[insnCtx]
1134 .modRMDecisions[insn->opcode]
1135 .modrm_type != MODRM_ONEENTRY) {
1136 if (readModRM(insn))
1137 return -1;
1138 *instructionID =
1139 decode(insn->opcodeType, insnCtx, insn->opcode, insn->modRM);
1140 } else {
1141 *instructionID = decode(insn->opcodeType, insnCtx, insn->opcode, 0);
1142 }
1143
1144 return 0;
1145}
1146
1148 if (insn->opcodeType != MAP4)
1149 return false;
1150 if (insn->opcode == 0x83 && regFromModRM(insn->modRM) == 7)
1151 return true;
1152 switch (insn->opcode & 0xfe) {
1153 default:
1154 return false;
1155 case 0x38:
1156 case 0x3a:
1157 case 0x84:
1158 return true;
1159 case 0x80:
1160 return regFromModRM(insn->modRM) == 7;
1161 case 0xf6:
1162 return regFromModRM(insn->modRM) == 0;
1163 }
1164}
1165
1166static bool isNF(InternalInstruction *insn) {
1168 return false;
1169 if (insn->opcodeType == MAP4)
1170 return true;
1171 // Below NF instructions are not in map4.
1172 if (insn->opcodeType == THREEBYTE_38 &&
1174 switch (insn->opcode) {
1175 case 0xf2: // ANDN
1176 case 0xf3: // BLSI, BLSR, BLSMSK
1177 case 0xf5: // BZHI
1178 case 0xf7: // BEXTR
1179 return true;
1180 default:
1181 break;
1182 }
1183 }
1184 return false;
1185}
1186
1187// Determine the ID of an instruction, consuming the ModR/M byte as appropriate
1188// for extended and escape opcodes. Determines the attributes and context for
1189// the instruction before doing so.
1191 const MCInstrInfo *mii) {
1192 uint16_t attrMask;
1193 uint16_t instructionID;
1194
1195 LLVM_DEBUG(dbgs() << "getID()");
1196
1197 attrMask = ATTR_NONE;
1198
1199 if (insn->mode == MODE_64BIT)
1200 attrMask |= ATTR_64BIT;
1201
1202 if (insn->vectorExtensionType != TYPE_NO_VEX_XOP) {
1203 attrMask |= (insn->vectorExtensionType == TYPE_EVEX) ? ATTR_EVEX : ATTR_VEX;
1204
1205 if (insn->vectorExtensionType == TYPE_EVEX) {
1206 switch (ppFromEVEX3of4(insn->vectorExtensionPrefix[2])) {
1207 case VEX_PREFIX_66:
1208 attrMask |= ATTR_OPSIZE;
1209 break;
1210 case VEX_PREFIX_F3:
1211 attrMask |= ATTR_XS;
1212 break;
1213 case VEX_PREFIX_F2:
1214 attrMask |= ATTR_XD;
1215 break;
1216 }
1217
1219 attrMask |= ATTR_EVEXKZ;
1220 if (isNF(insn) && !readModRM(insn) &&
1221 !isCCMPOrCTEST(insn)) // NF bit is the MSB of aaa.
1222 attrMask |= ATTR_EVEXNF;
1223 // aaa is not used a opmask in MAP4
1224 else if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]) &&
1225 (insn->opcodeType != MAP4))
1226 attrMask |= ATTR_EVEXK;
1227 if (bFromEVEX4of4(insn->vectorExtensionPrefix[3])) {
1228 attrMask |= ATTR_EVEXB;
1229 if (uFromEVEX3of4(insn->vectorExtensionPrefix[2]) && !readModRM(insn) &&
1230 modFromModRM(insn->modRM) == 3)
1231 attrMask |= ATTR_EVEXU;
1232 }
1234 attrMask |= ATTR_VEXL;
1236 attrMask |= ATTR_EVEXL2;
1237 } else if (insn->vectorExtensionType == TYPE_VEX_3B) {
1238 switch (ppFromVEX3of3(insn->vectorExtensionPrefix[2])) {
1239 case VEX_PREFIX_66:
1240 attrMask |= ATTR_OPSIZE;
1241 break;
1242 case VEX_PREFIX_F3:
1243 attrMask |= ATTR_XS;
1244 break;
1245 case VEX_PREFIX_F2:
1246 attrMask |= ATTR_XD;
1247 break;
1248 }
1249
1250 if (lFromVEX3of3(insn->vectorExtensionPrefix[2]))
1251 attrMask |= ATTR_VEXL;
1252 } else if (insn->vectorExtensionType == TYPE_VEX_2B) {
1253 switch (ppFromVEX2of2(insn->vectorExtensionPrefix[1])) {
1254 case VEX_PREFIX_66:
1255 attrMask |= ATTR_OPSIZE;
1256 if (insn->hasAdSize)
1257 attrMask |= ATTR_ADSIZE;
1258 break;
1259 case VEX_PREFIX_F3:
1260 attrMask |= ATTR_XS;
1261 break;
1262 case VEX_PREFIX_F2:
1263 attrMask |= ATTR_XD;
1264 break;
1265 }
1266
1267 if (lFromVEX2of2(insn->vectorExtensionPrefix[1]))
1268 attrMask |= ATTR_VEXL;
1269 } else if (insn->vectorExtensionType == TYPE_XOP) {
1270 switch (ppFromXOP3of3(insn->vectorExtensionPrefix[2])) {
1271 case VEX_PREFIX_66:
1272 attrMask |= ATTR_OPSIZE;
1273 break;
1274 case VEX_PREFIX_F3:
1275 attrMask |= ATTR_XS;
1276 break;
1277 case VEX_PREFIX_F2:
1278 attrMask |= ATTR_XD;
1279 break;
1280 }
1281
1282 if (lFromXOP3of3(insn->vectorExtensionPrefix[2]))
1283 attrMask |= ATTR_VEXL;
1284 } else {
1285 return -1;
1286 }
1287 } else if (!insn->mandatoryPrefix) {
1288 // If we don't have mandatory prefix we should use legacy prefixes here
1289 if (insn->hasOpSize && (insn->mode != MODE_16BIT))
1290 attrMask |= ATTR_OPSIZE;
1291 if (insn->hasAdSize)
1292 attrMask |= ATTR_ADSIZE;
1293 if (insn->opcodeType == ONEBYTE) {
1294 if (insn->repeatPrefix == 0xf3 && (insn->opcode == 0x90))
1295 // Special support for PAUSE
1296 attrMask |= ATTR_XS;
1297 } else {
1298 if (insn->repeatPrefix == 0xf2)
1299 attrMask |= ATTR_XD;
1300 else if (insn->repeatPrefix == 0xf3)
1301 attrMask |= ATTR_XS;
1302 }
1303 } else {
1304 switch (insn->mandatoryPrefix) {
1305 case 0xf2:
1306 attrMask |= ATTR_XD;
1307 break;
1308 case 0xf3:
1309 attrMask |= ATTR_XS;
1310 break;
1311 case 0x66:
1312 if (insn->mode != MODE_16BIT)
1313 attrMask |= ATTR_OPSIZE;
1314 if (insn->hasAdSize)
1315 attrMask |= ATTR_ADSIZE;
1316 break;
1317 case 0x67:
1318 attrMask |= ATTR_ADSIZE;
1319 break;
1320 }
1321 }
1322
1323 if (insn->rexPrefix & 0x08) {
1324 attrMask |= ATTR_REXW;
1325 attrMask &= ~ATTR_ADSIZE;
1326 }
1327
1328 // Absolute jump and pushp/popp need special handling
1329 if (insn->rex2ExtensionPrefix[0] == 0xd5 && insn->opcodeType == ONEBYTE &&
1330 (insn->opcode == 0xA1 || (insn->opcode & 0xf0) == 0x50))
1331 attrMask |= ATTR_REX2;
1332
1333 if (insn->mode == MODE_16BIT) {
1334 // JCXZ/JECXZ need special handling for 16-bit mode because the meaning
1335 // of the AdSize prefix is inverted w.r.t. 32-bit mode.
1336 if (insn->opcodeType == ONEBYTE && insn->opcode == 0xE3)
1337 attrMask ^= ATTR_ADSIZE;
1338 // If we're in 16-bit mode and this is one of the relative jumps and opsize
1339 // prefix isn't present, we need to force the opsize attribute since the
1340 // prefix is inverted relative to 32-bit mode.
1341 if (!insn->hasOpSize && insn->opcodeType == ONEBYTE &&
1342 (insn->opcode == 0xE8 || insn->opcode == 0xE9))
1343 attrMask |= ATTR_OPSIZE;
1344
1345 if (!insn->hasOpSize && insn->opcodeType == TWOBYTE &&
1346 insn->opcode >= 0x80 && insn->opcode <= 0x8F)
1347 attrMask |= ATTR_OPSIZE;
1348 }
1349
1350
1351 if (getInstructionIDWithAttrMask(&instructionID, insn, attrMask))
1352 return -1;
1353
1354 // The following clauses compensate for limitations of the tables.
1355
1356 if (insn->mode != MODE_64BIT &&
1358 // The tables can't distinquish between cases where the W-bit is used to
1359 // select register size and cases where its a required part of the opcode.
1360 if ((insn->vectorExtensionType == TYPE_EVEX &&
1362 (insn->vectorExtensionType == TYPE_VEX_3B &&
1364 (insn->vectorExtensionType == TYPE_XOP &&
1366
1367 uint16_t instructionIDWithREXW;
1368 if (getInstructionIDWithAttrMask(&instructionIDWithREXW, insn,
1369 attrMask | ATTR_REXW)) {
1370 insn->instructionID = instructionID;
1371 insn->spec = &INSTRUCTIONS_SYM[instructionID];
1372 return 0;
1373 }
1374
1375 auto SpecName = mii->getName(instructionIDWithREXW);
1376 // If not a 64-bit instruction. Switch the opcode.
1377 if (!is64Bit(SpecName.data())) {
1378 insn->instructionID = instructionIDWithREXW;
1379 insn->spec = &INSTRUCTIONS_SYM[instructionIDWithREXW];
1380 return 0;
1381 }
1382 }
1383 }
1384
1385 // Absolute moves, umonitor, and movdir64b need special handling.
1386 // -For 16-bit mode because the meaning of the AdSize and OpSize prefixes are
1387 // inverted w.r.t.
1388 // -For 32-bit mode we need to ensure the ADSIZE prefix is observed in
1389 // any position.
1390 if ((insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0)) ||
1391 (insn->opcodeType == TWOBYTE && (insn->opcode == 0xAE)) ||
1392 (insn->opcodeType == THREEBYTE_38 && insn->opcode == 0xF8) ||
1393 (insn->opcodeType == MAP4 && insn->opcode == 0xF8)) {
1394 // Make sure we observed the prefixes in any position.
1395 if (insn->hasAdSize)
1396 attrMask |= ATTR_ADSIZE;
1397 if (insn->hasOpSize)
1398 attrMask |= ATTR_OPSIZE;
1399
1400 // In 16-bit, invert the attributes.
1401 if (insn->mode == MODE_16BIT) {
1402 attrMask ^= ATTR_ADSIZE;
1403
1404 // The OpSize attribute is only valid with the absolute moves.
1405 if (insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0))
1406 attrMask ^= ATTR_OPSIZE;
1407 }
1408
1409 if (getInstructionIDWithAttrMask(&instructionID, insn, attrMask))
1410 return -1;
1411
1412 insn->instructionID = instructionID;
1413 insn->spec = &INSTRUCTIONS_SYM[instructionID];
1414 return 0;
1415 }
1416
1417 if ((insn->mode == MODE_16BIT || insn->hasOpSize) &&
1418 !(attrMask & ATTR_OPSIZE)) {
1419 // The instruction tables make no distinction between instructions that
1420 // allow OpSize anywhere (i.e., 16-bit operations) and that need it in a
1421 // particular spot (i.e., many MMX operations). In general we're
1422 // conservative, but in the specific case where OpSize is present but not in
1423 // the right place we check if there's a 16-bit operation.
1424 const struct InstructionSpecifier *spec;
1425 uint16_t instructionIDWithOpsize;
1426 llvm::StringRef specName, specWithOpSizeName;
1427
1428 spec = &INSTRUCTIONS_SYM[instructionID];
1429
1430 if (getInstructionIDWithAttrMask(&instructionIDWithOpsize, insn,
1431 attrMask | ATTR_OPSIZE)) {
1432 // ModRM required with OpSize but not present. Give up and return the
1433 // version without OpSize set.
1434 insn->instructionID = instructionID;
1435 insn->spec = spec;
1436 return 0;
1437 }
1438
1439 specName = mii->getName(instructionID);
1440 specWithOpSizeName = mii->getName(instructionIDWithOpsize);
1441
1442 if (is16BitEquivalent(specName.data(), specWithOpSizeName.data()) &&
1443 (insn->mode == MODE_16BIT) ^ insn->hasOpSize) {
1444 insn->instructionID = instructionIDWithOpsize;
1445 insn->spec = &INSTRUCTIONS_SYM[instructionIDWithOpsize];
1446 } else {
1447 insn->instructionID = instructionID;
1448 insn->spec = spec;
1449 }
1450 return 0;
1451 }
1452
1453 if (insn->opcodeType == ONEBYTE && insn->opcode == 0x90 &&
1454 insn->rexPrefix & 0x01) {
1455 // NOOP shouldn't decode as NOOP if REX.b is set. Instead it should decode
1456 // as XCHG %r8, %eax.
1457 const struct InstructionSpecifier *spec;
1458 uint16_t instructionIDWithNewOpcode;
1459 const struct InstructionSpecifier *specWithNewOpcode;
1460
1461 spec = &INSTRUCTIONS_SYM[instructionID];
1462
1463 // Borrow opcode from one of the other XCHGar opcodes
1464 insn->opcode = 0x91;
1465
1466 if (getInstructionIDWithAttrMask(&instructionIDWithNewOpcode, insn,
1467 attrMask)) {
1468 insn->opcode = 0x90;
1469
1470 insn->instructionID = instructionID;
1471 insn->spec = spec;
1472 return 0;
1473 }
1474
1475 specWithNewOpcode = &INSTRUCTIONS_SYM[instructionIDWithNewOpcode];
1476
1477 // Change back
1478 insn->opcode = 0x90;
1479
1480 insn->instructionID = instructionIDWithNewOpcode;
1481 insn->spec = specWithNewOpcode;
1482
1483 return 0;
1484 }
1485
1486 insn->instructionID = instructionID;
1487 insn->spec = &INSTRUCTIONS_SYM[insn->instructionID];
1488
1489 return 0;
1490}
1491
1492// Read an operand from the opcode field of an instruction and interprets it
1493// appropriately given the operand width. Handles AddRegFrm instructions.
1494//
1495// @param insn - the instruction whose opcode field is to be read.
1496// @param size - The width (in bytes) of the register being specified.
1497// 1 means AL and friends, 2 means AX, 4 means EAX, and 8 means
1498// RAX.
1499// @return - 0 on success; nonzero otherwise.
1500static int readOpcodeRegister(struct InternalInstruction *insn, uint8_t size) {
1501 LLVM_DEBUG(dbgs() << "readOpcodeRegister()");
1502
1503 if (size == 0)
1504 size = insn->registerSize;
1505
1506 auto setOpcodeRegister = [&](unsigned base) {
1507 insn->opcodeRegister =
1508 (Reg)(base + ((bFromREX(insn->rexPrefix) << 3) |
1509 (b2FromREX2(insn->rex2ExtensionPrefix[1]) << 4) |
1510 (insn->opcode & 7)));
1511 };
1512
1513 switch (size) {
1514 case 1:
1515 setOpcodeRegister(MODRM_REG_AL);
1516 if (insn->rexPrefix && insn->opcodeRegister >= MODRM_REG_AL + 0x4 &&
1517 insn->opcodeRegister < MODRM_REG_AL + 0x8) {
1518 insn->opcodeRegister =
1519 (Reg)(MODRM_REG_SPL + (insn->opcodeRegister - MODRM_REG_AL - 4));
1520 }
1521
1522 break;
1523 case 2:
1524 setOpcodeRegister(MODRM_REG_AX);
1525 break;
1526 case 4:
1527 setOpcodeRegister(MODRM_REG_EAX);
1528 break;
1529 case 8:
1530 setOpcodeRegister(MODRM_REG_RAX);
1531 break;
1532 }
1533
1534 return 0;
1535}
1536
1537// Consume an immediate operand from an instruction, given the desired operand
1538// size.
1539//
1540// @param insn - The instruction whose operand is to be read.
1541// @param size - The width (in bytes) of the operand.
1542// @return - 0 if the immediate was successfully consumed; nonzero
1543// otherwise.
1544static int readImmediate(struct InternalInstruction *insn, uint8_t size) {
1545 uint8_t imm8;
1546 uint16_t imm16;
1547 uint32_t imm32;
1548 uint64_t imm64;
1549
1550 LLVM_DEBUG(dbgs() << "readImmediate()");
1551
1552 assert(insn->numImmediatesConsumed < 2 && "Already consumed two immediates");
1553
1554 insn->immediateSize = size;
1555 insn->immediateOffset = insn->readerCursor - insn->startLocation;
1556
1557 switch (size) {
1558 case 1:
1559 if (consume(insn, imm8))
1560 return -1;
1561 insn->immediates[insn->numImmediatesConsumed] = imm8;
1562 break;
1563 case 2:
1564 if (consume(insn, imm16))
1565 return -1;
1566 insn->immediates[insn->numImmediatesConsumed] = imm16;
1567 break;
1568 case 4:
1569 if (consume(insn, imm32))
1570 return -1;
1571 insn->immediates[insn->numImmediatesConsumed] = imm32;
1572 break;
1573 case 8:
1574 if (consume(insn, imm64))
1575 return -1;
1576 insn->immediates[insn->numImmediatesConsumed] = imm64;
1577 break;
1578 default:
1579 llvm_unreachable("invalid size");
1580 }
1581
1582 insn->numImmediatesConsumed++;
1583
1584 return 0;
1585}
1586
1587// Consume vvvv from an instruction if it has a VEX prefix.
1588static int readVVVV(struct InternalInstruction *insn) {
1589 LLVM_DEBUG(dbgs() << "readVVVV()");
1590
1591 int vvvv;
1592 if (insn->vectorExtensionType == TYPE_EVEX)
1593 vvvv = (v2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 4 |
1595 else if (insn->vectorExtensionType == TYPE_VEX_3B)
1596 vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]);
1597 else if (insn->vectorExtensionType == TYPE_VEX_2B)
1598 vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]);
1599 else if (insn->vectorExtensionType == TYPE_XOP)
1600 vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]);
1601 else
1602 return -1;
1603
1604 if (insn->mode != MODE_64BIT)
1605 vvvv &= 0xf; // Can only clear bit 4. Bit 3 must be cleared later.
1606
1607 insn->vvvv = static_cast<Reg>(vvvv);
1608 return 0;
1609}
1610
1611// Read an mask register from the opcode field of an instruction.
1612//
1613// @param insn - The instruction whose opcode field is to be read.
1614// @return - 0 on success; nonzero otherwise.
1615static int readMaskRegister(struct InternalInstruction *insn) {
1616 LLVM_DEBUG(dbgs() << "readMaskRegister()");
1617
1618 if (insn->vectorExtensionType != TYPE_EVEX)
1619 return -1;
1620
1621 insn->writemask =
1622 static_cast<Reg>(aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]));
1623 return 0;
1624}
1625
1626// Consults the specifier for an instruction and consumes all
1627// operands for that instruction, interpreting them as it goes.
1628static int readOperands(struct InternalInstruction *insn) {
1629 int hasVVVV, needVVVV;
1630 int sawRegImm = 0;
1631
1632 LLVM_DEBUG(dbgs() << "readOperands()");
1633
1634 // If non-zero vvvv specified, make sure one of the operands uses it.
1635 hasVVVV = !readVVVV(insn);
1636 needVVVV = hasVVVV && (insn->vvvv != 0);
1637
1638 for (const auto &Op : x86OperandSets[insn->spec->operands]) {
1639 switch (Op.encoding) {
1640 case ENCODING_NONE:
1641 case ENCODING_SI:
1642 case ENCODING_DI:
1643 break;
1645 // VSIB can use the V2 bit so check only the other bits.
1646 if (needVVVV)
1647 needVVVV = hasVVVV & ((insn->vvvv & 0xf) != 0);
1648 if (readModRM(insn))
1649 return -1;
1650
1651 // Reject if SIB wasn't used.
1652 if (insn->eaBase != EA_BASE_sib && insn->eaBase != EA_BASE_sib64)
1653 return -1;
1654
1655 // If sibIndex was set to SIB_INDEX_NONE, index offset is 4.
1656 if (insn->sibIndex == SIB_INDEX_NONE)
1657 insn->sibIndex = (SIBIndex)(insn->sibIndexBase + 4);
1658
1659 // If EVEX.v2 is set this is one of the 16-31 registers.
1660 if (insn->vectorExtensionType == TYPE_EVEX && insn->mode == MODE_64BIT &&
1662 insn->sibIndex = (SIBIndex)(insn->sibIndex + 16);
1663
1664 // Adjust the index register to the correct size.
1665 switch ((OperandType)Op.type) {
1666 default:
1667 debug("Unhandled VSIB index type");
1668 return -1;
1669 case TYPE_MVSIBX:
1670 insn->sibIndex =
1671 (SIBIndex)(SIB_INDEX_XMM0 + (insn->sibIndex - insn->sibIndexBase));
1672 break;
1673 case TYPE_MVSIBY:
1674 insn->sibIndex =
1675 (SIBIndex)(SIB_INDEX_YMM0 + (insn->sibIndex - insn->sibIndexBase));
1676 break;
1677 case TYPE_MVSIBZ:
1678 insn->sibIndex =
1679 (SIBIndex)(SIB_INDEX_ZMM0 + (insn->sibIndex - insn->sibIndexBase));
1680 break;
1681 }
1682
1683 // Apply the AVX512 compressed displacement scaling factor.
1684 if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8)
1685 insn->displacement *= 1 << (Op.encoding - ENCODING_VSIB);
1686 break;
1687 case ENCODING_SIB:
1688 // Reject if SIB wasn't used.
1689 if (insn->eaBase != EA_BASE_sib && insn->eaBase != EA_BASE_sib64)
1690 return -1;
1691 if (readModRM(insn))
1692 return -1;
1693 if (fixupReg(insn, &Op))
1694 return -1;
1695 break;
1696 case ENCODING_REG:
1698 if (readModRM(insn))
1699 return -1;
1700 if (fixupReg(insn, &Op))
1701 return -1;
1702 // Apply the AVX512 compressed displacement scaling factor.
1703 if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8)
1704 insn->displacement *= 1 << (Op.encoding - ENCODING_RM);
1705 break;
1706 case ENCODING_IB:
1707 if (sawRegImm) {
1708 // Saw a register immediate so don't read again and instead split the
1709 // previous immediate. FIXME: This is a hack.
1710 insn->immediates[insn->numImmediatesConsumed] =
1711 insn->immediates[insn->numImmediatesConsumed - 1] & 0xf;
1712 ++insn->numImmediatesConsumed;
1713 break;
1714 }
1715 if (readImmediate(insn, 1))
1716 return -1;
1717 if (Op.type == TYPE_XMM || Op.type == TYPE_YMM)
1718 sawRegImm = 1;
1719 break;
1720 case ENCODING_IW:
1721 if (readImmediate(insn, 2))
1722 return -1;
1723 break;
1724 case ENCODING_ID:
1725 if (readImmediate(insn, 4))
1726 return -1;
1727 break;
1728 case ENCODING_IO:
1729 if (readImmediate(insn, 8))
1730 return -1;
1731 break;
1732 case ENCODING_Iv:
1733 if (readImmediate(insn, insn->immediateSize))
1734 return -1;
1735 break;
1736 case ENCODING_Ia:
1737 if (readImmediate(insn, insn->addressSize))
1738 return -1;
1739 break;
1740 case ENCODING_IRC:
1741 insn->RC = (l2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 1) |
1743 break;
1744 case ENCODING_RB:
1745 if (readOpcodeRegister(insn, 1))
1746 return -1;
1747 break;
1748 case ENCODING_RW:
1749 if (readOpcodeRegister(insn, 2))
1750 return -1;
1751 break;
1752 case ENCODING_RD:
1753 if (readOpcodeRegister(insn, 4))
1754 return -1;
1755 break;
1756 case ENCODING_RO:
1757 if (readOpcodeRegister(insn, 8))
1758 return -1;
1759 break;
1760 case ENCODING_Rv:
1761 if (readOpcodeRegister(insn, 0))
1762 return -1;
1763 break;
1764 case ENCODING_CF:
1766 needVVVV = false; // oszc shares the same bits with VVVV
1767 break;
1768 case ENCODING_CC:
1769 if (isCCMPOrCTEST(insn))
1770 insn->immediates[2] = scFromEVEX4of4(insn->vectorExtensionPrefix[3]);
1771 else
1772 insn->immediates[1] = insn->opcode & 0xf;
1773 break;
1774 case ENCODING_FP:
1775 break;
1776 case ENCODING_VVVV:
1777 needVVVV = 0; // Mark that we have found a VVVV operand.
1778 if (!hasVVVV)
1779 return -1;
1780 if (insn->mode != MODE_64BIT)
1781 insn->vvvv = static_cast<Reg>(insn->vvvv & 0x7);
1782 if (fixupReg(insn, &Op))
1783 return -1;
1784 break;
1785 case ENCODING_WRITEMASK:
1786 if (readMaskRegister(insn))
1787 return -1;
1788 break;
1789 case ENCODING_DUP:
1790 break;
1791 default:
1792 LLVM_DEBUG(dbgs() << "Encountered an operand with an unknown encoding.");
1793 return -1;
1794 }
1795 }
1796
1797 // If we didn't find ENCODING_VVVV operand, but non-zero vvvv present, fail
1798 if (needVVVV)
1799 return -1;
1800
1801 return 0;
1802}
1803
1804namespace llvm {
1805
1806// Fill-ins to make the compiler happy. These constants are never actually
1807// assigned; they are just filler to make an automatically-generated switch
1808// statement work.
1809namespace X86 {
1810 enum {
1811 BX_SI = 500,
1812 BX_DI = 501,
1813 BP_SI = 502,
1814 BP_DI = 503,
1815 sib = 504,
1816 sib64 = 505
1818} // namespace X86
1819
1820} // namespace llvm
1821
1822static bool translateInstruction(MCInst &target,
1823 InternalInstruction &source,
1824 const MCDisassembler *Dis);
1825
1826namespace {
1827
1828/// Generic disassembler for all X86 platforms. All each platform class should
1829/// have to do is subclass the constructor, and provide a different
1830/// disassemblerMode value.
1831class X86GenericDisassembler : public MCDisassembler {
1832 std::unique_ptr<const MCInstrInfo> MII;
1833public:
1834 X86GenericDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
1835 std::unique_ptr<const MCInstrInfo> MII);
1836public:
1838 ArrayRef<uint8_t> Bytes, uint64_t Address,
1839 raw_ostream &cStream) const override;
1840
1841private:
1842 DisassemblerMode fMode;
1843};
1844
1845} // namespace
1846
1847X86GenericDisassembler::X86GenericDisassembler(
1848 const MCSubtargetInfo &STI,
1849 MCContext &Ctx,
1850 std::unique_ptr<const MCInstrInfo> MII)
1851 : MCDisassembler(STI, Ctx), MII(std::move(MII)) {
1852 const FeatureBitset &FB = STI.getFeatureBits();
1853 if (FB[X86::Is16Bit]) {
1854 fMode = MODE_16BIT;
1855 return;
1856 } else if (FB[X86::Is32Bit]) {
1857 fMode = MODE_32BIT;
1858 return;
1859 } else if (FB[X86::Is64Bit]) {
1860 fMode = MODE_64BIT;
1861 return;
1862 }
1863
1864 llvm_unreachable("Invalid CPU mode");
1865}
1866
1867MCDisassembler::DecodeStatus X86GenericDisassembler::getInstruction(
1869 raw_ostream &CStream) const {
1870 CommentStream = &CStream;
1871
1873 memset(&Insn, 0, sizeof(InternalInstruction));
1874 Insn.bytes = Bytes;
1875 Insn.startLocation = Address;
1876 Insn.readerCursor = Address;
1877 Insn.mode = fMode;
1878
1879 if (Bytes.empty() || readPrefixes(&Insn) || readOpcode(&Insn) ||
1880 getInstructionID(&Insn, MII.get()) || Insn.instructionID == 0 ||
1881 readOperands(&Insn)) {
1882 Size = Insn.readerCursor - Address;
1883 return Fail;
1884 }
1885
1886 Insn.operands = x86OperandSets[Insn.spec->operands];
1887 Insn.length = Insn.readerCursor - Insn.startLocation;
1888 Size = Insn.length;
1889 if (Size > 15)
1890 LLVM_DEBUG(dbgs() << "Instruction exceeds 15-byte limit");
1891
1892 bool Ret = translateInstruction(Instr, Insn, this);
1893 if (!Ret) {
1894 unsigned Flags = X86::IP_NO_PREFIX;
1895 if (Insn.hasAdSize)
1897 if (!Insn.mandatoryPrefix) {
1898 if (Insn.hasOpSize)
1900 if (Insn.repeatPrefix == 0xf2)
1902 else if (Insn.repeatPrefix == 0xf3 &&
1903 // It should not be 'pause' f3 90
1904 Insn.opcode != 0x90)
1906 if (Insn.hasLockPrefix)
1908 }
1909 Instr.setFlags(Flags);
1910 }
1911 return (!Ret) ? Success : Fail;
1912}
1913
1914//
1915// Private code that translates from struct InternalInstructions to MCInsts.
1916//
1917
1918/// translateRegister - Translates an internal register to the appropriate LLVM
1919/// register, and appends it as an operand to an MCInst.
1920///
1921/// @param mcInst - The MCInst to append to.
1922/// @param reg - The Reg to append.
1923static void translateRegister(MCInst &mcInst, Reg reg) {
1924#define ENTRY(x) X86::x,
1925 static constexpr MCPhysReg llvmRegnums[] = {ALL_REGS};
1926#undef ENTRY
1927
1928 MCPhysReg llvmRegnum = llvmRegnums[reg];
1929 mcInst.addOperand(MCOperand::createReg(llvmRegnum));
1930}
1931
1932static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = {
1933 0, // SEG_OVERRIDE_NONE
1934 X86::CS,
1935 X86::SS,
1936 X86::DS,
1937 X86::ES,
1938 X86::FS,
1939 X86::GS
1940};
1941
1942/// translateSrcIndex - Appends a source index operand to an MCInst.
1943///
1944/// @param mcInst - The MCInst to append to.
1945/// @param insn - The internal instruction.
1946static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) {
1947 unsigned baseRegNo;
1948
1949 if (insn.mode == MODE_64BIT)
1950 baseRegNo = insn.hasAdSize ? X86::ESI : X86::RSI;
1951 else if (insn.mode == MODE_32BIT)
1952 baseRegNo = insn.hasAdSize ? X86::SI : X86::ESI;
1953 else {
1954 assert(insn.mode == MODE_16BIT);
1955 baseRegNo = insn.hasAdSize ? X86::ESI : X86::SI;
1956 }
1957 MCOperand baseReg = MCOperand::createReg(baseRegNo);
1958 mcInst.addOperand(baseReg);
1959
1960 MCOperand segmentReg;
1962 mcInst.addOperand(segmentReg);
1963 return false;
1964}
1965
1966/// translateDstIndex - Appends a destination index operand to an MCInst.
1967///
1968/// @param mcInst - The MCInst to append to.
1969/// @param insn - The internal instruction.
1970
1971static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn) {
1972 unsigned baseRegNo;
1973
1974 if (insn.mode == MODE_64BIT)
1975 baseRegNo = insn.hasAdSize ? X86::EDI : X86::RDI;
1976 else if (insn.mode == MODE_32BIT)
1977 baseRegNo = insn.hasAdSize ? X86::DI : X86::EDI;
1978 else {
1979 assert(insn.mode == MODE_16BIT);
1980 baseRegNo = insn.hasAdSize ? X86::EDI : X86::DI;
1981 }
1982 MCOperand baseReg = MCOperand::createReg(baseRegNo);
1983 mcInst.addOperand(baseReg);
1984 return false;
1985}
1986
1987/// translateImmediate - Appends an immediate operand to an MCInst.
1988///
1989/// @param mcInst - The MCInst to append to.
1990/// @param immediate - The immediate value to append.
1991/// @param operand - The operand, as stored in the descriptor table.
1992/// @param insn - The internal instruction.
1993static void translateImmediate(MCInst &mcInst, uint64_t immediate,
1994 const OperandSpecifier &operand,
1995 InternalInstruction &insn,
1996 const MCDisassembler *Dis) {
1997 // Sign-extend the immediate if necessary.
1998
1999 OperandType type = (OperandType)operand.type;
2000
2001 bool isBranch = false;
2002 uint64_t pcrel = 0;
2003 if (type == TYPE_REL) {
2004 isBranch = true;
2005 pcrel = insn.startLocation + insn.length;
2006 switch (operand.encoding) {
2007 default:
2008 break;
2009 case ENCODING_Iv:
2010 switch (insn.displacementSize) {
2011 default:
2012 break;
2013 case 1:
2014 if(immediate & 0x80)
2015 immediate |= ~(0xffull);
2016 break;
2017 case 2:
2018 if(immediate & 0x8000)
2019 immediate |= ~(0xffffull);
2020 break;
2021 case 4:
2022 if(immediate & 0x80000000)
2023 immediate |= ~(0xffffffffull);
2024 break;
2025 case 8:
2026 break;
2027 }
2028 break;
2029 case ENCODING_IB:
2030 if(immediate & 0x80)
2031 immediate |= ~(0xffull);
2032 break;
2033 case ENCODING_IW:
2034 if(immediate & 0x8000)
2035 immediate |= ~(0xffffull);
2036 break;
2037 case ENCODING_ID:
2038 if(immediate & 0x80000000)
2039 immediate |= ~(0xffffffffull);
2040 break;
2041 }
2042 }
2043 // By default sign-extend all X86 immediates based on their encoding.
2044 else if (type == TYPE_IMM) {
2045 switch (operand.encoding) {
2046 default:
2047 break;
2048 case ENCODING_IB:
2049 if(immediate & 0x80)
2050 immediate |= ~(0xffull);
2051 break;
2052 case ENCODING_IW:
2053 if(immediate & 0x8000)
2054 immediate |= ~(0xffffull);
2055 break;
2056 case ENCODING_ID:
2057 if(immediate & 0x80000000)
2058 immediate |= ~(0xffffffffull);
2059 break;
2060 case ENCODING_IO:
2061 break;
2062 }
2063 }
2064
2065 switch (type) {
2066 case TYPE_XMM:
2067 mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4)));
2068 return;
2069 case TYPE_YMM:
2070 mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4)));
2071 return;
2072 case TYPE_ZMM:
2073 mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4)));
2074 return;
2075 default:
2076 // operand is 64 bits wide. Do nothing.
2077 break;
2078 }
2079
2080 if (!Dis->tryAddingSymbolicOperand(
2081 mcInst, immediate + pcrel, insn.startLocation, isBranch,
2082 insn.immediateOffset, insn.immediateSize, insn.length))
2083 mcInst.addOperand(MCOperand::createImm(immediate));
2084
2085 if (type == TYPE_MOFFS) {
2086 MCOperand segmentReg;
2088 mcInst.addOperand(segmentReg);
2089 }
2090}
2091
2092/// translateRMRegister - Translates a register stored in the R/M field of the
2093/// ModR/M byte to its LLVM equivalent and appends it to an MCInst.
2094/// @param mcInst - The MCInst to append to.
2095/// @param insn - The internal instruction to extract the R/M field
2096/// from.
2097/// @return - 0 on success; -1 otherwise
2098static bool translateRMRegister(MCInst &mcInst,
2099 InternalInstruction &insn) {
2100 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
2101 debug("A R/M register operand may not have a SIB byte");
2102 return true;
2103 }
2104
2105 switch (insn.eaBase) {
2106 default:
2107 debug("Unexpected EA base register");
2108 return true;
2109 case EA_BASE_NONE:
2110 debug("EA_BASE_NONE for ModR/M base");
2111 return true;
2112#define ENTRY(x) case EA_BASE_##x:
2114#undef ENTRY
2115 debug("A R/M register operand may not have a base; "
2116 "the operand must be a register.");
2117 return true;
2118#define ENTRY(x) \
2119 case EA_REG_##x: \
2120 mcInst.addOperand(MCOperand::createReg(X86::x)); break;
2121 ALL_REGS
2122#undef ENTRY
2123 }
2124
2125 return false;
2126}
2127
2128/// translateRMMemory - Translates a memory operand stored in the Mod and R/M
2129/// fields of an internal instruction (and possibly its SIB byte) to a memory
2130/// operand in LLVM's format, and appends it to an MCInst.
2131///
2132/// @param mcInst - The MCInst to append to.
2133/// @param insn - The instruction to extract Mod, R/M, and SIB fields
2134/// from.
2135/// @param ForceSIB - The instruction must use SIB.
2136/// @return - 0 on success; nonzero otherwise
2138 const MCDisassembler *Dis,
2139 bool ForceSIB = false) {
2140 // Addresses in an MCInst are represented as five operands:
2141 // 1. basereg (register) The R/M base, or (if there is a SIB) the
2142 // SIB base
2143 // 2. scaleamount (immediate) 1, or (if there is a SIB) the specified
2144 // scale amount
2145 // 3. indexreg (register) x86_registerNONE, or (if there is a SIB)
2146 // the index (which is multiplied by the
2147 // scale amount)
2148 // 4. displacement (immediate) 0, or the displacement if there is one
2149 // 5. segmentreg (register) x86_registerNONE for now, but could be set
2150 // if we have segment overrides
2151
2152 MCOperand baseReg;
2153 MCOperand scaleAmount;
2154 MCOperand indexReg;
2155 MCOperand displacement;
2156 MCOperand segmentReg;
2157 uint64_t pcrel = 0;
2158
2159 if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
2160 if (insn.sibBase != SIB_BASE_NONE) {
2161 switch (insn.sibBase) {
2162 default:
2163 debug("Unexpected sibBase");
2164 return true;
2165#define ENTRY(x) \
2166 case SIB_BASE_##x: \
2167 baseReg = MCOperand::createReg(X86::x); break;
2169#undef ENTRY
2170 }
2171 } else {
2172 baseReg = MCOperand::createReg(X86::NoRegister);
2173 }
2174
2175 if (insn.sibIndex != SIB_INDEX_NONE) {
2176 switch (insn.sibIndex) {
2177 default:
2178 debug("Unexpected sibIndex");
2179 return true;
2180#define ENTRY(x) \
2181 case SIB_INDEX_##x: \
2182 indexReg = MCOperand::createReg(X86::x); break;
2185 REGS_XMM
2186 REGS_YMM
2187 REGS_ZMM
2188#undef ENTRY
2189 }
2190 } else {
2191 // Use EIZ/RIZ for a few ambiguous cases where the SIB byte is present,
2192 // but no index is used and modrm alone should have been enough.
2193 // -No base register in 32-bit mode. In 64-bit mode this is used to
2194 // avoid rip-relative addressing.
2195 // -Any base register used other than ESP/RSP/R12D/R12. Using these as a
2196 // base always requires a SIB byte.
2197 // -A scale other than 1 is used.
2198 if (!ForceSIB &&
2199 (insn.sibScale != 1 ||
2200 (insn.sibBase == SIB_BASE_NONE && insn.mode != MODE_64BIT) ||
2201 (insn.sibBase != SIB_BASE_NONE &&
2202 insn.sibBase != SIB_BASE_ESP && insn.sibBase != SIB_BASE_RSP &&
2203 insn.sibBase != SIB_BASE_R12D && insn.sibBase != SIB_BASE_R12))) {
2204 indexReg = MCOperand::createReg(insn.addressSize == 4 ? X86::EIZ :
2205 X86::RIZ);
2206 } else
2207 indexReg = MCOperand::createReg(X86::NoRegister);
2208 }
2209
2210 scaleAmount = MCOperand::createImm(insn.sibScale);
2211 } else {
2212 switch (insn.eaBase) {
2213 case EA_BASE_NONE:
2214 if (insn.eaDisplacement == EA_DISP_NONE) {
2215 debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base");
2216 return true;
2217 }
2218 if (insn.mode == MODE_64BIT){
2219 pcrel = insn.startLocation + insn.length;
2221 insn.startLocation +
2222 insn.displacementOffset);
2223 // Section 2.2.1.6
2224 baseReg = MCOperand::createReg(insn.addressSize == 4 ? X86::EIP :
2225 X86::RIP);
2226 }
2227 else
2228 baseReg = MCOperand::createReg(X86::NoRegister);
2229
2230 indexReg = MCOperand::createReg(X86::NoRegister);
2231 break;
2232 case EA_BASE_BX_SI:
2233 baseReg = MCOperand::createReg(X86::BX);
2234 indexReg = MCOperand::createReg(X86::SI);
2235 break;
2236 case EA_BASE_BX_DI:
2237 baseReg = MCOperand::createReg(X86::BX);
2238 indexReg = MCOperand::createReg(X86::DI);
2239 break;
2240 case EA_BASE_BP_SI:
2241 baseReg = MCOperand::createReg(X86::BP);
2242 indexReg = MCOperand::createReg(X86::SI);
2243 break;
2244 case EA_BASE_BP_DI:
2245 baseReg = MCOperand::createReg(X86::BP);
2246 indexReg = MCOperand::createReg(X86::DI);
2247 break;
2248 default:
2249 indexReg = MCOperand::createReg(X86::NoRegister);
2250 switch (insn.eaBase) {
2251 default:
2252 debug("Unexpected eaBase");
2253 return true;
2254 // Here, we will use the fill-ins defined above. However,
2255 // BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and
2256 // sib and sib64 were handled in the top-level if, so they're only
2257 // placeholders to keep the compiler happy.
2258#define ENTRY(x) \
2259 case EA_BASE_##x: \
2260 baseReg = MCOperand::createReg(X86::x); break;
2262#undef ENTRY
2263#define ENTRY(x) case EA_REG_##x:
2264 ALL_REGS
2265#undef ENTRY
2266 debug("A R/M memory operand may not be a register; "
2267 "the base field must be a base.");
2268 return true;
2269 }
2270 }
2271
2272 scaleAmount = MCOperand::createImm(1);
2273 }
2274
2275 displacement = MCOperand::createImm(insn.displacement);
2276
2278
2279 mcInst.addOperand(baseReg);
2280 mcInst.addOperand(scaleAmount);
2281 mcInst.addOperand(indexReg);
2282
2283 const uint8_t dispSize =
2284 (insn.eaDisplacement == EA_DISP_NONE) ? 0 : insn.displacementSize;
2285
2287 mcInst, insn.displacement + pcrel, insn.startLocation, false,
2288 insn.displacementOffset, dispSize, insn.length))
2289 mcInst.addOperand(displacement);
2290 mcInst.addOperand(segmentReg);
2291 return false;
2292}
2293
2294/// translateRM - Translates an operand stored in the R/M (and possibly SIB)
2295/// byte of an instruction to LLVM form, and appends it to an MCInst.
2296///
2297/// @param mcInst - The MCInst to append to.
2298/// @param operand - The operand, as stored in the descriptor table.
2299/// @param insn - The instruction to extract Mod, R/M, and SIB fields
2300/// from.
2301/// @return - 0 on success; nonzero otherwise
2302static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
2303 InternalInstruction &insn, const MCDisassembler *Dis) {
2304 switch (operand.type) {
2305 default:
2306 debug("Unexpected type for a R/M operand");
2307 return true;
2308 case TYPE_R8:
2309 case TYPE_R16:
2310 case TYPE_R32:
2311 case TYPE_R64:
2312 case TYPE_Rv:
2313 case TYPE_MM64:
2314 case TYPE_XMM:
2315 case TYPE_YMM:
2316 case TYPE_ZMM:
2317 case TYPE_TMM:
2318 case TYPE_VK_PAIR:
2319 case TYPE_VK:
2320 case TYPE_DEBUGREG:
2321 case TYPE_CONTROLREG:
2322 case TYPE_BNDR:
2323 return translateRMRegister(mcInst, insn);
2324 case TYPE_M:
2325 case TYPE_MVSIBX:
2326 case TYPE_MVSIBY:
2327 case TYPE_MVSIBZ:
2328 return translateRMMemory(mcInst, insn, Dis);
2329 case TYPE_MSIB:
2330 return translateRMMemory(mcInst, insn, Dis, true);
2331 }
2332}
2333
2334/// translateFPRegister - Translates a stack position on the FPU stack to its
2335/// LLVM form, and appends it to an MCInst.
2336///
2337/// @param mcInst - The MCInst to append to.
2338/// @param stackPos - The stack position to translate.
2339static void translateFPRegister(MCInst &mcInst,
2340 uint8_t stackPos) {
2341 mcInst.addOperand(MCOperand::createReg(X86::ST0 + stackPos));
2342}
2343
2344/// translateMaskRegister - Translates a 3-bit mask register number to
2345/// LLVM form, and appends it to an MCInst.
2346///
2347/// @param mcInst - The MCInst to append to.
2348/// @param maskRegNum - Number of mask register from 0 to 7.
2349/// @return - false on success; true otherwise.
2350static bool translateMaskRegister(MCInst &mcInst,
2351 uint8_t maskRegNum) {
2352 if (maskRegNum >= 8) {
2353 debug("Invalid mask register number");
2354 return true;
2355 }
2356
2357 mcInst.addOperand(MCOperand::createReg(X86::K0 + maskRegNum));
2358 return false;
2359}
2360
2361/// translateOperand - Translates an operand stored in an internal instruction
2362/// to LLVM's format and appends it to an MCInst.
2363///
2364/// @param mcInst - The MCInst to append to.
2365/// @param operand - The operand, as stored in the descriptor table.
2366/// @param insn - The internal instruction.
2367/// @return - false on success; true otherwise.
2368static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
2369 InternalInstruction &insn,
2370 const MCDisassembler *Dis) {
2371 switch (operand.encoding) {
2372 default:
2373 debug("Unhandled operand encoding during translation");
2374 return true;
2375 case ENCODING_REG:
2376 translateRegister(mcInst, insn.reg);
2377 return false;
2378 case ENCODING_WRITEMASK:
2379 return translateMaskRegister(mcInst, insn.writemask);
2380 case ENCODING_SIB:
2383 return translateRM(mcInst, operand, insn, Dis);
2384 case ENCODING_IB:
2385 case ENCODING_IW:
2386 case ENCODING_ID:
2387 case ENCODING_IO:
2388 case ENCODING_Iv:
2389 case ENCODING_Ia:
2390 translateImmediate(mcInst,
2392 operand,
2393 insn,
2394 Dis);
2395 return false;
2396 case ENCODING_IRC:
2397 mcInst.addOperand(MCOperand::createImm(insn.RC));
2398 return false;
2399 case ENCODING_SI:
2400 return translateSrcIndex(mcInst, insn);
2401 case ENCODING_DI:
2402 return translateDstIndex(mcInst, insn);
2403 case ENCODING_RB:
2404 case ENCODING_RW:
2405 case ENCODING_RD:
2406 case ENCODING_RO:
2407 case ENCODING_Rv:
2408 translateRegister(mcInst, insn.opcodeRegister);
2409 return false;
2410 case ENCODING_CF:
2412 return false;
2413 case ENCODING_CC:
2414 if (isCCMPOrCTEST(&insn))
2416 else
2418 return false;
2419 case ENCODING_FP:
2420 translateFPRegister(mcInst, insn.modRM & 7);
2421 return false;
2422 case ENCODING_VVVV:
2423 translateRegister(mcInst, insn.vvvv);
2424 return false;
2425 case ENCODING_DUP:
2426 return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0],
2427 insn, Dis);
2428 }
2429}
2430
2431/// translateInstruction - Translates an internal instruction and all its
2432/// operands to an MCInst.
2433///
2434/// @param mcInst - The MCInst to populate with the instruction's data.
2435/// @param insn - The internal instruction.
2436/// @return - false on success; true otherwise.
2437static bool translateInstruction(MCInst &mcInst,
2438 InternalInstruction &insn,
2439 const MCDisassembler *Dis) {
2440 if (!insn.spec) {
2441 debug("Instruction has no specification");
2442 return true;
2443 }
2444
2445 mcInst.clear();
2446 mcInst.setOpcode(insn.instructionID);
2447 // If when reading the prefix bytes we determined the overlapping 0xf2 or 0xf3
2448 // prefix bytes should be disassembled as xrelease and xacquire then set the
2449 // opcode to those instead of the rep and repne opcodes.
2450 if (insn.xAcquireRelease) {
2451 if(mcInst.getOpcode() == X86::REP_PREFIX)
2452 mcInst.setOpcode(X86::XRELEASE_PREFIX);
2453 else if(mcInst.getOpcode() == X86::REPNE_PREFIX)
2454 mcInst.setOpcode(X86::XACQUIRE_PREFIX);
2455 }
2456
2457 insn.numImmediatesTranslated = 0;
2458
2459 for (const auto &Op : insn.operands) {
2460 if (Op.encoding != ENCODING_NONE) {
2461 if (translateOperand(mcInst, Op, insn, Dis)) {
2462 return true;
2463 }
2464 }
2465 }
2466
2467 return false;
2468}
2469
2471 const MCSubtargetInfo &STI,
2472 MCContext &Ctx) {
2473 std::unique_ptr<const MCInstrInfo> MII(T.createMCInstrInfo());
2474 return new X86GenericDisassembler(STI, Ctx, std::move(MII));
2475}
2476
2478 // Register the disassembler.
2483}
#define Fail
#define Success
SmallVector< AArch64_IMM::ImmInsnModel, 4 > Insn
aarch64 promote const
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:131
#define LLVM_DEBUG(X)
Definition: Debug.h:101
uint64_t Size
#define op(i)
if(PassOpts->AAPipeline)
static bool isBranch(unsigned Opcode)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static const char * name
Definition: SMEABIPass.cpp:50
static uint8_t readOpcode(WasmObjectFile::ReadContext &Ctx)
static int nextByte(ArrayRef< uint8_t > Bytes, uint64_t &Size)
static bool isPrefix(unsigned Opcode, const MCInstrInfo &MCII)
Check if the instruction is a prefix.
#define TWOBYTE_SYM
#define MAP4_SYM
#define CASE_ENCODING_VSIB
#define XOP9_MAP_SYM
#define CASE_ENCODING_RM
#define THREEDNOW_MAP_SYM
#define INSTRUCTIONS_SYM
#define THREEBYTE3A_SYM
#define XOP8_MAP_SYM
#define THREEBYTE38_SYM
#define XOPA_MAP_SYM
#define MAP6_SYM
#define MAP7_SYM
#define ONEBYTE_SYM
#define MAP5_SYM
#define rFromEVEX2of4(evex)
#define lFromEVEX4of4(evex)
#define l2FromEVEX4of4(evex)
#define rFromVEX2of3(vex)
#define zFromEVEX4of4(evex)
#define wFromREX2(rex2)
#define rFromREX(rex)
#define bFromXOP2of3(xop)
#define xFromVEX2of3(vex)
#define mmmmmFromVEX2of3(vex)
#define rmFromModRM(modRM)
#define bFromREX2(rex2)
#define baseFromSIB(sib)
#define bFromEVEX4of4(evex)
#define rFromVEX2of2(vex)
#define ppFromEVEX3of4(evex)
#define v2FromEVEX4of4(evex)
#define modFromModRM(modRM)
#define rFromXOP2of3(xop)
#define wFromREX(rex)
#define lFromXOP3of3(xop)
#define EA_BASES_64BIT
#define lFromVEX2of2(vex)
#define REGS_YMM
#define x2FromREX2(rex2)
#define scFromEVEX4of4(evex)
#define scaleFromSIB(sib)
#define REGS_XMM
#define rFromREX2(rex2)
#define regFromModRM(modRM)
#define b2FromEVEX2of4(evex)
#define b2FromREX2(rex2)
#define vvvvFromVEX2of2(vex)
#define nfFromEVEX4of4(evex)
#define ALL_REGS
#define ppFromXOP3of3(xop)
#define ALL_SIB_BASES
#define vvvvFromVEX3of3(vex)
#define r2FromEVEX2of4(evex)
#define uFromEVEX3of4(evex)
#define xFromREX2(rex2)
#define EA_BASES_32BIT
#define xFromXOP2of3(xop)
#define wFromEVEX3of4(evex)
#define bFromVEX2of3(vex)
#define wFromVEX3of3(vex)
#define mmmmmFromXOP2of3(xop)
#define aaaFromEVEX4of4(evex)
#define lFromVEX3of3(vex)
#define mmmFromEVEX2of4(evex)
#define ppFromVEX3of3(vex)
#define bFromEVEX2of4(evex)
#define xFromEVEX2of4(evex)
#define REGS_ZMM
#define ppFromVEX2of2(vex)
#define indexFromSIB(sib)
#define ALL_EA_BASES
#define mFromREX2(rex2)
#define vvvvFromXOP3of3(xop)
#define wFromXOP3of3(xop)
#define r2FromREX2(rex2)
#define oszcFromEVEX3of4(evex)
#define vvvvFromEVEX3of4(evex)
#define xFromREX(rex)
#define bFromREX(rex)
static void translateRegister(MCInst &mcInst, Reg reg)
translateRegister - Translates an internal register to the appropriate LLVM register,...
static bool isREX2(struct InternalInstruction *insn, uint8_t prefix)
static int getInstructionID(struct InternalInstruction *insn, const MCInstrInfo *mii)
static bool readOpcode(struct InternalInstruction *insn)
static MCDisassembler * createX86Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static bool translateMaskRegister(MCInst &mcInst, uint8_t maskRegNum)
translateMaskRegister - Translates a 3-bit mask register number to LLVM form, and appends it to an MC...
static bool translateDstIndex(MCInst &mcInst, InternalInstruction &insn)
translateDstIndex - Appends a destination index operand to an MCInst.
static void translateImmediate(MCInst &mcInst, uint64_t immediate, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateImmediate - Appends an immediate operand to an MCInst.
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Disassembler()
static int readOperands(struct InternalInstruction *insn)
static void translateFPRegister(MCInst &mcInst, uint8_t stackPos)
translateFPRegister - Translates a stack position on the FPU stack to its LLVM form,...
static bool is64Bit(const char *name)
static const uint8_t segmentRegnums[SEG_OVERRIDE_max]
static int readImmediate(struct InternalInstruction *insn, uint8_t size)
static int getInstructionIDWithAttrMask(uint16_t *instructionID, struct InternalInstruction *insn, uint16_t attrMask)
static int readSIB(struct InternalInstruction *insn)
static bool isREX(struct InternalInstruction *insn, uint8_t prefix)
static int readVVVV(struct InternalInstruction *insn)
static bool isNF(InternalInstruction *insn)
static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn)
translateSrcIndex - Appends a source index operand to an MCInst.
#define GENERIC_FIXUP_FUNC(name, base, prefix)
static int readMaskRegister(struct InternalInstruction *insn)
static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateRM - Translates an operand stored in the R/M (and possibly SIB) byte of an instruction to LL...
static InstrUID decode(OpcodeType type, InstructionContext insnContext, uint8_t opcode, uint8_t modRM)
static int readOpcodeRegister(struct InternalInstruction *insn, uint8_t size)
static int readDisplacement(struct InternalInstruction *insn)
static bool isCCMPOrCTEST(InternalInstruction *insn)
static int fixupReg(struct InternalInstruction *insn, const struct OperandSpecifier *op)
#define debug(s)
static int readModRM(struct InternalInstruction *insn)
static bool is16BitEquivalent(const char *orig, const char *equiv)
static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn, const MCDisassembler *Dis, bool ForceSIB=false)
translateRMMemory - Translates a memory operand stored in the Mod and R/M fields of an internal instr...
static bool translateInstruction(MCInst &target, InternalInstruction &source, const MCDisassembler *Dis)
translateInstruction - Translates an internal instruction and all its operands to an MCInst.
static bool translateRMRegister(MCInst &mcInst, InternalInstruction &insn)
translateRMRegister - Translates a register stored in the R/M field of the ModR/M byte to its LLVM eq...
static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand, InternalInstruction &insn, const MCDisassembler *Dis)
translateOperand - Translates an operand stored in an internal instruction to LLVM's format and appen...
static int readPrefixes(struct InternalInstruction *insn)
static bool peek(struct InternalInstruction *insn, uint8_t &byte)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
This class represents an Operation in the Expression.
Container class for subtarget features.
Context object for machine code objects.
Definition: MCContext.h:83
Superclass for all disassemblers.
bool tryAddingSymbolicOperand(MCInst &Inst, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) const
void tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) const
DecodeStatus
Ternary decode status.
virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const =0
Returns the disassembly of a single instruction.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getOpcode() const
Definition: MCInst.h:198
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
void setOpcode(unsigned Op)
Definition: MCInst.h:197
void clear()
Definition: MCInst.h:215
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
StringRef getName(unsigned Opcode) const
Returns the name for the instructions with the given opcode.
Definition: MCInstrInfo.h:70
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
Generic base class for all target subtargets.
const FeatureBitset & getFeatureBits() const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:131
Target - Wrapper for Target specific information.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ X86
Windows x64, Windows Itanium (IA-64)
EABase
All possible values of the base field for effective-address computations, a.k.a.
Reg
All possible values of the reg field in the ModR/M byte.
DisassemblerMode
Decoding mode for the Intel disassembler.
SIBBase
All possible values of the SIB base field.
SIBIndex
All possible values of the SIB index field.
@ IP_HAS_AD_SIZE
Definition: X86BaseInfo.h:54
@ IP_HAS_REPEAT
Definition: X86BaseInfo.h:56
@ IP_HAS_OP_SIZE
Definition: X86BaseInfo.h:53
@ IP_NO_PREFIX
Definition: X86BaseInfo.h:52
@ IP_HAS_REPEAT_NE
Definition: X86BaseInfo.h:55
NodeAddr< InstrNode * > Instr
Definition: RDFGraph.h:389
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
LLVM_ATTRIBUTE_ALWAYS_INLINE DynamicAPInt mod(const DynamicAPInt &LHS, const DynamicAPInt &RHS)
is always non-negative.
Definition: DynamicAPInt.h:382
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1680
Target & getTheX86_32Target()
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:125
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1856
Target & getTheX86_64Target()
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858
OpcodeDecision opcodeDecisions[IC_max]
uint32_t instructionIDs
ModRMDecision modRMDecisions[256]
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
The specification for how to extract and interpret a full instruction and its operands.
The x86 internal instruction, which is produced by the decoder.
The specification for how to extract and interpret one operand.