#include "ScheduleDAGSDNodes.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/Register.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGenTypes/MachineValueType.h"
#include "llvm/Config/llvm-config.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <cstdlib>
#include <iterator>
#include <limits>
#include <memory>
#include <utility>
#include <vector>

Macros
#define	DEBUG_TYPE "pre-RA-sched"

Functions
	STATISTIC (NumBacktracks, "Number of times scheduler backtracked")
	STATISTIC (NumUnfolds, "Number of nodes unfolded")
	STATISTIC (NumDups, "Number of duplicated nodes")
	STATISTIC (NumPRCopies, "Number of physical register copies")
static void	GetCostForDef (const ScheduleDAGSDNodes::RegDefIter &RegDefPos, const TargetLowering TLI, const TargetInstrInfo TII, const TargetRegisterInfo *TRI, unsigned &RegClass, unsigned &Cost, const MachineFunction &MF)
	GetCostForDef - Looks up the register class and cost for a given definition.
static bool	IsChainDependent (SDNode Outer, SDNode Inner, unsigned NestLevel, const TargetInstrInfo *TII)
	IsChainDependent - Test if Outer is reachable from Inner through chain dependencies.
static SDNode *	FindCallSeqStart (SDNode N, unsigned &NestLevel, unsigned &MaxNest, const TargetInstrInfo TII)
	FindCallSeqStart - Starting from the (lowered) CALLSEQ_END node, locate the corresponding (lowered) CALLSEQ_BEGIN node.
static void	resetVRegCycle (SUnit *SU)
static bool	isOperandOf (const SUnit SU, SDNode N)
static void	CheckForLiveRegDef (SUnit SU, MCRegister Reg, SUnit LiveRegDefs, SmallSet< unsigned, 4 > &RegAdded, SmallVectorImpl< unsigned > &LRegs, const TargetRegisterInfo TRI, const SDNode *Node=nullptr)
	CheckForLiveRegDef - Return true and update live register vector if the specified register def of the specified SUnit clobbers any "live" registers.
static void	CheckForLiveRegDefMasked (SUnit SU, const uint32_t RegMask, ArrayRef< SUnit * > LiveRegDefs, SmallSet< unsigned, 4 > &RegAdded, SmallVectorImpl< unsigned > &LRegs)
	CheckForLiveRegDefMasked - Check for any live physregs that are clobbered by RegMask, and add them to LRegs.
static const uint32_t *	getNodeRegMask (const SDNode *N)
	getNodeRegMask - Returns the register mask attached to an SDNode, if any.
static int	checkSpecialNodes (const SUnit left, const SUnit right)
static unsigned	CalcNodeSethiUllmanNumber (const SUnit *SU, std::vector< unsigned > &SUNumbers)
	CalcNodeSethiUllmanNumber - Compute Sethi Ullman number.
static unsigned	closestSucc (const SUnit *SU)
	closestSucc - Returns the scheduled cycle of the successor which is closest to the current cycle.
static unsigned	calcMaxScratches (const SUnit *SU)
	calcMaxScratches - Returns an cost estimate of the worse case requirement for scratch registers, i.e.
static bool	hasOnlyLiveInOpers (const SUnit *SU)
	hasOnlyLiveInOpers - Return true if SU has only value predecessors that are CopyFromReg from a virtual register.
static bool	hasOnlyLiveOutUses (const SUnit *SU)
	hasOnlyLiveOutUses - Return true if SU has only value successors that are CopyToReg to a virtual register.
static void	initVRegCycle (SUnit *SU)
static bool	hasVRegCycleUse (const SUnit *SU)
static bool	BUHasStall (SUnit SU, int Height, RegReductionPQBase SPQ)
static int	BUCompareLatency (SUnit left, SUnit right, bool checkPref, RegReductionPQBase *SPQ)
static bool	BURRSort (SUnit left, SUnit right, RegReductionPQBase *SPQ)
static bool	canEnableCoalescing (SUnit *SU)
static bool	canClobberReachingPhysRegUse (const SUnit DepSU, const SUnit SU, ScheduleDAGRRList scheduleDAG, const TargetInstrInfo TII, const TargetRegisterInfo *TRI)
	canClobberReachingPhysRegUse - True if SU would clobber one of it's successor's explicit physregs whose definition can reach DepSU.
static bool	canClobberPhysRegDefs (const SUnit SuccSU, const SUnit SU, const TargetInstrInfo TII, const TargetRegisterInfo TRI)
	canClobberPhysRegDefs - True if SU would clobber one of SuccSU's physical register defs.

Variables
static RegisterScheduler	burrListDAGScheduler ("list-burr", "Bottom-up register reduction list scheduling", createBURRListDAGScheduler)
static RegisterScheduler	sourceListDAGScheduler ("source", "Similar to list-burr but schedules in source " "order when possible", createSourceListDAGScheduler)
static RegisterScheduler	hybridListDAGScheduler ("list-hybrid", "Bottom-up register pressure aware list scheduling " "which tries to balance latency and register pressure", createHybridListDAGScheduler)
static RegisterScheduler	ILPListDAGScheduler ("list-ilp", "Bottom-up register pressure aware list scheduling " "which tries to balance ILP and register pressure", createILPListDAGScheduler)
static cl::opt< bool >	DisableSchedCycles ("disable-sched-cycles", cl::Hidden, cl::init(false), cl::desc("Disable cycle-level precision during preRA scheduling"))
static cl::opt< bool >	DisableSchedRegPressure ("disable-sched-reg-pressure", cl::Hidden, cl::init(false), cl::desc("Disable regpressure priority in sched=list-ilp"))
static cl::opt< bool >	DisableSchedLiveUses ("disable-sched-live-uses", cl::Hidden, cl::init(true), cl::desc("Disable live use priority in sched=list-ilp"))
static cl::opt< bool >	DisableSchedVRegCycle ("disable-sched-vrcycle", cl::Hidden, cl::init(false), cl::desc("Disable virtual register cycle interference checks"))
static cl::opt< bool >	DisableSchedPhysRegJoin ("disable-sched-physreg-join", cl::Hidden, cl::init(false), cl::desc("Disable physreg def-use affinity"))
static cl::opt< bool >	DisableSchedStalls ("disable-sched-stalls", cl::Hidden, cl::init(true), cl::desc("Disable no-stall priority in sched=list-ilp"))
static cl::opt< bool >	DisableSchedCriticalPath ("disable-sched-critical-path", cl::Hidden, cl::init(false), cl::desc("Disable critical path priority in sched=list-ilp"))
static cl::opt< bool >	DisableSchedHeight ("disable-sched-height", cl::Hidden, cl::init(false), cl::desc("Disable scheduled-height priority in sched=list-ilp"))
static cl::opt< bool >	Disable2AddrHack ("disable-2addr-hack", cl::Hidden, cl::init(true), cl::desc("Disable scheduler's two-address hack"))
static cl::opt< int >	MaxReorderWindow ("max-sched-reorder", cl::Hidden, cl::init(6), cl::desc("Number of instructions to allow ahead of the critical path " "in sched=list-ilp"))
static cl::opt< unsigned >	AvgIPC ("sched-avg-ipc", cl::Hidden, cl::init(1), cl::desc("Average inst/cycle when no target itinerary exists."))
static constexpr unsigned	RegSequenceCost = 1

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE "pre-RA-sched"

Definition at line 62 of file ScheduleDAGRRList.cpp.

Function Documentation

◆ BUCompareLatency()

int BUCompareLatency	(	SUnit *	left,
		SUnit *	right,
		bool	checkPref,
		RegReductionPQBase *	SPQ )

static

Definition at line 2458 of file ScheduleDAGRRList.cpp.

References BUHasStall(), llvm::dbgs(), llvm::SUnit::getDepth(), llvm::SUnit::getHeight(), hasVRegCycleUse(), llvm::Sched::ILP, llvm::SUnit::Latency, LLVM_DEBUG, llvm::SUnit::NodeNum, and llvm::SUnit::SchedulingPref.

Referenced by BURRSort().

◆ BUHasStall()

bool BUHasStall	(	SUnit *	SU,
		int	Height,
		RegReductionPQBase *	SPQ )

static

Definition at line 2448 of file ScheduleDAGRRList.cpp.

References llvm::ScheduleHazardRecognizer::NoHazard.

Referenced by BUCompareLatency().

◆ BURRSort()

bool BURRSort	(	SUnit *	left,
		SUnit *	right,
		RegReductionPQBase *	SPQ )

static

Definition at line 2509 of file ScheduleDAGRRList.cpp.

References assert(), BUCompareLatency(), calcMaxScratches(), closestSucc(), llvm::dbgs(), DisableSchedCycles, DisableSchedPhysRegJoin, llvm::SUnit::getDepth(), llvm::SUnit::getHeight(), llvm::SUnit::getNode(), llvm::SDNode::getNumValues(), llvm::SUnit::hasPhysRegDefs, llvm::SUnit::isCall, llvm::SUnit::isCallOp, LLVM_DEBUG, llvm::SUnit::NodeNum, and llvm::SUnit::NodeQueueId.

◆ calcMaxScratches()

unsigned calcMaxScratches ( const SUnit * SU )

static

calcMaxScratches - Returns an cost estimate of the worse case requirement for scratch registers, i.e.

number of data dependencies.

Definition at line 2332 of file ScheduleDAGRRList.cpp.

References llvm::SUnit::Preds.

Referenced by BURRSort().

◆ CalcNodeSethiUllmanNumber()

unsigned CalcNodeSethiUllmanNumber	(	const SUnit *	SU,
		std::vector< unsigned > &	SUNumbers )

static

CalcNodeSethiUllmanNumber - Compute Sethi Ullman number.

Smaller number is the higher priority.

Definition at line 1920 of file ScheduleDAGRRList.cpp.

References assert(), llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::SUnit::NodeNum, P, llvm::SmallVectorTemplateBase< T, bool >::pop_back(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ canClobberPhysRegDefs()

bool canClobberPhysRegDefs	(	const SUnit *	SuccSU,
		const SUnit *	SU,
		const TargetInstrInfo *	TII,
		const TargetRegisterInfo *	TRI )

static

canClobberPhysRegDefs - True if SU would clobber one of SuccSU's physical register defs.

Definition at line 2860 of file ScheduleDAGRRList.cpp.

References assert(), llvm::MachineOperand::clobbersPhysReg(), llvm::ArrayRef< T >::empty(), llvm::SDNode::getGluedNode(), llvm::SUnit::getNode(), getNodeRegMask(), N, Reg, TII, and TRI.

◆ canClobberReachingPhysRegUse()

bool canClobberReachingPhysRegUse	(	const SUnit *	DepSU,
		const SUnit *	SU,
		ScheduleDAGRRList *	scheduleDAG,
		const TargetInstrInfo *	TII,
		const TargetRegisterInfo *	TRI )

static

canClobberReachingPhysRegUse - True if SU would clobber one of it's successor's explicit physregs whose definition can reach DepSU.

i.e. DepSU should not be scheduled above SU.

Definition at line 2824 of file ScheduleDAGRRList.cpp.

References llvm::MachineOperand::clobbersPhysReg(), llvm::ArrayRef< T >::empty(), llvm::SDNode::getMachineOpcode(), llvm::SUnit::getNode(), getNodeRegMask(), llvm::SDep::getReg(), llvm::SDep::getSUnit(), llvm::SDep::isAssignedRegDep(), llvm::SUnit::Preds, llvm::SUnit::Succs, TII, and TRI.

◆ canEnableCoalescing()

bool canEnableCoalescing ( SUnit * SU )

static

Definition at line 2697 of file ScheduleDAGRRList.cpp.

References llvm::ISD::CopyToReg, llvm::SUnit::getNode(), llvm::SDNode::getOpcode(), llvm::SUnit::NumPreds, llvm::SUnit::NumSuccs, Opc, and llvm::ISD::TokenFactor.

◆ CheckForLiveRegDef()

void CheckForLiveRegDef	(	SUnit *	SU,
		MCRegister	Reg,
		SUnit **	LiveRegDefs,
		SmallSet< unsigned, 4 > &	RegAdded,
		SmallVectorImpl< unsigned > &	LRegs,
		const TargetRegisterInfo *	TRI,
		const SDNode *	Node = nullptr )

static

CheckForLiveRegDef - Return true and update live register vector if the specified register def of the specified SUnit clobbers any "live" registers.

Definition at line 1265 of file ScheduleDAGRRList.cpp.

References getNode(), llvm::SmallSet< T, N, C >::insert(), llvm::MCRegAliasIterator::isValid(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), Reg, and TRI.

◆ CheckForLiveRegDefMasked()

void CheckForLiveRegDefMasked	(	SUnit *	SU,
		const uint32_t *	RegMask,
		ArrayRef< SUnit * >	LiveRegDefs,
		SmallSet< unsigned, 4 > &	RegAdded,
		SmallVectorImpl< unsigned > &	LRegs )

static

CheckForLiveRegDefMasked - Check for any live physregs that are clobbered by RegMask, and add them to LRegs.

Definition at line 1291 of file ScheduleDAGRRList.cpp.

References llvm::MachineOperand::clobbersPhysReg(), llvm::SmallSet< T, N, C >::insert(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::ArrayRef< T >::size().

◆ checkSpecialNodes()

int checkSpecialNodes	(	const SUnit *	left,
		const SUnit *	right )

static

Definition at line 1909 of file ScheduleDAGRRList.cpp.

References llvm::SUnit::isScheduleLow.

◆ closestSucc()

unsigned closestSucc ( const SUnit * SU )

static

closestSucc - Returns the scheduled cycle of the successor which is closest to the current cycle.

Definition at line 2314 of file ScheduleDAGRRList.cpp.

References closestSucc(), llvm::ISD::CopyToReg, llvm::SUnit::getHeight(), llvm::SUnit::getNode(), llvm::SDNode::getOpcode(), llvm::SDep::getSUnit(), llvm::SDep::isCtrl(), and llvm::SUnit::Succs.

Referenced by BURRSort(), and closestSucc().

◆ FindCallSeqStart()

SDNode * FindCallSeqStart	(	SDNode *	N,
		unsigned &	NestLevel,
		unsigned &	MaxNest,
		const TargetInstrInfo *	TII )

static

FindCallSeqStart - Starting from the (lowered) CALLSEQ_END node, locate the corresponding (lowered) CALLSEQ_BEGIN node.

NestLevel and MaxNested are used in recursion to indcate the current level of nesting of CALLSEQ_BEGIN and CALLSEQ_END pairs, as well as the maximum level seen so far.

TODO: It would be better to give CALLSEQ_END an explicit operand to point to the corresponding CALLSEQ_BEGIN to avoid needing to search for it.

Definition at line 483 of file ScheduleDAGRRList.cpp.

References assert(), llvm::ISD::EntryToken, FindCallSeqStart(), N, TII, and llvm::ISD::TokenFactor.

Referenced by FindCallSeqStart().

◆ GetCostForDef()

void GetCostForDef	(	const ScheduleDAGSDNodes::RegDefIter &	RegDefPos,
		const TargetLowering *	TLI,
		const TargetInstrInfo *	TII,
		const TargetRegisterInfo *	TRI,
		unsigned &	RegClass,
		unsigned &	Cost,
		const MachineFunction &	MF )

static

GetCostForDef - Looks up the register class and cost for a given definition.

Typically this just means looking up the representative register class, but for untyped values (MVT::Untyped) it means inspecting the node's opcode to determine what register class is being generated.

Definition at line 302 of file ScheduleDAGRRList.cpp.

References assert(), llvm::cast(), llvm::ISD::CopyFromReg, llvm::MCRegisterClass::getID(), llvm::ScheduleDAGSDNodes::RegDefIter::GetIdx(), llvm::ScheduleDAGSDNodes::RegDefIter::GetNode(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetLoweringBase::getRepRegClassCostFor(), llvm::TargetLoweringBase::getRepRegClassFor(), llvm::ScheduleDAGSDNodes::RegDefIter::GetValue(), Reg, RegSequenceCost, TII, and TRI.

◆ getNodeRegMask()

const uint32_t * getNodeRegMask ( const SDNode * N )

static

getNodeRegMask - Returns the register mask attached to an SDNode, if any.

Definition at line 1306 of file ScheduleDAGRRList.cpp.

References llvm::dyn_cast(), and N.

Referenced by canClobberPhysRegDefs(), and canClobberReachingPhysRegUse().

◆ hasOnlyLiveInOpers()

bool hasOnlyLiveInOpers ( const SUnit * SU )

static

hasOnlyLiveInOpers - Return true if SU has only value predecessors that are CopyFromReg from a virtual register.

Definition at line 2343 of file ScheduleDAGRRList.cpp.

References llvm::cast(), llvm::ISD::CopyFromReg, llvm::SUnit::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SUnit::Preds, and Reg.

Referenced by initVRegCycle().

◆ hasOnlyLiveOutUses()

bool hasOnlyLiveOutUses ( const SUnit * SU )

static

hasOnlyLiveOutUses - Return true if SU has only value successors that are CopyToReg to a virtual register.

This SU def is probably a liveout and it has no other use. It should be scheduled closer to the terminator.

Definition at line 2365 of file ScheduleDAGRRList.cpp.

References llvm::cast(), llvm::ISD::CopyToReg, llvm::SUnit::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDep::getSUnit(), llvm::SDep::isCtrl(), Reg, and llvm::SUnit::Succs.

Referenced by initVRegCycle().

◆ hasVRegCycleUse()

bool hasVRegCycleUse ( const SUnit * SU )

static

Definition at line 2429 of file ScheduleDAGRRList.cpp.

References llvm::ISD::CopyFromReg, llvm::dbgs(), llvm::SUnit::isVRegCycle, LLVM_DEBUG, llvm::SUnit::NodeNum, and llvm::SUnit::Preds.

Referenced by BUCompareLatency().

◆ initVRegCycle()

void initVRegCycle ( SUnit * SU )

static

Definition at line 2393 of file ScheduleDAGRRList.cpp.

References llvm::dbgs(), DisableSchedVRegCycle, hasOnlyLiveInOpers(), hasOnlyLiveOutUses(), llvm::SUnit::isVRegCycle, LLVM_DEBUG, llvm::SUnit::NodeNum, and llvm::SUnit::Preds.

◆ IsChainDependent()

bool IsChainDependent	(	SDNode *	Outer,
		SDNode *	Inner,
		unsigned	NestLevel,
		const TargetInstrInfo *	TII )

static

IsChainDependent - Test if Outer is reachable from Inner through chain dependencies.

Definition at line 434 of file ScheduleDAGRRList.cpp.

References llvm::ISD::EntryToken, IsChainDependent(), N, TII, and llvm::ISD::TokenFactor.

Referenced by IsChainDependent().

◆ isOperandOf()

bool isOperandOf	(	const SUnit *	SU,
		SDNode *	N )

static

Definition at line 965 of file ScheduleDAGRRList.cpp.

References llvm::SDNode::getGluedNode(), llvm::SUnit::getNode(), and N.

◆ resetVRegCycle()

void resetVRegCycle ( SUnit * SU )

static

Definition at line 2412 of file ScheduleDAGRRList.cpp.

References assert(), llvm::ISD::CopyFromReg, llvm::SUnit::getNode(), llvm::SDNode::getOpcode(), llvm::SUnit::isVRegCycle, and llvm::SUnit::Preds.

◆ STATISTIC() [1/4]

STATISTIC	(	NumBacktracks	,
		"Number of times scheduler backtracked"	)

◆ STATISTIC() [2/4]

STATISTIC	(	NumDups	,
		"Number of duplicated nodes"	)

◆ STATISTIC() [3/4]

STATISTIC	(	NumPRCopies	,
		"Number of physical register copies"	)

◆ STATISTIC() [4/4]

STATISTIC	(	NumUnfolds	,
		"Number of nodes unfolded"	)

Variable Documentation

◆ AvgIPC

cl::opt< unsigned > AvgIPC("sched-avg-ipc", cl::Hidden, cl::init(1), cl::desc("Average inst/cycle when no target itinerary exists."))	(	"sched-avg-ipc"	,
		cl::Hidden	,
		cl::init(1)	,
		cl::desc("Average inst/cycle when no target itinerary exists.")	)

static

◆ burrListDAGScheduler

RegisterScheduler burrListDAGScheduler("list-burr", "Bottom-up register reduction list scheduling", createBURRListDAGScheduler)	(	"list-burr"	,
		"Bottom-up register reduction list scheduling"	,
		createBURRListDAGScheduler	)

static

◆ Disable2AddrHack

cl::opt< bool > Disable2AddrHack("disable-2addr-hack", cl::Hidden, cl::init(true), cl::desc("Disable scheduler's two-address hack"))	(	"disable-2addr-hack"	,
		cl::Hidden	,
		cl::init(true)	,
		cl::desc("Disable scheduler's two-address hack")	)

static

◆ DisableSchedCriticalPath

cl::opt< bool > DisableSchedCriticalPath("disable-sched-critical-path", cl::Hidden, cl::init(false), cl::desc("Disable critical path priority in sched=list-ilp"))	(	"disable-sched-critical-path"	,
		cl::Hidden	,
		cl::init(false)	,
		cl::desc("Disable critical path priority in sched=list-ilp")	)

static

◆ DisableSchedCycles

cl::opt< bool > DisableSchedCycles("disable-sched-cycles", cl::Hidden, cl::init(false), cl::desc("Disable cycle-level precision during preRA scheduling"))	(	"disable-sched-cycles"	,
		cl::Hidden	,
		cl::init(false)	,
		cl::desc("Disable cycle-level precision during preRA scheduling")	)

static

Referenced by BURRSort().

◆ DisableSchedHeight

cl::opt< bool > DisableSchedHeight("disable-sched-height", cl::Hidden, cl::init(false), cl::desc("Disable scheduled-height priority in sched=list-ilp"))	(	"disable-sched-height"	,
		cl::Hidden	,
		cl::init(false)	,
		cl::desc("Disable scheduled-height priority in sched=list-ilp")	)

static

◆ DisableSchedLiveUses

cl::opt< bool > DisableSchedLiveUses("disable-sched-live-uses", cl::Hidden, cl::init(true), cl::desc("Disable live use priority in sched=list-ilp"))	(	"disable-sched-live-uses"	,
		cl::Hidden	,
		cl::init(true)	,
		cl::desc("Disable live use priority in sched=list-ilp")	)

static

◆ DisableSchedPhysRegJoin

cl::opt< bool > DisableSchedPhysRegJoin("disable-sched-physreg-join", cl::Hidden, cl::init(false), cl::desc("Disable physreg def-use affinity"))	(	"disable-sched-physreg-join"	,
		cl::Hidden	,
		cl::init(false)	,
		cl::desc("Disable physreg def-use affinity")	)

static

Referenced by BURRSort().

◆ DisableSchedRegPressure

cl::opt< bool > DisableSchedRegPressure("disable-sched-reg-pressure", cl::Hidden, cl::init(false), cl::desc("Disable regpressure priority in sched=list-ilp"))	(	"disable-sched-reg-pressure"	,
		cl::Hidden	,
		cl::init(false)	,
		cl::desc("Disable regpressure priority in sched=list-ilp")	)

static

◆ DisableSchedStalls

cl::opt< bool > DisableSchedStalls("disable-sched-stalls", cl::Hidden, cl::init(true), cl::desc("Disable no-stall priority in sched=list-ilp"))	(	"disable-sched-stalls"	,
		cl::Hidden	,
		cl::init(true)	,
		cl::desc("Disable no-stall priority in sched=list-ilp")	)

static

◆ DisableSchedVRegCycle

cl::opt< bool > DisableSchedVRegCycle("disable-sched-vrcycle", cl::Hidden, cl::init(false), cl::desc("Disable virtual register cycle interference checks"))	(	"disable-sched-vrcycle"	,
		cl::Hidden	,
		cl::init(false)	,
		cl::desc("Disable virtual register cycle interference checks")	)

static

Referenced by initVRegCycle().

◆ hybridListDAGScheduler

RegisterScheduler hybridListDAGScheduler("list-hybrid", "Bottom-up register pressure aware list scheduling " "which tries to balance latency and register pressure", createHybridListDAGScheduler)	(	"list-hybrid"	,
		"Bottom-up register pressure aware list scheduling " "which tries to balance latency and register pressure"	,
		createHybridListDAGScheduler	)

static

◆ ILPListDAGScheduler

RegisterScheduler ILPListDAGScheduler("list-ilp", "Bottom-up register pressure aware list scheduling " "which tries to balance ILP and register pressure", createILPListDAGScheduler)	(	"list-ilp"	,
		"Bottom-up register pressure aware list scheduling " "which tries to balance ILP and register pressure"	,
		createILPListDAGScheduler	)

static

◆ MaxReorderWindow

cl::opt< int > MaxReorderWindow("max-sched-reorder", cl::Hidden, cl::init(6), cl::desc("Number of instructions to allow ahead of the critical path " "in sched=list-ilp"))	(	"max-sched-reorder"	,
		cl::Hidden	,
		cl::init(6)	,
		cl::desc("Number of instructions to allow ahead of the critical path " "in sched=list-ilp")	)

static

◆ RegSequenceCost

unsigned RegSequenceCost = 1

staticconstexpr

Definition at line 296 of file ScheduleDAGRRList.cpp.

Referenced by GetCostForDef().

◆ sourceListDAGScheduler

RegisterScheduler sourceListDAGScheduler("source", "Similar to list-burr but schedules in source " "order when possible", createSourceListDAGScheduler)	(	"source"	,
		"Similar to list-burr but schedules in source " "order when possible"	,
		createSourceListDAGScheduler	)

static

Macros

Functions

Variables

Macro Definition Documentation

◆ DEBUG_TYPE

Function Documentation

◆ BUCompareLatency()

◆ BUHasStall()

◆ BURRSort()

◆ calcMaxScratches()

◆ CalcNodeSethiUllmanNumber()

◆ canClobberPhysRegDefs()

◆ canClobberReachingPhysRegUse()

◆ canEnableCoalescing()

◆ CheckForLiveRegDef()

◆ CheckForLiveRegDefMasked()

◆ checkSpecialNodes()

◆ closestSucc()

◆ FindCallSeqStart()

◆ GetCostForDef()

◆ getNodeRegMask()

◆ hasOnlyLiveInOpers()

◆ hasOnlyLiveOutUses()

◆ hasVRegCycleUse()

◆ initVRegCycle()

◆ IsChainDependent()

◆ isOperandOf()

◆ resetVRegCycle()

◆ STATISTIC() [1/4]

◆ STATISTIC() [2/4]

◆ STATISTIC() [3/4]

◆ STATISTIC() [4/4]

Variable Documentation

◆ AvgIPC

◆ burrListDAGScheduler

◆ Disable2AddrHack

◆ DisableSchedCriticalPath

◆ DisableSchedCycles

◆ DisableSchedHeight

◆ DisableSchedLiveUses

◆ DisableSchedPhysRegJoin

◆ DisableSchedRegPressure

◆ DisableSchedStalls

◆ DisableSchedVRegCycle

◆ hybridListDAGScheduler

◆ ILPListDAGScheduler

◆ MaxReorderWindow

◆ RegSequenceCost

◆ sourceListDAGScheduler