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PPCInstrInfo.cpp
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00001 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the PowerPC implementation of the TargetInstrInfo class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "PPCInstrInfo.h"
00015 #include "MCTargetDesc/PPCPredicates.h"
00016 #include "PPC.h"
00017 #include "PPCHazardRecognizers.h"
00018 #include "PPCInstrBuilder.h"
00019 #include "PPCMachineFunctionInfo.h"
00020 #include "PPCTargetMachine.h"
00021 #include "llvm/ADT/STLExtras.h"
00022 #include "llvm/ADT/Statistic.h"
00023 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
00024 #include "llvm/CodeGen/MachineFrameInfo.h"
00025 #include "llvm/CodeGen/MachineFunctionPass.h"
00026 #include "llvm/CodeGen/MachineInstrBuilder.h"
00027 #include "llvm/CodeGen/MachineMemOperand.h"
00028 #include "llvm/CodeGen/MachineRegisterInfo.h"
00029 #include "llvm/CodeGen/PseudoSourceValue.h"
00030 #include "llvm/CodeGen/ScheduleDAG.h"
00031 #include "llvm/CodeGen/SlotIndexes.h"
00032 #include "llvm/CodeGen/StackMaps.h"
00033 #include "llvm/MC/MCAsmInfo.h"
00034 #include "llvm/MC/MCInst.h"
00035 #include "llvm/Support/CommandLine.h"
00036 #include "llvm/Support/Debug.h"
00037 #include "llvm/Support/ErrorHandling.h"
00038 #include "llvm/Support/TargetRegistry.h"
00039 #include "llvm/Support/raw_ostream.h"
00040 
00041 using namespace llvm;
00042 
00043 #define DEBUG_TYPE "ppc-instr-info"
00044 
00045 #define GET_INSTRMAP_INFO
00046 #define GET_INSTRINFO_CTOR_DTOR
00047 #include "PPCGenInstrInfo.inc"
00048 
00049 static cl::
00050 opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
00051             cl::desc("Disable analysis for CTR loops"));
00052 
00053 static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
00054 cl::desc("Disable compare instruction optimization"), cl::Hidden);
00055 
00056 static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
00057 cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
00058 cl::Hidden);
00059 
00060 static cl::opt<bool>
00061 UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
00062   cl::desc("Use the old (incorrect) instruction latency calculation"));
00063 
00064 // Pin the vtable to this file.
00065 void PPCInstrInfo::anchor() {}
00066 
00067 PPCInstrInfo::PPCInstrInfo(PPCSubtarget &STI)
00068     : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
00069       Subtarget(STI), RI(STI.getTargetMachine()) {}
00070 
00071 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
00072 /// this target when scheduling the DAG.
00073 ScheduleHazardRecognizer *
00074 PPCInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
00075                                            const ScheduleDAG *DAG) const {
00076   unsigned Directive =
00077       static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
00078   if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
00079       Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
00080     const InstrItineraryData *II =
00081         static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
00082     return new ScoreboardHazardRecognizer(II, DAG);
00083   }
00084 
00085   return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
00086 }
00087 
00088 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
00089 /// to use for this target when scheduling the DAG.
00090 ScheduleHazardRecognizer *
00091 PPCInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
00092                                                  const ScheduleDAG *DAG) const {
00093   unsigned Directive =
00094       DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
00095 
00096   if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
00097     return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
00098 
00099   // Most subtargets use a PPC970 recognizer.
00100   if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
00101       Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
00102     assert(DAG->TII && "No InstrInfo?");
00103 
00104     return new PPCHazardRecognizer970(*DAG);
00105   }
00106 
00107   return new ScoreboardHazardRecognizer(II, DAG);
00108 }
00109 
00110 unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
00111                                        const MachineInstr *MI,
00112                                        unsigned *PredCost) const {
00113   if (!ItinData || UseOldLatencyCalc)
00114     return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
00115 
00116   // The default implementation of getInstrLatency calls getStageLatency, but
00117   // getStageLatency does not do the right thing for us. While we have
00118   // itinerary, most cores are fully pipelined, and so the itineraries only
00119   // express the first part of the pipeline, not every stage. Instead, we need
00120   // to use the listed output operand cycle number (using operand 0 here, which
00121   // is an output).
00122 
00123   unsigned Latency = 1;
00124   unsigned DefClass = MI->getDesc().getSchedClass();
00125   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
00126     const MachineOperand &MO = MI->getOperand(i);
00127     if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
00128       continue;
00129 
00130     int Cycle = ItinData->getOperandCycle(DefClass, i);
00131     if (Cycle < 0)
00132       continue;
00133 
00134     Latency = std::max(Latency, (unsigned) Cycle);
00135   }
00136 
00137   return Latency;
00138 }
00139 
00140 int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
00141                                     const MachineInstr *DefMI, unsigned DefIdx,
00142                                     const MachineInstr *UseMI,
00143                                     unsigned UseIdx) const {
00144   int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
00145                                                    UseMI, UseIdx);
00146 
00147   if (!DefMI->getParent())
00148     return Latency;
00149 
00150   const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
00151   unsigned Reg = DefMO.getReg();
00152 
00153   bool IsRegCR;
00154   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
00155     const MachineRegisterInfo *MRI =
00156       &DefMI->getParent()->getParent()->getRegInfo();
00157     IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
00158               MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
00159   } else {
00160     IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
00161               PPC::CRBITRCRegClass.contains(Reg);
00162   }
00163 
00164   if (UseMI->isBranch() && IsRegCR) {
00165     if (Latency < 0)
00166       Latency = getInstrLatency(ItinData, DefMI);
00167 
00168     // On some cores, there is an additional delay between writing to a condition
00169     // register, and using it from a branch.
00170     unsigned Directive = Subtarget.getDarwinDirective();
00171     switch (Directive) {
00172     default: break;
00173     case PPC::DIR_7400:
00174     case PPC::DIR_750:
00175     case PPC::DIR_970:
00176     case PPC::DIR_E5500:
00177     case PPC::DIR_PWR4:
00178     case PPC::DIR_PWR5:
00179     case PPC::DIR_PWR5X:
00180     case PPC::DIR_PWR6:
00181     case PPC::DIR_PWR6X:
00182     case PPC::DIR_PWR7:
00183     case PPC::DIR_PWR8:
00184       Latency += 2;
00185       break;
00186     }
00187   }
00188 
00189   return Latency;
00190 }
00191 
00192 // This function does not list all associative and commutative operations, but
00193 // only those worth feeding through the machine combiner in an attempt to
00194 // reduce the critical path. Mostly, this means floating-point operations,
00195 // because they have high latencies (compared to other operations, such and
00196 // and/or, which are also associative and commutative, but have low latencies).
00197 bool PPCInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
00198   switch (Inst.getOpcode()) {
00199   // FP Add:
00200   case PPC::FADD:
00201   case PPC::FADDS:
00202   // FP Multiply:
00203   case PPC::FMUL:
00204   case PPC::FMULS:
00205   // Altivec Add:
00206   case PPC::VADDFP:
00207   // VSX Add:
00208   case PPC::XSADDDP:
00209   case PPC::XVADDDP:
00210   case PPC::XVADDSP:
00211   case PPC::XSADDSP:
00212   // VSX Multiply:
00213   case PPC::XSMULDP:
00214   case PPC::XVMULDP:
00215   case PPC::XVMULSP:
00216   case PPC::XSMULSP:
00217   // QPX Add:
00218   case PPC::QVFADD:
00219   case PPC::QVFADDS:
00220   case PPC::QVFADDSs:
00221   // QPX Multiply:
00222   case PPC::QVFMUL:
00223   case PPC::QVFMULS:
00224   case PPC::QVFMULSs:
00225     return true;
00226   default:
00227     return false;
00228   }
00229 }
00230 
00231 bool PPCInstrInfo::getMachineCombinerPatterns(
00232     MachineInstr &Root,
00233     SmallVectorImpl<MachineCombinerPattern> &Patterns) const {
00234   // Using the machine combiner in this way is potentially expensive, so
00235   // restrict to when aggressive optimizations are desired.
00236   if (Subtarget.getTargetMachine().getOptLevel() != CodeGenOpt::Aggressive)
00237     return false;
00238 
00239   // FP reassociation is only legal when we don't need strict IEEE semantics.
00240   if (!Root.getParent()->getParent()->getTarget().Options.UnsafeFPMath)
00241     return false;
00242 
00243   return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns);
00244 }
00245 
00246 // Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
00247 bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
00248                                          unsigned &SrcReg, unsigned &DstReg,
00249                                          unsigned &SubIdx) const {
00250   switch (MI.getOpcode()) {
00251   default: return false;
00252   case PPC::EXTSW:
00253   case PPC::EXTSW_32_64:
00254     SrcReg = MI.getOperand(1).getReg();
00255     DstReg = MI.getOperand(0).getReg();
00256     SubIdx = PPC::sub_32;
00257     return true;
00258   }
00259 }
00260 
00261 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
00262                                            int &FrameIndex) const {
00263   // Note: This list must be kept consistent with LoadRegFromStackSlot.
00264   switch (MI->getOpcode()) {
00265   default: break;
00266   case PPC::LD:
00267   case PPC::LWZ:
00268   case PPC::LFS:
00269   case PPC::LFD:
00270   case PPC::RESTORE_CR:
00271   case PPC::RESTORE_CRBIT:
00272   case PPC::LVX:
00273   case PPC::LXVD2X:
00274   case PPC::QVLFDX:
00275   case PPC::QVLFSXs:
00276   case PPC::QVLFDXb:
00277   case PPC::RESTORE_VRSAVE:
00278     // Check for the operands added by addFrameReference (the immediate is the
00279     // offset which defaults to 0).
00280     if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
00281         MI->getOperand(2).isFI()) {
00282       FrameIndex = MI->getOperand(2).getIndex();
00283       return MI->getOperand(0).getReg();
00284     }
00285     break;
00286   }
00287   return 0;
00288 }
00289 
00290 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
00291                                           int &FrameIndex) const {
00292   // Note: This list must be kept consistent with StoreRegToStackSlot.
00293   switch (MI->getOpcode()) {
00294   default: break;
00295   case PPC::STD:
00296   case PPC::STW:
00297   case PPC::STFS:
00298   case PPC::STFD:
00299   case PPC::SPILL_CR:
00300   case PPC::SPILL_CRBIT:
00301   case PPC::STVX:
00302   case PPC::STXVD2X:
00303   case PPC::QVSTFDX:
00304   case PPC::QVSTFSXs:
00305   case PPC::QVSTFDXb:
00306   case PPC::SPILL_VRSAVE:
00307     // Check for the operands added by addFrameReference (the immediate is the
00308     // offset which defaults to 0).
00309     if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
00310         MI->getOperand(2).isFI()) {
00311       FrameIndex = MI->getOperand(2).getIndex();
00312       return MI->getOperand(0).getReg();
00313     }
00314     break;
00315   }
00316   return 0;
00317 }
00318 
00319 MachineInstr *PPCInstrInfo::commuteInstructionImpl(MachineInstr *MI,
00320                                                    bool NewMI,
00321                                                    unsigned OpIdx1,
00322                                                    unsigned OpIdx2) const {
00323   MachineFunction &MF = *MI->getParent()->getParent();
00324 
00325   // Normal instructions can be commuted the obvious way.
00326   if (MI->getOpcode() != PPC::RLWIMI &&
00327       MI->getOpcode() != PPC::RLWIMIo)
00328     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
00329   // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
00330   // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
00331   // changing the relative order of the mask operands might change what happens
00332   // to the high-bits of the mask (and, thus, the result).
00333 
00334   // Cannot commute if it has a non-zero rotate count.
00335   if (MI->getOperand(3).getImm() != 0)
00336     return nullptr;
00337 
00338   // If we have a zero rotate count, we have:
00339   //   M = mask(MB,ME)
00340   //   Op0 = (Op1 & ~M) | (Op2 & M)
00341   // Change this to:
00342   //   M = mask((ME+1)&31, (MB-1)&31)
00343   //   Op0 = (Op2 & ~M) | (Op1 & M)
00344 
00345   // Swap op1/op2
00346   assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&
00347          "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.");
00348   unsigned Reg0 = MI->getOperand(0).getReg();
00349   unsigned Reg1 = MI->getOperand(1).getReg();
00350   unsigned Reg2 = MI->getOperand(2).getReg();
00351   unsigned SubReg1 = MI->getOperand(1).getSubReg();
00352   unsigned SubReg2 = MI->getOperand(2).getSubReg();
00353   bool Reg1IsKill = MI->getOperand(1).isKill();
00354   bool Reg2IsKill = MI->getOperand(2).isKill();
00355   bool ChangeReg0 = false;
00356   // If machine instrs are no longer in two-address forms, update
00357   // destination register as well.
00358   if (Reg0 == Reg1) {
00359     // Must be two address instruction!
00360     assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
00361            "Expecting a two-address instruction!");
00362     assert(MI->getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
00363     Reg2IsKill = false;
00364     ChangeReg0 = true;
00365   }
00366 
00367   // Masks.
00368   unsigned MB = MI->getOperand(4).getImm();
00369   unsigned ME = MI->getOperand(5).getImm();
00370 
00371   // We can't commute a trivial mask (there is no way to represent an all-zero
00372   // mask).
00373   if (MB == 0 && ME == 31)
00374     return nullptr;
00375 
00376   if (NewMI) {
00377     // Create a new instruction.
00378     unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
00379     bool Reg0IsDead = MI->getOperand(0).isDead();
00380     return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
00381       .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
00382       .addReg(Reg2, getKillRegState(Reg2IsKill))
00383       .addReg(Reg1, getKillRegState(Reg1IsKill))
00384       .addImm((ME+1) & 31)
00385       .addImm((MB-1) & 31);
00386   }
00387 
00388   if (ChangeReg0) {
00389     MI->getOperand(0).setReg(Reg2);
00390     MI->getOperand(0).setSubReg(SubReg2);
00391   }
00392   MI->getOperand(2).setReg(Reg1);
00393   MI->getOperand(1).setReg(Reg2);
00394   MI->getOperand(2).setSubReg(SubReg1);
00395   MI->getOperand(1).setSubReg(SubReg2);
00396   MI->getOperand(2).setIsKill(Reg1IsKill);
00397   MI->getOperand(1).setIsKill(Reg2IsKill);
00398 
00399   // Swap the mask around.
00400   MI->getOperand(4).setImm((ME+1) & 31);
00401   MI->getOperand(5).setImm((MB-1) & 31);
00402   return MI;
00403 }
00404 
00405 bool PPCInstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
00406                                          unsigned &SrcOpIdx2) const {
00407   // For VSX A-Type FMA instructions, it is the first two operands that can be
00408   // commuted, however, because the non-encoded tied input operand is listed
00409   // first, the operands to swap are actually the second and third.
00410 
00411   int AltOpc = PPC::getAltVSXFMAOpcode(MI->getOpcode());
00412   if (AltOpc == -1)
00413     return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
00414 
00415   // The commutable operand indices are 2 and 3. Return them in SrcOpIdx1
00416   // and SrcOpIdx2.
00417   return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
00418 }
00419 
00420 void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
00421                               MachineBasicBlock::iterator MI) const {
00422   // This function is used for scheduling, and the nop wanted here is the type
00423   // that terminates dispatch groups on the POWER cores.
00424   unsigned Directive = Subtarget.getDarwinDirective();
00425   unsigned Opcode;
00426   switch (Directive) {
00427   default:            Opcode = PPC::NOP; break;
00428   case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
00429   case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
00430   case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
00431   }
00432 
00433   DebugLoc DL;
00434   BuildMI(MBB, MI, DL, get(Opcode));
00435 }
00436 
00437 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
00438 void PPCInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
00439   NopInst.setOpcode(PPC::NOP);
00440 }
00441 
00442 // Branch analysis.
00443 // Note: If the condition register is set to CTR or CTR8 then this is a
00444 // BDNZ (imm == 1) or BDZ (imm == 0) branch.
00445 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
00446                                  MachineBasicBlock *&FBB,
00447                                  SmallVectorImpl<MachineOperand> &Cond,
00448                                  bool AllowModify) const {
00449   bool isPPC64 = Subtarget.isPPC64();
00450 
00451   // If the block has no terminators, it just falls into the block after it.
00452   MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
00453   if (I == MBB.end())
00454     return false;
00455 
00456   if (!isUnpredicatedTerminator(I))
00457     return false;
00458 
00459   // Get the last instruction in the block.
00460   MachineInstr *LastInst = I;
00461 
00462   // If there is only one terminator instruction, process it.
00463   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
00464     if (LastInst->getOpcode() == PPC::B) {
00465       if (!LastInst->getOperand(0).isMBB())
00466         return true;
00467       TBB = LastInst->getOperand(0).getMBB();
00468       return false;
00469     } else if (LastInst->getOpcode() == PPC::BCC) {
00470       if (!LastInst->getOperand(2).isMBB())
00471         return true;
00472       // Block ends with fall-through condbranch.
00473       TBB = LastInst->getOperand(2).getMBB();
00474       Cond.push_back(LastInst->getOperand(0));
00475       Cond.push_back(LastInst->getOperand(1));
00476       return false;
00477     } else if (LastInst->getOpcode() == PPC::BC) {
00478       if (!LastInst->getOperand(1).isMBB())
00479         return true;
00480       // Block ends with fall-through condbranch.
00481       TBB = LastInst->getOperand(1).getMBB();
00482       Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
00483       Cond.push_back(LastInst->getOperand(0));
00484       return false;
00485     } else if (LastInst->getOpcode() == PPC::BCn) {
00486       if (!LastInst->getOperand(1).isMBB())
00487         return true;
00488       // Block ends with fall-through condbranch.
00489       TBB = LastInst->getOperand(1).getMBB();
00490       Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
00491       Cond.push_back(LastInst->getOperand(0));
00492       return false;
00493     } else if (LastInst->getOpcode() == PPC::BDNZ8 ||
00494                LastInst->getOpcode() == PPC::BDNZ) {
00495       if (!LastInst->getOperand(0).isMBB())
00496         return true;
00497       if (DisableCTRLoopAnal)
00498         return true;
00499       TBB = LastInst->getOperand(0).getMBB();
00500       Cond.push_back(MachineOperand::CreateImm(1));
00501       Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
00502                                                true));
00503       return false;
00504     } else if (LastInst->getOpcode() == PPC::BDZ8 ||
00505                LastInst->getOpcode() == PPC::BDZ) {
00506       if (!LastInst->getOperand(0).isMBB())
00507         return true;
00508       if (DisableCTRLoopAnal)
00509         return true;
00510       TBB = LastInst->getOperand(0).getMBB();
00511       Cond.push_back(MachineOperand::CreateImm(0));
00512       Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
00513                                                true));
00514       return false;
00515     }
00516 
00517     // Otherwise, don't know what this is.
00518     return true;
00519   }
00520 
00521   // Get the instruction before it if it's a terminator.
00522   MachineInstr *SecondLastInst = I;
00523 
00524   // If there are three terminators, we don't know what sort of block this is.
00525   if (SecondLastInst && I != MBB.begin() &&
00526       isUnpredicatedTerminator(--I))
00527     return true;
00528 
00529   // If the block ends with PPC::B and PPC:BCC, handle it.
00530   if (SecondLastInst->getOpcode() == PPC::BCC &&
00531       LastInst->getOpcode() == PPC::B) {
00532     if (!SecondLastInst->getOperand(2).isMBB() ||
00533         !LastInst->getOperand(0).isMBB())
00534       return true;
00535     TBB =  SecondLastInst->getOperand(2).getMBB();
00536     Cond.push_back(SecondLastInst->getOperand(0));
00537     Cond.push_back(SecondLastInst->getOperand(1));
00538     FBB = LastInst->getOperand(0).getMBB();
00539     return false;
00540   } else if (SecondLastInst->getOpcode() == PPC::BC &&
00541       LastInst->getOpcode() == PPC::B) {
00542     if (!SecondLastInst->getOperand(1).isMBB() ||
00543         !LastInst->getOperand(0).isMBB())
00544       return true;
00545     TBB =  SecondLastInst->getOperand(1).getMBB();
00546     Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
00547     Cond.push_back(SecondLastInst->getOperand(0));
00548     FBB = LastInst->getOperand(0).getMBB();
00549     return false;
00550   } else if (SecondLastInst->getOpcode() == PPC::BCn &&
00551       LastInst->getOpcode() == PPC::B) {
00552     if (!SecondLastInst->getOperand(1).isMBB() ||
00553         !LastInst->getOperand(0).isMBB())
00554       return true;
00555     TBB =  SecondLastInst->getOperand(1).getMBB();
00556     Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
00557     Cond.push_back(SecondLastInst->getOperand(0));
00558     FBB = LastInst->getOperand(0).getMBB();
00559     return false;
00560   } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
00561               SecondLastInst->getOpcode() == PPC::BDNZ) &&
00562       LastInst->getOpcode() == PPC::B) {
00563     if (!SecondLastInst->getOperand(0).isMBB() ||
00564         !LastInst->getOperand(0).isMBB())
00565       return true;
00566     if (DisableCTRLoopAnal)
00567       return true;
00568     TBB = SecondLastInst->getOperand(0).getMBB();
00569     Cond.push_back(MachineOperand::CreateImm(1));
00570     Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
00571                                              true));
00572     FBB = LastInst->getOperand(0).getMBB();
00573     return false;
00574   } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
00575               SecondLastInst->getOpcode() == PPC::BDZ) &&
00576       LastInst->getOpcode() == PPC::B) {
00577     if (!SecondLastInst->getOperand(0).isMBB() ||
00578         !LastInst->getOperand(0).isMBB())
00579       return true;
00580     if (DisableCTRLoopAnal)
00581       return true;
00582     TBB = SecondLastInst->getOperand(0).getMBB();
00583     Cond.push_back(MachineOperand::CreateImm(0));
00584     Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
00585                                              true));
00586     FBB = LastInst->getOperand(0).getMBB();
00587     return false;
00588   }
00589 
00590   // If the block ends with two PPC:Bs, handle it.  The second one is not
00591   // executed, so remove it.
00592   if (SecondLastInst->getOpcode() == PPC::B &&
00593       LastInst->getOpcode() == PPC::B) {
00594     if (!SecondLastInst->getOperand(0).isMBB())
00595       return true;
00596     TBB = SecondLastInst->getOperand(0).getMBB();
00597     I = LastInst;
00598     if (AllowModify)
00599       I->eraseFromParent();
00600     return false;
00601   }
00602 
00603   // Otherwise, can't handle this.
00604   return true;
00605 }
00606 
00607 unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
00608   MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
00609   if (I == MBB.end())
00610     return 0;
00611 
00612   if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
00613       I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
00614       I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
00615       I->getOpcode() != PPC::BDZ8  && I->getOpcode() != PPC::BDZ)
00616     return 0;
00617 
00618   // Remove the branch.
00619   I->eraseFromParent();
00620 
00621   I = MBB.end();
00622 
00623   if (I == MBB.begin()) return 1;
00624   --I;
00625   if (I->getOpcode() != PPC::BCC &&
00626       I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
00627       I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
00628       I->getOpcode() != PPC::BDZ8  && I->getOpcode() != PPC::BDZ)
00629     return 1;
00630 
00631   // Remove the branch.
00632   I->eraseFromParent();
00633   return 2;
00634 }
00635 
00636 unsigned
00637 PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
00638                            MachineBasicBlock *FBB,
00639                            ArrayRef<MachineOperand> Cond,
00640                            DebugLoc DL) const {
00641   // Shouldn't be a fall through.
00642   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
00643   assert((Cond.size() == 2 || Cond.size() == 0) &&
00644          "PPC branch conditions have two components!");
00645 
00646   bool isPPC64 = Subtarget.isPPC64();
00647 
00648   // One-way branch.
00649   if (!FBB) {
00650     if (Cond.empty())   // Unconditional branch
00651       BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
00652     else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
00653       BuildMI(&MBB, DL, get(Cond[0].getImm() ?
00654                               (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
00655                               (isPPC64 ? PPC::BDZ8  : PPC::BDZ))).addMBB(TBB);
00656     else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
00657       BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB);
00658     else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
00659       BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB);
00660     else                // Conditional branch
00661       BuildMI(&MBB, DL, get(PPC::BCC))
00662         .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB);
00663     return 1;
00664   }
00665 
00666   // Two-way Conditional Branch.
00667   if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
00668     BuildMI(&MBB, DL, get(Cond[0].getImm() ?
00669                             (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
00670                             (isPPC64 ? PPC::BDZ8  : PPC::BDZ))).addMBB(TBB);
00671   else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
00672     BuildMI(&MBB, DL, get(PPC::BC)).addOperand(Cond[1]).addMBB(TBB);
00673   else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
00674     BuildMI(&MBB, DL, get(PPC::BCn)).addOperand(Cond[1]).addMBB(TBB);
00675   else
00676     BuildMI(&MBB, DL, get(PPC::BCC))
00677       .addImm(Cond[0].getImm()).addOperand(Cond[1]).addMBB(TBB);
00678   BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
00679   return 2;
00680 }
00681 
00682 // Select analysis.
00683 bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
00684                 ArrayRef<MachineOperand> Cond,
00685                 unsigned TrueReg, unsigned FalseReg,
00686                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
00687   if (!Subtarget.hasISEL())
00688     return false;
00689 
00690   if (Cond.size() != 2)
00691     return false;
00692 
00693   // If this is really a bdnz-like condition, then it cannot be turned into a
00694   // select.
00695   if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
00696     return false;
00697 
00698   // Check register classes.
00699   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
00700   const TargetRegisterClass *RC =
00701     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
00702   if (!RC)
00703     return false;
00704 
00705   // isel is for regular integer GPRs only.
00706   if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
00707       !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
00708       !PPC::G8RCRegClass.hasSubClassEq(RC) &&
00709       !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
00710     return false;
00711 
00712   // FIXME: These numbers are for the A2, how well they work for other cores is
00713   // an open question. On the A2, the isel instruction has a 2-cycle latency
00714   // but single-cycle throughput. These numbers are used in combination with
00715   // the MispredictPenalty setting from the active SchedMachineModel.
00716   CondCycles = 1;
00717   TrueCycles = 1;
00718   FalseCycles = 1;
00719 
00720   return true;
00721 }
00722 
00723 void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB,
00724                                 MachineBasicBlock::iterator MI, DebugLoc dl,
00725                                 unsigned DestReg, ArrayRef<MachineOperand> Cond,
00726                                 unsigned TrueReg, unsigned FalseReg) const {
00727   assert(Cond.size() == 2 &&
00728          "PPC branch conditions have two components!");
00729 
00730   assert(Subtarget.hasISEL() &&
00731          "Cannot insert select on target without ISEL support");
00732 
00733   // Get the register classes.
00734   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
00735   const TargetRegisterClass *RC =
00736     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
00737   assert(RC && "TrueReg and FalseReg must have overlapping register classes");
00738 
00739   bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
00740                  PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
00741   assert((Is64Bit ||
00742           PPC::GPRCRegClass.hasSubClassEq(RC) ||
00743           PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
00744          "isel is for regular integer GPRs only");
00745 
00746   unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
00747   auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm());
00748 
00749   unsigned SubIdx = 0;
00750   bool SwapOps = false;
00751   switch (SelectPred) {
00752   case PPC::PRED_EQ:
00753   case PPC::PRED_EQ_MINUS:
00754   case PPC::PRED_EQ_PLUS:
00755       SubIdx = PPC::sub_eq; SwapOps = false; break;
00756   case PPC::PRED_NE:
00757   case PPC::PRED_NE_MINUS:
00758   case PPC::PRED_NE_PLUS:
00759       SubIdx = PPC::sub_eq; SwapOps = true; break;
00760   case PPC::PRED_LT:
00761   case PPC::PRED_LT_MINUS:
00762   case PPC::PRED_LT_PLUS:
00763       SubIdx = PPC::sub_lt; SwapOps = false; break;
00764   case PPC::PRED_GE:
00765   case PPC::PRED_GE_MINUS:
00766   case PPC::PRED_GE_PLUS:
00767       SubIdx = PPC::sub_lt; SwapOps = true; break;
00768   case PPC::PRED_GT:
00769   case PPC::PRED_GT_MINUS:
00770   case PPC::PRED_GT_PLUS:
00771       SubIdx = PPC::sub_gt; SwapOps = false; break;
00772   case PPC::PRED_LE:
00773   case PPC::PRED_LE_MINUS:
00774   case PPC::PRED_LE_PLUS:
00775       SubIdx = PPC::sub_gt; SwapOps = true; break;
00776   case PPC::PRED_UN:
00777   case PPC::PRED_UN_MINUS:
00778   case PPC::PRED_UN_PLUS:
00779       SubIdx = PPC::sub_un; SwapOps = false; break;
00780   case PPC::PRED_NU:
00781   case PPC::PRED_NU_MINUS:
00782   case PPC::PRED_NU_PLUS:
00783       SubIdx = PPC::sub_un; SwapOps = true; break;
00784   case PPC::PRED_BIT_SET:   SubIdx = 0; SwapOps = false; break;
00785   case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
00786   }
00787 
00788   unsigned FirstReg =  SwapOps ? FalseReg : TrueReg,
00789            SecondReg = SwapOps ? TrueReg  : FalseReg;
00790 
00791   // The first input register of isel cannot be r0. If it is a member
00792   // of a register class that can be r0, then copy it first (the
00793   // register allocator should eliminate the copy).
00794   if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
00795       MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
00796     const TargetRegisterClass *FirstRC =
00797       MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
00798         &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
00799     unsigned OldFirstReg = FirstReg;
00800     FirstReg = MRI.createVirtualRegister(FirstRC);
00801     BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
00802       .addReg(OldFirstReg);
00803   }
00804 
00805   BuildMI(MBB, MI, dl, get(OpCode), DestReg)
00806     .addReg(FirstReg).addReg(SecondReg)
00807     .addReg(Cond[1].getReg(), 0, SubIdx);
00808 }
00809 
00810 static unsigned getCRBitValue(unsigned CRBit) {
00811   unsigned Ret = 4;
00812   if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
00813       CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
00814       CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
00815       CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
00816     Ret = 3;
00817   if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
00818       CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
00819       CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
00820       CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
00821     Ret = 2;
00822   if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
00823       CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
00824       CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
00825       CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
00826     Ret = 1;
00827   if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
00828       CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
00829       CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
00830       CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
00831     Ret = 0;
00832 
00833   assert(Ret != 4 && "Invalid CR bit register");
00834   return Ret;
00835 }
00836 
00837 void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
00838                                MachineBasicBlock::iterator I, DebugLoc DL,
00839                                unsigned DestReg, unsigned SrcReg,
00840                                bool KillSrc) const {
00841   // We can end up with self copies and similar things as a result of VSX copy
00842   // legalization. Promote them here.
00843   const TargetRegisterInfo *TRI = &getRegisterInfo();
00844   if (PPC::F8RCRegClass.contains(DestReg) &&
00845       PPC::VSRCRegClass.contains(SrcReg)) {
00846     unsigned SuperReg =
00847       TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
00848 
00849     if (VSXSelfCopyCrash && SrcReg == SuperReg)
00850       llvm_unreachable("nop VSX copy");
00851 
00852     DestReg = SuperReg;
00853   } else if (PPC::VRRCRegClass.contains(DestReg) &&
00854              PPC::VSRCRegClass.contains(SrcReg)) {
00855     unsigned SuperReg =
00856       TRI->getMatchingSuperReg(DestReg, PPC::sub_128, &PPC::VSRCRegClass);
00857 
00858     if (VSXSelfCopyCrash && SrcReg == SuperReg)
00859       llvm_unreachable("nop VSX copy");
00860 
00861     DestReg = SuperReg;
00862   } else if (PPC::F8RCRegClass.contains(SrcReg) &&
00863              PPC::VSRCRegClass.contains(DestReg)) {
00864     unsigned SuperReg =
00865       TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
00866 
00867     if (VSXSelfCopyCrash && DestReg == SuperReg)
00868       llvm_unreachable("nop VSX copy");
00869 
00870     SrcReg = SuperReg;
00871   } else if (PPC::VRRCRegClass.contains(SrcReg) &&
00872              PPC::VSRCRegClass.contains(DestReg)) {
00873     unsigned SuperReg =
00874       TRI->getMatchingSuperReg(SrcReg, PPC::sub_128, &PPC::VSRCRegClass);
00875 
00876     if (VSXSelfCopyCrash && DestReg == SuperReg)
00877       llvm_unreachable("nop VSX copy");
00878 
00879     SrcReg = SuperReg;
00880   }
00881 
00882   // Different class register copy
00883   if (PPC::CRBITRCRegClass.contains(SrcReg) &&
00884       PPC::GPRCRegClass.contains(DestReg)) {
00885     unsigned CRReg = getCRFromCRBit(SrcReg);
00886     BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg)
00887        .addReg(CRReg), getKillRegState(KillSrc);
00888     // Rotate the CR bit in the CR fields to be the least significant bit and
00889     // then mask with 0x1 (MB = ME = 31).
00890     BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
00891        .addReg(DestReg, RegState::Kill)
00892        .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
00893        .addImm(31)
00894        .addImm(31);
00895     return;
00896   } else if (PPC::CRRCRegClass.contains(SrcReg) &&
00897       PPC::G8RCRegClass.contains(DestReg)) {
00898     BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg)
00899        .addReg(SrcReg), getKillRegState(KillSrc);
00900     return;
00901   } else if (PPC::CRRCRegClass.contains(SrcReg) &&
00902       PPC::GPRCRegClass.contains(DestReg)) {
00903     BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg)
00904        .addReg(SrcReg), getKillRegState(KillSrc);
00905     return;
00906    }
00907 
00908   unsigned Opc;
00909   if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
00910     Opc = PPC::OR;
00911   else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
00912     Opc = PPC::OR8;
00913   else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
00914     Opc = PPC::FMR;
00915   else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
00916     Opc = PPC::MCRF;
00917   else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
00918     Opc = PPC::VOR;
00919   else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
00920     // There are two different ways this can be done:
00921     //   1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
00922     //      issue in VSU pipeline 0.
00923     //   2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
00924     //      can go to either pipeline.
00925     // We'll always use xxlor here, because in practically all cases where
00926     // copies are generated, they are close enough to some use that the
00927     // lower-latency form is preferable.
00928     Opc = PPC::XXLOR;
00929   else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
00930            PPC::VSSRCRegClass.contains(DestReg, SrcReg))
00931     Opc = PPC::XXLORf;
00932   else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
00933     Opc = PPC::QVFMR;
00934   else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
00935     Opc = PPC::QVFMRs;
00936   else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
00937     Opc = PPC::QVFMRb;
00938   else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
00939     Opc = PPC::CROR;
00940   else
00941     llvm_unreachable("Impossible reg-to-reg copy");
00942 
00943   const MCInstrDesc &MCID = get(Opc);
00944   if (MCID.getNumOperands() == 3)
00945     BuildMI(MBB, I, DL, MCID, DestReg)
00946       .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
00947   else
00948     BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
00949 }
00950 
00951 // This function returns true if a CR spill is necessary and false otherwise.
00952 bool
00953 PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
00954                                   unsigned SrcReg, bool isKill,
00955                                   int FrameIdx,
00956                                   const TargetRegisterClass *RC,
00957                                   SmallVectorImpl<MachineInstr*> &NewMIs,
00958                                   bool &NonRI, bool &SpillsVRS) const{
00959   // Note: If additional store instructions are added here,
00960   // update isStoreToStackSlot.
00961 
00962   DebugLoc DL;
00963   if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
00964       PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
00965     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
00966                                        .addReg(SrcReg,
00967                                                getKillRegState(isKill)),
00968                                        FrameIdx));
00969   } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
00970              PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
00971     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
00972                                        .addReg(SrcReg,
00973                                                getKillRegState(isKill)),
00974                                        FrameIdx));
00975   } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
00976     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
00977                                        .addReg(SrcReg,
00978                                                getKillRegState(isKill)),
00979                                        FrameIdx));
00980   } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
00981     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
00982                                        .addReg(SrcReg,
00983                                                getKillRegState(isKill)),
00984                                        FrameIdx));
00985   } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
00986     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
00987                                        .addReg(SrcReg,
00988                                                getKillRegState(isKill)),
00989                                        FrameIdx));
00990     return true;
00991   } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
00992     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CRBIT))
00993                                        .addReg(SrcReg,
00994                                                getKillRegState(isKill)),
00995                                        FrameIdx));
00996     return true;
00997   } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
00998     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
00999                                        .addReg(SrcReg,
01000                                                getKillRegState(isKill)),
01001                                        FrameIdx));
01002     NonRI = true;
01003   } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
01004     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXVD2X))
01005                                        .addReg(SrcReg,
01006                                                getKillRegState(isKill)),
01007                                        FrameIdx));
01008     NonRI = true;
01009   } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
01010     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSDX))
01011                                        .addReg(SrcReg,
01012                                                getKillRegState(isKill)),
01013                                        FrameIdx));
01014     NonRI = true;
01015   } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
01016     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSSPX))
01017                                        .addReg(SrcReg,
01018                                                getKillRegState(isKill)),
01019                                        FrameIdx));
01020     NonRI = true;
01021   } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
01022     assert(Subtarget.isDarwin() &&
01023            "VRSAVE only needs spill/restore on Darwin");
01024     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE))
01025                                        .addReg(SrcReg,
01026                                                getKillRegState(isKill)),
01027                                        FrameIdx));
01028     SpillsVRS = true;
01029   } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
01030     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDX))
01031                                        .addReg(SrcReg,
01032                                                getKillRegState(isKill)),
01033                                        FrameIdx));
01034     NonRI = true;
01035   } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
01036     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFSXs))
01037                                        .addReg(SrcReg,
01038                                                getKillRegState(isKill)),
01039                                        FrameIdx));
01040     NonRI = true;
01041   } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
01042     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVSTFDXb))
01043                                        .addReg(SrcReg,
01044                                                getKillRegState(isKill)),
01045                                        FrameIdx));
01046     NonRI = true;
01047   } else {
01048     llvm_unreachable("Unknown regclass!");
01049   }
01050 
01051   return false;
01052 }
01053 
01054 void
01055 PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
01056                                   MachineBasicBlock::iterator MI,
01057                                   unsigned SrcReg, bool isKill, int FrameIdx,
01058                                   const TargetRegisterClass *RC,
01059                                   const TargetRegisterInfo *TRI) const {
01060   MachineFunction &MF = *MBB.getParent();
01061   SmallVector<MachineInstr*, 4> NewMIs;
01062 
01063   PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
01064   FuncInfo->setHasSpills();
01065 
01066   bool NonRI = false, SpillsVRS = false;
01067   if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
01068                           NonRI, SpillsVRS))
01069     FuncInfo->setSpillsCR();
01070 
01071   if (SpillsVRS)
01072     FuncInfo->setSpillsVRSAVE();
01073 
01074   if (NonRI)
01075     FuncInfo->setHasNonRISpills();
01076 
01077   for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
01078     MBB.insert(MI, NewMIs[i]);
01079 
01080   const MachineFrameInfo &MFI = *MF.getFrameInfo();
01081   MachineMemOperand *MMO = MF.getMachineMemOperand(
01082       MachinePointerInfo::getFixedStack(MF, FrameIdx),
01083       MachineMemOperand::MOStore, MFI.getObjectSize(FrameIdx),
01084       MFI.getObjectAlignment(FrameIdx));
01085   NewMIs.back()->addMemOperand(MF, MMO);
01086 }
01087 
01088 bool
01089 PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
01090                                    unsigned DestReg, int FrameIdx,
01091                                    const TargetRegisterClass *RC,
01092                                    SmallVectorImpl<MachineInstr*> &NewMIs,
01093                                    bool &NonRI, bool &SpillsVRS) const{
01094   // Note: If additional load instructions are added here,
01095   // update isLoadFromStackSlot.
01096 
01097   if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
01098       PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
01099     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
01100                                                DestReg), FrameIdx));
01101   } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
01102              PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
01103     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
01104                                        FrameIdx));
01105   } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
01106     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
01107                                        FrameIdx));
01108   } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
01109     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
01110                                        FrameIdx));
01111   } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
01112     NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
01113                                                get(PPC::RESTORE_CR), DestReg),
01114                                        FrameIdx));
01115     return true;
01116   } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
01117     NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
01118                                                get(PPC::RESTORE_CRBIT), DestReg),
01119                                        FrameIdx));
01120     return true;
01121   } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
01122     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
01123                                        FrameIdx));
01124     NonRI = true;
01125   } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
01126     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXVD2X), DestReg),
01127                                        FrameIdx));
01128     NonRI = true;
01129   } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
01130     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSDX), DestReg),
01131                                        FrameIdx));
01132     NonRI = true;
01133   } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
01134     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LXSSPX), DestReg),
01135                                        FrameIdx));
01136     NonRI = true;
01137   } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
01138     assert(Subtarget.isDarwin() &&
01139            "VRSAVE only needs spill/restore on Darwin");
01140     NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
01141                                                get(PPC::RESTORE_VRSAVE),
01142                                                DestReg),
01143                                        FrameIdx));
01144     SpillsVRS = true;
01145   } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
01146     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDX), DestReg),
01147                                        FrameIdx));
01148     NonRI = true;
01149   } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
01150     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFSXs), DestReg),
01151                                        FrameIdx));
01152     NonRI = true;
01153   } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
01154     NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::QVLFDXb), DestReg),
01155                                        FrameIdx));
01156     NonRI = true;
01157   } else {
01158     llvm_unreachable("Unknown regclass!");
01159   }
01160 
01161   return false;
01162 }
01163 
01164 void
01165 PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
01166                                    MachineBasicBlock::iterator MI,
01167                                    unsigned DestReg, int FrameIdx,
01168                                    const TargetRegisterClass *RC,
01169                                    const TargetRegisterInfo *TRI) const {
01170   MachineFunction &MF = *MBB.getParent();
01171   SmallVector<MachineInstr*, 4> NewMIs;
01172   DebugLoc DL;
01173   if (MI != MBB.end()) DL = MI->getDebugLoc();
01174 
01175   PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
01176   FuncInfo->setHasSpills();
01177 
01178   bool NonRI = false, SpillsVRS = false;
01179   if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
01180                            NonRI, SpillsVRS))
01181     FuncInfo->setSpillsCR();
01182 
01183   if (SpillsVRS)
01184     FuncInfo->setSpillsVRSAVE();
01185 
01186   if (NonRI)
01187     FuncInfo->setHasNonRISpills();
01188 
01189   for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
01190     MBB.insert(MI, NewMIs[i]);
01191 
01192   const MachineFrameInfo &MFI = *MF.getFrameInfo();
01193   MachineMemOperand *MMO = MF.getMachineMemOperand(
01194       MachinePointerInfo::getFixedStack(MF, FrameIdx),
01195       MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIdx),
01196       MFI.getObjectAlignment(FrameIdx));
01197   NewMIs.back()->addMemOperand(MF, MMO);
01198 }
01199 
01200 bool PPCInstrInfo::
01201 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
01202   assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
01203   if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
01204     Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
01205   else
01206     // Leave the CR# the same, but invert the condition.
01207     Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
01208   return false;
01209 }
01210 
01211 bool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
01212                              unsigned Reg, MachineRegisterInfo *MRI) const {
01213   // For some instructions, it is legal to fold ZERO into the RA register field.
01214   // A zero immediate should always be loaded with a single li.
01215   unsigned DefOpc = DefMI->getOpcode();
01216   if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
01217     return false;
01218   if (!DefMI->getOperand(1).isImm())
01219     return false;
01220   if (DefMI->getOperand(1).getImm() != 0)
01221     return false;
01222 
01223   // Note that we cannot here invert the arguments of an isel in order to fold
01224   // a ZERO into what is presented as the second argument. All we have here
01225   // is the condition bit, and that might come from a CR-logical bit operation.
01226 
01227   const MCInstrDesc &UseMCID = UseMI->getDesc();
01228 
01229   // Only fold into real machine instructions.
01230   if (UseMCID.isPseudo())
01231     return false;
01232 
01233   unsigned UseIdx;
01234   for (UseIdx = 0; UseIdx < UseMI->getNumOperands(); ++UseIdx)
01235     if (UseMI->getOperand(UseIdx).isReg() &&
01236         UseMI->getOperand(UseIdx).getReg() == Reg)
01237       break;
01238 
01239   assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI");
01240   assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg");
01241 
01242   const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
01243 
01244   // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
01245   // register (which might also be specified as a pointer class kind).
01246   if (UseInfo->isLookupPtrRegClass()) {
01247     if (UseInfo->RegClass /* Kind */ != 1)
01248       return false;
01249   } else {
01250     if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
01251         UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
01252       return false;
01253   }
01254 
01255   // Make sure this is not tied to an output register (or otherwise
01256   // constrained). This is true for ST?UX registers, for example, which
01257   // are tied to their output registers.
01258   if (UseInfo->Constraints != 0)
01259     return false;
01260 
01261   unsigned ZeroReg;
01262   if (UseInfo->isLookupPtrRegClass()) {
01263     bool isPPC64 = Subtarget.isPPC64();
01264     ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
01265   } else {
01266     ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
01267               PPC::ZERO8 : PPC::ZERO;
01268   }
01269 
01270   bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
01271   UseMI->getOperand(UseIdx).setReg(ZeroReg);
01272 
01273   if (DeleteDef)
01274     DefMI->eraseFromParent();
01275 
01276   return true;
01277 }
01278 
01279 static bool MBBDefinesCTR(MachineBasicBlock &MBB) {
01280   for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
01281        I != IE; ++I)
01282     if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
01283       return true;
01284   return false;
01285 }
01286 
01287 // We should make sure that, if we're going to predicate both sides of a
01288 // condition (a diamond), that both sides don't define the counter register. We
01289 // can predicate counter-decrement-based branches, but while that predicates
01290 // the branching, it does not predicate the counter decrement. If we tried to
01291 // merge the triangle into one predicated block, we'd decrement the counter
01292 // twice.
01293 bool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
01294                      unsigned NumT, unsigned ExtraT,
01295                      MachineBasicBlock &FMBB,
01296                      unsigned NumF, unsigned ExtraF,
01297                      BranchProbability Probability) const {
01298   return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
01299 }
01300 
01301 
01302 bool PPCInstrInfo::isPredicated(const MachineInstr *MI) const {
01303   // The predicated branches are identified by their type, not really by the
01304   // explicit presence of a predicate. Furthermore, some of them can be
01305   // predicated more than once. Because if conversion won't try to predicate
01306   // any instruction which already claims to be predicated (by returning true
01307   // here), always return false. In doing so, we let isPredicable() be the
01308   // final word on whether not the instruction can be (further) predicated.
01309 
01310   return false;
01311 }
01312 
01313 bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
01314   if (!MI->isTerminator())
01315     return false;
01316 
01317   // Conditional branch is a special case.
01318   if (MI->isBranch() && !MI->isBarrier())
01319     return true;
01320 
01321   return !isPredicated(MI);
01322 }
01323 
01324 bool PPCInstrInfo::PredicateInstruction(MachineInstr *MI,
01325                                         ArrayRef<MachineOperand> Pred) const {
01326   unsigned OpC = MI->getOpcode();
01327   if (OpC == PPC::BLR || OpC == PPC::BLR8) {
01328     if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
01329       bool isPPC64 = Subtarget.isPPC64();
01330       MI->setDesc(get(Pred[0].getImm() ?
01331                       (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) :
01332                       (isPPC64 ? PPC::BDZLR8  : PPC::BDZLR)));
01333     } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
01334       MI->setDesc(get(PPC::BCLR));
01335       MachineInstrBuilder(*MI->getParent()->getParent(), MI)
01336         .addReg(Pred[1].getReg());
01337     } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
01338       MI->setDesc(get(PPC::BCLRn));
01339       MachineInstrBuilder(*MI->getParent()->getParent(), MI)
01340         .addReg(Pred[1].getReg());
01341     } else {
01342       MI->setDesc(get(PPC::BCCLR));
01343       MachineInstrBuilder(*MI->getParent()->getParent(), MI)
01344         .addImm(Pred[0].getImm())
01345         .addReg(Pred[1].getReg());
01346     }
01347 
01348     return true;
01349   } else if (OpC == PPC::B) {
01350     if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
01351       bool isPPC64 = Subtarget.isPPC64();
01352       MI->setDesc(get(Pred[0].getImm() ?
01353                       (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
01354                       (isPPC64 ? PPC::BDZ8  : PPC::BDZ)));
01355     } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
01356       MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
01357       MI->RemoveOperand(0);
01358 
01359       MI->setDesc(get(PPC::BC));
01360       MachineInstrBuilder(*MI->getParent()->getParent(), MI)
01361         .addReg(Pred[1].getReg())
01362         .addMBB(MBB);
01363     } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
01364       MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
01365       MI->RemoveOperand(0);
01366 
01367       MI->setDesc(get(PPC::BCn));
01368       MachineInstrBuilder(*MI->getParent()->getParent(), MI)
01369         .addReg(Pred[1].getReg())
01370         .addMBB(MBB);
01371     } else {
01372       MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
01373       MI->RemoveOperand(0);
01374 
01375       MI->setDesc(get(PPC::BCC));
01376       MachineInstrBuilder(*MI->getParent()->getParent(), MI)
01377         .addImm(Pred[0].getImm())
01378         .addReg(Pred[1].getReg())
01379         .addMBB(MBB);
01380     }
01381 
01382     return true;
01383   } else if (OpC == PPC::BCTR  || OpC == PPC::BCTR8 ||
01384              OpC == PPC::BCTRL || OpC == PPC::BCTRL8) {
01385     if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
01386       llvm_unreachable("Cannot predicate bctr[l] on the ctr register");
01387 
01388     bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
01389     bool isPPC64 = Subtarget.isPPC64();
01390 
01391     if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
01392       MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) :
01393                                 (setLR ? PPC::BCCTRL  : PPC::BCCTR)));
01394       MachineInstrBuilder(*MI->getParent()->getParent(), MI)
01395         .addReg(Pred[1].getReg());
01396       return true;
01397     } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
01398       MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) :
01399                                 (setLR ? PPC::BCCTRLn  : PPC::BCCTRn)));
01400       MachineInstrBuilder(*MI->getParent()->getParent(), MI)
01401         .addReg(Pred[1].getReg());
01402       return true;
01403     }
01404 
01405     MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8) :
01406                               (setLR ? PPC::BCCCTRL  : PPC::BCCCTR)));
01407     MachineInstrBuilder(*MI->getParent()->getParent(), MI)
01408       .addImm(Pred[0].getImm())
01409       .addReg(Pred[1].getReg());
01410     return true;
01411   }
01412 
01413   return false;
01414 }
01415 
01416 bool PPCInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
01417                                      ArrayRef<MachineOperand> Pred2) const {
01418   assert(Pred1.size() == 2 && "Invalid PPC first predicate");
01419   assert(Pred2.size() == 2 && "Invalid PPC second predicate");
01420 
01421   if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
01422     return false;
01423   if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
01424     return false;
01425 
01426   // P1 can only subsume P2 if they test the same condition register.
01427   if (Pred1[1].getReg() != Pred2[1].getReg())
01428     return false;
01429 
01430   PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
01431   PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
01432 
01433   if (P1 == P2)
01434     return true;
01435 
01436   // Does P1 subsume P2, e.g. GE subsumes GT.
01437   if (P1 == PPC::PRED_LE &&
01438       (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
01439     return true;
01440   if (P1 == PPC::PRED_GE &&
01441       (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
01442     return true;
01443 
01444   return false;
01445 }
01446 
01447 bool PPCInstrInfo::DefinesPredicate(MachineInstr *MI,
01448                                     std::vector<MachineOperand> &Pred) const {
01449   // Note: At the present time, the contents of Pred from this function is
01450   // unused by IfConversion. This implementation follows ARM by pushing the
01451   // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
01452   // predicate, instructions defining CTR or CTR8 are also included as
01453   // predicate-defining instructions.
01454 
01455   const TargetRegisterClass *RCs[] =
01456     { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
01457       &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
01458 
01459   bool Found = false;
01460   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
01461     const MachineOperand &MO = MI->getOperand(i);
01462     for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
01463       const TargetRegisterClass *RC = RCs[c];
01464       if (MO.isReg()) {
01465         if (MO.isDef() && RC->contains(MO.getReg())) {
01466           Pred.push_back(MO);
01467           Found = true;
01468         }
01469       } else if (MO.isRegMask()) {
01470         for (TargetRegisterClass::iterator I = RC->begin(),
01471              IE = RC->end(); I != IE; ++I)
01472           if (MO.clobbersPhysReg(*I)) {
01473             Pred.push_back(MO);
01474             Found = true;
01475           }
01476       }
01477     }
01478   }
01479 
01480   return Found;
01481 }
01482 
01483 bool PPCInstrInfo::isPredicable(MachineInstr *MI) const {
01484   unsigned OpC = MI->getOpcode();
01485   switch (OpC) {
01486   default:
01487     return false;
01488   case PPC::B:
01489   case PPC::BLR:
01490   case PPC::BLR8:
01491   case PPC::BCTR:
01492   case PPC::BCTR8:
01493   case PPC::BCTRL:
01494   case PPC::BCTRL8:
01495     return true;
01496   }
01497 }
01498 
01499 bool PPCInstrInfo::analyzeCompare(const MachineInstr *MI,
01500                                   unsigned &SrcReg, unsigned &SrcReg2,
01501                                   int &Mask, int &Value) const {
01502   unsigned Opc = MI->getOpcode();
01503 
01504   switch (Opc) {
01505   default: return false;
01506   case PPC::CMPWI:
01507   case PPC::CMPLWI:
01508   case PPC::CMPDI:
01509   case PPC::CMPLDI:
01510     SrcReg = MI->getOperand(1).getReg();
01511     SrcReg2 = 0;
01512     Value = MI->getOperand(2).getImm();
01513     Mask = 0xFFFF;
01514     return true;
01515   case PPC::CMPW:
01516   case PPC::CMPLW:
01517   case PPC::CMPD:
01518   case PPC::CMPLD:
01519   case PPC::FCMPUS:
01520   case PPC::FCMPUD:
01521     SrcReg = MI->getOperand(1).getReg();
01522     SrcReg2 = MI->getOperand(2).getReg();
01523     return true;
01524   }
01525 }
01526 
01527 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr,
01528                                         unsigned SrcReg, unsigned SrcReg2,
01529                                         int Mask, int Value,
01530                                         const MachineRegisterInfo *MRI) const {
01531   if (DisableCmpOpt)
01532     return false;
01533 
01534   int OpC = CmpInstr->getOpcode();
01535   unsigned CRReg = CmpInstr->getOperand(0).getReg();
01536 
01537   // FP record forms set CR1 based on the execption status bits, not a
01538   // comparison with zero.
01539   if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
01540     return false;
01541 
01542   // The record forms set the condition register based on a signed comparison
01543   // with zero (so says the ISA manual). This is not as straightforward as it
01544   // seems, however, because this is always a 64-bit comparison on PPC64, even
01545   // for instructions that are 32-bit in nature (like slw for example).
01546   // So, on PPC32, for unsigned comparisons, we can use the record forms only
01547   // for equality checks (as those don't depend on the sign). On PPC64,
01548   // we are restricted to equality for unsigned 64-bit comparisons and for
01549   // signed 32-bit comparisons the applicability is more restricted.
01550   bool isPPC64 = Subtarget.isPPC64();
01551   bool is32BitSignedCompare   = OpC ==  PPC::CMPWI || OpC == PPC::CMPW;
01552   bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
01553   bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
01554 
01555   // Get the unique definition of SrcReg.
01556   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
01557   if (!MI) return false;
01558   int MIOpC = MI->getOpcode();
01559 
01560   bool equalityOnly = false;
01561   bool noSub = false;
01562   if (isPPC64) {
01563     if (is32BitSignedCompare) {
01564       // We can perform this optimization only if MI is sign-extending.
01565       if (MIOpC == PPC::SRAW  || MIOpC == PPC::SRAWo ||
01566           MIOpC == PPC::SRAWI || MIOpC == PPC::SRAWIo ||
01567           MIOpC == PPC::EXTSB || MIOpC == PPC::EXTSBo ||
01568           MIOpC == PPC::EXTSH || MIOpC == PPC::EXTSHo ||
01569           MIOpC == PPC::EXTSW || MIOpC == PPC::EXTSWo) {
01570         noSub = true;
01571       } else
01572         return false;
01573     } else if (is32BitUnsignedCompare) {
01574       // We can perform this optimization, equality only, if MI is
01575       // zero-extending.
01576       if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo ||
01577           MIOpC == PPC::SLW    || MIOpC == PPC::SLWo ||
01578           MIOpC == PPC::SRW    || MIOpC == PPC::SRWo) {
01579         noSub = true;
01580         equalityOnly = true;
01581       } else
01582         return false;
01583     } else
01584       equalityOnly = is64BitUnsignedCompare;
01585   } else
01586     equalityOnly = is32BitUnsignedCompare;
01587 
01588   if (equalityOnly) {
01589     // We need to check the uses of the condition register in order to reject
01590     // non-equality comparisons.
01591     for (MachineRegisterInfo::use_instr_iterator I =MRI->use_instr_begin(CRReg),
01592          IE = MRI->use_instr_end(); I != IE; ++I) {
01593       MachineInstr *UseMI = &*I;
01594       if (UseMI->getOpcode() == PPC::BCC) {
01595         unsigned Pred = UseMI->getOperand(0).getImm();
01596         if (Pred != PPC::PRED_EQ && Pred != PPC::PRED_NE)
01597           return false;
01598       } else if (UseMI->getOpcode() == PPC::ISEL ||
01599                  UseMI->getOpcode() == PPC::ISEL8) {
01600         unsigned SubIdx = UseMI->getOperand(3).getSubReg();
01601         if (SubIdx != PPC::sub_eq)
01602           return false;
01603       } else
01604         return false;
01605     }
01606   }
01607 
01608   MachineBasicBlock::iterator I = CmpInstr;
01609 
01610   // Scan forward to find the first use of the compare.
01611   for (MachineBasicBlock::iterator EL = CmpInstr->getParent()->end();
01612        I != EL; ++I) {
01613     bool FoundUse = false;
01614     for (MachineRegisterInfo::use_instr_iterator J =MRI->use_instr_begin(CRReg),
01615          JE = MRI->use_instr_end(); J != JE; ++J)
01616       if (&*J == &*I) {
01617         FoundUse = true;
01618         break;
01619       }
01620 
01621     if (FoundUse)
01622       break;
01623   }
01624 
01625   // There are two possible candidates which can be changed to set CR[01].
01626   // One is MI, the other is a SUB instruction.
01627   // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
01628   MachineInstr *Sub = nullptr;
01629   if (SrcReg2 != 0)
01630     // MI is not a candidate for CMPrr.
01631     MI = nullptr;
01632   // FIXME: Conservatively refuse to convert an instruction which isn't in the
01633   // same BB as the comparison. This is to allow the check below to avoid calls
01634   // (and other explicit clobbers); instead we should really check for these
01635   // more explicitly (in at least a few predecessors).
01636   else if (MI->getParent() != CmpInstr->getParent() || Value != 0) {
01637     // PPC does not have a record-form SUBri.
01638     return false;
01639   }
01640 
01641   // Search for Sub.
01642   const TargetRegisterInfo *TRI = &getRegisterInfo();
01643   --I;
01644 
01645   // Get ready to iterate backward from CmpInstr.
01646   MachineBasicBlock::iterator E = MI,
01647                               B = CmpInstr->getParent()->begin();
01648 
01649   for (; I != E && !noSub; --I) {
01650     const MachineInstr &Instr = *I;
01651     unsigned IOpC = Instr.getOpcode();
01652 
01653     if (&*I != CmpInstr && (
01654         Instr.modifiesRegister(PPC::CR0, TRI) ||
01655         Instr.readsRegister(PPC::CR0, TRI)))
01656       // This instruction modifies or uses the record condition register after
01657       // the one we want to change. While we could do this transformation, it
01658       // would likely not be profitable. This transformation removes one
01659       // instruction, and so even forcing RA to generate one move probably
01660       // makes it unprofitable.
01661       return false;
01662 
01663     // Check whether CmpInstr can be made redundant by the current instruction.
01664     if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
01665          OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
01666         (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
01667         ((Instr.getOperand(1).getReg() == SrcReg &&
01668           Instr.getOperand(2).getReg() == SrcReg2) ||
01669         (Instr.getOperand(1).getReg() == SrcReg2 &&
01670          Instr.getOperand(2).getReg() == SrcReg))) {
01671       Sub = &*I;
01672       break;
01673     }
01674 
01675     if (I == B)
01676       // The 'and' is below the comparison instruction.
01677       return false;
01678   }
01679 
01680   // Return false if no candidates exist.
01681   if (!MI && !Sub)
01682     return false;
01683 
01684   // The single candidate is called MI.
01685   if (!MI) MI = Sub;
01686 
01687   int NewOpC = -1;
01688   MIOpC = MI->getOpcode();
01689   if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
01690     NewOpC = MIOpC;
01691   else {
01692     NewOpC = PPC::getRecordFormOpcode(MIOpC);
01693     if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
01694       NewOpC = MIOpC;
01695   }
01696 
01697   // FIXME: On the non-embedded POWER architectures, only some of the record
01698   // forms are fast, and we should use only the fast ones.
01699 
01700   // The defining instruction has a record form (or is already a record
01701   // form). It is possible, however, that we'll need to reverse the condition
01702   // code of the users.
01703   if (NewOpC == -1)
01704     return false;
01705 
01706   SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate;
01707   SmallVector<std::pair<MachineOperand*, unsigned>, 4> SubRegsToUpdate;
01708 
01709   // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
01710   // needs to be updated to be based on SUB.  Push the condition code
01711   // operands to OperandsToUpdate.  If it is safe to remove CmpInstr, the
01712   // condition code of these operands will be modified.
01713   bool ShouldSwap = false;
01714   if (Sub) {
01715     ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
01716       Sub->getOperand(2).getReg() == SrcReg;
01717 
01718     // The operands to subf are the opposite of sub, so only in the fixed-point
01719     // case, invert the order.
01720     ShouldSwap = !ShouldSwap;
01721   }
01722 
01723   if (ShouldSwap)
01724     for (MachineRegisterInfo::use_instr_iterator
01725          I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
01726          I != IE; ++I) {
01727       MachineInstr *UseMI = &*I;
01728       if (UseMI->getOpcode() == PPC::BCC) {
01729         PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
01730         assert((!equalityOnly ||
01731                 Pred == PPC::PRED_EQ || Pred == PPC::PRED_NE) &&
01732                "Invalid predicate for equality-only optimization");
01733         PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
01734                                 PPC::getSwappedPredicate(Pred)));
01735       } else if (UseMI->getOpcode() == PPC::ISEL ||
01736                  UseMI->getOpcode() == PPC::ISEL8) {
01737         unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
01738         assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&
01739                "Invalid CR bit for equality-only optimization");
01740 
01741         if (NewSubReg == PPC::sub_lt)
01742           NewSubReg = PPC::sub_gt;
01743         else if (NewSubReg == PPC::sub_gt)
01744           NewSubReg = PPC::sub_lt;
01745 
01746         SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
01747                                                  NewSubReg));
01748       } else // We need to abort on a user we don't understand.
01749         return false;
01750     }
01751 
01752   // Create a new virtual register to hold the value of the CR set by the
01753   // record-form instruction. If the instruction was not previously in
01754   // record form, then set the kill flag on the CR.
01755   CmpInstr->eraseFromParent();
01756 
01757   MachineBasicBlock::iterator MII = MI;
01758   BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
01759           get(TargetOpcode::COPY), CRReg)
01760     .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
01761 
01762   if (MIOpC != NewOpC) {
01763     // We need to be careful here: we're replacing one instruction with
01764     // another, and we need to make sure that we get all of the right
01765     // implicit uses and defs. On the other hand, the caller may be holding
01766     // an iterator to this instruction, and so we can't delete it (this is
01767     // specifically the case if this is the instruction directly after the
01768     // compare).
01769 
01770     const MCInstrDesc &NewDesc = get(NewOpC);
01771     MI->setDesc(NewDesc);
01772 
01773     if (NewDesc.ImplicitDefs)
01774       for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
01775            *ImpDefs; ++ImpDefs)
01776         if (!MI->definesRegister(*ImpDefs))
01777           MI->addOperand(*MI->getParent()->getParent(),
01778                          MachineOperand::CreateReg(*ImpDefs, true, true));
01779     if (NewDesc.ImplicitUses)
01780       for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
01781            *ImpUses; ++ImpUses)
01782         if (!MI->readsRegister(*ImpUses))
01783           MI->addOperand(*MI->getParent()->getParent(),
01784                          MachineOperand::CreateReg(*ImpUses, false, true));
01785   }
01786 
01787   // Modify the condition code of operands in OperandsToUpdate.
01788   // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
01789   // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
01790   for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
01791     PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
01792 
01793   for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
01794     SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
01795 
01796   return true;
01797 }
01798 
01799 /// GetInstSize - Return the number of bytes of code the specified
01800 /// instruction may be.  This returns the maximum number of bytes.
01801 ///
01802 unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
01803   unsigned Opcode = MI->getOpcode();
01804 
01805   if (Opcode == PPC::INLINEASM) {
01806     const MachineFunction *MF = MI->getParent()->getParent();
01807     const char *AsmStr = MI->getOperand(0).getSymbolName();
01808     return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
01809   } else if (Opcode == TargetOpcode::STACKMAP) {
01810     return MI->getOperand(1).getImm();
01811   } else if (Opcode == TargetOpcode::PATCHPOINT) {
01812     PatchPointOpers Opers(MI);
01813     return Opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
01814   } else {
01815     const MCInstrDesc &Desc = get(Opcode);
01816     return Desc.getSize();
01817   }
01818 }
01819 
01820 std::pair<unsigned, unsigned>
01821 PPCInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
01822   const unsigned Mask = PPCII::MO_ACCESS_MASK;
01823   return std::make_pair(TF & Mask, TF & ~Mask);
01824 }
01825 
01826 ArrayRef<std::pair<unsigned, const char *>>
01827 PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
01828   using namespace PPCII;
01829   static const std::pair<unsigned, const char *> TargetFlags[] = {
01830       {MO_LO, "ppc-lo"},
01831       {MO_HA, "ppc-ha"},
01832       {MO_TPREL_LO, "ppc-tprel-lo"},
01833       {MO_TPREL_HA, "ppc-tprel-ha"},
01834       {MO_DTPREL_LO, "ppc-dtprel-lo"},
01835       {MO_TLSLD_LO, "ppc-tlsld-lo"},
01836       {MO_TOC_LO, "ppc-toc-lo"},
01837       {MO_TLS, "ppc-tls"}};
01838   return makeArrayRef(TargetFlags);
01839 }
01840 
01841 ArrayRef<std::pair<unsigned, const char *>>
01842 PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
01843   using namespace PPCII;
01844   static const std::pair<unsigned, const char *> TargetFlags[] = {
01845       {MO_PLT_OR_STUB, "ppc-plt-or-stub"},
01846       {MO_PIC_FLAG, "ppc-pic"},
01847       {MO_NLP_FLAG, "ppc-nlp"},
01848       {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}};
01849   return makeArrayRef(TargetFlags);
01850 }
01851