32#define DEBUG_TYPE "arm-pseudo"
36 cl::desc(
"Verify machine code after expanding ARM pseudos"));
38#define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass"
55 MachineFunctionProperties::Property::NoVRegs);
71 unsigned Opc,
bool IsExt);
111 unsigned StrexOp,
unsigned UxtOp,
118 char ARMExpandPseudo::ID = 0;
129 enum NEONRegSpacing {
140 struct NEONLdStTableEntry {
145 bool hasWritebackOperand;
154 bool copyAllListRegs;
157 bool operator<(
const NEONLdStTableEntry &TE)
const {
158 return PseudoOpc < TE.PseudoOpc;
160 friend bool operator<(
const NEONLdStTableEntry &TE,
unsigned PseudoOpc) {
161 return TE.PseudoOpc < PseudoOpc;
164 const NEONLdStTableEntry &TE) {
165 return PseudoOpc < TE.PseudoOpc;
171{ ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16,
true,
false,
false, EvenDblSpc, 1, 4 ,
true},
172{ ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD,
true,
true,
true, EvenDblSpc, 1, 4 ,
true},
173{ ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32,
true,
false,
false, EvenDblSpc, 1, 2 ,
true},
174{ ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD,
true,
true,
true, EvenDblSpc, 1, 2 ,
true},
175{ ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8,
true,
false,
false, EvenDblSpc, 1, 8 ,
true},
176{ ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD,
true,
true,
true, EvenDblSpc, 1, 8 ,
true},
178{ ARM::VLD1d16QPseudo, ARM::VLD1d16Q,
true,
false,
false, SingleSpc, 4, 4 ,
false},
179{ ARM::VLD1d16QPseudoWB_fixed, ARM::VLD1d16Qwb_fixed,
true,
true,
false, SingleSpc, 4, 4 ,
false},
180{ ARM::VLD1d16QPseudoWB_register, ARM::VLD1d16Qwb_register,
true,
true,
true, SingleSpc, 4, 4 ,
false},
181{ ARM::VLD1d16TPseudo, ARM::VLD1d16T,
true,
false,
false, SingleSpc, 3, 4 ,
false},
182{ ARM::VLD1d16TPseudoWB_fixed, ARM::VLD1d16Twb_fixed,
true,
true,
false, SingleSpc, 3, 4 ,
false},
183{ ARM::VLD1d16TPseudoWB_register, ARM::VLD1d16Twb_register,
true,
true,
true, SingleSpc, 3, 4 ,
false},
185{ ARM::VLD1d32QPseudo, ARM::VLD1d32Q,
true,
false,
false, SingleSpc, 4, 2 ,
false},
186{ ARM::VLD1d32QPseudoWB_fixed, ARM::VLD1d32Qwb_fixed,
true,
true,
false, SingleSpc, 4, 2 ,
false},
187{ ARM::VLD1d32QPseudoWB_register, ARM::VLD1d32Qwb_register,
true,
true,
true, SingleSpc, 4, 2 ,
false},
188{ ARM::VLD1d32TPseudo, ARM::VLD1d32T,
true,
false,
false, SingleSpc, 3, 2 ,
false},
189{ ARM::VLD1d32TPseudoWB_fixed, ARM::VLD1d32Twb_fixed,
true,
true,
false, SingleSpc, 3, 2 ,
false},
190{ ARM::VLD1d32TPseudoWB_register, ARM::VLD1d32Twb_register,
true,
true,
true, SingleSpc, 3, 2 ,
false},
192{ ARM::VLD1d64QPseudo, ARM::VLD1d64Q,
true,
false,
false, SingleSpc, 4, 1 ,
false},
193{ ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed,
true,
true,
false, SingleSpc, 4, 1 ,
false},
194{ ARM::VLD1d64QPseudoWB_register, ARM::VLD1d64Qwb_register,
true,
true,
true, SingleSpc, 4, 1 ,
false},
195{ ARM::VLD1d64TPseudo, ARM::VLD1d64T,
true,
false,
false, SingleSpc, 3, 1 ,
false},
196{ ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed,
true,
true,
false, SingleSpc, 3, 1 ,
false},
197{ ARM::VLD1d64TPseudoWB_register, ARM::VLD1d64Twb_register,
true,
true,
true, SingleSpc, 3, 1 ,
false},
199{ ARM::VLD1d8QPseudo, ARM::VLD1d8Q,
true,
false,
false, SingleSpc, 4, 8 ,
false},
200{ ARM::VLD1d8QPseudoWB_fixed, ARM::VLD1d8Qwb_fixed,
true,
true,
false, SingleSpc, 4, 8 ,
false},
201{ ARM::VLD1d8QPseudoWB_register, ARM::VLD1d8Qwb_register,
true,
true,
true, SingleSpc, 4, 8 ,
false},
202{ ARM::VLD1d8TPseudo, ARM::VLD1d8T,
true,
false,
false, SingleSpc, 3, 8 ,
false},
203{ ARM::VLD1d8TPseudoWB_fixed, ARM::VLD1d8Twb_fixed,
true,
true,
false, SingleSpc, 3, 8 ,
false},
204{ ARM::VLD1d8TPseudoWB_register, ARM::VLD1d8Twb_register,
true,
true,
true, SingleSpc, 3, 8 ,
false},
206{ ARM::VLD1q16HighQPseudo, ARM::VLD1d16Q,
true,
false,
false, SingleHighQSpc, 4, 4 ,
false},
207{ ARM::VLD1q16HighQPseudo_UPD, ARM::VLD1d16Qwb_fixed,
true,
true,
true, SingleHighQSpc, 4, 4 ,
false},
208{ ARM::VLD1q16HighTPseudo, ARM::VLD1d16T,
true,
false,
false, SingleHighTSpc, 3, 4 ,
false},
209{ ARM::VLD1q16HighTPseudo_UPD, ARM::VLD1d16Twb_fixed,
true,
true,
true, SingleHighTSpc, 3, 4 ,
false},
210{ ARM::VLD1q16LowQPseudo_UPD, ARM::VLD1d16Qwb_fixed,
true,
true,
true, SingleLowSpc, 4, 4 ,
false},
211{ ARM::VLD1q16LowTPseudo_UPD, ARM::VLD1d16Twb_fixed,
true,
true,
true, SingleLowSpc, 3, 4 ,
false},
213{ ARM::VLD1q32HighQPseudo, ARM::VLD1d32Q,
true,
false,
false, SingleHighQSpc, 4, 2 ,
false},
214{ ARM::VLD1q32HighQPseudo_UPD, ARM::VLD1d32Qwb_fixed,
true,
true,
true, SingleHighQSpc, 4, 2 ,
false},
215{ ARM::VLD1q32HighTPseudo, ARM::VLD1d32T,
true,
false,
false, SingleHighTSpc, 3, 2 ,
false},
216{ ARM::VLD1q32HighTPseudo_UPD, ARM::VLD1d32Twb_fixed,
true,
true,
true, SingleHighTSpc, 3, 2 ,
false},
217{ ARM::VLD1q32LowQPseudo_UPD, ARM::VLD1d32Qwb_fixed,
true,
true,
true, SingleLowSpc, 4, 2 ,
false},
218{ ARM::VLD1q32LowTPseudo_UPD, ARM::VLD1d32Twb_fixed,
true,
true,
true, SingleLowSpc, 3, 2 ,
false},
220{ ARM::VLD1q64HighQPseudo, ARM::VLD1d64Q,
true,
false,
false, SingleHighQSpc, 4, 1 ,
false},
221{ ARM::VLD1q64HighQPseudo_UPD, ARM::VLD1d64Qwb_fixed,
true,
true,
true, SingleHighQSpc, 4, 1 ,
false},
222{ ARM::VLD1q64HighTPseudo, ARM::VLD1d64T,
true,
false,
false, SingleHighTSpc, 3, 1 ,
false},
223{ ARM::VLD1q64HighTPseudo_UPD, ARM::VLD1d64Twb_fixed,
true,
true,
true, SingleHighTSpc, 3, 1 ,
false},
224{ ARM::VLD1q64LowQPseudo_UPD, ARM::VLD1d64Qwb_fixed,
true,
true,
true, SingleLowSpc, 4, 1 ,
false},
225{ ARM::VLD1q64LowTPseudo_UPD, ARM::VLD1d64Twb_fixed,
true,
true,
true, SingleLowSpc, 3, 1 ,
false},
227{ ARM::VLD1q8HighQPseudo, ARM::VLD1d8Q,
true,
false,
false, SingleHighQSpc, 4, 8 ,
false},
228{ ARM::VLD1q8HighQPseudo_UPD, ARM::VLD1d8Qwb_fixed,
true,
true,
true, SingleHighQSpc, 4, 8 ,
false},
229{ ARM::VLD1q8HighTPseudo, ARM::VLD1d8T,
true,
false,
false, SingleHighTSpc, 3, 8 ,
false},
230{ ARM::VLD1q8HighTPseudo_UPD, ARM::VLD1d8Twb_fixed,
true,
true,
true, SingleHighTSpc, 3, 8 ,
false},
231{ ARM::VLD1q8LowQPseudo_UPD, ARM::VLD1d8Qwb_fixed,
true,
true,
true, SingleLowSpc, 4, 8 ,
false},
232{ ARM::VLD1q8LowTPseudo_UPD, ARM::VLD1d8Twb_fixed,
true,
true,
true, SingleLowSpc, 3, 8 ,
false},
234{ ARM::VLD2DUPq16EvenPseudo, ARM::VLD2DUPd16x2,
true,
false,
false, EvenDblSpc, 2, 4 ,
false},
235{ ARM::VLD2DUPq16OddPseudo, ARM::VLD2DUPd16x2,
true,
false,
false, OddDblSpc, 2, 4 ,
false},
236{ ARM::VLD2DUPq16OddPseudoWB_fixed, ARM::VLD2DUPd16x2wb_fixed,
true,
true,
false, OddDblSpc, 2, 4 ,
false},
237{ ARM::VLD2DUPq16OddPseudoWB_register, ARM::VLD2DUPd16x2wb_register,
true,
true,
true, OddDblSpc, 2, 4 ,
false},
238{ ARM::VLD2DUPq32EvenPseudo, ARM::VLD2DUPd32x2,
true,
false,
false, EvenDblSpc, 2, 2 ,
false},
239{ ARM::VLD2DUPq32OddPseudo, ARM::VLD2DUPd32x2,
true,
false,
false, OddDblSpc, 2, 2 ,
false},
240{ ARM::VLD2DUPq32OddPseudoWB_fixed, ARM::VLD2DUPd32x2wb_fixed,
true,
true,
false, OddDblSpc, 2, 2 ,
false},
241{ ARM::VLD2DUPq32OddPseudoWB_register, ARM::VLD2DUPd32x2wb_register,
true,
true,
true, OddDblSpc, 2, 2 ,
false},
242{ ARM::VLD2DUPq8EvenPseudo, ARM::VLD2DUPd8x2,
true,
false,
false, EvenDblSpc, 2, 8 ,
false},
243{ ARM::VLD2DUPq8OddPseudo, ARM::VLD2DUPd8x2,
true,
false,
false, OddDblSpc, 2, 8 ,
false},
244{ ARM::VLD2DUPq8OddPseudoWB_fixed, ARM::VLD2DUPd8x2wb_fixed,
true,
true,
false, OddDblSpc, 2, 8 ,
false},
245{ ARM::VLD2DUPq8OddPseudoWB_register, ARM::VLD2DUPd8x2wb_register,
true,
true,
true, OddDblSpc, 2, 8 ,
false},
247{ ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16,
true,
false,
false, SingleSpc, 2, 4 ,
true},
248{ ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD,
true,
true,
true, SingleSpc, 2, 4 ,
true},
249{ ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32,
true,
false,
false, SingleSpc, 2, 2 ,
true},
250{ ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD,
true,
true,
true, SingleSpc, 2, 2 ,
true},
251{ ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8,
true,
false,
false, SingleSpc, 2, 8 ,
true},
252{ ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD,
true,
true,
true, SingleSpc, 2, 8 ,
true},
253{ ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16,
true,
false,
false, EvenDblSpc, 2, 4 ,
true},
254{ ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD,
true,
true,
true, EvenDblSpc, 2, 4 ,
true},
255{ ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32,
true,
false,
false, EvenDblSpc, 2, 2 ,
true},
256{ ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD,
true,
true,
true, EvenDblSpc, 2, 2 ,
true},
258{ ARM::VLD2q16Pseudo, ARM::VLD2q16,
true,
false,
false, SingleSpc, 4, 4 ,
false},
259{ ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed,
true,
true,
false, SingleSpc, 4, 4 ,
false},
260{ ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register,
true,
true,
true, SingleSpc, 4, 4 ,
false},
261{ ARM::VLD2q32Pseudo, ARM::VLD2q32,
true,
false,
false, SingleSpc, 4, 2 ,
false},
262{ ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed,
true,
true,
false, SingleSpc, 4, 2 ,
false},
263{ ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register,
true,
true,
true, SingleSpc, 4, 2 ,
false},
264{ ARM::VLD2q8Pseudo, ARM::VLD2q8,
true,
false,
false, SingleSpc, 4, 8 ,
false},
265{ ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed,
true,
true,
false, SingleSpc, 4, 8 ,
false},
266{ ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register,
true,
true,
true, SingleSpc, 4, 8 ,
false},
268{ ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16,
true,
false,
false, SingleSpc, 3, 4,
true},
269{ ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD,
true,
true,
true, SingleSpc, 3, 4,
true},
270{ ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32,
true,
false,
false, SingleSpc, 3, 2,
true},
271{ ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD,
true,
true,
true, SingleSpc, 3, 2,
true},
272{ ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8,
true,
false,
false, SingleSpc, 3, 8,
true},
273{ ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD,
true,
true,
true, SingleSpc, 3, 8,
true},
274{ ARM::VLD3DUPq16EvenPseudo, ARM::VLD3DUPq16,
true,
false,
false, EvenDblSpc, 3, 4 ,
true},
275{ ARM::VLD3DUPq16OddPseudo, ARM::VLD3DUPq16,
true,
false,
false, OddDblSpc, 3, 4 ,
true},
276{ ARM::VLD3DUPq16OddPseudo_UPD, ARM::VLD3DUPq16_UPD,
true,
true,
true, OddDblSpc, 3, 4 ,
true},
277{ ARM::VLD3DUPq32EvenPseudo, ARM::VLD3DUPq32,
true,
false,
false, EvenDblSpc, 3, 2 ,
true},
278{ ARM::VLD3DUPq32OddPseudo, ARM::VLD3DUPq32,
true,
false,
false, OddDblSpc, 3, 2 ,
true},
279{ ARM::VLD3DUPq32OddPseudo_UPD, ARM::VLD3DUPq32_UPD,
true,
true,
true, OddDblSpc, 3, 2 ,
true},
280{ ARM::VLD3DUPq8EvenPseudo, ARM::VLD3DUPq8,
true,
false,
false, EvenDblSpc, 3, 8 ,
true},
281{ ARM::VLD3DUPq8OddPseudo, ARM::VLD3DUPq8,
true,
false,
false, OddDblSpc, 3, 8 ,
true},
282{ ARM::VLD3DUPq8OddPseudo_UPD, ARM::VLD3DUPq8_UPD,
true,
true,
true, OddDblSpc, 3, 8 ,
true},
284{ ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16,
true,
false,
false, SingleSpc, 3, 4 ,
true},
285{ ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD,
true,
true,
true, SingleSpc, 3, 4 ,
true},
286{ ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32,
true,
false,
false, SingleSpc, 3, 2 ,
true},
287{ ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD,
true,
true,
true, SingleSpc, 3, 2 ,
true},
288{ ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8,
true,
false,
false, SingleSpc, 3, 8 ,
true},
289{ ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD,
true,
true,
true, SingleSpc, 3, 8 ,
true},
290{ ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16,
true,
false,
false, EvenDblSpc, 3, 4 ,
true},
291{ ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD,
true,
true,
true, EvenDblSpc, 3, 4 ,
true},
292{ ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32,
true,
false,
false, EvenDblSpc, 3, 2 ,
true},
293{ ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD,
true,
true,
true, EvenDblSpc, 3, 2 ,
true},
295{ ARM::VLD3d16Pseudo, ARM::VLD3d16,
true,
false,
false, SingleSpc, 3, 4 ,
true},
296{ ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD,
true,
true,
true, SingleSpc, 3, 4 ,
true},
297{ ARM::VLD3d32Pseudo, ARM::VLD3d32,
true,
false,
false, SingleSpc, 3, 2 ,
true},
298{ ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD,
true,
true,
true, SingleSpc, 3, 2 ,
true},
299{ ARM::VLD3d8Pseudo, ARM::VLD3d8,
true,
false,
false, SingleSpc, 3, 8 ,
true},
300{ ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD,
true,
true,
true, SingleSpc, 3, 8 ,
true},
302{ ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD,
true,
true,
true, EvenDblSpc, 3, 4 ,
true},
303{ ARM::VLD3q16oddPseudo, ARM::VLD3q16,
true,
false,
false, OddDblSpc, 3, 4 ,
true},
304{ ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD,
true,
true,
true, OddDblSpc, 3, 4 ,
true},
305{ ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD,
true,
true,
true, EvenDblSpc, 3, 2 ,
true},
306{ ARM::VLD3q32oddPseudo, ARM::VLD3q32,
true,
false,
false, OddDblSpc, 3, 2 ,
true},
307{ ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD,
true,
true,
true, OddDblSpc, 3, 2 ,
true},
308{ ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD,
true,
true,
true, EvenDblSpc, 3, 8 ,
true},
309{ ARM::VLD3q8oddPseudo, ARM::VLD3q8,
true,
false,
false, OddDblSpc, 3, 8 ,
true},
310{ ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD,
true,
true,
true, OddDblSpc, 3, 8 ,
true},
312{ ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16,
true,
false,
false, SingleSpc, 4, 4,
true},
313{ ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD,
true,
true,
true, SingleSpc, 4, 4,
true},
314{ ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32,
true,
false,
false, SingleSpc, 4, 2,
true},
315{ ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD,
true,
true,
true, SingleSpc, 4, 2,
true},
316{ ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8,
true,
false,
false, SingleSpc, 4, 8,
true},
317{ ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD,
true,
true,
true, SingleSpc, 4, 8,
true},
318{ ARM::VLD4DUPq16EvenPseudo, ARM::VLD4DUPq16,
true,
false,
false, EvenDblSpc, 4, 4 ,
true},
319{ ARM::VLD4DUPq16OddPseudo, ARM::VLD4DUPq16,
true,
false,
false, OddDblSpc, 4, 4 ,
true},
320{ ARM::VLD4DUPq16OddPseudo_UPD, ARM::VLD4DUPq16_UPD,
true,
true,
true, OddDblSpc, 4, 4 ,
true},
321{ ARM::VLD4DUPq32EvenPseudo, ARM::VLD4DUPq32,
true,
false,
false, EvenDblSpc, 4, 2 ,
true},
322{ ARM::VLD4DUPq32OddPseudo, ARM::VLD4DUPq32,
true,
false,
false, OddDblSpc, 4, 2 ,
true},
323{ ARM::VLD4DUPq32OddPseudo_UPD, ARM::VLD4DUPq32_UPD,
true,
true,
true, OddDblSpc, 4, 2 ,
true},
324{ ARM::VLD4DUPq8EvenPseudo, ARM::VLD4DUPq8,
true,
false,
false, EvenDblSpc, 4, 8 ,
true},
325{ ARM::VLD4DUPq8OddPseudo, ARM::VLD4DUPq8,
true,
false,
false, OddDblSpc, 4, 8 ,
true},
326{ ARM::VLD4DUPq8OddPseudo_UPD, ARM::VLD4DUPq8_UPD,
true,
true,
true, OddDblSpc, 4, 8 ,
true},
328{ ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16,
true,
false,
false, SingleSpc, 4, 4 ,
true},
329{ ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD,
true,
true,
true, SingleSpc, 4, 4 ,
true},
330{ ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32,
true,
false,
false, SingleSpc, 4, 2 ,
true},
331{ ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD,
true,
true,
true, SingleSpc, 4, 2 ,
true},
332{ ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8,
true,
false,
false, SingleSpc, 4, 8 ,
true},
333{ ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD,
true,
true,
true, SingleSpc, 4, 8 ,
true},
334{ ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16,
true,
false,
false, EvenDblSpc, 4, 4 ,
true},
335{ ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD,
true,
true,
true, EvenDblSpc, 4, 4 ,
true},
336{ ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32,
true,
false,
false, EvenDblSpc, 4, 2 ,
true},
337{ ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD,
true,
true,
true, EvenDblSpc, 4, 2 ,
true},
339{ ARM::VLD4d16Pseudo, ARM::VLD4d16,
true,
false,
false, SingleSpc, 4, 4 ,
true},
340{ ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD,
true,
true,
true, SingleSpc, 4, 4 ,
true},
341{ ARM::VLD4d32Pseudo, ARM::VLD4d32,
true,
false,
false, SingleSpc, 4, 2 ,
true},
342{ ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD,
true,
true,
true, SingleSpc, 4, 2 ,
true},
343{ ARM::VLD4d8Pseudo, ARM::VLD4d8,
true,
false,
false, SingleSpc, 4, 8 ,
true},
344{ ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD,
true,
true,
true, SingleSpc, 4, 8 ,
true},
346{ ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD,
true,
true,
true, EvenDblSpc, 4, 4 ,
true},
347{ ARM::VLD4q16oddPseudo, ARM::VLD4q16,
true,
false,
false, OddDblSpc, 4, 4 ,
true},
348{ ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD,
true,
true,
true, OddDblSpc, 4, 4 ,
true},
349{ ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD,
true,
true,
true, EvenDblSpc, 4, 2 ,
true},
350{ ARM::VLD4q32oddPseudo, ARM::VLD4q32,
true,
false,
false, OddDblSpc, 4, 2 ,
true},
351{ ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD,
true,
true,
true, OddDblSpc, 4, 2 ,
true},
352{ ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD,
true,
true,
true, EvenDblSpc, 4, 8 ,
true},
353{ ARM::VLD4q8oddPseudo, ARM::VLD4q8,
true,
false,
false, OddDblSpc, 4, 8 ,
true},
354{ ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD,
true,
true,
true, OddDblSpc, 4, 8 ,
true},
356{ ARM::VST1LNq16Pseudo, ARM::VST1LNd16,
false,
false,
false, EvenDblSpc, 1, 4 ,
true},
357{ ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD,
false,
true,
true, EvenDblSpc, 1, 4 ,
true},
358{ ARM::VST1LNq32Pseudo, ARM::VST1LNd32,
false,
false,
false, EvenDblSpc, 1, 2 ,
true},
359{ ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD,
false,
true,
true, EvenDblSpc, 1, 2 ,
true},
360{ ARM::VST1LNq8Pseudo, ARM::VST1LNd8,
false,
false,
false, EvenDblSpc, 1, 8 ,
true},
361{ ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD,
false,
true,
true, EvenDblSpc, 1, 8 ,
true},
363{ ARM::VST1d16QPseudo, ARM::VST1d16Q,
false,
false,
false, SingleSpc, 4, 4 ,
false},
364{ ARM::VST1d16QPseudoWB_fixed, ARM::VST1d16Qwb_fixed,
false,
true,
false, SingleSpc, 4, 4 ,
false},
365{ ARM::VST1d16QPseudoWB_register, ARM::VST1d16Qwb_register,
false,
true,
true, SingleSpc, 4, 4 ,
false},
366{ ARM::VST1d16TPseudo, ARM::VST1d16T,
false,
false,
false, SingleSpc, 3, 4 ,
false},
367{ ARM::VST1d16TPseudoWB_fixed, ARM::VST1d16Twb_fixed,
false,
true,
false, SingleSpc, 3, 4 ,
false},
368{ ARM::VST1d16TPseudoWB_register, ARM::VST1d16Twb_register,
false,
true,
true, SingleSpc, 3, 4 ,
false},
370{ ARM::VST1d32QPseudo, ARM::VST1d32Q,
false,
false,
false, SingleSpc, 4, 2 ,
false},
371{ ARM::VST1d32QPseudoWB_fixed, ARM::VST1d32Qwb_fixed,
false,
true,
false, SingleSpc, 4, 2 ,
false},
372{ ARM::VST1d32QPseudoWB_register, ARM::VST1d32Qwb_register,
false,
true,
true, SingleSpc, 4, 2 ,
false},
373{ ARM::VST1d32TPseudo, ARM::VST1d32T,
false,
false,
false, SingleSpc, 3, 2 ,
false},
374{ ARM::VST1d32TPseudoWB_fixed, ARM::VST1d32Twb_fixed,
false,
true,
false, SingleSpc, 3, 2 ,
false},
375{ ARM::VST1d32TPseudoWB_register, ARM::VST1d32Twb_register,
false,
true,
true, SingleSpc, 3, 2 ,
false},
377{ ARM::VST1d64QPseudo, ARM::VST1d64Q,
false,
false,
false, SingleSpc, 4, 1 ,
false},
378{ ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed,
false,
true,
false, SingleSpc, 4, 1 ,
false},
379{ ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register,
false,
true,
true, SingleSpc, 4, 1 ,
false},
380{ ARM::VST1d64TPseudo, ARM::VST1d64T,
false,
false,
false, SingleSpc, 3, 1 ,
false},
381{ ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed,
false,
true,
false, SingleSpc, 3, 1 ,
false},
382{ ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register,
false,
true,
true, SingleSpc, 3, 1 ,
false},
384{ ARM::VST1d8QPseudo, ARM::VST1d8Q,
false,
false,
false, SingleSpc, 4, 8 ,
false},
385{ ARM::VST1d8QPseudoWB_fixed, ARM::VST1d8Qwb_fixed,
false,
true,
false, SingleSpc, 4, 8 ,
false},
386{ ARM::VST1d8QPseudoWB_register, ARM::VST1d8Qwb_register,
false,
true,
true, SingleSpc, 4, 8 ,
false},
387{ ARM::VST1d8TPseudo, ARM::VST1d8T,
false,
false,
false, SingleSpc, 3, 8 ,
false},
388{ ARM::VST1d8TPseudoWB_fixed, ARM::VST1d8Twb_fixed,
false,
true,
false, SingleSpc, 3, 8 ,
false},
389{ ARM::VST1d8TPseudoWB_register, ARM::VST1d8Twb_register,
false,
true,
true, SingleSpc, 3, 8 ,
false},
391{ ARM::VST1q16HighQPseudo, ARM::VST1d16Q,
false,
false,
false, SingleHighQSpc, 4, 4 ,
false},
392{ ARM::VST1q16HighQPseudo_UPD, ARM::VST1d16Qwb_fixed,
false,
true,
true, SingleHighQSpc, 4, 8 ,
false},
393{ ARM::VST1q16HighTPseudo, ARM::VST1d16T,
false,
false,
false, SingleHighTSpc, 3, 4 ,
false},
394{ ARM::VST1q16HighTPseudo_UPD, ARM::VST1d16Twb_fixed,
false,
true,
true, SingleHighTSpc, 3, 4 ,
false},
395{ ARM::VST1q16LowQPseudo_UPD, ARM::VST1d16Qwb_fixed,
false,
true,
true, SingleLowSpc, 4, 4 ,
false},
396{ ARM::VST1q16LowTPseudo_UPD, ARM::VST1d16Twb_fixed,
false,
true,
true, SingleLowSpc, 3, 4 ,
false},
398{ ARM::VST1q32HighQPseudo, ARM::VST1d32Q,
false,
false,
false, SingleHighQSpc, 4, 2 ,
false},
399{ ARM::VST1q32HighQPseudo_UPD, ARM::VST1d32Qwb_fixed,
false,
true,
true, SingleHighQSpc, 4, 8 ,
false},
400{ ARM::VST1q32HighTPseudo, ARM::VST1d32T,
false,
false,
false, SingleHighTSpc, 3, 2 ,
false},
401{ ARM::VST1q32HighTPseudo_UPD, ARM::VST1d32Twb_fixed,
false,
true,
true, SingleHighTSpc, 3, 2 ,
false},
402{ ARM::VST1q32LowQPseudo_UPD, ARM::VST1d32Qwb_fixed,
false,
true,
true, SingleLowSpc, 4, 2 ,
false},
403{ ARM::VST1q32LowTPseudo_UPD, ARM::VST1d32Twb_fixed,
false,
true,
true, SingleLowSpc, 3, 2 ,
false},
405{ ARM::VST1q64HighQPseudo, ARM::VST1d64Q,
false,
false,
false, SingleHighQSpc, 4, 1 ,
false},
406{ ARM::VST1q64HighQPseudo_UPD, ARM::VST1d64Qwb_fixed,
false,
true,
true, SingleHighQSpc, 4, 8 ,
false},
407{ ARM::VST1q64HighTPseudo, ARM::VST1d64T,
false,
false,
false, SingleHighTSpc, 3, 1 ,
false},
408{ ARM::VST1q64HighTPseudo_UPD, ARM::VST1d64Twb_fixed,
false,
true,
true, SingleHighTSpc, 3, 1 ,
false},
409{ ARM::VST1q64LowQPseudo_UPD, ARM::VST1d64Qwb_fixed,
false,
true,
true, SingleLowSpc, 4, 1 ,
false},
410{ ARM::VST1q64LowTPseudo_UPD, ARM::VST1d64Twb_fixed,
false,
true,
true, SingleLowSpc, 3, 1 ,
false},
412{ ARM::VST1q8HighQPseudo, ARM::VST1d8Q,
false,
false,
false, SingleHighQSpc, 4, 8 ,
false},
413{ ARM::VST1q8HighQPseudo_UPD, ARM::VST1d8Qwb_fixed,
false,
true,
true, SingleHighQSpc, 4, 8 ,
false},
414{ ARM::VST1q8HighTPseudo, ARM::VST1d8T,
false,
false,
false, SingleHighTSpc, 3, 8 ,
false},
415{ ARM::VST1q8HighTPseudo_UPD, ARM::VST1d8Twb_fixed,
false,
true,
true, SingleHighTSpc, 3, 8 ,
false},
416{ ARM::VST1q8LowQPseudo_UPD, ARM::VST1d8Qwb_fixed,
false,
true,
true, SingleLowSpc, 4, 8 ,
false},
417{ ARM::VST1q8LowTPseudo_UPD, ARM::VST1d8Twb_fixed,
false,
true,
true, SingleLowSpc, 3, 8 ,
false},
419{ ARM::VST2LNd16Pseudo, ARM::VST2LNd16,
false,
false,
false, SingleSpc, 2, 4 ,
true},
420{ ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD,
false,
true,
true, SingleSpc, 2, 4 ,
true},
421{ ARM::VST2LNd32Pseudo, ARM::VST2LNd32,
false,
false,
false, SingleSpc, 2, 2 ,
true},
422{ ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD,
false,
true,
true, SingleSpc, 2, 2 ,
true},
423{ ARM::VST2LNd8Pseudo, ARM::VST2LNd8,
false,
false,
false, SingleSpc, 2, 8 ,
true},
424{ ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD,
false,
true,
true, SingleSpc, 2, 8 ,
true},
425{ ARM::VST2LNq16Pseudo, ARM::VST2LNq16,
false,
false,
false, EvenDblSpc, 2, 4,
true},
426{ ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD,
false,
true,
true, EvenDblSpc, 2, 4,
true},
427{ ARM::VST2LNq32Pseudo, ARM::VST2LNq32,
false,
false,
false, EvenDblSpc, 2, 2,
true},
428{ ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD,
false,
true,
true, EvenDblSpc, 2, 2,
true},
430{ ARM::VST2q16Pseudo, ARM::VST2q16,
false,
false,
false, SingleSpc, 4, 4 ,
false},
431{ ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed,
false,
true,
false, SingleSpc, 4, 4 ,
false},
432{ ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register,
false,
true,
true, SingleSpc, 4, 4 ,
false},
433{ ARM::VST2q32Pseudo, ARM::VST2q32,
false,
false,
false, SingleSpc, 4, 2 ,
false},
434{ ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed,
false,
true,
false, SingleSpc, 4, 2 ,
false},
435{ ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register,
false,
true,
true, SingleSpc, 4, 2 ,
false},
436{ ARM::VST2q8Pseudo, ARM::VST2q8,
false,
false,
false, SingleSpc, 4, 8 ,
false},
437{ ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed,
false,
true,
false, SingleSpc, 4, 8 ,
false},
438{ ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register,
false,
true,
true, SingleSpc, 4, 8 ,
false},
440{ ARM::VST3LNd16Pseudo, ARM::VST3LNd16,
false,
false,
false, SingleSpc, 3, 4 ,
true},
441{ ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD,
false,
true,
true, SingleSpc, 3, 4 ,
true},
442{ ARM::VST3LNd32Pseudo, ARM::VST3LNd32,
false,
false,
false, SingleSpc, 3, 2 ,
true},
443{ ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD,
false,
true,
true, SingleSpc, 3, 2 ,
true},
444{ ARM::VST3LNd8Pseudo, ARM::VST3LNd8,
false,
false,
false, SingleSpc, 3, 8 ,
true},
445{ ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD,
false,
true,
true, SingleSpc, 3, 8 ,
true},
446{ ARM::VST3LNq16Pseudo, ARM::VST3LNq16,
false,
false,
false, EvenDblSpc, 3, 4,
true},
447{ ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD,
false,
true,
true, EvenDblSpc, 3, 4,
true},
448{ ARM::VST3LNq32Pseudo, ARM::VST3LNq32,
false,
false,
false, EvenDblSpc, 3, 2,
true},
449{ ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD,
false,
true,
true, EvenDblSpc, 3, 2,
true},
451{ ARM::VST3d16Pseudo, ARM::VST3d16,
false,
false,
false, SingleSpc, 3, 4 ,
true},
452{ ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD,
false,
true,
true, SingleSpc, 3, 4 ,
true},
453{ ARM::VST3d32Pseudo, ARM::VST3d32,
false,
false,
false, SingleSpc, 3, 2 ,
true},
454{ ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD,
false,
true,
true, SingleSpc, 3, 2 ,
true},
455{ ARM::VST3d8Pseudo, ARM::VST3d8,
false,
false,
false, SingleSpc, 3, 8 ,
true},
456{ ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD,
false,
true,
true, SingleSpc, 3, 8 ,
true},
458{ ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD,
false,
true,
true, EvenDblSpc, 3, 4 ,
true},
459{ ARM::VST3q16oddPseudo, ARM::VST3q16,
false,
false,
false, OddDblSpc, 3, 4 ,
true},
460{ ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD,
false,
true,
true, OddDblSpc, 3, 4 ,
true},
461{ ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD,
false,
true,
true, EvenDblSpc, 3, 2 ,
true},
462{ ARM::VST3q32oddPseudo, ARM::VST3q32,
false,
false,
false, OddDblSpc, 3, 2 ,
true},
463{ ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD,
false,
true,
true, OddDblSpc, 3, 2 ,
true},
464{ ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD,
false,
true,
true, EvenDblSpc, 3, 8 ,
true},
465{ ARM::VST3q8oddPseudo, ARM::VST3q8,
false,
false,
false, OddDblSpc, 3, 8 ,
true},
466{ ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD,
false,
true,
true, OddDblSpc, 3, 8 ,
true},
468{ ARM::VST4LNd16Pseudo, ARM::VST4LNd16,
false,
false,
false, SingleSpc, 4, 4 ,
true},
469{ ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD,
false,
true,
true, SingleSpc, 4, 4 ,
true},
470{ ARM::VST4LNd32Pseudo, ARM::VST4LNd32,
false,
false,
false, SingleSpc, 4, 2 ,
true},
471{ ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD,
false,
true,
true, SingleSpc, 4, 2 ,
true},
472{ ARM::VST4LNd8Pseudo, ARM::VST4LNd8,
false,
false,
false, SingleSpc, 4, 8 ,
true},
473{ ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD,
false,
true,
true, SingleSpc, 4, 8 ,
true},
474{ ARM::VST4LNq16Pseudo, ARM::VST4LNq16,
false,
false,
false, EvenDblSpc, 4, 4,
true},
475{ ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD,
false,
true,
true, EvenDblSpc, 4, 4,
true},
476{ ARM::VST4LNq32Pseudo, ARM::VST4LNq32,
false,
false,
false, EvenDblSpc, 4, 2,
true},
477{ ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD,
false,
true,
true, EvenDblSpc, 4, 2,
true},
479{ ARM::VST4d16Pseudo, ARM::VST4d16,
false,
false,
false, SingleSpc, 4, 4 ,
true},
480{ ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD,
false,
true,
true, SingleSpc, 4, 4 ,
true},
481{ ARM::VST4d32Pseudo, ARM::VST4d32,
false,
false,
false, SingleSpc, 4, 2 ,
true},
482{ ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD,
false,
true,
true, SingleSpc, 4, 2 ,
true},
483{ ARM::VST4d8Pseudo, ARM::VST4d8,
false,
false,
false, SingleSpc, 4, 8 ,
true},
484{ ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD,
false,
true,
true, SingleSpc, 4, 8 ,
true},
486{ ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD,
false,
true,
true, EvenDblSpc, 4, 4 ,
true},
487{ ARM::VST4q16oddPseudo, ARM::VST4q16,
false,
false,
false, OddDblSpc, 4, 4 ,
true},
488{ ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD,
false,
true,
true, OddDblSpc, 4, 4 ,
true},
489{ ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD,
false,
true,
true, EvenDblSpc, 4, 2 ,
true},
490{ ARM::VST4q32oddPseudo, ARM::VST4q32,
false,
false,
false, OddDblSpc, 4, 2 ,
true},
491{ ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD,
false,
true,
true, OddDblSpc, 4, 2 ,
true},
492{ ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD,
false,
true,
true, EvenDblSpc, 4, 8 ,
true},
493{ ARM::VST4q8oddPseudo, ARM::VST4q8,
false,
false,
false, OddDblSpc, 4, 8 ,
true},
494{ ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD,
false,
true,
true, OddDblSpc, 4, 8 ,
true}
502 static std::atomic<bool> TableChecked(
false);
503 if (!TableChecked.load(std::memory_order_relaxed)) {
505 TableChecked.store(
true, std::memory_order_relaxed);
520 unsigned &D1,
unsigned &D2,
unsigned &D3) {
521 if (RegSpc == SingleSpc || RegSpc == SingleLowSpc) {
522 D0 =
TRI->getSubReg(Reg, ARM::dsub_0);
523 D1 =
TRI->getSubReg(Reg, ARM::dsub_1);
524 D2 =
TRI->getSubReg(Reg, ARM::dsub_2);
525 D3 =
TRI->getSubReg(Reg, ARM::dsub_3);
526 }
else if (RegSpc == SingleHighQSpc) {
527 D0 =
TRI->getSubReg(Reg, ARM::dsub_4);
528 D1 =
TRI->getSubReg(Reg, ARM::dsub_5);
529 D2 =
TRI->getSubReg(Reg, ARM::dsub_6);
530 D3 =
TRI->getSubReg(Reg, ARM::dsub_7);
531 }
else if (RegSpc == SingleHighTSpc) {
532 D0 =
TRI->getSubReg(Reg, ARM::dsub_3);
533 D1 =
TRI->getSubReg(Reg, ARM::dsub_4);
534 D2 =
TRI->getSubReg(Reg, ARM::dsub_5);
535 D3 =
TRI->getSubReg(Reg, ARM::dsub_6);
536 }
else if (RegSpc == EvenDblSpc) {
537 D0 =
TRI->getSubReg(Reg, ARM::dsub_0);
538 D1 =
TRI->getSubReg(Reg, ARM::dsub_2);
539 D2 =
TRI->getSubReg(Reg, ARM::dsub_4);
540 D3 =
TRI->getSubReg(Reg, ARM::dsub_6);
542 assert(RegSpc == OddDblSpc &&
"unknown register spacing");
543 D0 =
TRI->getSubReg(Reg, ARM::dsub_1);
544 D1 =
TRI->getSubReg(Reg, ARM::dsub_3);
545 D2 =
TRI->getSubReg(Reg, ARM::dsub_5);
546 D3 =
TRI->getSubReg(Reg, ARM::dsub_7);
559 NEONRegSpacing RegSpc = (NEONRegSpacing)
TableEntry->RegSpacing;
566 bool DstIsDead =
MI.getOperand(OpIdx).isDead();
567 Register DstReg =
MI.getOperand(OpIdx++).getReg();
569 bool IsVLD2DUP =
TableEntry->RealOpc == ARM::VLD2DUPd8x2 ||
572 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_fixed ||
573 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_fixed ||
574 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_fixed ||
575 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_register ||
576 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_register ||
577 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_register;
580 unsigned SubRegIndex;
581 if (RegSpc == EvenDblSpc) {
582 SubRegIndex = ARM::dsub_0;
584 assert(RegSpc == OddDblSpc &&
"Unexpected spacing!");
585 SubRegIndex = ARM::dsub_1;
588 unsigned DstRegPair =
TRI->getMatchingSuperReg(
SubReg, ARM::dsub_0,
589 &ARM::DPairSpcRegClass);
592 unsigned D0, D1, D2, D3;
595 if (NumRegs > 1 &&
TableEntry->copyAllListRegs)
597 if (NumRegs > 2 &&
TableEntry->copyAllListRegs)
599 if (NumRegs > 3 &&
TableEntry->copyAllListRegs)
604 MIB.add(
MI.getOperand(OpIdx++));
607 MIB.add(
MI.getOperand(OpIdx++));
608 MIB.add(
MI.getOperand(OpIdx++));
620 if (
TableEntry->RealOpc == ARM::VLD1d8Qwb_fixed ||
621 TableEntry->RealOpc == ARM::VLD1d16Qwb_fixed ||
622 TableEntry->RealOpc == ARM::VLD1d32Qwb_fixed ||
623 TableEntry->RealOpc == ARM::VLD1d64Qwb_fixed ||
624 TableEntry->RealOpc == ARM::VLD1d8Twb_fixed ||
625 TableEntry->RealOpc == ARM::VLD1d16Twb_fixed ||
626 TableEntry->RealOpc == ARM::VLD1d32Twb_fixed ||
627 TableEntry->RealOpc == ARM::VLD1d64Twb_fixed ||
628 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_fixed ||
629 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_fixed ||
630 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_fixed) {
632 "A fixed writing-back pseudo instruction provides an offset "
642 unsigned SrcOpIdx = 0;
643 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc || RegSpc == SingleLowSpc ||
644 RegSpc == SingleHighQSpc || RegSpc == SingleHighTSpc)
648 MIB.add(
MI.getOperand(OpIdx++));
649 MIB.add(
MI.getOperand(OpIdx++));
660 MIB.copyImplicitOps(
MI);
663 MIB.cloneMemRefs(
MI);
664 MI.eraseFromParent();
677 NEONRegSpacing RegSpc = (NEONRegSpacing)
TableEntry->RegSpacing;
684 MIB.add(
MI.getOperand(OpIdx++));
687 MIB.add(
MI.getOperand(OpIdx++));
688 MIB.add(
MI.getOperand(OpIdx++));
699 if (
TableEntry->RealOpc == ARM::VST1d8Qwb_fixed ||
700 TableEntry->RealOpc == ARM::VST1d16Qwb_fixed ||
701 TableEntry->RealOpc == ARM::VST1d32Qwb_fixed ||
702 TableEntry->RealOpc == ARM::VST1d64Qwb_fixed ||
703 TableEntry->RealOpc == ARM::VST1d8Twb_fixed ||
704 TableEntry->RealOpc == ARM::VST1d16Twb_fixed ||
705 TableEntry->RealOpc == ARM::VST1d32Twb_fixed ||
706 TableEntry->RealOpc == ARM::VST1d64Twb_fixed) {
708 "A fixed writing-back pseudo instruction provides an offset "
715 bool SrcIsKill =
MI.getOperand(OpIdx).isKill();
716 bool SrcIsUndef =
MI.getOperand(OpIdx).isUndef();
717 Register SrcReg =
MI.getOperand(OpIdx++).getReg();
718 unsigned D0, D1, D2, D3;
721 if (NumRegs > 1 &&
TableEntry->copyAllListRegs)
723 if (NumRegs > 2 &&
TableEntry->copyAllListRegs)
725 if (NumRegs > 3 &&
TableEntry->copyAllListRegs)
729 MIB.add(
MI.getOperand(OpIdx++));
730 MIB.add(
MI.getOperand(OpIdx++));
732 if (SrcIsKill && !SrcIsUndef)
733 MIB->addRegisterKilled(SrcReg,
TRI,
true);
734 else if (!SrcIsUndef)
736 MIB.copyImplicitOps(
MI);
739 MIB.cloneMemRefs(
MI);
740 MI.eraseFromParent();
753 NEONRegSpacing RegSpc = (NEONRegSpacing)
TableEntry->RegSpacing;
762 unsigned Lane =
MI.getOperand(
MI.getDesc().getNumOperands() - 3).getImm();
765 assert(RegSpc != OddDblSpc &&
"unexpected register spacing for VLD/VST-lane");
766 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
770 assert(Lane < RegElts &&
"out of range lane for VLD/VST-lane");
772 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
774 bool DstIsDead =
false;
776 DstIsDead =
MI.getOperand(OpIdx).isDead();
777 DstReg =
MI.getOperand(OpIdx++).getReg();
789 MIB.add(
MI.getOperand(OpIdx++));
792 MIB.add(
MI.getOperand(OpIdx++));
793 MIB.add(
MI.getOperand(OpIdx++));
796 MIB.add(
MI.getOperand(OpIdx++));
806 MIB.addReg(D0, SrcFlags);
808 MIB.addReg(D1, SrcFlags);
810 MIB.addReg(D2, SrcFlags);
812 MIB.addReg(D3, SrcFlags);
819 MIB.add(
MI.getOperand(OpIdx++));
820 MIB.add(
MI.getOperand(OpIdx++));
828 MIB.copyImplicitOps(
MI);
830 MIB.cloneMemRefs(
MI);
831 MI.eraseFromParent();
837 unsigned Opc,
bool IsExt) {
846 MIB.
add(
MI.getOperand(OpIdx++));
852 bool SrcIsKill =
MI.getOperand(OpIdx).isKill();
853 Register SrcReg =
MI.getOperand(OpIdx++).getReg();
854 unsigned D0, D1, D2, D3;
863 MIB.
add(
MI.getOperand(OpIdx++));
864 MIB.
add(
MI.getOperand(OpIdx++));
869 MI.eraseFromParent();
877 MI.getOpcode() == ARM::MQQPRStore ||
MI.getOpcode() == ARM::MQQQQPRStore
888 MIB.
add(
MI.getOperand(1));
890 MIB.
addReg(
TRI->getSubReg(SrcReg, ARM::dsub_0), Flags);
891 MIB.
addReg(
TRI->getSubReg(SrcReg, ARM::dsub_1), Flags);
892 MIB.
addReg(
TRI->getSubReg(SrcReg, ARM::dsub_2), Flags);
893 MIB.
addReg(
TRI->getSubReg(SrcReg, ARM::dsub_3), Flags);
894 if (
MI.getOpcode() == ARM::MQQQQPRStore ||
895 MI.getOpcode() == ARM::MQQQQPRLoad) {
896 MIB.
addReg(
TRI->getSubReg(SrcReg, ARM::dsub_4), Flags);
897 MIB.
addReg(
TRI->getSubReg(SrcReg, ARM::dsub_5), Flags);
898 MIB.
addReg(
TRI->getSubReg(SrcReg, ARM::dsub_6), Flags);
899 MIB.
addReg(
TRI->getSubReg(SrcReg, ARM::dsub_7), Flags);
902 if (NewOpc == ARM::VSTMDIA)
907 MI.eraseFromParent();
955 unsigned TargetFlag) {
959 unsigned Imm = MO.
getImm();
960 switch (TargetFlag) {
962 Imm = (Imm >> 24) & 0xff;
965 Imm = (Imm >> 16) & 0xff;
968 Imm = (Imm >> 8) & 0xff;
974 Imm = (Imm >> 16) & 0xffff;
997 bool DstIsDead =
MI.getOperand(0).isDead();
999 unsigned MIFlags =
MI.getFlags();
1008 unsigned PendingShift = 0;
1009 for (
unsigned Byte = 0;
Byte < 4; ++
Byte) {
1015 bool ZeroImm = Operand.
isImm() && Operand.
getImm() == 0;
1016 unsigned Op = PendingShift ? ARM::tADDi8 : ARM::tMOVi8;
1020 if (PendingShift && (!ZeroImm || Byte == 3)) {
1038 if (
Op == ARM::tADDi8)
1048 if (PendingShift || !ZeroImm)
1054 (--
MBBI)->getOperand(0).setIsDead(DstIsDead);
1056 MI.eraseFromParent();
1062 unsigned Opcode =
MI.getOpcode();
1066 bool DstIsDead =
MI.getOperand(0).isDead();
1067 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
1073 if (!STI->hasV6T2Ops() &&
1074 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
1076 assert(!STI->isTargetWindows() &&
"Windows on ARM requires ARMv7+");
1078 assert (MO.
isImm() &&
"MOVi32imm w/ non-immediate source operand!");
1080 unsigned SOImmValV1 = 0, SOImmValV2 = 0;
1096 SOImmValV1 = ~(-SOImmValV1);
1099 unsigned MIFlags =
MI.getFlags();
1100 LO16 = LO16.
addImm(SOImmValV1);
1101 HI16 = HI16.
addImm(SOImmValV2);
1112 MI.eraseFromParent();
1116 unsigned LO16Opc = 0;
1117 unsigned HI16Opc = 0;
1118 unsigned MIFlags =
MI.getFlags();
1119 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
1120 LO16Opc = ARM::t2MOVi16;
1121 HI16Opc = ARM::t2MOVTi16;
1123 LO16Opc = ARM::MOVi16;
1124 HI16Opc = ARM::MOVTi16;
1138 if (!(HIOperand.isImm() && HIOperand.getImm() == 0)) {
1143 HI16.
add(HIOperand);
1152 if (RequiresBundling)
1155 MI.eraseFromParent();
1163 const std::initializer_list<unsigned> &Regs,
1167 if (!
Op.isReg() || !
Op.isUse())
1173 std::set_difference(Regs.begin(), Regs.end(), OpRegs.
begin(), OpRegs.
end(),
1174 std::back_inserter(ClearRegs));
1177void ARMExpandPseudo::CMSEClearGPRegs(
1180 unsigned ClobberReg) {
1182 if (STI->hasV8_1MMainlineOps()) {
1186 for (
unsigned R : ClearRegs)
1193 for (
unsigned Reg : ClearRegs) {
1194 if (Reg == ClobberReg)
1202 .
addImm(STI->hasDSP() ? 0xc00 : 0x800)
1221 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) ||
1222 (Reg >= ARM::D0 && Reg <= ARM::D15) ||
1223 (Reg >= ARM::S0 && Reg <= ARM::S31))
1228 if (Reg >= ARM::Q0 && Reg <= ARM::Q7) {
1229 int R = Reg - ARM::Q0;
1230 ClearRegs.
reset(R * 4, (R + 1) * 4);
1231 }
else if (Reg >= ARM::D0 && Reg <= ARM::D15) {
1232 int R = Reg - ARM::D0;
1233 ClearRegs.
reset(R * 2, (R + 1) * 2);
1234 }
else if (Reg >= ARM::S0 && Reg <= ARM::S31) {
1235 ClearRegs[Reg - ARM::S0] =
false;
1247 if (STI->hasV8_1MMainlineOps())
1248 return CMSEClearFPRegsV81(
MBB,
MBBI, ClearRegs);
1250 return CMSEClearFPRegsV8(
MBB,
MBBI, ClearRegs);
1259 if (!STI->hasFPRegs())
1269 if (STI->hasMinSize()) {
1270 ClearBB = DoneBB = &
MBB;
1291 if (Reg == ARM::NoRegister || Reg == ARM::LR)
1293 assert(
Reg.isPhysical() &&
"Unallocated register");
1317 for (
unsigned D = 0;
D < 8;
D++) {
1319 if (ClearRegs[
D * 2 + 0] && ClearRegs[
D * 2 + 1]) {
1320 unsigned Reg = ARM::D0 +
D;
1327 if (ClearRegs[
D * 2 + 0]) {
1328 unsigned Reg = ARM::S0 +
D * 2;
1334 if (ClearRegs[
D * 2 + 1]) {
1335 unsigned Reg = ARM::S0 +
D * 2 + 1;
1372 int Start = -1,
End = -1;
1373 for (
int S = 0, E = ClearRegs.
size(); S != E; ++S) {
1374 if (ClearRegs[S] && S ==
End + 1) {
1383 while (++Start <=
End)
1394 while (++Start <=
End)
1402void ARMExpandPseudo::CMSESaveClearFPRegs(
1405 if (STI->hasV8_1MMainlineOps())
1406 CMSESaveClearFPRegsV81(
MBB,
MBBI,
DL, LiveRegs);
1407 else if (STI->hasV8MMainlineOps())
1408 CMSESaveClearFPRegsV8(
MBB,
MBBI,
DL, LiveRegs, ScratchRegs);
1412void ARMExpandPseudo::CMSESaveClearFPRegsV8(
1418 unsigned SpareReg = ScratchRegs.
front();
1427 std::vector<std::tuple<unsigned, unsigned, unsigned>> ClearedFPRegs;
1428 std::vector<unsigned> NonclearedFPRegs;
1430 if (
Op.isReg() &&
Op.isUse()) {
1433 ARM::DPR_VFP2RegClass.
contains(Reg));
1435 if (ARM::DPR_VFP2RegClass.
contains(Reg)) {
1436 if (ScratchRegs.
size() >= 2) {
1439 ClearedFPRegs.emplace_back(Reg, SaveReg1, SaveReg2);
1448 NonclearedFPRegs.push_back(Reg);
1450 }
else if (ARM::SPRRegClass.
contains(Reg)) {
1451 if (ScratchRegs.
size() >= 1) {
1453 ClearedFPRegs.emplace_back(Reg, SaveReg, 0);
1460 NonclearedFPRegs.push_back(Reg);
1466 bool passesFPReg = (!NonclearedFPRegs.empty() || !ClearedFPRegs.empty());
1469 assert(STI->hasFPRegs() &&
"Subtarget needs fpregs");
1488 for (
const auto &Regs : ClearedFPRegs) {
1489 unsigned Reg, SaveReg1, SaveReg2;
1490 std::tie(Reg, SaveReg1, SaveReg2) = Regs;
1491 if (ARM::DPR_VFP2RegClass.
contains(Reg))
1496 else if (ARM::SPRRegClass.
contains(Reg))
1502 for (
unsigned Reg : NonclearedFPRegs) {
1503 if (ARM::DPR_VFP2RegClass.
contains(Reg)) {
1504 if (STI->isLittle()) {
1507 .
addImm((Reg - ARM::D0) * 2)
1512 unsigned SReg0 =
TRI->getSubReg(Reg, ARM::ssub_0);
1515 .
addImm((Reg - ARM::D0) * 2)
1519 .
addImm((Reg - ARM::D0) * 2 + 1)
1522 }
else if (ARM::SPRRegClass.
contains(Reg)) {
1565 if (!DefFP && ClearRegs.
count() == ClearRegs.
size()) {
1592 for (
int Reg = ARM::S16;
Reg <= ARM::S31; ++
Reg)
1596 (void)CMSEClearFPRegsV81(
MBB,
MBBI, ClearRegs);
1607void ARMExpandPseudo::CMSERestoreFPRegs(
1610 if (STI->hasV8_1MMainlineOps())
1611 CMSERestoreFPRegsV81(
MBB,
MBBI,
DL, AvailableRegs);
1612 else if (STI->hasV8MMainlineOps())
1613 CMSERestoreFPRegsV8(
MBB,
MBBI,
DL, AvailableRegs);
1616void ARMExpandPseudo::CMSERestoreFPRegsV8(
1621 unsigned ScratchReg = ARM::NoRegister;
1622 if (STI->fixCMSE_CVE_2021_35465())
1626 std::vector<std::tuple<unsigned, unsigned, unsigned>> ClearedFPRegs;
1627 std::vector<unsigned> NonclearedFPRegs;
1629 if (
Op.isReg() &&
Op.isDef()) {
1632 ARM::DPR_VFP2RegClass.
contains(Reg));
1634 if (ARM::DPR_VFP2RegClass.
contains(Reg)) {
1635 if (AvailableRegs.
size() >= 2) {
1638 ClearedFPRegs.emplace_back(Reg, SaveReg1, SaveReg2);
1647 NonclearedFPRegs.push_back(Reg);
1649 }
else if (ARM::SPRRegClass.
contains(Reg)) {
1650 if (AvailableRegs.
size() >= 1) {
1652 ClearedFPRegs.emplace_back(Reg, SaveReg, 0);
1659 NonclearedFPRegs.push_back(Reg);
1665 bool returnsFPReg = (!NonclearedFPRegs.empty() || !ClearedFPRegs.empty());
1668 assert(STI->hasFPRegs() &&
"Subtarget needs fpregs");
1671 for (
unsigned Reg : NonclearedFPRegs) {
1672 if (ARM::DPR_VFP2RegClass.
contains(Reg))
1676 .
addImm((Reg - ARM::D0) * 2)
1678 else if (ARM::SPRRegClass.
contains(Reg))
1695 if (STI->fixCMSE_CVE_2021_35465()) {
1715 if (STI->hasFPRegs())
1728 for (
const auto &Regs : ClearedFPRegs) {
1729 unsigned Reg, SaveReg1, SaveReg2;
1730 std::tie(Reg, SaveReg1, SaveReg2) = Regs;
1731 if (ARM::DPR_VFP2RegClass.
contains(Reg))
1736 else if (ARM::SPRRegClass.
contains(Reg))
1754 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) ||
1755 (Reg >= ARM::D0 && Reg <= ARM::D15) ||
1756 (Reg >= ARM::S0 && Reg <= ARM::S31))
1762void ARMExpandPseudo::CMSERestoreFPRegsV81(
1766 if (STI->fixCMSE_CVE_2021_35465()) {
1797 for (
int Reg = ARM::S16;
Reg <= ARM::S31; ++
Reg)
1807 unsigned LdrexOp,
unsigned StrexOp,
1810 bool IsThumb = STI->isThumb();
1811 bool IsThumb1Only = STI->isThumb1Only();
1815 Register TempReg =
MI.getOperand(1).getReg();
1818 assert(!
MI.getOperand(2).isUndef() &&
"cannot handle undef");
1819 Register AddrReg =
MI.getOperand(2).getReg();
1820 Register DesiredReg =
MI.getOperand(3).getReg();
1824 assert(STI->hasV8MBaselineOps() &&
1825 "CMP_SWAP not expected to be custom expanded for Thumb1");
1826 assert((UxtOp == 0 || UxtOp == ARM::tUXTB || UxtOp == ARM::tUXTH) &&
1827 "ARMv8-M.baseline does not have t2UXTB/t2UXTH");
1829 "DesiredReg used for UXT op must be tGPR");
1838 MF->
insert(++LoadCmpBB->getIterator(), StoreBB);
1839 MF->
insert(++StoreBB->getIterator(), DoneBB);
1858 if (LdrexOp == ARM::t2LDREX)
1862 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
1867 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
1872 LoadCmpBB->addSuccessor(DoneBB);
1873 LoadCmpBB->addSuccessor(StoreBB);
1882 if (StrexOp == ARM::t2STREX)
1887 IsThumb ? (IsThumb1Only ? ARM::tCMPi8 : ARM::t2CMPri) : ARM::CMPri;
1896 StoreBB->addSuccessor(LoadCmpBB);
1897 StoreBB->addSuccessor(DoneBB);
1905 MI.eraseFromParent();
1913 StoreBB->clearLiveIns();
1915 LoadCmpBB->clearLiveIns();
1925 unsigned Flags,
bool IsThumb,
1928 Register RegLo =
TRI->getSubReg(Reg.getReg(), ARM::gsub_0);
1929 Register RegHi =
TRI->getSubReg(Reg.getReg(), ARM::gsub_1);
1930 MIB.
addReg(RegLo, Flags);
1931 MIB.
addReg(RegHi, Flags);
1933 MIB.
addReg(Reg.getReg(), Flags);
1940 bool IsThumb = STI->isThumb();
1941 assert(!STI->isThumb1Only() &&
"CMP_SWAP_64 unsupported under Thumb1!");
1945 Register TempReg =
MI.getOperand(1).getReg();
1948 assert(!
MI.getOperand(2).isUndef() &&
"cannot handle undef");
1949 Register AddrReg =
MI.getOperand(2).getReg();
1950 Register DesiredReg =
MI.getOperand(3).getReg();
1952 New.setIsKill(
false);
1956 Register DesiredLo =
TRI->getSubReg(DesiredReg, ARM::gsub_0);
1957 Register DesiredHi =
TRI->getSubReg(DesiredReg, ARM::gsub_1);
1965 MF->
insert(++LoadCmpBB->getIterator(), StoreBB);
1966 MF->
insert(++StoreBB->getIterator(), DoneBB);
1973 unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD;
1979 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
1990 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
1995 LoadCmpBB->addSuccessor(DoneBB);
1996 LoadCmpBB->addSuccessor(StoreBB);
2002 unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD;
2008 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
2017 StoreBB->addSuccessor(LoadCmpBB);
2018 StoreBB->addSuccessor(DoneBB);
2026 MI.eraseFromParent();
2034 StoreBB->clearLiveIns();
2036 LoadCmpBB->clearLiveIns();
2050 for (
int Reg = ARM::R4; Reg < ARM::R8; ++Reg) {
2062 for (
int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) {
2063 if (JumpReg == LoReg)
2072 for (
int Reg = ARM::R4; Reg < ARM::R8; ++Reg) {
2081 if (JumpReg >= ARM::R4 && JumpReg <= ARM::R7) {
2082 int LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4;
2095 for (
int Reg = ARM::R4; Reg < ARM::R12; ++Reg) {
2110 for (
int R = 0; R < 4; ++R) {
2118 for (
int R = 0; R < 4; ++R)
2125 for (
int Reg = ARM::R4; Reg < ARM::R12; ++Reg)
2134 unsigned Opcode =
MI.getOpcode();
2142 if (DstReg ==
MI.getOperand(3).getReg()) {
2144 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBITd : ARM::VBITq;
2146 .
add(
MI.getOperand(0))
2147 .
add(
MI.getOperand(3))
2148 .
add(
MI.getOperand(2))
2149 .
add(
MI.getOperand(1))
2151 .
add(
MI.getOperand(5));
2152 }
else if (DstReg ==
MI.getOperand(2).getReg()) {
2154 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBIFd : ARM::VBIFq;
2156 .
add(
MI.getOperand(0))
2157 .
add(
MI.getOperand(2))
2158 .
add(
MI.getOperand(3))
2159 .
add(
MI.getOperand(1))
2161 .
add(
MI.getOperand(5));
2164 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBSLd : ARM::VBSLq;
2165 if (DstReg ==
MI.getOperand(1).getReg()) {
2167 .
add(
MI.getOperand(0))
2168 .
add(
MI.getOperand(1))
2169 .
add(
MI.getOperand(2))
2170 .
add(
MI.getOperand(3))
2172 .
add(
MI.getOperand(5));
2175 unsigned MoveOpc = Opcode == ARM::VBSPd ? ARM::VORRd : ARM::VORRq;
2180 .
add(
MI.getOperand(1))
2181 .
add(
MI.getOperand(1))
2183 .
add(
MI.getOperand(5));
2185 .
add(
MI.getOperand(0))
2189 .
add(
MI.getOperand(2))
2190 .
add(
MI.getOperand(3))
2192 .
add(
MI.getOperand(5));
2195 MI.eraseFromParent();
2199 case ARM::TCRETURNdi:
2200 case ARM::TCRETURNri:
2201 case ARM::TCRETURNrinotr12: {
2203 if (
MBBI->getOpcode() == ARM::SEH_EpilogEnd)
2205 if (
MBBI->getOpcode() == ARM::SEH_Nop_Ret)
2208 "Can only insert epilog into returning blocks");
2209 unsigned RetOpcode =
MBBI->getOpcode();
2216 if (
MBBI->getOpcode() == ARM::SEH_EpilogEnd)
2218 if (
MBBI->getOpcode() == ARM::SEH_Nop_Ret)
2223 if (RetOpcode == ARM::TCRETURNdi) {
2229 ? ((STI->isTargetMachO() || NeedsWinCFI) ? ARM::tTAILJMPd
2245 }
else if (RetOpcode == ARM::TCRETURNri ||
2246 RetOpcode == ARM::TCRETURNrinotr12) {
2248 STI->isThumb() ? ARM::tTAILJMPr
2249 : (STI->hasV4TOps() ? ARM::TAILJMPr : ARM::TAILJMPr4);
2255 auto NewMI = std::prev(
MBBI);
2256 for (
unsigned i = 2, e =
MBBI->getNumOperands(); i != e; ++i)
2257 NewMI->addOperand(
MBBI->getOperand(i));
2261 if (
MI.isCandidateForCallSiteEntry())
2262 MI.getMF()->moveCallSiteInfo(&
MI, &*NewMI);
2271 case ARM::tBXNS_RET: {
2274 if (!STI->hasV8_1MMainlineOps() && AFI->shouldSignReturnAddress())
2279 if (STI->hasV8_1MMainlineOps()) {
2282 TII->get(ARM::VLDR_FPCXTNS_post), ARM::SP)
2287 if (AFI->shouldSignReturnAddress())
2293 return !Op.isReg() || Op.getReg() != ARM::R12;
2297 *
MBBI, {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12}, ClearRegs);
2298 CMSEClearGPRegs(AfterBB, AfterBB.
end(),
MBBI->getDebugLoc(), ClearRegs,
2303 TII->get(ARM::tBXNS))
2308 MI.eraseFromParent();
2311 case ARM::tBLXNS_CALL: {
2326 AFI->isThumb1OnlyFunction());
2330 {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4,
2331 ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9,
2332 ARM::R10, ARM::R11, ARM::R12},
2334 auto OriginalClearRegs = ClearRegs;
2338 unsigned ScratchReg = ClearRegs.
front();
2341 if (AFI->isThumb2Function()) {
2362 CMSESaveClearFPRegs(
MBB,
MBBI,
DL, LiveRegs,
2364 CMSEClearGPRegs(
MBB,
MBBI,
DL, ClearRegs, JumpReg);
2373 if (
MI.isCandidateForCallSiteEntry())
2376 CMSERestoreFPRegs(
MBB,
MBBI,
DL, OriginalClearRegs);
2380 MI.eraseFromParent();
2385 case ARM::VMOVDcc: {
2386 unsigned newOpc = Opcode != ARM::VMOVDcc ? ARM::VMOVS : ARM::VMOVD;
2388 MI.getOperand(1).getReg())
2389 .
add(
MI.getOperand(2))
2391 .
add(
MI.getOperand(4))
2394 MI.eraseFromParent();
2399 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
2401 MI.getOperand(1).getReg())
2402 .
add(
MI.getOperand(2))
2404 .
add(
MI.getOperand(4))
2408 MI.eraseFromParent();
2411 case ARM::MOVCCsi: {
2413 (
MI.getOperand(1).getReg()))
2414 .
add(
MI.getOperand(2))
2417 .
add(
MI.getOperand(5))
2421 MI.eraseFromParent();
2424 case ARM::MOVCCsr: {
2426 (
MI.getOperand(1).getReg()))
2427 .
add(
MI.getOperand(2))
2428 .
add(
MI.getOperand(3))
2431 .
add(
MI.getOperand(6))
2435 MI.eraseFromParent();
2438 case ARM::t2MOVCCi16:
2439 case ARM::MOVCCi16: {
2440 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16;
2442 MI.getOperand(1).getReg())
2445 .
add(
MI.getOperand(4))
2447 MI.eraseFromParent();
2452 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
2454 MI.getOperand(1).getReg())
2457 .
add(
MI.getOperand(4))
2461 MI.eraseFromParent();
2466 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi;
2468 MI.getOperand(1).getReg())
2471 .
add(
MI.getOperand(4))
2475 MI.eraseFromParent();
2478 case ARM::t2MOVCClsl:
2479 case ARM::t2MOVCClsr:
2480 case ARM::t2MOVCCasr:
2481 case ARM::t2MOVCCror: {
2484 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri;
break;
2485 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri;
break;
2486 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri;
break;
2487 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri;
break;
2491 MI.getOperand(1).getReg())
2492 .
add(
MI.getOperand(2))
2495 .
add(
MI.getOperand(5))
2498 MI.eraseFromParent();
2501 case ARM::Int_eh_sjlj_dispatchsetup: {
2510 int32_t NumBytes = AFI->getFramePtrSpillOffset();
2513 "base pointer without frame pointer?");
2515 if (AFI->isThumb2Function()) {
2518 }
else if (AFI->isThumbFunction()) {
2527 if (RI.hasStackRealignment(MF)) {
2530 assert (!AFI->isThumb1OnlyFunction());
2533 "The BIC instruction cannot encode "
2534 "immediates larger than 256 with all lower "
2536 unsigned bicOpc = AFI->isThumbFunction() ?
2537 ARM::t2BICri : ARM::BICri;
2545 MI.eraseFromParent();
2549 case ARM::MOVsrl_glue:
2550 case ARM::MOVsra_glue: {
2553 MI.getOperand(0).getReg())
2554 .
add(
MI.getOperand(1))
2559 MI.eraseFromParent();
2565 MI.getOperand(0).getReg())
2566 .
add(
MI.getOperand(1))
2571 MI.eraseFromParent();
2576 const bool Thumb = Opcode == ARM::tTPsoft;
2580 if (STI->genLongCalls()) {
2582 unsigned PCLabelID = AFI->createPICLabelUId();
2585 "__aeabi_read_tp", PCLabelID, 0);
2589 TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg)
2603 TII->get(Thumb ? ARM::tBL : ARM::BL));
2612 if (
MI.isCandidateForCallSiteEntry())
2614 MI.eraseFromParent();
2617 case ARM::tLDRpci_pic:
2618 case ARM::t2LDRpci_pic: {
2619 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
2620 ? ARM::tLDRpci : ARM::t2LDRpci;
2622 bool DstIsDead =
MI.getOperand(0).isDead();
2624 .
add(
MI.getOperand(1))
2631 .
add(
MI.getOperand(2))
2633 MI.eraseFromParent();
2637 case ARM::LDRLIT_ga_abs:
2638 case ARM::LDRLIT_ga_pcrel:
2639 case ARM::LDRLIT_ga_pcrel_ldr:
2640 case ARM::tLDRLIT_ga_abs:
2641 case ARM::t2LDRLIT_ga_pcrel:
2642 case ARM::tLDRLIT_ga_pcrel: {
2644 bool DstIsDead =
MI.getOperand(0).isDead();
2648 bool IsARM = Opcode != ARM::tLDRLIT_ga_pcrel &&
2649 Opcode != ARM::tLDRLIT_ga_abs &&
2650 Opcode != ARM::t2LDRLIT_ga_pcrel;
2652 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs;
2653 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci;
2654 if (Opcode == ARM::t2LDRLIT_ga_pcrel)
2655 LDRLITOpc = ARM::t2LDRpci;
2656 unsigned PICAddOpc =
2658 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
2663 unsigned ARMPCLabelIndex = 0;
2667 unsigned PCAdj = IsARM ? 8 : 4;
2671 ARMPCLabelIndex = AFI->createPICLabelUId();
2690 .
addImm(ARMPCLabelIndex);
2696 MI.eraseFromParent();
2699 case ARM::MOV_ga_pcrel:
2700 case ARM::MOV_ga_pcrel_ldr:
2701 case ARM::t2MOV_ga_pcrel: {
2703 unsigned LabelId = AFI->createPICLabelUId();
2705 bool DstIsDead =
MI.getOperand(0).isDead();
2709 bool isARM = Opcode != ARM::t2MOV_ga_pcrel;
2710 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
2711 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
2714 unsigned PICAddOpc = isARM
2715 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
2729 TII->get(PICAddOpc))
2734 if (Opcode == ARM::MOV_ga_pcrel_ldr)
2738 MI.eraseFromParent();
2742 case ARM::MOVi32imm:
2743 case ARM::MOVCCi32imm:
2744 case ARM::t2MOVi32imm:
2745 case ARM::t2MOVCCi32imm:
2749 case ARM::tMOVi32imm:
2750 ExpandTMOV32BitImm(
MBB,
MBBI);
2753 case ARM::tLEApcrelJT:
2755 if (
MI.getMF()->getJumpTableInfo()->getEntryKind() ==
2760 assert(STI->isThumb() &&
"Non-inline jump tables expected only in thumb");
2761 ExpandTMOV32BitImm(
MBB,
MBBI);
2764 case ARM::SUBS_PC_LR: {
2767 .
add(
MI.getOperand(0))
2768 .
add(
MI.getOperand(1))
2769 .
add(
MI.getOperand(2))
2772 MI.eraseFromParent();
2775 case ARM::VLDMQIA: {
2776 unsigned NewOpc = ARM::VLDMDIA;
2782 bool DstIsDead =
MI.getOperand(OpIdx).isDead();
2783 Register DstReg =
MI.getOperand(OpIdx++).getReg();
2786 MIB.
add(
MI.getOperand(OpIdx++));
2789 MIB.
add(
MI.getOperand(OpIdx++));
2790 MIB.
add(
MI.getOperand(OpIdx++));
2793 Register D0 =
TRI->getSubReg(DstReg, ARM::dsub_0);
2794 Register D1 =
TRI->getSubReg(DstReg, ARM::dsub_1);
2802 MI.eraseFromParent();
2806 case ARM::VSTMQIA: {
2807 unsigned NewOpc = ARM::VSTMDIA;
2813 bool SrcIsKill =
MI.getOperand(OpIdx).isKill();
2814 Register SrcReg =
MI.getOperand(OpIdx++).getReg();
2821 MIB.
add(
MI.getOperand(OpIdx++));
2822 MIB.
add(
MI.getOperand(OpIdx++));
2825 Register D0 =
TRI->getSubReg(SrcReg, ARM::dsub_0);
2826 Register D1 =
TRI->getSubReg(SrcReg, ARM::dsub_1);
2835 MI.eraseFromParent();
2839 case ARM::VLD2q8Pseudo:
2840 case ARM::VLD2q16Pseudo:
2841 case ARM::VLD2q32Pseudo:
2842 case ARM::VLD2q8PseudoWB_fixed:
2843 case ARM::VLD2q16PseudoWB_fixed:
2844 case ARM::VLD2q32PseudoWB_fixed:
2845 case ARM::VLD2q8PseudoWB_register:
2846 case ARM::VLD2q16PseudoWB_register:
2847 case ARM::VLD2q32PseudoWB_register:
2848 case ARM::VLD3d8Pseudo:
2849 case ARM::VLD3d16Pseudo:
2850 case ARM::VLD3d32Pseudo:
2851 case ARM::VLD1d8TPseudo:
2852 case ARM::VLD1d8TPseudoWB_fixed:
2853 case ARM::VLD1d8TPseudoWB_register:
2854 case ARM::VLD1d16TPseudo:
2855 case ARM::VLD1d16TPseudoWB_fixed:
2856 case ARM::VLD1d16TPseudoWB_register:
2857 case ARM::VLD1d32TPseudo:
2858 case ARM::VLD1d32TPseudoWB_fixed:
2859 case ARM::VLD1d32TPseudoWB_register:
2860 case ARM::VLD1d64TPseudo:
2861 case ARM::VLD1d64TPseudoWB_fixed:
2862 case ARM::VLD1d64TPseudoWB_register:
2863 case ARM::VLD3d8Pseudo_UPD:
2864 case ARM::VLD3d16Pseudo_UPD:
2865 case ARM::VLD3d32Pseudo_UPD:
2866 case ARM::VLD3q8Pseudo_UPD:
2867 case ARM::VLD3q16Pseudo_UPD:
2868 case ARM::VLD3q32Pseudo_UPD:
2869 case ARM::VLD3q8oddPseudo:
2870 case ARM::VLD3q16oddPseudo:
2871 case ARM::VLD3q32oddPseudo:
2872 case ARM::VLD3q8oddPseudo_UPD:
2873 case ARM::VLD3q16oddPseudo_UPD:
2874 case ARM::VLD3q32oddPseudo_UPD:
2875 case ARM::VLD4d8Pseudo:
2876 case ARM::VLD4d16Pseudo:
2877 case ARM::VLD4d32Pseudo:
2878 case ARM::VLD1d8QPseudo:
2879 case ARM::VLD1d8QPseudoWB_fixed:
2880 case ARM::VLD1d8QPseudoWB_register:
2881 case ARM::VLD1d16QPseudo:
2882 case ARM::VLD1d16QPseudoWB_fixed:
2883 case ARM::VLD1d16QPseudoWB_register:
2884 case ARM::VLD1d32QPseudo:
2885 case ARM::VLD1d32QPseudoWB_fixed:
2886 case ARM::VLD1d32QPseudoWB_register:
2887 case ARM::VLD1d64QPseudo:
2888 case ARM::VLD1d64QPseudoWB_fixed:
2889 case ARM::VLD1d64QPseudoWB_register:
2890 case ARM::VLD1q8HighQPseudo:
2891 case ARM::VLD1q8HighQPseudo_UPD:
2892 case ARM::VLD1q8LowQPseudo_UPD:
2893 case ARM::VLD1q8HighTPseudo:
2894 case ARM::VLD1q8HighTPseudo_UPD:
2895 case ARM::VLD1q8LowTPseudo_UPD:
2896 case ARM::VLD1q16HighQPseudo:
2897 case ARM::VLD1q16HighQPseudo_UPD:
2898 case ARM::VLD1q16LowQPseudo_UPD:
2899 case ARM::VLD1q16HighTPseudo:
2900 case ARM::VLD1q16HighTPseudo_UPD:
2901 case ARM::VLD1q16LowTPseudo_UPD:
2902 case ARM::VLD1q32HighQPseudo:
2903 case ARM::VLD1q32HighQPseudo_UPD:
2904 case ARM::VLD1q32LowQPseudo_UPD:
2905 case ARM::VLD1q32HighTPseudo:
2906 case ARM::VLD1q32HighTPseudo_UPD:
2907 case ARM::VLD1q32LowTPseudo_UPD:
2908 case ARM::VLD1q64HighQPseudo:
2909 case ARM::VLD1q64HighQPseudo_UPD:
2910 case ARM::VLD1q64LowQPseudo_UPD:
2911 case ARM::VLD1q64HighTPseudo:
2912 case ARM::VLD1q64HighTPseudo_UPD:
2913 case ARM::VLD1q64LowTPseudo_UPD:
2914 case ARM::VLD4d8Pseudo_UPD:
2915 case ARM::VLD4d16Pseudo_UPD:
2916 case ARM::VLD4d32Pseudo_UPD:
2917 case ARM::VLD4q8Pseudo_UPD:
2918 case ARM::VLD4q16Pseudo_UPD:
2919 case ARM::VLD4q32Pseudo_UPD:
2920 case ARM::VLD4q8oddPseudo:
2921 case ARM::VLD4q16oddPseudo:
2922 case ARM::VLD4q32oddPseudo:
2923 case ARM::VLD4q8oddPseudo_UPD:
2924 case ARM::VLD4q16oddPseudo_UPD:
2925 case ARM::VLD4q32oddPseudo_UPD:
2926 case ARM::VLD3DUPd8Pseudo:
2927 case ARM::VLD3DUPd16Pseudo:
2928 case ARM::VLD3DUPd32Pseudo:
2929 case ARM::VLD3DUPd8Pseudo_UPD:
2930 case ARM::VLD3DUPd16Pseudo_UPD:
2931 case ARM::VLD3DUPd32Pseudo_UPD:
2932 case ARM::VLD4DUPd8Pseudo:
2933 case ARM::VLD4DUPd16Pseudo:
2934 case ARM::VLD4DUPd32Pseudo:
2935 case ARM::VLD4DUPd8Pseudo_UPD:
2936 case ARM::VLD4DUPd16Pseudo_UPD:
2937 case ARM::VLD4DUPd32Pseudo_UPD:
2938 case ARM::VLD2DUPq8EvenPseudo:
2939 case ARM::VLD2DUPq8OddPseudo:
2940 case ARM::VLD2DUPq16EvenPseudo:
2941 case ARM::VLD2DUPq16OddPseudo:
2942 case ARM::VLD2DUPq32EvenPseudo:
2943 case ARM::VLD2DUPq32OddPseudo:
2944 case ARM::VLD2DUPq8OddPseudoWB_fixed:
2945 case ARM::VLD2DUPq8OddPseudoWB_register:
2946 case ARM::VLD2DUPq16OddPseudoWB_fixed:
2947 case ARM::VLD2DUPq16OddPseudoWB_register:
2948 case ARM::VLD2DUPq32OddPseudoWB_fixed:
2949 case ARM::VLD2DUPq32OddPseudoWB_register:
2950 case ARM::VLD3DUPq8EvenPseudo:
2951 case ARM::VLD3DUPq8OddPseudo:
2952 case ARM::VLD3DUPq16EvenPseudo:
2953 case ARM::VLD3DUPq16OddPseudo:
2954 case ARM::VLD3DUPq32EvenPseudo:
2955 case ARM::VLD3DUPq32OddPseudo:
2956 case ARM::VLD3DUPq8OddPseudo_UPD:
2957 case ARM::VLD3DUPq16OddPseudo_UPD:
2958 case ARM::VLD3DUPq32OddPseudo_UPD:
2959 case ARM::VLD4DUPq8EvenPseudo:
2960 case ARM::VLD4DUPq8OddPseudo:
2961 case ARM::VLD4DUPq16EvenPseudo:
2962 case ARM::VLD4DUPq16OddPseudo:
2963 case ARM::VLD4DUPq32EvenPseudo:
2964 case ARM::VLD4DUPq32OddPseudo:
2965 case ARM::VLD4DUPq8OddPseudo_UPD:
2966 case ARM::VLD4DUPq16OddPseudo_UPD:
2967 case ARM::VLD4DUPq32OddPseudo_UPD:
2971 case ARM::VST2q8Pseudo:
2972 case ARM::VST2q16Pseudo:
2973 case ARM::VST2q32Pseudo:
2974 case ARM::VST2q8PseudoWB_fixed:
2975 case ARM::VST2q16PseudoWB_fixed:
2976 case ARM::VST2q32PseudoWB_fixed:
2977 case ARM::VST2q8PseudoWB_register:
2978 case ARM::VST2q16PseudoWB_register:
2979 case ARM::VST2q32PseudoWB_register:
2980 case ARM::VST3d8Pseudo:
2981 case ARM::VST3d16Pseudo:
2982 case ARM::VST3d32Pseudo:
2983 case ARM::VST1d8TPseudo:
2984 case ARM::VST1d8TPseudoWB_fixed:
2985 case ARM::VST1d8TPseudoWB_register:
2986 case ARM::VST1d16TPseudo:
2987 case ARM::VST1d16TPseudoWB_fixed:
2988 case ARM::VST1d16TPseudoWB_register:
2989 case ARM::VST1d32TPseudo:
2990 case ARM::VST1d32TPseudoWB_fixed:
2991 case ARM::VST1d32TPseudoWB_register:
2992 case ARM::VST1d64TPseudo:
2993 case ARM::VST1d64TPseudoWB_fixed:
2994 case ARM::VST1d64TPseudoWB_register:
2995 case ARM::VST3d8Pseudo_UPD:
2996 case ARM::VST3d16Pseudo_UPD:
2997 case ARM::VST3d32Pseudo_UPD:
2998 case ARM::VST3q8Pseudo_UPD:
2999 case ARM::VST3q16Pseudo_UPD:
3000 case ARM::VST3q32Pseudo_UPD:
3001 case ARM::VST3q8oddPseudo:
3002 case ARM::VST3q16oddPseudo:
3003 case ARM::VST3q32oddPseudo:
3004 case ARM::VST3q8oddPseudo_UPD:
3005 case ARM::VST3q16oddPseudo_UPD:
3006 case ARM::VST3q32oddPseudo_UPD:
3007 case ARM::VST4d8Pseudo:
3008 case ARM::VST4d16Pseudo:
3009 case ARM::VST4d32Pseudo:
3010 case ARM::VST1d8QPseudo:
3011 case ARM::VST1d8QPseudoWB_fixed:
3012 case ARM::VST1d8QPseudoWB_register:
3013 case ARM::VST1d16QPseudo:
3014 case ARM::VST1d16QPseudoWB_fixed:
3015 case ARM::VST1d16QPseudoWB_register:
3016 case ARM::VST1d32QPseudo:
3017 case ARM::VST1d32QPseudoWB_fixed:
3018 case ARM::VST1d32QPseudoWB_register:
3019 case ARM::VST1d64QPseudo:
3020 case ARM::VST1d64QPseudoWB_fixed:
3021 case ARM::VST1d64QPseudoWB_register:
3022 case ARM::VST4d8Pseudo_UPD:
3023 case ARM::VST4d16Pseudo_UPD:
3024 case ARM::VST4d32Pseudo_UPD:
3025 case ARM::VST1q8HighQPseudo:
3026 case ARM::VST1q8LowQPseudo_UPD:
3027 case ARM::VST1q8HighTPseudo:
3028 case ARM::VST1q8LowTPseudo_UPD:
3029 case ARM::VST1q16HighQPseudo:
3030 case ARM::VST1q16LowQPseudo_UPD:
3031 case ARM::VST1q16HighTPseudo:
3032 case ARM::VST1q16LowTPseudo_UPD:
3033 case ARM::VST1q32HighQPseudo:
3034 case ARM::VST1q32LowQPseudo_UPD:
3035 case ARM::VST1q32HighTPseudo:
3036 case ARM::VST1q32LowTPseudo_UPD:
3037 case ARM::VST1q64HighQPseudo:
3038 case ARM::VST1q64LowQPseudo_UPD:
3039 case ARM::VST1q64HighTPseudo:
3040 case ARM::VST1q64LowTPseudo_UPD:
3041 case ARM::VST1q8HighTPseudo_UPD:
3042 case ARM::VST1q16HighTPseudo_UPD:
3043 case ARM::VST1q32HighTPseudo_UPD:
3044 case ARM::VST1q64HighTPseudo_UPD:
3045 case ARM::VST1q8HighQPseudo_UPD:
3046 case ARM::VST1q16HighQPseudo_UPD:
3047 case ARM::VST1q32HighQPseudo_UPD:
3048 case ARM::VST1q64HighQPseudo_UPD:
3049 case ARM::VST4q8Pseudo_UPD:
3050 case ARM::VST4q16Pseudo_UPD:
3051 case ARM::VST4q32Pseudo_UPD:
3052 case ARM::VST4q8oddPseudo:
3053 case ARM::VST4q16oddPseudo:
3054 case ARM::VST4q32oddPseudo:
3055 case ARM::VST4q8oddPseudo_UPD:
3056 case ARM::VST4q16oddPseudo_UPD:
3057 case ARM::VST4q32oddPseudo_UPD:
3061 case ARM::VLD1LNq8Pseudo:
3062 case ARM::VLD1LNq16Pseudo:
3063 case ARM::VLD1LNq32Pseudo:
3064 case ARM::VLD1LNq8Pseudo_UPD:
3065 case ARM::VLD1LNq16Pseudo_UPD:
3066 case ARM::VLD1LNq32Pseudo_UPD:
3067 case ARM::VLD2LNd8Pseudo:
3068 case ARM::VLD2LNd16Pseudo:
3069 case ARM::VLD2LNd32Pseudo:
3070 case ARM::VLD2LNq16Pseudo:
3071 case ARM::VLD2LNq32Pseudo:
3072 case ARM::VLD2LNd8Pseudo_UPD:
3073 case ARM::VLD2LNd16Pseudo_UPD:
3074 case ARM::VLD2LNd32Pseudo_UPD:
3075 case ARM::VLD2LNq16Pseudo_UPD:
3076 case ARM::VLD2LNq32Pseudo_UPD:
3077 case ARM::VLD3LNd8Pseudo:
3078 case ARM::VLD3LNd16Pseudo:
3079 case ARM::VLD3LNd32Pseudo:
3080 case ARM::VLD3LNq16Pseudo:
3081 case ARM::VLD3LNq32Pseudo:
3082 case ARM::VLD3LNd8Pseudo_UPD:
3083 case ARM::VLD3LNd16Pseudo_UPD:
3084 case ARM::VLD3LNd32Pseudo_UPD:
3085 case ARM::VLD3LNq16Pseudo_UPD:
3086 case ARM::VLD3LNq32Pseudo_UPD:
3087 case ARM::VLD4LNd8Pseudo:
3088 case ARM::VLD4LNd16Pseudo:
3089 case ARM::VLD4LNd32Pseudo:
3090 case ARM::VLD4LNq16Pseudo:
3091 case ARM::VLD4LNq32Pseudo:
3092 case ARM::VLD4LNd8Pseudo_UPD:
3093 case ARM::VLD4LNd16Pseudo_UPD:
3094 case ARM::VLD4LNd32Pseudo_UPD:
3095 case ARM::VLD4LNq16Pseudo_UPD:
3096 case ARM::VLD4LNq32Pseudo_UPD:
3097 case ARM::VST1LNq8Pseudo:
3098 case ARM::VST1LNq16Pseudo:
3099 case ARM::VST1LNq32Pseudo:
3100 case ARM::VST1LNq8Pseudo_UPD:
3101 case ARM::VST1LNq16Pseudo_UPD:
3102 case ARM::VST1LNq32Pseudo_UPD:
3103 case ARM::VST2LNd8Pseudo:
3104 case ARM::VST2LNd16Pseudo:
3105 case ARM::VST2LNd32Pseudo:
3106 case ARM::VST2LNq16Pseudo:
3107 case ARM::VST2LNq32Pseudo:
3108 case ARM::VST2LNd8Pseudo_UPD:
3109 case ARM::VST2LNd16Pseudo_UPD:
3110 case ARM::VST2LNd32Pseudo_UPD:
3111 case ARM::VST2LNq16Pseudo_UPD:
3112 case ARM::VST2LNq32Pseudo_UPD:
3113 case ARM::VST3LNd8Pseudo:
3114 case ARM::VST3LNd16Pseudo:
3115 case ARM::VST3LNd32Pseudo:
3116 case ARM::VST3LNq16Pseudo:
3117 case ARM::VST3LNq32Pseudo:
3118 case ARM::VST3LNd8Pseudo_UPD:
3119 case ARM::VST3LNd16Pseudo_UPD:
3120 case ARM::VST3LNd32Pseudo_UPD:
3121 case ARM::VST3LNq16Pseudo_UPD:
3122 case ARM::VST3LNq32Pseudo_UPD:
3123 case ARM::VST4LNd8Pseudo:
3124 case ARM::VST4LNd16Pseudo:
3125 case ARM::VST4LNd32Pseudo:
3126 case ARM::VST4LNq16Pseudo:
3127 case ARM::VST4LNq32Pseudo:
3128 case ARM::VST4LNd8Pseudo_UPD:
3129 case ARM::VST4LNd16Pseudo_UPD:
3130 case ARM::VST4LNd32Pseudo_UPD:
3131 case ARM::VST4LNq16Pseudo_UPD:
3132 case ARM::VST4LNq32Pseudo_UPD:
3136 case ARM::VTBL3Pseudo: ExpandVTBL(
MBBI, ARM::VTBL3,
false);
return true;
3137 case ARM::VTBL4Pseudo: ExpandVTBL(
MBBI, ARM::VTBL4,
false);
return true;
3138 case ARM::VTBX3Pseudo: ExpandVTBL(
MBBI, ARM::VTBX3,
true);
return true;
3139 case ARM::VTBX4Pseudo: ExpandVTBL(
MBBI, ARM::VTBX4,
true);
return true;
3141 case ARM::MQQPRLoad:
3142 case ARM::MQQPRStore:
3143 case ARM::MQQQQPRLoad:
3144 case ARM::MQQQQPRStore:
3145 ExpandMQQPRLoadStore(
MBBI);
3148 case ARM::tCMP_SWAP_8:
3150 return ExpandCMP_SWAP(
MBB,
MBBI, ARM::t2LDREXB, ARM::t2STREXB, ARM::tUXTB,
3152 case ARM::tCMP_SWAP_16:
3154 return ExpandCMP_SWAP(
MBB,
MBBI, ARM::t2LDREXH, ARM::t2STREXH, ARM::tUXTH,
3156 case ARM::tCMP_SWAP_32:
3158 return ExpandCMP_SWAP(
MBB,
MBBI, ARM::t2LDREX, ARM::t2STREX, 0, NextMBBI);
3160 case ARM::CMP_SWAP_8:
3162 return ExpandCMP_SWAP(
MBB,
MBBI, ARM::LDREXB, ARM::STREXB, ARM::UXTB,
3164 case ARM::CMP_SWAP_16:
3166 return ExpandCMP_SWAP(
MBB,
MBBI, ARM::LDREXH, ARM::STREXH, ARM::UXTH,
3168 case ARM::CMP_SWAP_32:
3170 return ExpandCMP_SWAP(
MBB,
MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI);
3172 case ARM::CMP_SWAP_64:
3173 return ExpandCMP_SWAP_64(
MBB,
MBBI, NextMBBI);
3175 case ARM::tBL_PUSHLR:
3176 case ARM::BL_PUSHLR: {
3177 const bool Thumb = Opcode == ARM::tBL_PUSHLR;
3179 assert(Reg == ARM::LR &&
"expect LR register!");
3203 MI.eraseFromParent();
3206 case ARM::t2CALL_BTI: {
3211 for (
unsigned i = 0; i <
MI.getNumOperands(); ++i)
3212 MIB.
add(
MI.getOperand(i));
3213 if (
MI.isCandidateForCallSiteEntry())
3216 Bundler.append(MIB);
3217 Bundler.append(
BuildMI(MF,
MI.getDebugLoc(),
TII->get(ARM::t2BTI)));
3219 MI.eraseFromParent();
3223 case ARM::STOREDUAL: {
3224 Register PairReg =
MI.getOperand(0).getReg();
3228 TII->get(Opcode == ARM::LOADDUAL ? ARM::LDRD : ARM::STRD))
3229 .
addReg(
TRI->getSubReg(PairReg, ARM::gsub_0),
3231 .
addReg(
TRI->getSubReg(PairReg, ARM::gsub_1),
3237 MI.eraseFromParent();
3258 TII = STI->getInstrInfo();
3259 TRI = STI->getRegisterInfo();
3262 LLVM_DEBUG(
dbgs() <<
"********** ARM EXPAND PSEUDO INSTRUCTIONS **********\n"
3263 <<
"********** Function: " << MF.
getName() <<
'\n');
3269 MF.verify(
this,
"After expanding ARM pseudo instructions.");
3271 LLVM_DEBUG(
dbgs() <<
"***************************************************\n");
3278 return new ARMExpandPseudo();
static bool determineFPRegsToClear(const MachineInstr &MI, BitVector &ClearRegs)
static void CMSEPopCalleeSaves(const TargetInstrInfo &TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int JumpReg, bool Thumb1Only)
static MachineOperand getMovOperand(const MachineOperand &MO, unsigned TargetFlag)
static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, const TargetRegisterInfo *TRI, unsigned &D0, unsigned &D1, unsigned &D2, unsigned &D3)
GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, corresponding to the specified regis...
static MachineOperand makeImplicit(const MachineOperand &MO)
static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg, unsigned Flags, bool IsThumb, const TargetRegisterInfo *TRI)
ARM's ldrexd/strexd take a consecutive register pair (represented as a single GPRPair register),...
static cl::opt< bool > VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden, cl::desc("Verify machine code after expanding ARM pseudos"))
static void CMSEPushCalleeSaves(const TargetInstrInfo &TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, int JumpReg, const LivePhysRegs &LiveRegs, bool Thumb1Only)
static bool definesOrUsesFPReg(const MachineInstr &MI)
static void determineGPRegsToClear(const MachineInstr &MI, const std::initializer_list< unsigned > &Regs, SmallVectorImpl< unsigned > &ClearRegs)
static bool IsAnAddressOperand(const MachineOperand &MO)
#define ARM_EXPAND_PSEUDO_NAME
static const int CMSE_FP_SAVE_SIZE
static const NEONLdStTableEntry * LookupNEONLdSt(unsigned Opcode)
LookupNEONLdSt - Search the NEONLdStTable for information about a NEON load or store pseudo instructi...
static const NEONLdStTableEntry NEONLdStTable[]
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
#define LLVM_ATTRIBUTE_UNUSED
const HexagonInstrInfo * TII
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
static const unsigned FramePtr
virtual const ARMBaseRegisterInfo & getRegisterInfo() const =0
bool hasBasePointer(const MachineFunction &MF) const
Register getFrameRegister(const MachineFunction &MF) const override
static ARMConstantPoolConstant * Create(const Constant *C, unsigned ID)
static ARMConstantPoolSymbol * Create(LLVMContext &C, StringRef s, unsigned ID, unsigned char PCAdj)
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
size_type count() const
count - Returns the number of bits which are set.
size_type size() const
size - Returns the number of bits in this bitvector.
This class represents an Operation in the Expression.
FunctionPass class - This class is used to implement most global optimizations.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
bool needsUnwindTableEntry() const
True if this function needs an unwind table.
A set of physical registers with utility functions to track liveness when walking backward/forward th...
bool contains(MCPhysReg Reg) const
Returns true if register Reg is contained in the set.
void stepBackward(const MachineInstr &MI)
Simulates liveness when stepping backwards over an instruction(bundle).
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
bool usesWindowsCFI() const
Helper class for constructing bundles of MachineInstrs.
void transferSuccessors(MachineBasicBlock *FromMBB)
Transfers all the successors from MBB to this machine basic block (i.e., copies all the successors Fr...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
reverse_iterator rbegin()
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Abstract base class for all machine specific constantpool value subclasses.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
unsigned getConstantPoolIndex(const Constant *C, Align Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
void moveCallSiteInfo(const MachineInstr *Old, const MachineInstr *New)
Move the call site info from Old to \New call site info.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const
Copy all the implicit operands from OtherMI onto this one.
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Representation of each machine instruction.
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
iterator_range< mop_iterator > implicit_operands()
const MachineOperand & getOperand(unsigned i) const
@ EK_Inline
EK_Inline - Jump table entries are emitted inline at their point of use.
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
void setImplicit(bool Val=true)
static MachineOperand CreateES(const char *SymName, unsigned TargetFlags=0)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setIsDead(bool Val=true)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
unsigned getTargetFlags() const
static MachineOperand CreateImm(int64_t Val)
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags=0)
const char * getSymbolName() const
void setIsUndef(bool Val=true)
Register getReg() const
getReg - Returns the register number.
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
@ MO_CFIIndex
MCCFIInstruction index.
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
@ MO_Predicate
Generic predicate for ISel.
@ MO_GlobalAddress
Address of a global value.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_ShuffleMask
Other IR Constant for ISel (shuffle masks)
@ MO_CImmediate
Immediate >64bit operand.
@ MO_BlockAddress
Address of a basic block.
@ MO_DbgInstrRef
Integer indices referring to an instruction+operand.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_FrameIndex
Abstract Stack Frame Index.
@ MO_Register
Register operand.
@ MO_ExternalSymbol
Name of external global symbol.
@ MO_IntrinsicID
Intrinsic ID for ISel.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
@ MO_TargetIndex
Target-dependent index+offset operand.
@ MO_Metadata
Metadata reference (for debug info)
@ MO_FPImmediate
Floating-point immediate operand.
@ MO_RegisterLiveOut
Mask of live-out registers.
int64_t getOffset() const
Return the offset from the symbol in this operand.
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register.
TargetInstrInfo - Interface to description of machine instruction set.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetFrameLowering * getFrameLowering() const
virtual const TargetInstrInfo * getInstrInfo() const
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ GOT_PREL
Thread Local Storage (General Dynamic Mode)
@ MO_LO16
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address.
@ MO_LO_0_7
MO_LO_0_7 - On a symbol operand, this represents a relocation containing bits 0 through 7 of the addr...
@ MO_LO_8_15
MO_LO_8_15 - On a symbol operand, this represents a relocation containing bits 8 through 15 of the ad...
@ MO_HI_8_15
MO_HI_8_15 - On a symbol operand, this represents a relocation containing bits 24 through 31 of the a...
@ MO_HI16
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address.
@ MO_HI_0_7
MO_HI_0_7 - On a symbol operand, this represents a relocation containing bits 16 through 23 of the ad...
@ MO_GOT
MO_GOT - On a symbol operand, this represents a GOT relative relocation.
unsigned getSOImmTwoPartSecond(unsigned V)
getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, return the second chunk of ...
bool isSOImmTwoPartVal(unsigned V)
isSOImmTwoPartVal - Return true if the specified value can be obtained by or'ing together two SOImmVa...
unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm)
unsigned getSOImmTwoPartFirst(unsigned V)
getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, return the first chunk of it...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Define
Register definition.
@ Kill
The last use of a register.
@ Undef
Value of the register doesn't matter.
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)
bool operator<(int64_t V1, const APSInt &V2)
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
unsigned getDeadRegState(bool B)
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
void sort(IteratorTy Start, IteratorTy End)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool is_sorted(R &&Range, Compare C)
Wrapper function around std::is_sorted to check if elements in a range R are sorted with respect to a...
unsigned getUndefRegState(bool B)
unsigned getDefRegState(bool B)
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
unsigned getKillRegState(bool B)
void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immed...
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, Register &PredReg)
getInstrPredicate - If instruction is predicated, returns its predicate condition,...
unsigned getRenamableRegState(bool B)
static MachineOperand t1CondCodeOp(bool isDead=false)
Get the operand corresponding to the conditional code result for Thumb1.
void computeAndAddLiveIns(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB)
Convenience function combining computeLiveIns() and addLiveIns().
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
FunctionPass * createARMExpandPseudoPass()
createARMExpandPseudoPass - returns an instance of the pseudo instruction expansion pass.
unsigned gettBLXrOpcode(const MachineFunction &MF)
unsigned getBLXOpcode(const MachineFunction &MF)
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.