LLVM  17.0.0git
AArch64TargetTransformInfo.h
Go to the documentation of this file.
1 //===- AArch64TargetTransformInfo.h - AArch64 specific TTI ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file a TargetTransformInfo::Concept conforming object specific to the
10 /// AArch64 target machine. It uses the target's detailed information to
11 /// provide more precise answers to certain TTI queries, while letting the
12 /// target independent and default TTI implementations handle the rest.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
17 #define LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
18 
19 #include "AArch64.h"
20 #include "AArch64Subtarget.h"
21 #include "AArch64TargetMachine.h"
22 #include "llvm/ADT/ArrayRef.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/Intrinsics.h"
27 #include <cstdint>
28 #include <optional>
29 
30 namespace llvm {
31 
32 class APInt;
33 class Instruction;
34 class IntrinsicInst;
35 class Loop;
36 class SCEV;
37 class ScalarEvolution;
38 class Type;
39 class Value;
40 class VectorType;
41 
42 class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
44  using TTI = TargetTransformInfo;
45 
46  friend BaseT;
47 
48  const AArch64Subtarget *ST;
49  const AArch64TargetLowering *TLI;
50 
51  const AArch64Subtarget *getST() const { return ST; }
52  const AArch64TargetLowering *getTLI() const { return TLI; }
53 
54  enum MemIntrinsicType {
55  VECTOR_LDST_TWO_ELEMENTS,
56  VECTOR_LDST_THREE_ELEMENTS,
57  VECTOR_LDST_FOUR_ELEMENTS
58  };
59 
60  bool isWideningInstruction(Type *Ty, unsigned Opcode,
62 
63  // A helper function called by 'getVectorInstrCost'.
64  //
65  // 'Val' and 'Index' are forwarded from 'getVectorInstrCost'; 'HasRealUse'
66  // indicates whether the vector instruction is available in the input IR or
67  // just imaginary in vectorizer passes.
68  InstructionCost getVectorInstrCostHelper(Type *Val, unsigned Index,
69  bool HasRealUse);
70 
71 public:
72  explicit AArch64TTIImpl(const AArch64TargetMachine *TM, const Function &F)
73  : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
74  TLI(ST->getTargetLowering()) {}
75 
76  bool areInlineCompatible(const Function *Caller,
77  const Function *Callee) const;
78 
79  /// \name Scalar TTI Implementations
80  /// @{
81 
83  InstructionCost getIntImmCost(int64_t Val);
86  InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
87  const APInt &Imm, Type *Ty,
89  Instruction *Inst = nullptr);
91  const APInt &Imm, Type *Ty,
93  TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
94 
95  /// @}
96 
97  /// \name Vector TTI Implementations
98  /// @{
99 
100  bool enableInterleavedAccessVectorization() { return true; }
101 
102  unsigned getNumberOfRegisters(unsigned ClassID) const {
103  bool Vector = (ClassID == 1);
104  if (Vector) {
105  if (ST->hasNEON())
106  return 32;
107  return 0;
108  }
109  return 31;
110  }
111 
114 
115  std::optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
116  IntrinsicInst &II) const;
117 
118  std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
119  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
120  APInt &UndefElts2, APInt &UndefElts3,
121  std::function<void(Instruction *, unsigned, APInt, APInt &)>
122  SimplifyAndSetOp) const;
123 
125 
126  unsigned getMinVectorRegisterBitWidth() const {
127  return ST->getMinVectorRegisterBitWidth();
128  }
129 
130  std::optional<unsigned> getVScaleForTuning() const {
131  return ST->getVScaleForTuning();
132  }
133 
135 
136  /// Try to return an estimate cost factor that can be used as a multiplier
137  /// when scalarizing an operation for a vector with ElementCount \p VF.
138  /// For scalable vectors this currently takes the most pessimistic view based
139  /// upon the maximum possible value for vscale.
140  unsigned getMaxNumElements(ElementCount VF) const {
141  if (!VF.isScalable())
142  return VF.getFixedValue();
143 
144  return VF.getKnownMinValue() * ST->getVScaleForTuning();
145  }
146 
147  unsigned getMaxInterleaveFactor(unsigned VF);
148 
149  bool prefersVectorizedAddressing() const;
150 
151  InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
152  Align Alignment, unsigned AddressSpace,
154 
155  InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
156  const Value *Ptr, bool VariableMask,
157  Align Alignment,
159  const Instruction *I = nullptr);
160 
161  InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
164  const Instruction *I = nullptr);
165 
166  InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst,
167  VectorType *VecTy, unsigned Index);
168 
170  const Instruction *I = nullptr);
171 
172  InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
174  unsigned Index, Value *Op0, Value *Op1);
177  unsigned Index);
178 
180  bool IsUnsigned,
182 
184  VectorType *ValTy,
186 
188 
190  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
192  TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
193  ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
194  const Instruction *CxtI = nullptr);
195 
196  InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE,
197  const SCEV *Ptr);
198 
199  InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
200  CmpInst::Predicate VecPred,
202  const Instruction *I = nullptr);
203 
204  TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize,
205  bool IsZeroCmp) const;
206  bool useNeonVector(const Type *Ty) const;
207 
208  InstructionCost
209  getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment,
211  TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None},
212  const Instruction *I = nullptr);
213 
214  InstructionCost getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys);
215 
216  void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
217  TTI::UnrollingPreferences &UP,
218  OptimizationRemarkEmitter *ORE);
219 
220  void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
221  TTI::PeelingPreferences &PP);
222 
223  Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst,
224  Type *ExpectedType);
225 
226  bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info);
227 
229  if (Ty->isPointerTy())
230  return true;
231 
232  if (Ty->isBFloatTy() && ST->hasBF16())
233  return true;
234 
235  if (Ty->isHalfTy() || Ty->isFloatTy() || Ty->isDoubleTy())
236  return true;
237 
238  if (Ty->isIntegerTy(8) || Ty->isIntegerTy(16) ||
239  Ty->isIntegerTy(32) || Ty->isIntegerTy(64))
240  return true;
241 
242  return false;
243  }
244 
245  bool isLegalMaskedLoadStore(Type *DataType, Align Alignment) {
246  if (!ST->hasSVE())
247  return false;
248 
249  // For fixed vectors, avoid scalarization if using SVE for them.
250  if (isa<FixedVectorType>(DataType) && !ST->useSVEForFixedLengthVectors())
251  return false; // Fall back to scalarization of masked operations.
252 
254  }
255 
256  bool isLegalMaskedLoad(Type *DataType, Align Alignment) {
257  return isLegalMaskedLoadStore(DataType, Alignment);
258  }
259 
260  bool isLegalMaskedStore(Type *DataType, Align Alignment) {
261  return isLegalMaskedLoadStore(DataType, Alignment);
262  }
263 
264  bool isLegalMaskedGatherScatter(Type *DataType) const {
265  if (!ST->hasSVE() || ST->forceStreamingCompatibleSVE())
266  return false;
267 
268  // For fixed vectors, scalarize if not using SVE for them.
269  auto *DataTypeFVTy = dyn_cast<FixedVectorType>(DataType);
270  if (DataTypeFVTy && (!ST->useSVEForFixedLengthVectors() ||
271  DataTypeFVTy->getNumElements() < 2))
272  return false;
273 
275  }
276 
277  bool isLegalMaskedGather(Type *DataType, Align Alignment) const {
278  return isLegalMaskedGatherScatter(DataType);
279  }
280  bool isLegalMaskedScatter(Type *DataType, Align Alignment) const {
281  return isLegalMaskedGatherScatter(DataType);
282  }
283 
284  bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const {
285  // Return true if we can generate a `ld1r` splat load instruction.
286  if (!ST->hasNEON() || NumElements.isScalable())
287  return false;
288  switch (unsigned ElementBits = ElementTy->getScalarSizeInBits()) {
289  case 8:
290  case 16:
291  case 32:
292  case 64: {
293  // We accept bit-widths >= 64bits and elements {8,16,32,64} bits.
294  unsigned VectorBits = NumElements.getFixedValue() * ElementBits;
295  return VectorBits >= 64;
296  }
297  }
298  return false;
299  }
300 
301  bool isLegalNTStoreLoad(Type *DataType, Align Alignment) {
302  // NOTE: The logic below is mostly geared towards LV, which calls it with
303  // vectors with 2 elements. We might want to improve that, if other
304  // users show up.
305  // Nontemporal vector loads/stores can be directly lowered to LDNP/STNP, if
306  // the vector can be halved so that each half fits into a register. That's
307  // the case if the element type fits into a register and the number of
308  // elements is a power of 2 > 1.
309  if (auto *DataTypeTy = dyn_cast<FixedVectorType>(DataType)) {
310  unsigned NumElements = DataTypeTy->getNumElements();
311  unsigned EltSize = DataTypeTy->getElementType()->getScalarSizeInBits();
312  return NumElements > 1 && isPowerOf2_64(NumElements) && EltSize >= 8 &&
313  EltSize <= 128 && isPowerOf2_64(EltSize);
314  }
315  return BaseT::isLegalNTStore(DataType, Alignment);
316  }
317 
318  bool isLegalNTStore(Type *DataType, Align Alignment) {
319  return isLegalNTStoreLoad(DataType, Alignment);
320  }
321 
322  bool isLegalNTLoad(Type *DataType, Align Alignment) {
323  // Only supports little-endian targets.
324  if (ST->isLittleEndian())
325  return isLegalNTStoreLoad(DataType, Alignment);
326  return BaseT::isLegalNTLoad(DataType, Alignment);
327  }
328 
329  bool enableOrderedReductions() const { return true; }
330 
332  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
333  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
334  bool UseMaskForCond = false, bool UseMaskForGaps = false);
335 
336  bool
338  bool &AllowPromotionWithoutCommonHeader);
339 
340  bool shouldExpandReduction(const IntrinsicInst *II) const { return false; }
341 
342  unsigned getGISelRematGlobalCost() const {
343  return 2;
344  }
345 
347  return ST->hasSVE() ? 5 : 0;
348  }
349 
351  if (ST->hasSVE())
353  return PredicationStyle::None;
354  }
355 
358  DominatorTree *DT,
360  InterleavedAccessInfo *IAI);
361 
362  bool supportsScalableVectors() const { return ST->hasSVE(); }
363 
364  bool enableScalableVectorization() const { return ST->hasSVE(); }
365 
367  ElementCount VF) const;
368 
369  bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty,
370  TTI::ReductionFlags Flags) const {
371  return ST->hasSVE();
372  }
373 
375  std::optional<FastMathFlags> FMF,
377 
381  VectorType *SubTp,
382  ArrayRef<const Value *> Args = std::nullopt);
383 
384  /// Return the cost of the scaling factor used in the addressing
385  /// mode represented by AM for this target, for a load/store
386  /// of the specified type.
387  /// If the AM is supported, the return value must be >= 0.
388  /// If the AM is not supported, it returns a negative value.
390  int64_t BaseOffset, bool HasBaseReg,
391  int64_t Scale, unsigned AddrSpace) const;
392  /// @}
393 
394  bool enableSelectOptimize() { return ST->enableSelectOptimize(); }
395 };
396 
397 } // end namespace llvm
398 
399 #endif // LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
llvm::AArch64TTIImpl::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: AArch64TargetTransformInfo.cpp:264
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::AArch64TTIImpl::isLegalBroadcastLoad
bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
Definition: AArch64TargetTransformInfo.h:284
llvm::AArch64TTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
Definition: AArch64TargetTransformInfo.cpp:2724
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:217
llvm::AArch64TTIImpl::isLegalMaskedGatherScatter
bool isLegalMaskedGatherScatter(Type *DataType) const
Definition: AArch64TargetTransformInfo.h:264
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::TargetTransformInfo::ReductionFlags
Flags describing the kind of vector reduction.
Definition: TargetTransformInfo.h:1462
AArch64.h
llvm::AArch64TTIImpl::getVScaleForTuning
std::optional< unsigned > getVScaleForTuning() const
Definition: AArch64TargetTransformInfo.h:130
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:718
llvm::AArch64TTIImpl::getIntImmCost
InstructionCost getIntImmCost(int64_t Val)
Calculate the cost of materializing a 64-bit value.
Definition: AArch64TargetTransformInfo.cpp:155
llvm::Type::isPointerTy
bool isPointerTy() const
True if this is an instance of PointerType.
Definition: Type.h:249
llvm::ElementCount
Definition: TypeSize.h:279
llvm::AArch64TTIImpl::instCombineIntrinsic
std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Definition: AArch64TargetTransformInfo.cpp:1578
llvm::Function
Definition: Function.h:59
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:547
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:584
llvm::details::FixedOrScalableQuantity::isScalable
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:166
llvm::AArch64TTIImpl::emitGetActiveLaneMask
PredicationStyle emitGetActiveLaneMask() const
Definition: AArch64TargetTransformInfo.h:350
llvm::Type::getScalarType
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:341
llvm::AArch64TTIImpl::enableScalableVectorization
bool enableScalableVectorization() const
Definition: AArch64TargetTransformInfo.h:364
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:172
llvm::AArch64TTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: AArch64TargetTransformInfo.cpp:1683
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:452
llvm::LoopVectorizationLegality
LoopVectorizationLegality checks if it is legal to vectorize a loop, and to what vectorization factor...
Definition: LoopVectorizationLegality.h:241
llvm::AArch64TTIImpl::supportsScalableVectors
bool supportsScalableVectors() const
Definition: AArch64TargetTransformInfo.h:362
llvm::AArch64TTIImpl::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: AArch64TargetTransformInfo.h:342
llvm::AArch64TTIImpl::AArch64TTIImpl
AArch64TTIImpl(const AArch64TargetMachine *TM, const Function &F)
Definition: AArch64TargetTransformInfo.h:72
llvm::DominatorTree
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:166
llvm::AArch64TTIImpl::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: AArch64TargetTransformInfo.h:340
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::AArch64TTIImpl::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
Definition: AArch64TargetTransformInfo.cpp:2241
llvm::AArch64TTIImpl::isLegalNTLoad
bool isLegalNTLoad(Type *DataType, Align Alignment)
Definition: AArch64TargetTransformInfo.h:322
Vector
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::AArch64TTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: AArch64TargetTransformInfo.h:102
llvm::TargetTransformInfoImplBase::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:398
VectorType
Definition: ItaniumDemangle.h:1075
llvm::TargetTransformInfo::OperandValueInfo
Definition: TargetTransformInfo.h:928
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::AArch64TTIImpl::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: AArch64TargetTransformInfo.cpp:124
llvm::AArch64TTIImpl::getExtractWithExtendCost
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index)
Definition: AArch64TargetTransformInfo.cpp:2116
llvm::AArch64TTIImpl::getMaxNumElements
unsigned getMaxNumElements(ElementCount VF) const
Try to return an estimate cost factor that can be used as a multiplier when scalarizing an operation ...
Definition: AArch64TargetTransformInfo.h:140
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:47
llvm::AArch64TTIImpl::prefersVectorizedAddressing
bool prefersVectorizedAddressing() const
Definition: AArch64TargetTransformInfo.cpp:2503
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::AArch64TTIImpl::enableSelectOptimize
bool enableSelectOptimize()
Definition: AArch64TargetTransformInfo.h:394
AArch64TargetMachine.h
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:920
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:891
llvm::AArch64TTIImpl::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
Definition: AArch64TargetTransformInfo.cpp:2975
llvm::AArch64TTIImpl::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
Definition: AArch64TargetTransformInfo.cpp:2566
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1144
Intrinsics.h
llvm::AArch64TTIImpl::getCostOfKeepingLiveOverCall
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys)
Definition: AArch64TargetTransformInfo.cpp:2654
llvm::AArch64TTIImpl::preferPredicatedReductionSelect
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
Definition: AArch64TargetTransformInfo.h:369
llvm::dwarf::Index
Index
Definition: Dwarf.h:550
llvm::AArch64TTIImpl::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
Definition: AArch64TargetTransformInfo.cpp:195
llvm::Instruction
Definition: Instruction.h:41
llvm::InterleavedAccessInfo
Drive the analysis of interleaved memory accesses in the loop.
Definition: VectorUtils.h:765
llvm::Type::getScalarSizeInBits
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
Definition: Type.cpp:188
llvm::AArch64TargetMachine
Definition: AArch64TargetMachine.h:24
llvm::AArch64TTIImpl::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: AArch64TargetTransformInfo.cpp:1781
llvm::AArch64TTIImpl::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind)
Definition: AArch64TargetTransformInfo.cpp:2924
llvm::AArch64TTIImpl::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: AArch64TargetTransformInfo.h:126
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::AArch64TTIImpl::isLegalMaskedLoadStore
bool isLegalMaskedLoadStore(Type *DataType, Align Alignment)
Definition: AArch64TargetTransformInfo.h:245
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:119
llvm::PredicationStyle::DataAndControlFlow
@ DataAndControlFlow
llvm::AArch64TTIImpl::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Definition: AArch64TargetTransformInfo.cpp:325
llvm::Type::isIntegerTy
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:222
llvm::AArch64TTIImpl::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Definition: AArch64TargetTransformInfo.cpp:2626
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::AArch64TTIImpl::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=std::nullopt)
Definition: AArch64TargetTransformInfo.cpp:3131
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::AArch64TTIImpl::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
Definition: AArch64TargetTransformInfo.cpp:2508
llvm::TargetTransformInfoImplBase::isLegalNTStore
bool isLegalNTStore(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:249
llvm::AArch64TTIImpl
Definition: AArch64TargetTransformInfo.h:42
llvm::AArch64TTIImpl::getArithmeticReductionCostSVE
InstructionCost getArithmeticReductionCostSVE(unsigned Opcode, VectorType *ValTy, TTI::TargetCostKind CostKind)
Definition: AArch64TargetTransformInfo.cpp:2949
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::BasicTTIImplBase
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:79
ArrayRef.h
TemplateParamKind::Type
@ Type
llvm::Type::isHalfTy
bool isHalfTy() const
Return true if this is 'half', a 16-bit IEEE fp type.
Definition: Type.h:143
llvm::AArch64TTIImpl::isLegalToVectorizeReduction
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
Definition: AArch64TargetTransformInfo.cpp:2893
llvm::details::FixedOrScalableQuantity::getFixedValue
constexpr ScalarTy getFixedValue() const
Definition: TypeSize.h:182
llvm::AArch64TTIImpl::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Definition: AArch64TargetTransformInfo.h:277
Ptr
@ Ptr
Definition: TargetLibraryInfo.cpp:62
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::AArch64TTIImpl::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF)
Definition: AArch64TargetTransformInfo.cpp:2668
llvm::AArch64TTIImpl::getSpliceCost
InstructionCost getSpliceCost(VectorType *Tp, int Index)
Definition: AArch64TargetTransformInfo.cpp:3075
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::AArch64TTIImpl::simplifyDemandedVectorEltsIntrinsic
std::optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Definition: AArch64TargetTransformInfo.cpp:1656
llvm::SystemZ::VectorBits
const unsigned VectorBits
Definition: SystemZ.h:154
llvm::TargetTransformInfoImplBase::isLegalNTLoad
bool isLegalNTLoad(Type *DataType, Align Alignment) const
Definition: TargetTransformInfoImpl.h:256
llvm::AArch64TTIImpl::getMinTripCountTailFoldingThreshold
unsigned getMinTripCountTailFoldingThreshold() const
Definition: AArch64TargetTransformInfo.h:346
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:33
llvm::LoopInfo
Definition: LoopInfo.h:1108
llvm::AArch64TTIImpl::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization()
Definition: AArch64TargetTransformInfo.h:100
llvm::details::FixedOrScalableQuantity::getKnownMinValue
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
Definition: TypeSize.h:163
llvm::AssumptionCache
A cache of @llvm.assume calls within a function.
Definition: AssumptionCache.h:42
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:806
llvm::AArch64TTIImpl::enableOrderedReductions
bool enableOrderedReductions() const
Definition: AArch64TargetTransformInfo.h:329
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:912
llvm::AArch64TTIImpl::getPopcntSupport
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
Definition: AArch64TargetTransformInfo.cpp:316
llvm::AArch64TTIImpl::isLegalNTStore
bool isLegalNTStore(Type *DataType, Align Alignment)
Definition: AArch64TargetTransformInfo.h:318
llvm::AArch64TTIImpl::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: AArch64TargetTransformInfo.cpp:2418
llvm::Type::isFloatTy
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
Definition: Type.h:154
llvm::TypeSize
Definition: TypeSize.h:314
llvm::AArch64TTIImpl::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info)
Definition: AArch64TargetTransformInfo.cpp:2821
Function.h
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:234
llvm::Type::isDoubleTy
bool isDoubleTy() const
Return true if this is 'double', a 64-bit IEEE fp type.
Definition: Type.h:157
llvm::AArch64TTIImpl::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: AArch64TargetTransformInfo.cpp:2177
llvm::PredicationStyle
PredicationStyle
Definition: TargetTransformInfo.h:165
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:47
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::AArch64TTIImpl::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Definition: AArch64TargetTransformInfo.h:280
llvm::RecurrenceDescriptor
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:69
llvm::AArch64TTIImpl::getScalingFactorCost
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
Definition: AArch64TargetTransformInfo.cpp:3385
AArch64Subtarget.h
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:969
llvm::Type::isBFloatTy
bool isBFloatTy() const
Return true if this is 'bfloat', a 16-bit bfloat type.
Definition: Type.h:146
llvm::AArch64TTIImpl::isLegalNTStoreLoad
bool isLegalNTStoreLoad(Type *DataType, Align Alignment)
Definition: AArch64TargetTransformInfo.h:301
TargetTransformInfo.h
llvm::AArch64TTIImpl::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: AArch64TargetTransformInfo.cpp:2532
llvm::AArch64TTIImpl::preferPredicateOverEpilogue
bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, LoopVectorizationLegality *LVL, InterleavedAccessInfo *IAI)
Definition: AArch64TargetTransformInfo.cpp:3360
llvm::AArch64TTIImpl::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: AArch64TargetTransformInfo.cpp:2780
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::AArch64TTIImpl::shouldMaximizeVectorBandwidth
bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
Definition: AArch64TargetTransformInfo.cpp:146
llvm::AArch64TTIImpl::shouldConsiderAddressTypePromotion
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader)
See if I should be considered for address type promotion.
Definition: AArch64TargetTransformInfo.cpp:2866
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
BasicTTIImpl.h
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::AArch64TargetLowering
Definition: AArch64ISelLowering.h:510
llvm::AArch64TTIImpl::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
Definition: AArch64TargetTransformInfo.cpp:2227
llvm::AArch64TTIImpl::isElementTypeLegalForScalableVector
bool isElementTypeLegalForScalableVector(Type *Ty) const
Definition: AArch64TargetTransformInfo.h:228
llvm::isPowerOf2_64
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
Definition: MathExtras.h:293
llvm::AArch64TTIImpl::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment)
Definition: AArch64TargetTransformInfo.h:256
llvm::PredicationStyle::None
@ None
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::AArch64TTIImpl::useNeonVector
bool useNeonVector(const Type *Ty) const
Definition: AArch64TargetTransformInfo.cpp:2562
llvm::AArch64TTIImpl::getOrCreateResultFromMemIntrinsic
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType)
Definition: AArch64TargetTransformInfo.cpp:2785
llvm::AArch64TTIImpl::enableMemCmpExpansion
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
Definition: AArch64TargetTransformInfo.cpp:2486
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:39
llvm::AArch64TTIImpl::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE, const SCEV *Ptr)
Definition: AArch64TargetTransformInfo.cpp:2399
llvm::AArch64TTIImpl::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment)
Definition: AArch64TargetTransformInfo.h:260