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16 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
17 #define LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
37 class ScalarEvolution;
54 enum MemIntrinsicType {
55 VECTOR_LDST_TWO_ELEMENTS,
56 VECTOR_LDST_THREE_ELEMENTS,
57 VECTOR_LDST_FOUR_ELEMENTS
60 bool isWideningInstruction(
Type *Ty,
unsigned Opcode,
74 TLI(ST->getTargetLowering()) {}
103 bool Vector = (ClassID == 1);
122 SimplifyAndSetOp)
const;
127 return ST->getMinVectorRegisterBitWidth();
131 return ST->getVScaleForTuning();
156 const Value *
Ptr,
bool VariableMask,
193 ArrayRef<const Value *>
Args = ArrayRef<const Value *>(),
194 const Instruction *CxtI =
nullptr);
202 const Instruction *
I =
nullptr);
205 bool IsZeroCmp)
const;
212 const Instruction *
I =
nullptr);
217 TTI::UnrollingPreferences &UP,
218 OptimizationRemarkEmitter *ORE);
221 TTI::PeelingPreferences &PP);
250 if (isa<FixedVectorType>(DataType) && !ST->useSVEForFixedLengthVectors())
265 if (!ST->hasSVE() || ST->forceStreamingCompatibleSVE())
269 auto *DataTypeFVTy = dyn_cast<FixedVectorType>(DataType);
270 if (DataTypeFVTy && (!ST->useSVEForFixedLengthVectors() ||
271 DataTypeFVTy->getNumElements() < 2))
286 if (!ST->hasNEON() || NumElements.
isScalable())
309 if (
auto *DataTypeTy = dyn_cast<FixedVectorType>(DataType)) {
310 unsigned NumElements = DataTypeTy->getNumElements();
311 unsigned EltSize = DataTypeTy->getElementType()->getScalarSizeInBits();
312 return NumElements > 1 &&
isPowerOf2_64(NumElements) && EltSize >= 8 &&
324 if (ST->isLittleEndian())
334 bool UseMaskForCond =
false,
bool UseMaskForGaps =
false);
338 bool &AllowPromotionWithoutCommonHeader);
347 return ST->hasSVE() ? 5 : 0;
375 std::optional<FastMathFlags> FMF,
390 int64_t BaseOffset,
bool HasBaseReg,
391 int64_t Scale,
unsigned AddrSpace)
const;
399 #endif // LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
bool isLegalMaskedGatherScatter(Type *DataType) const
This is an optimization pass for GlobalISel generic memory operations.
std::optional< unsigned > getVScaleForTuning() const
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
InstructionCost getIntImmCost(int64_t Val)
Calculate the cost of materializing a 64-bit value.
bool isPointerTy() const
True if this is an instance of PointerType.
std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Represents a single loop in the control flow graph.
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
PredicationStyle emitGetActiveLaneMask() const
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
bool enableScalableVectorization() const
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
The main scalar evolution driver.
LoopVectorizationLegality checks if it is legal to vectorize a loop, and to what vectorization factor...
bool supportsScalableVectors() const
unsigned getGISelRematGlobalCost() const
AArch64TTIImpl(const AArch64TargetMachine *TM, const Function &F)
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
bool shouldExpandReduction(const IntrinsicInst *II) const
The instances of the Type class are immutable: once they are created, they are never changed.
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
bool isLegalNTLoad(Type *DataType, Align Alignment)
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
unsigned getNumberOfRegisters(unsigned ClassID) const
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index)
unsigned getMaxNumElements(ElementCount VF) const
Try to return an estimate cost factor that can be used as a multiplier when scalarizing an operation ...
bool prefersVectorizedAddressing() const
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
bool enableSelectOptimize()
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys)
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
Drive the analysis of interleaved memory accesses in the loop.
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind)
unsigned getMinVectorRegisterBitWidth() const
Analysis containing CSE Info
This struct is a compact representation of a valid (non-zero power of two) alignment.
bool isLegalMaskedLoadStore(Type *DataType, Align Alignment)
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
bool isIntegerTy() const
True if this is an instance of IntegerType.
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Base class of all SIMD vector types.
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=std::nullopt)
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
InstructionCost getArithmeticReductionCostSVE(unsigned Opcode, VectorType *ValTy, TTI::TargetCostKind CostKind)
Base class which can be used to help build a TTI implementation.
bool isHalfTy() const
Return true if this is 'half', a 16-bit IEEE fp type.
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
constexpr ScalarTy getFixedValue() const
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
print Print MemDeps of function
unsigned getMaxInterleaveFactor(unsigned VF)
InstructionCost getSpliceCost(VectorType *Tp, int Index)
Class for arbitrary precision integers.
std::optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
const unsigned VectorBits
unsigned getMinTripCountTailFoldingThreshold() const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool enableInterleavedAccessVectorization()
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
A cache of @llvm.assume calls within a function.
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
static const Function * getParent(const Value *V)
bool enableOrderedReductions() const
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
bool isLegalNTStore(Type *DataType, Align Alignment)
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info)
Provides information about what library functions are available for the current target.
bool isDoubleTy() const
Return true if this is 'double', a 64-bit IEEE fp type.
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
The core instruction combiner logic.
A wrapper class for inspecting calls to intrinsic functions.
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
bool isBFloatTy() const
Return true if this is 'bfloat', a 16-bit bfloat type.
bool isLegalNTStoreLoad(Type *DataType, Align Alignment)
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, LoopVectorizationLegality *LVL, InterleavedAccessInfo *IAI)
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
const char LLVMTargetMachineRef TM
bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader)
See if I should be considered for address type promotion.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
bool isElementTypeLegalForScalableVector(Type *Ty) const
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
bool isLegalMaskedLoad(Type *DataType, Align Alignment)
LLVM Value Representation.
bool useNeonVector(const Type *Ty) const
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType)
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE, const SCEV *Ptr)
bool isLegalMaskedStore(Type *DataType, Align Alignment)