LLVM  11.0.0git
AArch64TargetTransformInfo.h
Go to the documentation of this file.
1 //===- AArch64TargetTransformInfo.h - AArch64 specific TTI ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file a TargetTransformInfo::Concept conforming object specific to the
10 /// AArch64 target machine. It uses the target's detailed information to
11 /// provide more precise answers to certain TTI queries, while letting the
12 /// target independent and default TTI implementations handle the rest.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
17 #define LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
18 
19 #include "AArch64.h"
20 #include "AArch64Subtarget.h"
21 #include "AArch64TargetMachine.h"
22 #include "llvm/ADT/ArrayRef.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/Intrinsics.h"
27 #include <cstdint>
28 
29 namespace llvm {
30 
31 class APInt;
32 class Instruction;
33 class IntrinsicInst;
34 class Loop;
35 class SCEV;
36 class ScalarEvolution;
37 class Type;
38 class Value;
39 class VectorType;
40 
41 class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
43  using TTI = TargetTransformInfo;
44 
45  friend BaseT;
46 
47  const AArch64Subtarget *ST;
48  const AArch64TargetLowering *TLI;
49 
50  const AArch64Subtarget *getST() const { return ST; }
51  const AArch64TargetLowering *getTLI() const { return TLI; }
52 
53  enum MemIntrinsicType {
54  VECTOR_LDST_TWO_ELEMENTS,
55  VECTOR_LDST_THREE_ELEMENTS,
56  VECTOR_LDST_FOUR_ELEMENTS
57  };
58 
59  bool isWideningInstruction(Type *Ty, unsigned Opcode,
61 
62 public:
63  explicit AArch64TTIImpl(const AArch64TargetMachine *TM, const Function &F)
64  : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
65  TLI(ST->getTargetLowering()) {}
66 
67  bool areInlineCompatible(const Function *Caller,
68  const Function *Callee) const;
69 
70  /// \name Scalar TTI Implementations
71  /// @{
72 
74  int getIntImmCost(int64_t Val);
75  int getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind);
76  int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm,
77  Type *Ty, TTI::TargetCostKind CostKind);
78  int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
79  Type *Ty, TTI::TargetCostKind CostKind);
80  TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
81 
82  /// @}
83 
84  /// \name Vector TTI Implementations
85  /// @{
86 
87  bool enableInterleavedAccessVectorization() { return true; }
88 
89  unsigned getNumberOfRegisters(unsigned ClassID) const {
90  bool Vector = (ClassID == 1);
91  if (Vector) {
92  if (ST->hasNEON())
93  return 32;
94  return 0;
95  }
96  return 31;
97  }
98 
99  unsigned getRegisterBitWidth(bool Vector) const {
100  if (Vector) {
101  if (ST->hasNEON())
102  return 128;
103  return 0;
104  }
105  return 64;
106  }
107 
109  return ST->getMinVectorRegisterBitWidth();
110  }
111 
112  unsigned getMaxInterleaveFactor(unsigned VF);
113 
114  int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
115  TTI::TargetCostKind CostKind,
116  const Instruction *I = nullptr);
117 
118  int getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy,
119  unsigned Index);
120 
121  int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
122 
124  unsigned Opcode, Type *Ty,
131  const Instruction *CxtI = nullptr);
132 
133  int getAddressComputationCost(Type *Ty, ScalarEvolution *SE, const SCEV *Ptr);
134 
135  int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
136  TTI::TargetCostKind CostKind,
137  const Instruction *I = nullptr);
138 
140  bool IsZeroCmp) const;
141 
142  int getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment,
143  unsigned AddressSpace,
144  TTI::TargetCostKind CostKind,
145  const Instruction *I = nullptr);
146 
148 
151 
153  Type *ExpectedType);
154 
156 
158  if (!isa<VectorType>(DataType) || !ST->hasSVE())
159  return false;
160 
161  Type *Ty = cast<VectorType>(DataType)->getElementType();
162  if (Ty->isHalfTy() || Ty->isFloatTy() || Ty->isDoubleTy())
163  return true;
164 
165  if (Ty->isIntegerTy(8) || Ty->isIntegerTy(16) ||
166  Ty->isIntegerTy(32) || Ty->isIntegerTy(64))
167  return true;
168 
169  return false;
170  }
171 
173  return isLegalMaskedLoadStore(DataType, Alignment);
174  }
175 
177  return isLegalMaskedLoadStore(DataType, Alignment);
178  }
179 
180  bool isLegalNTStore(Type *DataType, Align Alignment) {
181  // NOTE: The logic below is mostly geared towards LV, which calls it with
182  // vectors with 2 elements. We might want to improve that, if other
183  // users show up.
184  // Nontemporal vector stores can be directly lowered to STNP, if the vector
185  // can be halved so that each half fits into a register. That's the case if
186  // the element type fits into a register and the number of elements is a
187  // power of 2 > 1.
188  if (auto *DataTypeVTy = dyn_cast<VectorType>(DataType)) {
189  unsigned NumElements = DataTypeVTy->getNumElements();
190  unsigned EltSize = DataTypeVTy->getElementType()->getScalarSizeInBits();
191  return NumElements > 1 && isPowerOf2_64(NumElements) && EltSize >= 8 &&
192  EltSize <= 128 && isPowerOf2_64(EltSize);
193  }
194  return BaseT::isLegalNTStore(DataType, Alignment);
195  }
196 
197  int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor,
198  ArrayRef<unsigned> Indices, unsigned Alignment,
199  unsigned AddressSpace,
201  bool UseMaskForCond = false,
202  bool UseMaskForGaps = false);
203 
204  bool
206  bool &AllowPromotionWithoutCommonHeader);
207 
208  bool shouldExpandReduction(const IntrinsicInst *II) const {
209  switch (II->getIntrinsicID()) {
210  case Intrinsic::experimental_vector_reduce_v2_fadd:
211  case Intrinsic::experimental_vector_reduce_v2_fmul:
212  // We don't have legalization support for ordered FP reductions.
213  return !II->getFastMathFlags().allowReassoc();
214 
215  case Intrinsic::experimental_vector_reduce_fmax:
216  case Intrinsic::experimental_vector_reduce_fmin:
217  // Lowering asserts that there are no NaNs.
218  return !II->getFastMathFlags().noNaNs();
219 
220  default:
221  // Don't expand anything else, let legalization deal with it.
222  return false;
223  }
224  }
225 
226  unsigned getGISelRematGlobalCost() const {
227  return 2;
228  }
229 
230  bool useReductionIntrinsic(unsigned Opcode, Type *Ty,
231  TTI::ReductionFlags Flags) const;
232 
233  int getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
234  bool IsPairwiseForm,
236 
237  int getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, int Index,
238  VectorType *SubTp);
239  /// @}
240 };
241 
242 } // end namespace llvm
243 
244 #endif // LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
bool noNaNs() const
Definition: Operator.h:206
This class represents lattice values for constants.
Definition: AllocatorList.h:23
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
int getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value *> Args=ArrayRef< const Value *>(), const Instruction *CxtI=nullptr)
The main scalar evolution driver.
unsigned getRegisterBitWidth(bool Vector) const
F(f)
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:76
unsigned getMaxInterleaveFactor(unsigned VF)
int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, unsigned Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, bool UseMaskForCond=false, bool UseMaskForGaps=false)
bool isLegalNTStore(Type *DataType, Align Alignment)
int getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index)
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size")))
int getAddressComputationCost(Type *Ty, ScalarEvolution *SE, const SCEV *Ptr)
int getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
int getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, int Index, VectorType *SubTp)
int getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, bool IsPairwiseForm, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput)
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:198
FastMathFlags getFastMathFlags() const
Convenience function for getting all the fast-math flags, which must be an operator which supports th...
PopcntSupportKind
Flags indicating the kind of support for population count.
int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
Analysis containing CSE Info
Definition: CSEInfo.cpp:25
The weighted sum of size and latency.
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info)
unsigned getMinVectorRegisterBitWidth() const
bool isFloatTy() const
Return true if this is &#39;float&#39;, a 32-bit IEEE fp type.
Definition: Type.h:147
bool useReductionIntrinsic(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
Returns options for expansion of memcmp. IsZeroCmp is.
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType)
int getIntImmCost(int64_t Val)
Calculate the cost of materializing a 64-bit value.
Flags describing the kind of vector reduction.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader)
See if I should be considered for address type promotion.
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
Definition: MathExtras.h:497
bool isHalfTy() const
Return true if this is &#39;half&#39;, a 16-bit IEEE fp type.
Definition: Type.h:141
This file provides a helper that implements much of the TTI interface in terms of the target-independ...
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
bool isLegalNTStore(Type *DataType, Align Alignment)
bool shouldExpandReduction(const IntrinsicInst *II) const
AArch64TTIImpl(const AArch64TargetMachine *TM, const Function &F)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
OperandValueProperties
Additional properties of an operand&#39;s values.
int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:51
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment...
Definition: Alignment.h:119
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
int getCostOfKeepingLiveOverCall(ArrayRef< Type *> Tys)
AddressSpace
Definition: NVPTXBaseInfo.h:21
bool isLegalMaskedStore(Type *DataType, MaybeAlign Alignment)
unsigned getNumberOfRegisters(unsigned ClassID) const
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP)
bool isLegalMaskedLoad(Type *DataType, MaybeAlign Alignment)
Base class of all SIMD vector types.
Definition: DerivedTypes.h:390
Class for arbitrary precision integers.
Definition: APInt.h:69
amdgpu Simplify well known AMD library false FunctionCallee Callee
bool isLegalMaskedLoadStore(Type *DataType, MaybeAlign Alignment)
unsigned getGISelRematGlobalCost() const
This class represents an analyzed expression in the program.
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:516
Parameters that control the generic loop unrolling transformation.
#define I(x, y, z)
Definition: MD5.cpp:59
unsigned getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
LLVM Value Representation.
Definition: Value.h:74
static const Function * getParent(const Value *V)
bool allowReassoc() const
Flag queries.
Definition: Operator.h:205
const DataLayout & getDataLayout() const
OperandValueKind
Additional information about an operand&#39;s possible values.
This pass exposes codegen information to IR-level passes.
TargetCostKind
The kind of cost model.
bool isDoubleTy() const
Return true if this is &#39;double&#39;, a 64-bit IEEE fp type.
Definition: Type.h:150
Information about a load/store intrinsic defined by the target.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:44
ShuffleKind
The various kinds of shuffle patterns for vector queries.