LLVM 19.0.0git
AArch64TargetTransformInfo.h
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1//===- AArch64TargetTransformInfo.h - AArch64 specific TTI ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file a TargetTransformInfo::Concept conforming object specific to the
10/// AArch64 target machine. It uses the target's detailed information to
11/// provide more precise answers to certain TTI queries, while letting the
12/// target independent and default TTI implementations handle the rest.
13///
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
17#define LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
18
19#include "AArch64.h"
20#include "AArch64Subtarget.h"
22#include "llvm/ADT/ArrayRef.h"
25#include "llvm/IR/Function.h"
26#include "llvm/IR/Intrinsics.h"
27#include <cstdint>
28#include <optional>
29
30namespace llvm {
31
32class APInt;
33class Instruction;
34class IntrinsicInst;
35class Loop;
36class SCEV;
37class ScalarEvolution;
38class Type;
39class Value;
40class VectorType;
41
42class AArch64TTIImpl : public BasicTTIImplBase<AArch64TTIImpl> {
45
46 friend BaseT;
47
48 const AArch64Subtarget *ST;
49 const AArch64TargetLowering *TLI;
50
51 const AArch64Subtarget *getST() const { return ST; }
52 const AArch64TargetLowering *getTLI() const { return TLI; }
53
54 enum MemIntrinsicType {
55 VECTOR_LDST_TWO_ELEMENTS,
56 VECTOR_LDST_THREE_ELEMENTS,
57 VECTOR_LDST_FOUR_ELEMENTS
58 };
59
60 bool isWideningInstruction(Type *DstTy, unsigned Opcode,
62 Type *SrcOverrideTy = nullptr);
63
64 // A helper function called by 'getVectorInstrCost'.
65 //
66 // 'Val' and 'Index' are forwarded from 'getVectorInstrCost'; 'HasRealUse'
67 // indicates whether the vector instruction is available in the input IR or
68 // just imaginary in vectorizer passes.
69 InstructionCost getVectorInstrCostHelper(const Instruction *I, Type *Val,
70 unsigned Index, bool HasRealUse);
71
72public:
74 : BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)),
75 TLI(ST->getTargetLowering()) {}
76
77 bool areInlineCompatible(const Function *Caller,
78 const Function *Callee) const;
79
80 bool areTypesABICompatible(const Function *Caller, const Function *Callee,
81 const ArrayRef<Type *> &Types) const;
82
83 unsigned getInlineCallPenalty(const Function *F, const CallBase &Call,
84 unsigned DefaultCallPenalty) const;
85
86 /// \name Scalar TTI Implementations
87 /// @{
88
90 InstructionCost getIntImmCost(int64_t Val);
93 InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
94 const APInt &Imm, Type *Ty,
96 Instruction *Inst = nullptr);
98 const APInt &Imm, Type *Ty,
101
102 /// @}
103
104 /// \name Vector TTI Implementations
105 /// @{
106
108
109 bool enableMaskedInterleavedAccessVectorization() { return ST->hasSVE(); }
110
111 unsigned getNumberOfRegisters(unsigned ClassID) const {
112 bool Vector = (ClassID == 1);
113 if (Vector) {
114 if (ST->hasNEON())
115 return 32;
116 return 0;
117 }
118 return 31;
119 }
120
123
124 std::optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
125 IntrinsicInst &II) const;
126
127 std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
128 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
129 APInt &UndefElts2, APInt &UndefElts3,
130 std::function<void(Instruction *, unsigned, APInt, APInt &)>
131 SimplifyAndSetOp) const;
132
134
136 return ST->getMinVectorRegisterBitWidth();
137 }
138
139 std::optional<unsigned> getVScaleForTuning() const {
140 return ST->getVScaleForTuning();
141 }
142
143 bool isVScaleKnownToBeAPowerOfTwo() const { return true; }
144
146
147 /// Try to return an estimate cost factor that can be used as a multiplier
148 /// when scalarizing an operation for a vector with ElementCount \p VF.
149 /// For scalable vectors this currently takes the most pessimistic view based
150 /// upon the maximum possible value for vscale.
151 unsigned getMaxNumElements(ElementCount VF) const {
152 if (!VF.isScalable())
153 return VF.getFixedValue();
154
155 return VF.getKnownMinValue() * ST->getVScaleForTuning();
156 }
157
159
160 bool prefersVectorizedAddressing() const;
161
162 InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
163 Align Alignment, unsigned AddressSpace,
165
166 InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
167 const Value *Ptr, bool VariableMask,
168 Align Alignment,
170 const Instruction *I = nullptr);
171
172 bool isExtPartOfAvgExpr(const Instruction *ExtUser, Type *Dst, Type *Src);
173
174 InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
177 const Instruction *I = nullptr);
178
179 InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst,
180 VectorType *VecTy, unsigned Index);
181
183 const Instruction *I = nullptr);
184
185 InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
187 unsigned Index, Value *Op0, Value *Op1);
190 unsigned Index);
191
193 FastMathFlags FMF,
195
197 VectorType *ValTy,
199
201
203 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
205 TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
206 ArrayRef<const Value *> Args = std::nullopt,
207 const Instruction *CxtI = nullptr);
208
209 InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE,
210 const SCEV *Ptr);
211
212 InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
213 CmpInst::Predicate VecPred,
215 const Instruction *I = nullptr);
216
217 TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize,
218 bool IsZeroCmp) const;
219 bool useNeonVector(const Type *Ty) const;
220
221 InstructionCost
222 getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment,
224 TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None},
225 const Instruction *I = nullptr);
226
227 InstructionCost getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys);
228
229 void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
230 TTI::UnrollingPreferences &UP,
231 OptimizationRemarkEmitter *ORE);
232
233 void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
234 TTI::PeelingPreferences &PP);
235
236 Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst,
237 Type *ExpectedType);
238
239 bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info);
240
242 if (Ty->isPointerTy())
243 return true;
244
245 if (Ty->isBFloatTy() && ST->hasBF16())
246 return true;
247
248 if (Ty->isHalfTy() || Ty->isFloatTy() || Ty->isDoubleTy())
249 return true;
250
251 if (Ty->isIntegerTy(1) || Ty->isIntegerTy(8) || Ty->isIntegerTy(16) ||
252 Ty->isIntegerTy(32) || Ty->isIntegerTy(64))
253 return true;
254
255 return false;
256 }
257
258 bool isLegalMaskedLoadStore(Type *DataType, Align Alignment) {
259 if (!ST->hasSVE())
260 return false;
261
262 // For fixed vectors, avoid scalarization if using SVE for them.
263 if (isa<FixedVectorType>(DataType) && !ST->useSVEForFixedLengthVectors() &&
264 DataType->getPrimitiveSizeInBits() != 128)
265 return false; // Fall back to scalarization of masked operations.
266
268 }
269
270 bool isLegalMaskedLoad(Type *DataType, Align Alignment) {
271 return isLegalMaskedLoadStore(DataType, Alignment);
272 }
273
274 bool isLegalMaskedStore(Type *DataType, Align Alignment) {
275 return isLegalMaskedLoadStore(DataType, Alignment);
276 }
277
278 bool isLegalMaskedGatherScatter(Type *DataType) const {
279 if (!ST->isSVEAvailable())
280 return false;
281
282 // For fixed vectors, scalarize if not using SVE for them.
283 auto *DataTypeFVTy = dyn_cast<FixedVectorType>(DataType);
284 if (DataTypeFVTy && (!ST->useSVEForFixedLengthVectors() ||
285 DataTypeFVTy->getNumElements() < 2))
286 return false;
287
289 }
290
291 bool isLegalMaskedGather(Type *DataType, Align Alignment) const {
292 return isLegalMaskedGatherScatter(DataType);
293 }
294
295 bool isLegalMaskedScatter(Type *DataType, Align Alignment) const {
296 return isLegalMaskedGatherScatter(DataType);
297 }
298
299 bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const {
300 // Return true if we can generate a `ld1r` splat load instruction.
301 if (!ST->hasNEON() || NumElements.isScalable())
302 return false;
303 switch (unsigned ElementBits = ElementTy->getScalarSizeInBits()) {
304 case 8:
305 case 16:
306 case 32:
307 case 64: {
308 // We accept bit-widths >= 64bits and elements {8,16,32,64} bits.
309 unsigned VectorBits = NumElements.getFixedValue() * ElementBits;
310 return VectorBits >= 64;
311 }
312 }
313 return false;
314 }
315
316 bool isLegalNTStoreLoad(Type *DataType, Align Alignment) {
317 // NOTE: The logic below is mostly geared towards LV, which calls it with
318 // vectors with 2 elements. We might want to improve that, if other
319 // users show up.
320 // Nontemporal vector loads/stores can be directly lowered to LDNP/STNP, if
321 // the vector can be halved so that each half fits into a register. That's
322 // the case if the element type fits into a register and the number of
323 // elements is a power of 2 > 1.
324 if (auto *DataTypeTy = dyn_cast<FixedVectorType>(DataType)) {
325 unsigned NumElements = DataTypeTy->getNumElements();
326 unsigned EltSize = DataTypeTy->getElementType()->getScalarSizeInBits();
327 return NumElements > 1 && isPowerOf2_64(NumElements) && EltSize >= 8 &&
328 EltSize <= 128 && isPowerOf2_64(EltSize);
329 }
330 return BaseT::isLegalNTStore(DataType, Alignment);
331 }
332
333 bool isLegalNTStore(Type *DataType, Align Alignment) {
334 return isLegalNTStoreLoad(DataType, Alignment);
335 }
336
337 bool isLegalNTLoad(Type *DataType, Align Alignment) {
338 // Only supports little-endian targets.
339 if (ST->isLittleEndian())
340 return isLegalNTStoreLoad(DataType, Alignment);
341 return BaseT::isLegalNTLoad(DataType, Alignment);
342 }
343
344 bool enableOrderedReductions() const { return true; }
345
347 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
348 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
349 bool UseMaskForCond = false, bool UseMaskForGaps = false);
350
351 bool
353 bool &AllowPromotionWithoutCommonHeader);
354
355 bool shouldExpandReduction(const IntrinsicInst *II) const { return false; }
356
357 unsigned getGISelRematGlobalCost() const {
358 return 2;
359 }
360
362 return ST->hasSVE() ? 5 : 0;
363 }
364
365 TailFoldingStyle getPreferredTailFoldingStyle(bool IVUpdateMayOverflow) const {
366 if (ST->hasSVE())
367 return IVUpdateMayOverflow
370
372 }
373
375
377 return ST->isSVEorStreamingSVEAvailable();
378 }
379
380 bool enableScalableVectorization() const { return ST->isSVEAvailable(); }
381
383 ElementCount VF) const;
384
385 bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty,
386 TTI::ReductionFlags Flags) const {
387 return ST->hasSVE();
388 }
389
391 std::optional<FastMathFlags> FMF,
393
395 ArrayRef<int> Mask,
397 VectorType *SubTp,
398 ArrayRef<const Value *> Args = std::nullopt,
399 const Instruction *CxtI = nullptr);
400
402 const APInt &DemandedElts,
403 bool Insert, bool Extract,
405
406 /// Return the cost of the scaling factor used in the addressing
407 /// mode represented by AM for this target, for a load/store
408 /// of the specified type.
409 /// If the AM is supported, the return value must be >= 0.
410 /// If the AM is not supported, it returns a negative value.
412 StackOffset BaseOffset, bool HasBaseReg,
413 int64_t Scale, unsigned AddrSpace) const;
414 /// @}
415
416 bool enableSelectOptimize() { return ST->enableSelectOptimize(); }
417
419
420 unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy,
421 Type *ScalarValTy) const {
422 // We can vectorize store v4i8.
423 if (ScalarMemTy->isIntegerTy(8) && isPowerOf2_32(VF) && VF >= 4)
424 return 4;
425
426 return BaseT::getStoreMinimumVF(VF, ScalarMemTy, ScalarValTy);
427 }
428
429 std::optional<unsigned> getMinPageSize() const { return 4096; }
430
433};
434
435} // end namespace llvm
436
437#endif // LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
This file provides a helper that implements much of the TTI interface in terms of the target-independ...
RelocType Type
Definition: COFFYAML.cpp:391
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
uint64_t IntrinsicInst * II
const char LLVMTargetMachineRef TM
This pass exposes codegen information to IR-level passes.
InstructionCost getSpliceCost(VectorType *Tp, int Index)
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
unsigned getMinTripCountTailFoldingThreshold() const
bool isLegalNTStoreLoad(Type *DataType, Align Alignment)
unsigned getGISelRematGlobalCost() const
bool shouldTreatInstructionLikeSelect(const Instruction *I)
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
std::optional< unsigned > getVScaleForTuning() const
InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE, const SCEV *Ptr)
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index)
bool isLegalMaskedStore(Type *DataType, Align Alignment)
unsigned getInlineCallPenalty(const Function *F, const CallBase &Call, unsigned DefaultCallPenalty) const
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType)
bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader)
See if I should be considered for address type promotion.
InstructionCost getArithmeticReductionCostSVE(unsigned Opcode, VectorType *ValTy, TTI::TargetCostKind CostKind)
std::optional< unsigned > getMinPageSize() const
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
bool shouldExpandReduction(const IntrinsicInst *II) const
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, TTI::TargetCostKind CostKind)
unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, Type *ScalarValTy) const
unsigned getMinVectorRegisterBitWidth() const
std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2)
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
bool isElementTypeLegalForScalableVector(Type *Ty) const
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys)
bool isLegalMaskedLoadStore(Type *DataType, Align Alignment)
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
bool useNeonVector(const Type *Ty) const
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
bool isLegalMaskedLoad(Type *DataType, Align Alignment)
AArch64TTIImpl(const AArch64TargetMachine *TM, const Function &F)
unsigned getMaxNumElements(ElementCount VF) const
Try to return an estimate cost factor that can be used as a multiplier when scalarizing an operation ...
bool isLegalNTLoad(Type *DataType, Align Alignment)
bool preferPredicateOverEpilogue(TailFoldingInfo *TFI)
TailFoldingStyle getPreferredTailFoldingStyle(bool IVUpdateMayOverflow) const
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=std::nullopt, const Instruction *CxtI=nullptr)
bool isLegalMaskedGatherScatter(Type *DataType) const
unsigned getMaxInterleaveFactor(ElementCount VF)
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
InstructionCost getIntImmCost(int64_t Val)
Calculate the cost of materializing a 64-bit value.
unsigned getNumberOfRegisters(unsigned ClassID) const
std::optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=std::nullopt, const Instruction *CxtI=nullptr)
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info)
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind)
bool isLegalNTStore(Type *DataType, Align Alignment)
bool isExtPartOfAvgExpr(const Instruction *ExtUser, Type *Dst, Type *Src)
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Class for arbitrary precision integers.
Definition: APInt.h:78
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:81
unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, Type *ScalarValTy) const
Definition: BasicTTIImpl.h:357
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1236
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:757
Convenience struct for specifying and reasoning about fast-math flags.
Definition: FMF.h:20
The core instruction combiner logic.
Definition: InstCombiner.h:47
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:48
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:71
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:33
const DataLayout & getDataLayout() const
bool isLegalNTStore(Type *DataType, Align Alignment) const
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
bool isLegalNTLoad(Type *DataType, Align Alignment) const
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
TargetCostKind
The kind of cost model.
PopcntSupportKind
Flags indicating the kind of support for population count.
ShuffleKind
The various kinds of shuffle patterns for vector queries.
CastContextHint
Represents a hint about the context in which a cast is used.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
bool isPointerTy() const
True if this is an instance of PointerType.
Definition: Type.h:255
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
Definition: Type.h:154
bool isBFloatTy() const
Return true if this is 'bfloat', a 16-bit bfloat type.
Definition: Type.h:146
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
bool isHalfTy() const
Return true if this is 'half', a 16-bit IEEE fp type.
Definition: Type.h:143
bool isDoubleTy() const
Return true if this is 'double', a 64-bit IEEE fp type.
Definition: Type.h:157
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:228
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:348
LLVM Value Representation.
Definition: Value.h:74
Base class of all SIMD vector types.
Definition: DerivedTypes.h:403
constexpr ScalarTy getFixedValue() const
Definition: TypeSize.h:202
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:171
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
Definition: TypeSize.h:168
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
AddressSpace
Definition: NVPTXBaseInfo.h:21
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
Definition: MathExtras.h:296
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:291
@ DataAndControlFlowWithoutRuntimeCheck
Use predicate to control both data and control flow, but modify the trip count so that a runtime over...
@ DataAndControlFlow
Use predicate to control both data and control flow.
@ DataWithoutLaneMask
Same as Data, but avoids using the get.active.lane.mask intrinsic to calculate the mask and instead i...
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Flags describing the kind of vector reduction.