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16 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
17 #define LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
36 class ScalarEvolution;
53 enum MemIntrinsicType {
54 VECTOR_LDST_TWO_ELEMENTS,
55 VECTOR_LDST_THREE_ELEMENTS,
56 VECTOR_LDST_FOUR_ELEMENTS
59 bool isWideningInstruction(
Type *Ty,
unsigned Opcode,
65 TLI(ST->getTargetLowering()) {}
94 bool Vector = (ClassID == 1);
113 SimplifyAndSetOp)
const;
122 std::max(ST->getMinSVEVectorSizeInBits(), 128u));
131 return ST->getMinVectorRegisterBitWidth();
135 return ST->getVScaleForTuning();
156 const Value *Ptr,
bool VariableMask,
203 bool IsZeroCmp)
const;
247 if (isa<FixedVectorType>(DataType) && !ST->useSVEForFixedLengthVectors())
266 auto *DataTypeFVTy = dyn_cast<FixedVectorType>(DataType);
267 if (DataTypeFVTy && (!ST->useSVEForFixedLengthVectors() ||
268 DataTypeFVTy->getNumElements() < 2))
283 if (!ST->hasNEON() || NumElements.
isScalable())
306 if (
auto *DataTypeVTy = dyn_cast<VectorType>(DataType)) {
307 unsigned NumElements =
308 cast<FixedVectorType>(DataTypeVTy)->getNumElements();
309 unsigned EltSize = DataTypeVTy->getElementType()->getScalarSizeInBits();
310 return NumElements > 1 &&
isPowerOf2_64(NumElements) && EltSize >= 8 &&
321 bool UseMaskForCond =
false,
bool UseMaskForGaps =
false);
325 bool &AllowPromotionWithoutCommonHeader);
357 #endif // LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
bool emitGetActiveLaneMask() const
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
bool isLegalMaskedGatherScatter(Type *DataType) const
This is an optimization pass for GlobalISel generic memory operations.
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
InstructionCost getIntImmCost(int64_t Val)
Calculate the cost of materializing a 64-bit value.
bool isPointerTy() const
True if this is an instance of PointerType.
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Represents a single loop in the control flow graph.
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
bool enableScalableVectorization() const
The main scalar evolution driver.
bool supportsScalableVectors() const
unsigned getGISelRematGlobalCost() const
AArch64TTIImpl(const AArch64TargetMachine *TM, const Function &F)
bool shouldExpandReduction(const IntrinsicInst *II) const
The instances of the Type class are immutable: once they are created, they are never changed.
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
unsigned getNumberOfRegisters(unsigned ClassID) const
bool isScalable() const
Returns whether the size is scaled by a runtime quantity (vscale).
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index)
unsigned getMaxNumElements(ElementCount VF) const
Try to return an estimate cost factor that can be used as a multiplier when scalarizing an operation ...
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys)
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind)
unsigned getMinVectorRegisterBitWidth() const
Analysis containing CSE Info
This struct is a compact representation of a valid (non-zero power of two) alignment.
static TypeSize getFixed(ScalarTy MinVal)
bool isLegalMaskedLoadStore(Type *DataType, Align Alignment)
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
bool isIntegerTy() const
True if this is an instance of IntegerType.
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Base class of all SIMD vector types.
This class represents an analyzed expression in the program.
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
InstructionCost getArithmeticReductionCostSVE(unsigned Opcode, VectorType *ValTy, TTI::TargetCostKind CostKind)
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
Base class which can be used to help build a TTI implementation.
bool isHalfTy() const
Return true if this is 'half', a 16-bit IEEE fp type.
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
print Print MemDeps of function
ScalarTy getKnownMinValue() const
Returns the minimum value this size can represent.
unsigned getMaxInterleaveFactor(unsigned VF)
InstructionCost getSpliceCost(VectorType *Tp, int Index)
Class for arbitrary precision integers.
const unsigned VectorBits
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool enableInterleavedAccessVectorization()
ScalarTy getFixedValue() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
static const Function * getParent(const Value *V)
bool enableOrderedReductions() const
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=None)
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
bool isLegalNTStore(Type *DataType, Align Alignment)
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info)
static TypeSize getScalable(ScalarTy MinVal)
bool isDoubleTy() const
Return true if this is 'double', a 64-bit IEEE fp type.
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
The core instruction combiner logic.
A wrapper class for inspecting calls to intrinsic functions.
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
bool isBFloatTy() const
Return true if this is 'bfloat', a 16-bit bfloat type.
Align max(MaybeAlign Lhs, Align Rhs)
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Information about a load/store intrinsic defined by the target.
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
const char LLVMTargetMachineRef TM
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader)
See if I should be considered for address type promotion.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
bool isElementTypeLegalForScalableVector(Type *Ty) const
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
bool isLegalMaskedLoad(Type *DataType, Align Alignment)
LLVM Value Representation.
bool useNeonVector(const Type *Ty) const
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType)
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE, const SCEV *Ptr)
bool isLegalMaskedStore(Type *DataType, Align Alignment)
Optional< unsigned > getVScaleForTuning() const