#include "Target/AArch64/AArch64TargetTransformInfo.h"

Inheritance diagram for llvm::AArch64TTIImpl:

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Collaboration diagram for llvm::AArch64TTIImpl:

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Public Member Functions
	AArch64TTIImpl (const AArch64TargetMachine *TM, const Function &F)

bool	areInlineCompatible (const Function Caller, const Function Callee) const

Scalar TTI Implementations
int	getIntImmCost (int64_t Val)
	Calculate the cost of materializing a 64-bit value. More...

int	getIntImmCost (const APInt &Imm, Type *Ty)
	Calculate the cost of materializing the given constant. More...

int	getIntImmCost (unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty)

int	getIntImmCost (Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty)

TTI::PopcntSupportKind	getPopcntSupport (unsigned TyWidth)

Vector TTI Implementations
bool	enableInterleavedAccessVectorization ()

unsigned	getNumberOfRegisters (bool Vector)

unsigned	getRegisterBitWidth (bool Vector) const

unsigned	getMinVectorRegisterBitWidth ()

unsigned	getMaxInterleaveFactor (unsigned VF)

int	getCastInstrCost (unsigned Opcode, Type Dst, Type Src, const Instruction *I=nullptr)

int	getExtractWithExtendCost (unsigned Opcode, Type Dst, VectorType VecTy, unsigned Index)

int	getVectorInstrCost (unsigned Opcode, Type *Val, unsigned Index)

int	getArithmeticInstrCost (unsigned Opcode, Type Ty, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value > Args=ArrayRef< const Value *>())

int	getAddressComputationCost (Type Ty, ScalarEvolution SE, const SCEV *Ptr)

int	getCmpSelInstrCost (unsigned Opcode, Type ValTy, Type CondTy, const Instruction *I=nullptr)

TTI::MemCmpExpansionOptions	enableMemCmpExpansion (bool OptSize, bool IsZeroCmp) const

int	getMemoryOpCost (unsigned Opcode, Type Src, unsigned Alignment, unsigned AddressSpace, const Instruction I=nullptr)

int	getCostOfKeepingLiveOverCall (ArrayRef< Type *> Tys)

void	getUnrollingPreferences (Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP)

Value *	getOrCreateResultFromMemIntrinsic (IntrinsicInst Inst, Type ExpectedType)

bool	getTgtMemIntrinsic (IntrinsicInst *Inst, MemIntrinsicInfo &Info)

int	getInterleavedMemoryOpCost (unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond=false, bool UseMaskForGaps=false)

bool	shouldConsiderAddressTypePromotion (const Instruction &I, bool &AllowPromotionWithoutCommonHeader)
	See if `I` should be considered for address type promotion. More...

unsigned	getCacheLineSize ()

unsigned	getPrefetchDistance ()

unsigned	getMinPrefetchStride ()

unsigned	getMaxPrefetchIterationsAhead ()

bool	shouldExpandReduction (const IntrinsicInst *II) const

unsigned	getGISelRematGlobalCost () const

bool	useReductionIntrinsic (unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const

int	getArithmeticReductionCost (unsigned Opcode, Type *Ty, bool IsPairwiseForm)

int	getShuffleCost (TTI::ShuffleKind Kind, Type Tp, int Index, Type SubTp)

Public Member Functions inherited from llvm::BasicTTIImplBase< AArch64TTIImpl >
bool	allowsMisalignedMemoryAccesses (LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, unsigned Alignment, bool *Fast) const

bool	hasBranchDivergence ()

bool	isSourceOfDivergence (const Value *V)

bool	isAlwaysUniform (const Value *V)

unsigned	getFlatAddressSpace ()

bool	collectFlatAddressOperands (SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const

bool	rewriteIntrinsicWithAddressSpace (IntrinsicInst II, Value OldV, Value *NewV) const

bool	isLegalAddImmediate (int64_t imm)

bool	isLegalICmpImmediate (int64_t imm)

bool	isLegalAddressingMode (Type Ty, GlobalValue BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr)

bool	isIndexedLoadLegal (TTI::MemIndexedMode M, Type *Ty, const DataLayout &DL) const

bool	isIndexedStoreLegal (TTI::MemIndexedMode M, Type *Ty, const DataLayout &DL) const

bool	isLSRCostLess (TTI::LSRCost C1, TTI::LSRCost C2)

int	getScalingFactorCost (Type Ty, GlobalValue BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace)

bool	isTruncateFree (Type Ty1, Type Ty2)

bool	isProfitableToHoist (Instruction *I)

bool	useAA () const

bool	isTypeLegal (Type *Ty)

int	getGEPCost (Type PointeeType, const Value Ptr, ArrayRef< const Value * > Operands)

int	getExtCost (const Instruction I, const Value Src)

unsigned	getIntrinsicCost (Intrinsic::ID IID, Type RetTy, ArrayRef< const Value > Arguments, const User *U)

unsigned	getIntrinsicCost (Intrinsic::ID IID, Type RetTy, ArrayRef< Type > ParamTys, const User *U)

unsigned	getEstimatedNumberOfCaseClusters (const SwitchInst &SI, unsigned &JumpTableSize)

bool	shouldBuildLookupTables ()

bool	haveFastSqrt (Type *Ty)

bool	isFCmpOrdCheaperThanFCmpZero (Type *Ty)

unsigned	getFPOpCost (Type *Ty)

unsigned	getOperationCost (unsigned Opcode, Type Ty, Type OpTy)

unsigned	getInliningThresholdMultiplier ()

int	getInlinerVectorBonusPercent ()

void	getUnrollingPreferences (Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP)

bool	isHardwareLoopProfitable (Loop L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo LibInfo, HardwareLoopInfo &HWLoopInfo)

int	getInstructionLatency (const Instruction *I)

unsigned	getNumberOfRegisters (bool Vector)

unsigned	getRegisterBitWidth (bool Vector) const

unsigned	getScalarizationOverhead (Type *Ty, bool Insert, bool Extract)
	Estimate the overhead of scalarizing an instruction. More...

unsigned	getScalarizationOverhead (Type VecTy, ArrayRef< const Value > Args)

unsigned	getOperandsScalarizationOverhead (ArrayRef< const Value * > Args, unsigned VF)
	Estimate the overhead of scalarizing an instructions unique non-constant operands. More...

unsigned	getMaxInterleaveFactor (unsigned VF)

unsigned	getArithmeticInstrCost (unsigned Opcode, Type Ty, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value > Args=ArrayRef< const Value * >())

unsigned	getShuffleCost (TTI::ShuffleKind Kind, Type Tp, int Index, Type SubTp)

unsigned	getCastInstrCost (unsigned Opcode, Type Dst, Type Src, const Instruction *I=nullptr)

unsigned	getExtractWithExtendCost (unsigned Opcode, Type Dst, VectorType VecTy, unsigned Index)

unsigned	getCFInstrCost (unsigned Opcode)

unsigned	getCmpSelInstrCost (unsigned Opcode, Type ValTy, Type CondTy, const Instruction *I)

unsigned	getVectorInstrCost (unsigned Opcode, Type *Val, unsigned Index)

unsigned	getMemoryOpCost (unsigned Opcode, Type Src, unsigned Alignment, unsigned AddressSpace, const Instruction I=nullptr)

unsigned	getInterleavedMemoryOpCost (unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond=false, bool UseMaskForGaps=false)

unsigned	getIntrinsicInstrCost (Intrinsic::ID IID, Type RetTy, ArrayRef< Value > Args, FastMathFlags FMF, unsigned VF=1)
	Get intrinsic cost based on arguments. More...

unsigned	getIntrinsicInstrCost (Intrinsic::ID IID, Type RetTy, ArrayRef< Type > Tys, FastMathFlags FMF, unsigned ScalarizationCostPassed=std::numeric_limits< unsigned >::max())
	Get intrinsic cost based on argument types. More...

unsigned	getCallInstrCost (Function F, Type RetTy, ArrayRef< Type * > Tys)
	Compute a cost of the given call instruction. More...

unsigned	getNumberOfParts (Type *Tp)

unsigned	getAddressComputationCost (Type Ty, ScalarEvolution , const SCEV *)

unsigned	getArithmeticReductionCost (unsigned Opcode, Type *Ty, bool IsPairwise)
	Try to calculate arithmetic and shuffle op costs for reduction operations. More...

unsigned	getMinMaxReductionCost (Type Ty, Type CondTy, bool IsPairwise, bool)
	Try to calculate op costs for min/max reduction operations. More...

unsigned	getVectorSplitCost ()

Public Member Functions inherited from llvm::TargetTransformInfoImplCRTPBase< AArch64TTIImpl >
unsigned	getCallCost (const Function F, int NumArgs, const User U)

unsigned	getCallCost (const Function F, ArrayRef< const Value > Arguments, const User *U)

int	getGEPCost (Type PointeeType, const Value Ptr, ArrayRef< const Value * > Operands)

unsigned	getIntrinsicCost (Intrinsic::ID IID, Type RetTy, ArrayRef< Type > ParamTys, const User *U)

unsigned	getIntrinsicCost (Intrinsic::ID IID, Type RetTy, ArrayRef< const Value > Arguments, const User *U)

unsigned	getUserCost (const User U, ArrayRef< const Value > Operands)

int	getInstructionLatency (const Instruction *I)

Public Member Functions inherited from llvm::TargetTransformInfoImplBase
	TargetTransformInfoImplBase (const TargetTransformInfoImplBase &Arg)

	TargetTransformInfoImplBase (TargetTransformInfoImplBase &&Arg)

const DataLayout &	getDataLayout () const

unsigned	getOperationCost (unsigned Opcode, Type Ty, Type OpTy)

int	getGEPCost (Type PointeeType, const Value Ptr, ArrayRef< const Value *> Operands)

unsigned	getEstimatedNumberOfCaseClusters (const SwitchInst &SI, unsigned &JTSize)

int	getExtCost (const Instruction I, const Value Src)

unsigned	getCallCost (FunctionType FTy, int NumArgs, const User U)

unsigned	getInliningThresholdMultiplier ()

int	getInlinerVectorBonusPercent ()

unsigned	getMemcpyCost (const Instruction *I)

bool	hasBranchDivergence ()

bool	isSourceOfDivergence (const Value *V)

bool	isAlwaysUniform (const Value *V)

unsigned	getFlatAddressSpace ()

bool	collectFlatAddressOperands (SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const

bool	rewriteIntrinsicWithAddressSpace (IntrinsicInst II, Value OldV, Value *NewV) const

bool	isLoweredToCall (const Function *F)

bool	isHardwareLoopProfitable (Loop L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo LibInfo, HardwareLoopInfo &HWLoopInfo)

void	getUnrollingPreferences (Loop *, ScalarEvolution &, TTI::UnrollingPreferences &)

bool	isLegalAddImmediate (int64_t Imm)

bool	isLegalICmpImmediate (int64_t Imm)

bool	isLegalAddressingMode (Type Ty, GlobalValue BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr)

bool	isLSRCostLess (TTI::LSRCost &C1, TTI::LSRCost &C2)

bool	canMacroFuseCmp ()

bool	canSaveCmp (Loop L, BranchInst BI, ScalarEvolution SE, LoopInfo LI, DominatorTree DT, AssumptionCache AC, TargetLibraryInfo LibInfo)

bool	shouldFavorPostInc () const

bool	shouldFavorBackedgeIndex (const Loop *L) const

bool	isLegalMaskedStore (Type *DataType)

bool	isLegalMaskedLoad (Type *DataType)

bool	isLegalNTStore (Type *DataType, llvm::Align Alignment)

bool	isLegalNTLoad (Type *DataType, llvm::Align Alignment)

bool	isLegalMaskedScatter (Type *DataType)

bool	isLegalMaskedGather (Type *DataType)

bool	isLegalMaskedCompressStore (Type *DataType)

bool	isLegalMaskedExpandLoad (Type *DataType)

bool	hasDivRemOp (Type *DataType, bool IsSigned)

bool	hasVolatileVariant (Instruction *I, unsigned AddrSpace)

bool	prefersVectorizedAddressing ()

int	getScalingFactorCost (Type Ty, GlobalValue BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace)

bool	LSRWithInstrQueries ()

bool	isTruncateFree (Type Ty1, Type Ty2)

bool	isProfitableToHoist (Instruction *I)

bool	useAA ()

bool	isTypeLegal (Type *Ty)

bool	shouldBuildLookupTables ()

bool	shouldBuildLookupTablesForConstant (Constant *C)

bool	useColdCCForColdCall (Function &F)

unsigned	getScalarizationOverhead (Type *Ty, bool Insert, bool Extract)

unsigned	getOperandsScalarizationOverhead (ArrayRef< const Value *> Args, unsigned VF)

bool	supportsEfficientVectorElementLoadStore ()

bool	enableAggressiveInterleaving (bool LoopHasReductions)

TTI::MemCmpExpansionOptions	enableMemCmpExpansion (bool OptSize, bool IsZeroCmp) const

bool	enableInterleavedAccessVectorization ()

bool	enableMaskedInterleavedAccessVectorization ()

bool	isFPVectorizationPotentiallyUnsafe ()

bool	allowsMisalignedMemoryAccesses (LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, unsigned Alignment, bool *Fast)

TTI::PopcntSupportKind	getPopcntSupport (unsigned IntTyWidthInBit)

bool	haveFastSqrt (Type *Ty)

bool	isFCmpOrdCheaperThanFCmpZero (Type *Ty)

unsigned	getFPOpCost (Type *Ty)

int	getIntImmCodeSizeCost (unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty)

unsigned	getIntImmCost (const APInt &Imm, Type *Ty)

unsigned	getIntImmCost (unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty)

unsigned	getIntImmCost (Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty)

unsigned	getNumberOfRegisters (bool Vector)

unsigned	getRegisterBitWidth (bool Vector) const

unsigned	getMinVectorRegisterBitWidth ()

bool	shouldMaximizeVectorBandwidth (bool OptSize) const

unsigned	getMinimumVF (unsigned ElemWidth) const

bool	shouldConsiderAddressTypePromotion (const Instruction &I, bool &AllowPromotionWithoutCommonHeader)

unsigned	getCacheLineSize ()

llvm::Optional< unsigned >	getCacheSize (TargetTransformInfo::CacheLevel Level)

llvm::Optional< unsigned >	getCacheAssociativity (TargetTransformInfo::CacheLevel Level)

unsigned	getPrefetchDistance ()

unsigned	getMinPrefetchStride ()

unsigned	getMaxPrefetchIterationsAhead ()

unsigned	getMaxInterleaveFactor (unsigned VF)

unsigned	getArithmeticInstrCost (unsigned Opcode, Type Ty, TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo, TTI::OperandValueProperties Opd2PropInfo, ArrayRef< const Value > Args)

unsigned	getShuffleCost (TTI::ShuffleKind Kind, Type Ty, int Index, Type SubTp)

unsigned	getCastInstrCost (unsigned Opcode, Type Dst, Type Src, const Instruction *I)

unsigned	getExtractWithExtendCost (unsigned Opcode, Type Dst, VectorType VecTy, unsigned Index)

unsigned	getCFInstrCost (unsigned Opcode)

unsigned	getCmpSelInstrCost (unsigned Opcode, Type ValTy, Type CondTy, const Instruction *I)

unsigned	getVectorInstrCost (unsigned Opcode, Type *Val, unsigned Index)

unsigned	getMemoryOpCost (unsigned Opcode, Type Src, unsigned Alignment, unsigned AddressSpace, const Instruction I)

unsigned	getMaskedMemoryOpCost (unsigned Opcode, Type *Src, unsigned Alignment, unsigned AddressSpace)

unsigned	getGatherScatterOpCost (unsigned Opcode, Type DataTy, Value Ptr, bool VariableMask, unsigned Alignment)

unsigned	getInterleavedMemoryOpCost (unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond=false, bool UseMaskForGaps=false)

unsigned	getIntrinsicInstrCost (Intrinsic::ID ID, Type RetTy, ArrayRef< Type > Tys, FastMathFlags FMF, unsigned ScalarizationCostPassed)

unsigned	getIntrinsicInstrCost (Intrinsic::ID ID, Type RetTy, ArrayRef< Value > Args, FastMathFlags FMF, unsigned VF)

unsigned	getCallInstrCost (Function F, Type RetTy, ArrayRef< Type *> Tys)

unsigned	getNumberOfParts (Type *Tp)

unsigned	getAddressComputationCost (Type Tp, ScalarEvolution , const SCEV *)

unsigned	getArithmeticReductionCost (unsigned, Type *, bool)

unsigned	getMinMaxReductionCost (Type , Type , bool, bool)

unsigned	getCostOfKeepingLiveOverCall (ArrayRef< Type *> Tys)

bool	getTgtMemIntrinsic (IntrinsicInst *Inst, MemIntrinsicInfo &Info)

unsigned	getAtomicMemIntrinsicMaxElementSize () const

Value *	getOrCreateResultFromMemIntrinsic (IntrinsicInst Inst, Type ExpectedType)

Type *	getMemcpyLoopLoweringType (LLVMContext &Context, Value *Length, unsigned SrcAlign, unsigned DestAlign) const

void	getMemcpyLoopResidualLoweringType (SmallVectorImpl< Type *> &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAlign, unsigned DestAlign) const

bool	areInlineCompatible (const Function Caller, const Function Callee) const

bool	areFunctionArgsABICompatible (const Function Caller, const Function Callee, SmallPtrSetImpl< Argument *> &Args) const

bool	isIndexedLoadLegal (TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const

bool	isIndexedStoreLegal (TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const

unsigned	getLoadStoreVecRegBitWidth (unsigned AddrSpace) const

bool	isLegalToVectorizeLoad (LoadInst *LI) const

bool	isLegalToVectorizeStore (StoreInst *SI) const

bool	isLegalToVectorizeLoadChain (unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const

bool	isLegalToVectorizeStoreChain (unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const

unsigned	getLoadVectorFactor (unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const

unsigned	getStoreVectorFactor (unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const

bool	useReductionIntrinsic (unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const

bool	shouldExpandReduction (const IntrinsicInst *II) const

unsigned	getGISelRematGlobalCost () const

Additional Inherited Members
Protected Types inherited from llvm::TargetTransformInfoImplBase
typedef TargetTransformInfo	TTI

Protected Member Functions inherited from llvm::BasicTTIImplBase< AArch64TTIImpl >
	BasicTTIImplBase (const TargetMachine *TM, const DataLayout &DL)

Protected Member Functions inherited from llvm::TargetTransformInfoImplCRTPBase< AArch64TTIImpl >
	TargetTransformInfoImplCRTPBase (const DataLayout &DL)

Protected Member Functions inherited from llvm::TargetTransformInfoImplBase
	TargetTransformInfoImplBase (const DataLayout &DL)

unsigned	minRequiredElementSize (const Value *Val, bool &isSigned)

bool	isStridedAccess (const SCEV *Ptr)

const SCEVConstant *	getConstantStrideStep (ScalarEvolution SE, const SCEV Ptr)

bool	isConstantStridedAccessLessThan (ScalarEvolution SE, const SCEV Ptr, int64_t MergeDistance)

Protected Attributes inherited from llvm::TargetTransformInfoImplBase
const DataLayout &	DL

Detailed Description

Definition at line 41 of file AArch64TargetTransformInfo.h.

Constructor & Destructor Documentation

◆ AArch64TTIImpl()

llvm::AArch64TTIImpl::AArch64TTIImpl	(	const AArch64TargetMachine *	TM,
		const Function &	F
	)

inlineexplicit

Definition at line 63 of file AArch64TargetTransformInfo.h.

References areInlineCompatible(), Callee, getIntImmCost(), llvm::TargetTransformInfoImplBase::getIntImmCost(), and getPopcntSupport().

Member Function Documentation

◆ areInlineCompatible()

bool AArch64TTIImpl::areInlineCompatible	(	const Function *	Caller,
		const Function *	Callee
	)		const

Definition at line 27 of file AArch64TargetTransformInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits(), llvm::TargetMachine::getSubtargetImpl(), llvm::TargetLoweringBase::getTargetMachine(), and llvm::SystemZISD::TM.

Referenced by AArch64TTIImpl().

◆ enableInterleavedAccessVectorization()

bool llvm::AArch64TTIImpl::enableInterleavedAccessVectorization ( )

inline

Definition at line 86 of file AArch64TargetTransformInfo.h.

◆ enableMemCmpExpansion()

AArch64TTIImpl::TTI::MemCmpExpansionOptions AArch64TTIImpl::enableMemCmpExpansion	(	bool	OptSize,
		bool	IsZeroCmp
	)		const

Definition at line 622 of file AArch64TargetTransformInfo.cpp.

References llvm::TargetTransformInfo::MemCmpExpansionOptions::AllowOverlappingLoads, llvm::TargetLoweringBase::getMaxExpandSizeMemcmp(), llvm::TargetTransformInfo::MemCmpExpansionOptions::LoadSizes, llvm::TargetTransformInfo::MemCmpExpansionOptions::MaxNumLoads, llvm::TargetTransformInfo::MemCmpExpansionOptions::NumLoadsPerBlock, and llvm::AArch64Subtarget::requiresStrictAlign().

Referenced by getMinVectorRegisterBitWidth().

◆ getAddressComputationCost()

int AArch64TTIImpl::getAddressComputationCost	(	Type *	Ty,
		ScalarEvolution *	SE,
		const SCEV *	Ptr
	)

Definition at line 572 of file AArch64TargetTransformInfo.cpp.

References llvm::TargetTransformInfoImplBase::isConstantStridedAccessLessThan(), and llvm::Type::isVectorTy().

Referenced by getMinVectorRegisterBitWidth().

◆ getArithmeticInstrCost()

int AArch64TTIImpl::getArithmeticInstrCost	(	unsigned	Opcode,
		Type *	Ty,
		TTI::OperandValueKind	Opd1Info = `TTI::OK_AnyValue`,
		TTI::OperandValueKind	Opd2Info = `TTI::OK_AnyValue`,
		TTI::OperandValueProperties	Opd1PropInfo = `TTI::OP_None`,
		TTI::OperandValueProperties	Opd2PropInfo = `TTI::OP_None`,
		ArrayRef< const Value *>	Args = `ArrayRef<const Value *>()`
	)

Definition at line 478 of file AArch64TargetTransformInfo.cpp.

References llvm::MCID::Add, llvm::ISD::ADD, llvm::ISD::AND, llvm::TargetTransformInfoImplBase::DL, llvm::BasicTTIImplBase< AArch64TTIImpl >::getArithmeticInstrCost(), llvm::TargetLoweringBase::getTypeLegalizationCost(), llvm::TargetLoweringBase::getValueType(), llvm::AArch64Subtarget::getWideningBaseCost(), llvm::TargetLoweringBase::InstructionOpcodeToISD(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::Type::isVectorTy(), LLVM_FALLTHROUGH, llvm::AArch64CC::LT, llvm::ISD::MUL, llvm::ISD::MULHU, llvm::TargetTransformInfo::OK_UniformConstantValue, llvm::TargetTransformInfo::OP_None, llvm::TargetTransformInfo::OP_PowerOf2, llvm::ISD::OR, llvm::ISD::SDIV, llvm::MCID::Select, llvm::ISD::UDIV, and llvm::ISD::XOR.

Referenced by getMinVectorRegisterBitWidth().

◆ getArithmeticReductionCost()

int AArch64TTIImpl::getArithmeticReductionCost	(	unsigned	Opcode,
		Type *	Ty,
		bool	IsPairwiseForm
	)

Definition at line 936 of file AArch64TargetTransformInfo.cpp.

References llvm::ISD::ADD, assert(), llvm::CostTableLookup(), llvm::TargetTransformInfoImplBase::DL, llvm::BasicTTIImplBase< AArch64TTIImpl >::getArithmeticReductionCost(), llvm::TargetLoweringBase::getTypeLegalizationCost(), llvm::TargetLoweringBase::InstructionOpcodeToISD(), llvm::AArch64CC::LT, llvm::MVT::v16i8, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8i16, and llvm::MVT::v8i8.

Referenced by getGISelRematGlobalCost().

◆ getCacheLineSize()

unsigned AArch64TTIImpl::getCacheLineSize ( )

Definition at line 895 of file AArch64TargetTransformInfo.cpp.

References llvm::AArch64Subtarget::getCacheLineSize().

Referenced by getMinVectorRegisterBitWidth().

◆ getCastInstrCost()

int AArch64TTIImpl::getCastInstrCost	(	unsigned	Opcode,
		Type *	Dst,
		Type *	Src,
		const Instruction *	I = `nullptr`
	)

Definition at line 262 of file AArch64TargetTransformInfo.cpp.

References assert(), llvm::ConvertCostTableLookup(), llvm::TargetTransformInfoImplBase::DL, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::BasicTTIImplBase< AArch64TTIImpl >::getCastInstrCost(), llvm::Instruction::getOpcode(), llvm::User::getOperand(), llvm::EVT::getSimpleVT(), llvm::TargetLoweringBase::getValueType(), llvm::Value::hasOneUse(), llvm::TargetLoweringBase::InstructionOpcodeToISD(), llvm::EVT::isSimple(), Operands, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::TRUNCATE, llvm::ISD::UINT_TO_FP, llvm::Value::user_begin(), llvm::MVT::v16f32, llvm::MVT::v16i16, llvm::MVT::v16i32, llvm::MVT::v16i8, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i16, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v2i8, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v4i8, llvm::MVT::v8f32, llvm::MVT::v8i16, llvm::MVT::v8i32, llvm::MVT::v8i64, llvm::MVT::v8i8, and llvm::ISD::ZERO_EXTEND.

Referenced by getExtractWithExtendCost(), and getMinVectorRegisterBitWidth().

◆ getCmpSelInstrCost()

int AArch64TTIImpl::getCmpSelInstrCost	(	unsigned	Opcode,
		Type *	ValTy,
		Type *	CondTy,
		const Instruction *	I = `nullptr`
	)

◆ getCostOfKeepingLiveOverCall()

int AArch64TTIImpl::getCostOfKeepingLiveOverCall ( ArrayRef< Type *> Tys )

Definition at line 700 of file AArch64TargetTransformInfo.cpp.

References getMemoryOpCost(), I, llvm::SPII::Load, and llvm::SPII::Store.

Referenced by getMinVectorRegisterBitWidth().

◆ getExtractWithExtendCost()

int AArch64TTIImpl::getExtractWithExtendCost	(	unsigned	Opcode,
		Type *	Dst,
		VectorType *	VecTy,
		unsigned	Index
	)

Definition at line 398 of file AArch64TargetTransformInfo.cpp.

References assert(), llvm::TargetTransformInfoImplBase::DL, getCastInstrCost(), llvm::SequentialType::getElementType(), llvm::TargetLoweringBase::getTypeLegalizationCost(), llvm::TargetLoweringBase::getValueType(), getVectorInstrCost(), llvm::TargetLoweringBase::isTypeLegal(), and llvm_unreachable.

Referenced by getMinVectorRegisterBitWidth().

◆ getGISelRematGlobalCost()

unsigned llvm::AArch64TTIImpl::getGISelRematGlobalCost ( ) const

inline

Definition at line 171 of file AArch64TargetTransformInfo.h.

References getArithmeticReductionCost(), getShuffleCost(), and useReductionIntrinsic().

◆ getInterleavedMemoryOpCost()

int AArch64TTIImpl::getInterleavedMemoryOpCost	(	unsigned	Opcode,
		Type *	VecTy,
		unsigned	Factor,
		ArrayRef< unsigned >	Indices,
		unsigned	Alignment,
		unsigned	AddressSpace,
		bool	UseMaskForCond = `false`,
		bool	UseMaskForGaps = `false`
	)

Definition at line 672 of file AArch64TargetTransformInfo.cpp.

References assert(), llvm::TargetTransformInfoImplBase::DL, llvm::VectorType::get(), llvm::BasicTTIImplBase< AArch64TTIImpl >::getInterleavedMemoryOpCost(), llvm::AArch64TargetLowering::getNumInterleavedAccesses(), llvm::Type::getScalarType(), llvm::Type::getVectorNumElements(), and llvm::AArch64TargetLowering::isLegalInterleavedAccessType().

Referenced by getMinVectorRegisterBitWidth().

◆ getIntImmCost() [1/4]

int AArch64TTIImpl::getIntImmCost ( int64_t Val )

Calculate the cost of materializing a 64-bit value.

This helper method might only calculate a fraction of a larger immediate. Therefore it is valid to return a cost of ZERO.

Definition at line 44 of file AArch64TargetTransformInfo.cpp.

References llvm::AArch64_IMM::expandMOVImm(), llvm::AArch64_AM::isLogicalImmediate(), and llvm::SmallVectorBase::size().

Referenced by AArch64TTIImpl(), and getIntImmCost().

◆ getIntImmCost() [2/4]

int AArch64TTIImpl::getIntImmCost	(	const APInt &	Imm,
		Type *	Ty
	)

Calculate the cost of materializing the given constant.

Definition at line 59 of file AArch64TargetTransformInfo.cpp.

References llvm::APInt::ashr(), assert(), getIntImmCost(), llvm::Type::getPrimitiveSizeInBits(), llvm::APInt::getSExtValue(), llvm::Type::isIntegerTy(), llvm::max(), llvm::APInt::sext(), and llvm::APInt::sextOrTrunc().

◆ getIntImmCost() [3/4]

int AArch64TTIImpl::getIntImmCost	(	unsigned	Opcode,
		unsigned	Idx,
		const APInt &	Imm,
		Type *	Ty
	)

Definition at line 83 of file AArch64TargetTransformInfo.cpp.

References llvm::MCID::Add, assert(), llvm::MCID::Call, getIntImmCost(), llvm::Type::getPrimitiveSizeInBits(), llvm::Type::isIntegerTy(), llvm::SPII::Load, llvm::MipsISD::Ret, llvm::MCID::Select, llvm::SPII::Store, llvm::TargetTransformInfo::TCC_Basic, and llvm::TargetTransformInfo::TCC_Free.

◆ getIntImmCost() [4/4]

int AArch64TTIImpl::getIntImmCost	(	Intrinsic::ID	IID,
		unsigned	Idx,
		const APInt &	Imm,
		Type *	Ty
	)

Definition at line 149 of file AArch64TargetTransformInfo.cpp.

References assert(), llvm::APInt::getBitWidth(), getIntImmCost(), llvm::Type::getPrimitiveSizeInBits(), llvm::APInt::getSExtValue(), llvm::Type::isIntegerTy(), llvm::TargetTransformInfo::TCC_Basic, and llvm::TargetTransformInfo::TCC_Free.

◆ getMaxInterleaveFactor()

unsigned AArch64TTIImpl::getMaxInterleaveFactor ( unsigned VF )

Definition at line 712 of file AArch64TargetTransformInfo.cpp.

References llvm::AArch64Subtarget::getMaxInterleaveFactor().

Referenced by getMinVectorRegisterBitWidth().

◆ getMaxPrefetchIterationsAhead()

unsigned AArch64TTIImpl::getMaxPrefetchIterationsAhead ( )

Definition at line 907 of file AArch64TargetTransformInfo.cpp.

References llvm::AArch64Subtarget::getMaxPrefetchIterationsAhead().

Referenced by getMinVectorRegisterBitWidth().

◆ getMemoryOpCost()

int AArch64TTIImpl::getMemoryOpCost	(	unsigned	Opcode,
		Type *	Src,
		unsigned	Alignment,
		unsigned	AddressSpace,
		const Instruction *	I = `nullptr`
	)

Definition at line 634 of file AArch64TargetTransformInfo.cpp.

References llvm::TargetTransformInfoImplBase::DL, llvm::TargetLoweringBase::getTypeLegalizationCost(), llvm::Type::getVectorElementType(), llvm::Type::getVectorNumElements(), llvm::Type::isIntegerTy(), llvm::AArch64Subtarget::isMisaligned128StoreSlow(), llvm::Type::isVectorTy(), llvm::AArch64CC::LT, and llvm::SPII::Store.

Referenced by getCostOfKeepingLiveOverCall(), and getMinVectorRegisterBitWidth().

◆ getMinPrefetchStride()

unsigned AArch64TTIImpl::getMinPrefetchStride ( )

Definition at line 903 of file AArch64TargetTransformInfo.cpp.

References llvm::AArch64Subtarget::getMinPrefetchStride().

Referenced by getMinVectorRegisterBitWidth().

◆ getMinVectorRegisterBitWidth()

unsigned llvm::AArch64TTIImpl::getMinVectorRegisterBitWidth ( )

inline

◆ getNumberOfRegisters()

unsigned llvm::AArch64TTIImpl::getNumberOfRegisters ( bool Vector )

inline

Definition at line 88 of file AArch64TargetTransformInfo.h.

References llvm::AArch64Subtarget::hasNEON().

◆ getOrCreateResultFromMemIntrinsic()

Value * AArch64TTIImpl::getOrCreateResultFromMemIntrinsic	(	IntrinsicInst *	Inst,
		Type *	ExpectedType
	)

Definition at line 787 of file AArch64TargetTransformInfo.cpp.

References llvm::IRBuilder< T, Inserter >::CreateInsertValue(), llvm::dyn_cast(), llvm::UndefValue::get(), llvm::CallBase::getArgOperand(), llvm::StructType::getElementType(), llvm::IntrinsicInst::getIntrinsicID(), llvm::CallBase::getNumArgOperands(), llvm::StructType::getNumElements(), and llvm::Value::getType().

Referenced by getMinVectorRegisterBitWidth().

◆ getPopcntSupport()

TargetTransformInfo::PopcntSupportKind AArch64TTIImpl::getPopcntSupport ( unsigned TyWidth )

Definition at line 190 of file AArch64TargetTransformInfo.cpp.

References llvm::MCID::Add, llvm::AMDGPU::HSAMD::Kernel::Key::Args, assert(), llvm::TargetTransformInfoImplBase::DL, llvm::VectorType::get(), llvm::Type::getScalarSizeInBits(), llvm::TargetLoweringBase::getTypeLegalizationCost(), llvm::Type::getVectorNumElements(), hasOneUse(), llvm::isPowerOf2_32(), llvm::Type::isVectorTy(), llvm::TargetTransformInfo::PSK_FastHardware, llvm::TargetTransformInfo::PSK_Software, and llvm::ArrayRef< T >::size().

Referenced by AArch64TTIImpl().

◆ getPrefetchDistance()

unsigned AArch64TTIImpl::getPrefetchDistance ( )

Definition at line 899 of file AArch64TargetTransformInfo.cpp.

References llvm::AArch64Subtarget::getPrefetchDistance().

Referenced by getMinVectorRegisterBitWidth().

◆ getRegisterBitWidth()

unsigned llvm::AArch64TTIImpl::getRegisterBitWidth ( bool Vector ) const

inline

Definition at line 97 of file AArch64TargetTransformInfo.h.

References llvm::AArch64Subtarget::hasNEON().

◆ getShuffleCost()

int AArch64TTIImpl::getShuffleCost	(	TTI::ShuffleKind	Kind,
		Type *	Tp,
		int	Index,
		Type *	SubTp
	)

◆ getTgtMemIntrinsic()

bool AArch64TTIImpl::getTgtMemIntrinsic	(	IntrinsicInst *	Inst,
		MemIntrinsicInfo &	Info
	)

Definition at line 823 of file AArch64TargetTransformInfo.cpp.

References llvm::CallBase::getArgOperand(), llvm::IntrinsicInst::getIntrinsicID(), llvm::CallBase::getNumArgOperands(), llvm::MemIntrinsicInfo::MatchingId, llvm::MemIntrinsicInfo::PtrVal, llvm::MemIntrinsicInfo::ReadMem, and llvm::MemIntrinsicInfo::WriteMem.

Referenced by getMinVectorRegisterBitWidth().

◆ getUnrollingPreferences()

void AArch64TTIImpl::getUnrollingPreferences	(	Loop *	L,
		ScalarEvolution &	SE,
		TTI::UnrollingPreferences &	UP
	)

Definition at line 768 of file AArch64TargetTransformInfo.cpp.

References EnableFalkorHWPFUnrollFix, llvm::AArch64Subtarget::Falkor, getFalkorUnrollingPreferences(), llvm::LoopBase< BlockT, LoopT >::getLoopDepth(), llvm::AArch64Subtarget::getProcFamily(), llvm::BasicTTIImplBase< AArch64TTIImpl >::getUnrollingPreferences(), if(), llvm::TargetTransformInfo::UnrollingPreferences::PartialOptSizeThreshold, and llvm::TargetTransformInfo::UnrollingPreferences::PartialThreshold.

Referenced by getMinVectorRegisterBitWidth().

◆ getVectorInstrCost()

int AArch64TTIImpl::getVectorInstrCost	(	unsigned	Opcode,
		Type *	Val,
		unsigned	Index
	)

Definition at line 453 of file AArch64TargetTransformInfo.cpp.

References assert(), llvm::TargetTransformInfoImplBase::DL, llvm::TargetLoweringBase::getTypeLegalizationCost(), llvm::AArch64Subtarget::getVectorInsertExtractBaseCost(), llvm::Type::isVectorTy(), and llvm::AArch64CC::LT.

Referenced by getExtractWithExtendCost(), and getMinVectorRegisterBitWidth().

◆ shouldConsiderAddressTypePromotion()

bool AArch64TTIImpl::shouldConsiderAddressTypePromotion	(	const Instruction &	I,
		bool &	AllowPromotionWithoutCommonHeader
	)

See if I should be considered for address type promotion.

We check if I is a sext with right type and used in memory accesses. If it used in a "complex" getelementptr, we allow it to be promoted without finding other sext instructions that sign extended the same initial value. A getelementptr is considered as "complex" if it has more than 2 operands.

Definition at line 868 of file AArch64TargetTransformInfo.cpp.

References llvm::Function::getContext(), llvm::Type::getInt64Ty(), llvm::Instruction::getParent(), llvm::BasicBlock::getParent(), llvm::Value::getType(), and llvm::Value::users().

Referenced by getMinVectorRegisterBitWidth().