ARMISelDAGToDAG.cpp File Reference

#include "ARM.h"
#include "ARMBaseInstrInfo.h"
#include "ARMTargetMachine.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "Utils/ARMBaseInfo.h"
#include "llvm/ADT/APSInt.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IntrinsicsARM.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/TargetOptions.h"
#include <optional>
#include "ARMGenDAGISel.inc"

Go to the source code of this file.

Macros
#define	DEBUG_TYPE   "arm-isel"
#define	PASS_NAME   "ARM Instruction Selection"

Functions
static bool	isInt32Immediate (SDNode *N, unsigned &Imm)
	isInt32Immediate - This method tests to see if the node is a 32-bit constant operand.
static bool	isInt32Immediate (SDValue N, unsigned &Imm)
static bool	isOpcWithIntImmediate (SDNode *N, unsigned Opc, unsigned &Imm)
static bool	isScaledConstantInRange (SDValue Node, int Scale, int RangeMin, int RangeMax, int &ScaledConstant)
	Check whether a particular node is a constant value representable as (N * Scale) where (N in [RangeMin, RangeMax).
static bool	shouldUseZeroOffsetLdSt (SDValue N)
static SDValue	getAL (SelectionDAG *CurDAG, const SDLoc &dl)
	getAL - Returns a ARMCC::AL immediate node.
static bool	isVLDfixed (unsigned Opc)
static bool	isVSTfixed (unsigned Opc)
static unsigned	getVLDSTRegisterUpdateOpcode (unsigned Opc)
static bool	isPerfectIncrement (SDValue Inc, EVT VecTy, unsigned NumVecs)
	Returns true if the given increment is a Constant known to be equal to the access size performed by a NEON load/store.
static bool	SDValueToConstBool (SDValue SDVal)
static std::optional< std::pair< unsigned, unsigned > >	getContiguousRangeOfSetBits (const APInt &A)
static unsigned	getVectorShuffleOpcode (EVT VT, unsigned Opc64[3], unsigned Opc128[3])
static void	getIntOperandsFromRegisterString (StringRef RegString, SelectionDAG *CurDAG, const SDLoc &DL, std::vector< SDValue > &Ops)
static int	getBankedRegisterMask (StringRef RegString)
static int	getMClassFlagsMask (StringRef Flags)
static int	getMClassRegisterMask (StringRef Reg, const ARMSubtarget *Subtarget)
static int	getARClassRegisterMask (StringRef Reg, StringRef Flags)

Variables
static cl::opt< bool >	DisableShifterOp ("disable-shifter-op", cl::Hidden, cl::desc("Disable isel of shifter-op"), cl::init(false))

Macro Definition Documentation

DEBUG_TYPE

#define DEBUG_TYPE   "arm-isel"

Definition at line 42 of file ARMISelDAGToDAG.cpp.

PASS_NAME

#define PASS_NAME   "ARM Instruction Selection"

Definition at line 43 of file ARMISelDAGToDAG.cpp.

Function Documentation

getAL()

static SDValue getAL ( SelectionDAG *  CurDAG, const SDLoc &  dl  )

inlinestatic

getAL - Returns a ARMCC::AL immediate node.

Definition at line 1581 of file ARMISelDAGToDAG.cpp.

References llvm::ARMCC::AL, and llvm::SelectionDAG::getTargetConstant().

getARClassRegisterMask()

static int getARClassRegisterMask ( StringRef  Reg, StringRef  Flags  )

static

Definition at line 5432 of file ARMISelDAGToDAG.cpp.

References Flags, and getMClassFlagsMask().

getBankedRegisterMask()

static int getBankedRegisterMask ( StringRef  RegString )

inlinestatic

Definition at line 5401 of file ARMISelDAGToDAG.cpp.

References llvm::StringRef::lower().

getContiguousRangeOfSetBits()

static std::optional< std::pair< unsigned, unsigned > > getContiguousRangeOfSetBits ( const APInt &  A )

static

Definition at line 3539 of file ARMISelDAGToDAG.cpp.

References A.

getIntOperandsFromRegisterString()

static void getIntOperandsFromRegisterString ( StringRef  RegString, SelectionDAG *  CurDAG, const SDLoc &  DL, std::vector< SDValue > &  Ops  )

static

Definition at line 5373 of file ARMISelDAGToDAG.cpp.

References assert(), DL, llvm::SelectionDAG::getTargetConstant(), llvm::SmallVectorBase< Size_T >::size(), and llvm::StringRef::split().

getMClassFlagsMask()

static int getMClassFlagsMask ( StringRef  Flags )

inlinestatic

Definition at line 5411 of file ARMISelDAGToDAG.cpp.

References llvm::StringSwitch< T, R >::Case(), llvm::StringSwitch< T, R >::Default(), and Flags.

Referenced by getARClassRegisterMask().

getMClassRegisterMask()

static int getMClassRegisterMask ( StringRef  Reg, const ARMSubtarget *  Subtarget  )

static

Definition at line 5424 of file ARMISelDAGToDAG.cpp.

getVectorShuffleOpcode()

static unsigned getVectorShuffleOpcode ( EVT  VT, unsigned  Opc64[3], unsigned  Opc128[3]  )

static

Definition at line 3618 of file ARMISelDAGToDAG.cpp.

References assert(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), and llvm_unreachable.

getVLDSTRegisterUpdateOpcode()

static unsigned getVLDSTRegisterUpdateOpcode ( unsigned  Opc )

static

Definition at line 2031 of file ARMISelDAGToDAG.cpp.

References assert(), isVLDfixed(), and isVSTfixed().

isInt32Immediate() [1/2]

static bool isInt32Immediate ( SDNode *  N, unsigned &  Imm  )

static

isInt32Immediate - This method tests to see if the node is a 32-bit constant operand.

If so Imm will receive the 32-bit value.

Definition at line 372 of file ARMISelDAGToDAG.cpp.

References llvm::ISD::Constant, and N.

Referenced by isInt32Immediate(), and isOpcWithIntImmediate().

isInt32Immediate() [2/2]

static bool isInt32Immediate ( SDValue  N, unsigned &  Imm  )

static

Definition at line 382 of file ARMISelDAGToDAG.cpp.

References isInt32Immediate(), and N.

isOpcWithIntImmediate()

static bool isOpcWithIntImmediate ( SDNode *  N, unsigned  Opc, unsigned &  Imm  )

static

Definition at line 389 of file ARMISelDAGToDAG.cpp.

References isInt32Immediate(), and N.

isPerfectIncrement()

static bool isPerfectIncrement ( SDValue  Inc, EVT  VecTy, unsigned  NumVecs  )

static

Returns true if the given increment is a Constant known to be equal to the access size performed by a NEON load/store.

This means the "[rN]!" form can be used.

Definition at line 2105 of file ARMISelDAGToDAG.cpp.

References llvm::CallingConv::C, and llvm::EVT::getSizeInBits().

isScaledConstantInRange()

static bool isScaledConstantInRange ( SDValue  Node, int  Scale, int  RangeMin, int  RangeMax, int &  ScaledConstant  )

static

Check whether a particular node is a constant value representable as (N * Scale) where (N in [RangeMin, RangeMax).

Parameters

ScaledConstant

[out] - On success, the pre-scaled constant value.

Definition at line 398 of file ARMISelDAGToDAG.cpp.

References assert(), and llvm::CallingConv::C.

isVLDfixed()

static bool isVLDfixed ( unsigned  Opc )

static

Definition at line 1958 of file ARMISelDAGToDAG.cpp.

Referenced by getVLDSTRegisterUpdateOpcode().

isVSTfixed()

static bool isVSTfixed ( unsigned  Opc )

static

Definition at line 2000 of file ARMISelDAGToDAG.cpp.

Referenced by getVLDSTRegisterUpdateOpcode().

SDValueToConstBool()

static bool SDValueToConstBool ( SDValue  SDVal )

static

Definition at line 2699 of file ARMISelDAGToDAG.cpp.

References assert(), and llvm::ConstantSDNode::getZExtValue().

shouldUseZeroOffsetLdSt()

static bool shouldUseZeroOffsetLdSt ( SDValue  N )

static

Definition at line 1116 of file ARMISelDAGToDAG.cpp.

References llvm::ISD::ADD, llvm::CallingConv::C, and N.

Variable Documentation

DisableShifterOp

cl::opt< bool > DisableShifterOp("disable-shifter-op", cl::Hidden, cl::desc("Disable isel of shifter-op"), cl::init(false)) ( "disable-shifter-op"  , cl::Hidden  , cl::desc("Disable isel of shifter-op")  , cl::init(false)    )

static