#include "ARM.h"#include "ARMBaseInstrInfo.h"#include "ARMTargetMachine.h"#include "MCTargetDesc/ARMAddressingModes.h"#include "Utils/ARMBaseInfo.h"#include "llvm/ADT/StringSwitch.h"#include "llvm/CodeGen/MachineFrameInfo.h"#include "llvm/CodeGen/MachineFunction.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/CodeGen/SelectionDAG.h"#include "llvm/CodeGen/SelectionDAGISel.h"#include "llvm/CodeGen/TargetLowering.h"#include "llvm/IR/CallingConv.h"#include "llvm/IR/Constants.h"#include "llvm/IR/DerivedTypes.h"#include "llvm/IR/Function.h"#include "llvm/IR/Intrinsics.h"#include "llvm/IR/LLVMContext.h"#include "llvm/Support/CommandLine.h"#include "llvm/Support/Debug.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Target/TargetOptions.h"#include "ARMGenDAGISel.inc"
Go to the source code of this file.
Macros | |
| #define | DEBUG_TYPE "arm-isel" |
Functions | |
| static bool | isInt32Immediate (SDNode *N, unsigned &Imm) |
| isInt32Immediate - This method tests to see if the node is a 32-bit constant operand. More... | |
| static bool | isInt32Immediate (SDValue N, unsigned &Imm) |
| static bool | isOpcWithIntImmediate (SDNode *N, unsigned Opc, unsigned &Imm) |
| static bool | isScaledConstantInRange (SDValue Node, int Scale, int RangeMin, int RangeMax, int &ScaledConstant) |
Check whether a particular node is a constant value representable as (N * Scale) where (N in [RangeMin, RangeMax). More... | |
| static bool | shouldUseZeroOffsetLdSt (SDValue N) |
| static SDValue | getAL (SelectionDAG *CurDAG, const SDLoc &dl) |
| getAL - Returns a ARMCC::AL immediate node. More... | |
| static bool | isVLDfixed (unsigned Opc) |
| static bool | isVSTfixed (unsigned Opc) |
| static unsigned | getVLDSTRegisterUpdateOpcode (unsigned Opc) |
| static bool | isPerfectIncrement (SDValue Inc, EVT VecTy, unsigned NumVecs) |
| Returns true if the given increment is a Constant known to be equal to the access size performed by a NEON load/store. More... | |
| static Optional< std::pair< unsigned, unsigned > > | getContiguousRangeOfSetBits (const APInt &A) |
| static void | getIntOperandsFromRegisterString (StringRef RegString, SelectionDAG *CurDAG, const SDLoc &DL, std::vector< SDValue > &Ops) |
| static int | getBankedRegisterMask (StringRef RegString) |
| static int | getMClassFlagsMask (StringRef Flags) |
| static int | getMClassRegisterMask (StringRef Reg, const ARMSubtarget *Subtarget) |
| static int | getARClassRegisterMask (StringRef Reg, StringRef Flags) |
Variables | |
| static cl::opt< bool > | DisableShifterOp ("disable-shifter-op", cl::Hidden, cl::desc("Disable isel of shifter-op"), cl::init(false)) |
Macro Definition Documentation
◆ DEBUG_TYPE
| #define DEBUG_TYPE "arm-isel" |
Definition at line 39 of file ARMISelDAGToDAG.cpp.
Function Documentation
◆ getAL()
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inlinestatic |
getAL - Returns a ARMCC::AL immediate node.
Definition at line 1429 of file ARMISelDAGToDAG.cpp.
References llvm::ARMCC::AL, llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, createGPRPairNode(), llvm::dyn_cast(), llvm::LSBaseSDNode::getAddressingMode(), llvm::MemSDNode::getAlignment(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::LoadSDNode::getExtensionType(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::LoadSDNode::getOffset(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetConstant(), llvm::SDNode::getValueType(), llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i8, llvm::ARMSubtarget::isLittle(), llvm::EVT::isVector(), llvm::ARM_MB::LD, llvm::Match, N, llvm::ISD::NON_EXTLOAD, llvm::ARMVCC::None, llvm::MVT::Other, llvm::ISD::POST_INC, llvm::ISD::PRE_DEC, llvm::ISD::PRE_INC, llvm::ISD::SEXTLOAD, llvm::MVT::SimpleTy, llvm::ISD::UNINDEXED, llvm::MVT::v16i8, llvm::NVPTX::PTXLdStInstCode::V2, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v4i8, llvm::MVT::v8f16, llvm::MVT::v8i16, and llvm::MVT::v8i8.
Referenced by getARClassRegisterMask(), getContiguousRangeOfSetBits(), and isPerfectIncrement().
◆ getARClassRegisterMask()
Definition at line 4106 of file ARMISelDAGToDAG.cpp.
References llvm::SmallVectorImpl< T >::append(), assert(), C, llvm::StringSwitch< T, R >::Case(), llvm::InlineAsm::Constraint_i, llvm::InlineAsm::Constraint_m, llvm::InlineAsm::Constraint_o, llvm::InlineAsm::Constraint_Q, llvm::InlineAsm::Constraint_Um, llvm::InlineAsm::Constraint_Un, llvm::InlineAsm::Constraint_Uq, llvm::InlineAsm::Constraint_Us, llvm::InlineAsm::Constraint_Ut, llvm::InlineAsm::Constraint_Uv, llvm::InlineAsm::Constraint_Uy, createGPRPairNode(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::StringSwitch< T, R >::Default(), llvm::dyn_cast(), llvm::numbers::e, llvm::StringRef::empty(), getAL(), getBankedRegisterMask(), llvm::InlineAsm::getFlagWord(), llvm::InlineAsm::getFlagWordForMatchingOp(), llvm::InlineAsm::getFlagWordForRegClass(), llvm::SDNode::getGluedNode(), llvm::SDNode::getGluedUser(), getIntOperandsFromRegisterString(), llvm::InlineAsm::getKind(), getMClassFlagsMask(), getMClassRegisterMask(), llvm::MDNodeSDNode::getMD(), llvm::SDValue::getNode(), llvm::InlineAsm::getNumOperandRegisters(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::MDNode::getOperand(), getReg(), llvm::SDValue::getValue(), llvm::MVT::Glue, llvm::ARMSubtarget::hasFPARMv8Base(), llvm::InlineAsm::hasRegClassConstraint(), llvm::ARMSubtarget::hasVFP2Base(), llvm::MVT::i32, llvm::ARMSubtarget::isMClass(), llvm::ARMSubtarget::isThumb2(), llvm::InlineAsm::isUseOperandTiedToDef(), llvm::InlineAsm::Kind_Imm, llvm::InlineAsm::Kind_Mem, llvm::InlineAsm::Kind_RegDef, llvm::InlineAsm::Kind_RegDefEarlyClobber, llvm::InlineAsm::Kind_RegUse, LLVM_FALLTHROUGH, llvm_unreachable, llvm::BitmaskEnumDetail::Mask(), MRI, op, llvm::SDNode::op_begin(), llvm::SDNode::op_end(), llvm::InlineAsm::Op_FirstOperand, llvm::InlineAsm::Op_InputChain, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T >::push_back(), Reg, llvm::StringRef::rsplit(), llvm::SDNode::setNodeId(), llvm::SmallVectorBase::size(), T1, and llvm::MVT::Untyped.
◆ getBankedRegisterMask()
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inlinestatic |
Definition at line 4075 of file ARMISelDAGToDAG.cpp.
References llvm::StringRef::lower().
Referenced by getARClassRegisterMask().
◆ getContiguousRangeOfSetBits()
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static |
Definition at line 2643 of file ARMISelDAGToDAG.cpp.
References llvm::MCID::Add, llvm::ISD::ADD, llvm::ISD::AND, llvm::AMDGPU::HSAMD::Kernel::Key::Args, assert(), llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::BasicBlock, llvm::ARMISD::BRCOND, llvm::ARMISD::BUILD_VECTOR, C, llvm::ARMISD::CMOV, llvm::ARMISD::CMPZ, llvm::ISD::Constant, llvm::ConstantMaterializationCost(), llvm::ISD::CopyFromReg, llvm::APInt::countLeadingZeros(), llvm::APInt::countPopulation(), llvm::APInt::countTrailingZeros(), createGPRPairNode(), llvm::dyn_cast(), llvm::ARMCC::EQ, llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FrameIndex, llvm::ConstantInt::get(), getAL(), llvm::StoreSDNode::getBasePtr(), llvm::APInt::getBitWidth(), llvm::MemSDNode::getChain(), llvm::MachinePointerInfo::getConstantPool(), llvm::Type::getInt32Ty(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineFunction::getMachineMemOperand(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SDNode::getNodeId(), llvm::SDNode::getNumValues(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), getReg(), llvm::SDValue::getResNo(), llvm::EVT::getSimpleVT(), llvm::ARM_AM::getSORegOpc(), llvm::SDValue::getValue(), llvm::StoreSDNode::getValue(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SDNode::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::Glue, llvm::ARMSubtarget::hasDSP(), llvm::ARMSubtarget::hasMVEIntegerOps(), llvm::SDNode::hasOneUse(), llvm::ARMSubtarget::hasThumb2(), llvm::ARMSubtarget::hasV6Ops(), llvm::ARMSubtarget::hasV6T2Ops(), llvm::ARMSubtarget::hasV8MBaselineOps(), llvm::MVT::i32, llvm::X86II::Imm16, llvm::ISD::INLINEASM, llvm::ISD::INLINEASM_BR, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::SDNode::isMachineOpcode(), llvm::isPowerOf2_32(), isScaledConstantInRange(), isThumb(), llvm::ARMSubtarget::isThumb(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), llvm::LSBaseSDNode::isUnindexed(), llvm::ARMISD::LE, llvm_unreachable, llvm::ISD::LOAD, llvm::Log2_32(), llvm::ARMISD::LOOP_DEC, llvm::ARM_AM::lsl, llvm::ARMCC::MI, llvm::MachineMemOperand::MOLoad, llvm::ISD::MUL, N, llvm::ARMCC::NE, llvm::ISD::OR, llvm::MVT::Other, llvm::ARMCC::PL, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::ISD::READ_REGISTER, llvm::ISD::Register, llvm::MCID::Select, llvm::SDNode::setNodeId(), llvm::MachineFrameInfo::setObjectAlignment(), llvm::ISD::SIGN_EXTEND_INREG, llvm::MVT::SimpleTy, Size, llvm::ARMISD::SMLAL, llvm::ISD::SMUL_LOHI, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ARM_MB::ST, llvm::ISD::STORE, llvm::ARMISD::SUBC, llvm::ARMISD::SUBE, llvm::ARMISD::UMAAL, llvm::ARMISD::UMLAL, llvm::MVT::Untyped, llvm::SDValue::use_empty(), llvm::MVT::v16i8, llvm::MVT::v2f32, llvm::MVT::v2i32, llvm::MVT::v4f16, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8f16, llvm::MVT::v8i16, llvm::MVT::v8i8, llvm::ARMISD::VLD1_UPD, llvm::ARMISD::VLD1DUP, llvm::ARMISD::VLD1DUP_UPD, llvm::ARMISD::VLD2_UPD, llvm::ARMISD::VLD2DUP, llvm::ARMISD::VLD2DUP_UPD, llvm::ARMISD::VLD2LN_UPD, llvm::ARMISD::VLD3_UPD, llvm::ARMISD::VLD3DUP, llvm::ARMISD::VLD3DUP_UPD, llvm::ARMISD::VLD3LN_UPD, llvm::ARMISD::VLD4_UPD, llvm::ARMISD::VLD4DUP, llvm::ARMISD::VLD4DUP_UPD, llvm::ARMISD::VLD4LN_UPD, llvm::ARMISD::VST1_UPD, llvm::ARMISD::VST2_UPD, llvm::ARMISD::VST2LN_UPD, llvm::ARMISD::VST3_UPD, llvm::ARMISD::VST3LN_UPD, llvm::ARMISD::VST4_UPD, llvm::ARMISD::VST4LN_UPD, llvm::ARMISD::VTRN, llvm::ARMISD::VUZP, llvm::ARMISD::VZIP, llvm::ARMISD::WLS, llvm::ISD::WRITE_REGISTER, X, and llvm::ISD::XOR.
◆ getIntOperandsFromRegisterString()
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static |
Definition at line 4048 of file ARMISelDAGToDAG.cpp.
References assert(), llvm::tgtok::Field, llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i32, llvm::SmallVectorBase::size(), and llvm::StringRef::split().
Referenced by getARClassRegisterMask().
◆ getMClassFlagsMask()
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inlinestatic |
Definition at line 4085 of file ARMISelDAGToDAG.cpp.
References llvm::StringSwitch< T, R >::Case(), and llvm::StringSwitch< T, R >::Default().
Referenced by getARClassRegisterMask().
◆ getMClassRegisterMask()
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static |
Definition at line 4098 of file ARMISelDAGToDAG.cpp.
Referenced by getARClassRegisterMask().
◆ getVLDSTRegisterUpdateOpcode()
Definition at line 1826 of file ARMISelDAGToDAG.cpp.
References assert(), isVLDfixed(), and isVSTfixed().
Referenced by isPerfectIncrement().
◆ isInt32Immediate() [1/2]
isInt32Immediate - This method tests to see if the node is a 32-bit constant operand.
If so Imm will receive the 32-bit value.
Definition at line 271 of file ARMISelDAGToDAG.cpp.
References llvm::ISD::Constant, llvm::SDNode::getOpcode(), llvm::SDNode::getValueType(), llvm::MVT::i32, and N.
Referenced by isInt32Immediate(), isOpcWithIntImmediate(), and isPerfectIncrement().
◆ isInt32Immediate() [2/2]
Definition at line 281 of file ARMISelDAGToDAG.cpp.
References llvm::SDValue::getNode(), and isInt32Immediate().
◆ isOpcWithIntImmediate()
Definition at line 288 of file ARMISelDAGToDAG.cpp.
References llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), and isInt32Immediate().
Referenced by isPerfectIncrement().
◆ isPerfectIncrement()
Returns true if the given increment is a Constant known to be equal to the access size performed by a NEON load/store.
This means the "[rN]!" form can be used.
Definition at line 1885 of file ARMISelDAGToDAG.cpp.
References llvm::ISD::ABS, llvm::ISD::ADD, llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::ISD::AND, assert(), C, llvm::countLeadingZeros(), llvm::countTrailingOnes(), llvm::countTrailingZeros(), llvm::dyn_cast(), getAL(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::ARM_AM::getShiftOpcForNode(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::ARM_AM::getSORegOpc(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), getVLDSTRegisterUpdateOpcode(), llvm::ConstantSDNode::getZExtValue(), llvm::ARMSubtarget::hasV6T2Ops(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::EVT::is64BitVector(), isInt32Immediate(), isOpcWithIntImmediate(), llvm::isShiftedMask_32(), llvm::ARMSubtarget::isThumb(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), isVLDfixed(), isVSTfixed(), llvm_unreachable, N, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, llvm::MVT::SimpleTy, Size, llvm::ISD::SRA, llvm::ISD::SRL, llvm::MVT::v16i8, llvm::MVT::v1f64, llvm::MVT::v1i64, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4f16, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v8f16, llvm::MVT::v8i16, llvm::MVT::v8i64, and llvm::MVT::v8i8.
◆ isScaledConstantInRange()
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static |
Check whether a particular node is a constant value representable as (N * Scale) where (N in [RangeMin, RangeMax).
- Parameters
-
ScaledConstant [out] - On success, the pre-scaled constant value.
Definition at line 297 of file ARMISelDAGToDAG.cpp.
Referenced by getContiguousRangeOfSetBits(), and shouldUseZeroOffsetLdSt().
◆ isVLDfixed()
Definition at line 1768 of file ARMISelDAGToDAG.cpp.
Referenced by getVLDSTRegisterUpdateOpcode(), and isPerfectIncrement().
◆ isVSTfixed()
Definition at line 1801 of file ARMISelDAGToDAG.cpp.
Referenced by getVLDSTRegisterUpdateOpcode(), and isPerfectIncrement().
◆ shouldUseZeroOffsetLdSt()
Definition at line 1017 of file ARMISelDAGToDAG.cpp.
References llvm::ISD::ADD, C, llvm::dyn_cast(), llvm::ISD::FrameIndex, llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::ARM_AM::getShiftOpcForNode(), llvm::HandleSDNode::getValue(), llvm::ConstantSDNode::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::MVT::i32, llvm::MachineFrameInfo::isFixedObjectIndex(), llvm::ConstantSDNode::isNullValue(), isScaledConstantInRange(), llvm::ISD::LOAD, llvm::ARM_AM::lsl, llvm::ISD::MUL, N, NC, llvm::ISD::POST_INC, llvm::ISD::PRE_INC, llvm::MachineFrameInfo::setObjectAlignment(), llvm::ISD::SUB, std::swap(), llvm::ISD::TargetConstantPool, llvm::ISD::TargetExternalSymbol, llvm::ISD::TargetGlobalAddress, llvm::ISD::TargetGlobalTLSAddress, and llvm::ARMISD::Wrapper.
