LLVM 20.0.0git
|
#include "ARM.h"
#include "ARMBaseInstrInfo.h"
#include "ARMTargetMachine.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "Utils/ARMBaseInfo.h"
#include "llvm/ADT/APSInt.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IntrinsicsARM.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/TargetOptions.h"
#include <optional>
#include "ARMGenDAGISel.inc"
Go to the source code of this file.
Macros | |
#define | DEBUG_TYPE "arm-isel" |
#define | PASS_NAME "ARM Instruction Selection" |
Functions | |
static bool | isInt32Immediate (SDNode *N, unsigned &Imm) |
isInt32Immediate - This method tests to see if the node is a 32-bit constant operand. | |
static bool | isInt32Immediate (SDValue N, unsigned &Imm) |
static bool | isOpcWithIntImmediate (SDNode *N, unsigned Opc, unsigned &Imm) |
static bool | isScaledConstantInRange (SDValue Node, int Scale, int RangeMin, int RangeMax, int &ScaledConstant) |
Check whether a particular node is a constant value representable as (N * Scale) where (N in [RangeMin , RangeMax ). | |
static bool | shouldUseZeroOffsetLdSt (SDValue N) |
static SDValue | getAL (SelectionDAG *CurDAG, const SDLoc &dl) |
getAL - Returns a ARMCC::AL immediate node. | |
static bool | isVLDfixed (unsigned Opc) |
static bool | isVSTfixed (unsigned Opc) |
static unsigned | getVLDSTRegisterUpdateOpcode (unsigned Opc) |
static bool | isPerfectIncrement (SDValue Inc, EVT VecTy, unsigned NumVecs) |
Returns true if the given increment is a Constant known to be equal to the access size performed by a NEON load/store. | |
static bool | SDValueToConstBool (SDValue SDVal) |
static std::optional< std::pair< unsigned, unsigned > > | getContiguousRangeOfSetBits (const APInt &A) |
static unsigned | getVectorShuffleOpcode (EVT VT, unsigned Opc64[3], unsigned Opc128[3]) |
static void | getIntOperandsFromRegisterString (StringRef RegString, SelectionDAG *CurDAG, const SDLoc &DL, std::vector< SDValue > &Ops) |
static int | getBankedRegisterMask (StringRef RegString) |
static int | getMClassFlagsMask (StringRef Flags) |
static int | getMClassRegisterMask (StringRef Reg, const ARMSubtarget *Subtarget) |
static int | getARClassRegisterMask (StringRef Reg, StringRef Flags) |
Variables | |
static cl::opt< bool > | DisableShifterOp ("disable-shifter-op", cl::Hidden, cl::desc("Disable isel of shifter-op"), cl::init(false)) |
#define DEBUG_TYPE "arm-isel" |
Definition at line 40 of file ARMISelDAGToDAG.cpp.
#define PASS_NAME "ARM Instruction Selection" |
Definition at line 41 of file ARMISelDAGToDAG.cpp.
|
inlinestatic |
getAL - Returns a ARMCC::AL immediate node.
Definition at line 1577 of file ARMISelDAGToDAG.cpp.
References llvm::ARMCC::AL, and llvm::SelectionDAG::getTargetConstant().
Definition at line 5413 of file ARMISelDAGToDAG.cpp.
References getMClassFlagsMask().
|
inlinestatic |
Definition at line 5382 of file ARMISelDAGToDAG.cpp.
References llvm::StringRef::lower().
|
static |
Definition at line 3529 of file ARMISelDAGToDAG.cpp.
References A.
|
static |
Definition at line 5354 of file ARMISelDAGToDAG.cpp.
References assert(), DL, llvm::SelectionDAG::getTargetConstant(), llvm::SmallVectorBase< Size_T >::size(), and llvm::StringRef::split().
|
inlinestatic |
Definition at line 5392 of file ARMISelDAGToDAG.cpp.
References llvm::StringSwitch< T, R >::Case(), and llvm::StringSwitch< T, R >::Default().
Referenced by getARClassRegisterMask().
|
static |
Definition at line 5405 of file ARMISelDAGToDAG.cpp.
Definition at line 3611 of file ARMISelDAGToDAG.cpp.
References assert(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), and llvm_unreachable.
Definition at line 2027 of file ARMISelDAGToDAG.cpp.
References assert(), isVLDfixed(), and isVSTfixed().
isInt32Immediate - This method tests to see if the node is a 32-bit constant operand.
If so Imm will receive the 32-bit value.
Definition at line 370 of file ARMISelDAGToDAG.cpp.
References llvm::ISD::Constant, and N.
Referenced by isInt32Immediate(), and isOpcWithIntImmediate().
Definition at line 380 of file ARMISelDAGToDAG.cpp.
References isInt32Immediate(), and N.
Definition at line 387 of file ARMISelDAGToDAG.cpp.
References isInt32Immediate(), and N.
Returns true if the given increment is a Constant known to be equal to the access size performed by a NEON load/store.
This means the "[rN]!" form can be used.
Definition at line 2101 of file ARMISelDAGToDAG.cpp.
References llvm::CallingConv::C, and llvm::EVT::getSizeInBits().
|
static |
Check whether a particular node is a constant value representable as (N * Scale) where (N in [RangeMin
, RangeMax
).
ScaledConstant | [out] - On success, the pre-scaled constant value. |
Definition at line 396 of file ARMISelDAGToDAG.cpp.
References assert(), and llvm::CallingConv::C.
Definition at line 1954 of file ARMISelDAGToDAG.cpp.
Referenced by getVLDSTRegisterUpdateOpcode().
Definition at line 1996 of file ARMISelDAGToDAG.cpp.
Referenced by getVLDSTRegisterUpdateOpcode().
Definition at line 2694 of file ARMISelDAGToDAG.cpp.
References assert(), and llvm::ConstantSDNode::getZExtValue().
Definition at line 1113 of file ARMISelDAGToDAG.cpp.
References llvm::ISD::ADD, llvm::CallingConv::C, and N.