20#define DEBUG_TYPE "instructionselector"
25 : Renderers(MaxRenderers) {}
34 return VRegVal->Value.getSExtValue() ==
Value;
44 if (RootI->
getOpcode() != TargetOpcode::G_PTR_ADD)
49 if (RHSI->
getOpcode() != TargetOpcode::G_CONSTANT)
63 if (
MI.isConvergent() &&
MI.getParent() != IntoMI.
getParent())
66 return !
MI.mayLoadOrStore() && !
MI.mayRaiseFPException() &&
67 !
MI.hasUnmodeledSideEffects() &&
MI.implicit_operands().empty();
unsigned const MachineRegisterInfo * MRI
bool isOperandImmEqual(const MachineOperand &MO, int64_t Value, const MachineRegisterInfo &MRI) const
bool isBaseWithConstantOffset(const MachineOperand &Root, const MachineRegisterInfo &MRI) const
Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on the right-hand side.
bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const
Return true if MI can obviously be folded into IntoMI.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
LLVM Value Representation.
self_iterator getIterator()
This is an optimization pass for GlobalISel generic memory operations.
std::optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
MatcherState(unsigned MaxRenderers)