LLVM 20.0.0git
X86RegisterBankInfo.h
Go to the documentation of this file.
1//===- X86RegisterBankInfo ---------------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the targeting of the RegisterBankInfo class for X86.
10/// \todo This should be generated by TableGen.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_X86_X86REGISTERBANKINFO_H
14#define LLVM_LIB_TARGET_X86_X86REGISTERBANKINFO_H
15
17
18#define GET_REGBANK_DECLARATIONS
19#include "X86GenRegisterBank.inc"
20
21namespace llvm {
22
23class LLT;
24
26protected:
27#define GET_TARGET_REGBANK_CLASS
28#include "X86GenRegisterBank.inc"
29#define GET_TARGET_REGBANK_INFO_CLASS
30#include "X86GenRegisterBankInfo.def"
31
34
35 static PartialMappingIdx getPartialMappingIdx(const MachineInstr &MI,
36 const LLT &Ty, bool isFP);
38 getValueMapping(PartialMappingIdx Idx, unsigned NumOperands);
39};
40
42
43/// This class provides the information for the target register banks.
45private:
46 /// Get an instruction mapping.
47 /// \return An InstructionMappings with a statically allocated
48 /// OperandsMapping.
49 const InstructionMapping &getSameOperandsMapping(const MachineInstr &MI,
50 bool isFP) const;
51
52 /// Track the bank of each instruction operand(register)
53 static void
54 getInstrPartialMappingIdxs(const MachineInstr &MI,
55 const MachineRegisterInfo &MRI, const bool isFP,
57
58 /// Construct the instruction ValueMapping from PartialMappingIdxs
59 /// \return true if mapping succeeded.
60 static bool
61 getInstrValueMapping(const MachineInstr &MI,
62 const SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx,
64
65 // Maximum recursion depth for hasFPConstraints.
66 const unsigned MaxFPRSearchDepth = 2;
67
68 /// \returns true if \p MI only uses and defines FPRs.
69 bool hasFPConstraints(const MachineInstr &MI, const MachineRegisterInfo &MRI,
71 unsigned Depth = 0) const;
72
73 /// \returns true if \p MI only uses FPRs.
74 bool onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
75 const TargetRegisterInfo &TRI, unsigned Depth = 0) const;
76
77 /// \returns true if \p MI only defines FPRs.
78 bool onlyDefinesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
79 const TargetRegisterInfo &TRI, unsigned Depth = 0) const;
80
81public:
83
85 getInstrAlternativeMappings(const MachineInstr &MI) const override;
86
87 /// See RegisterBankInfo::applyMapping.
89 const OperandsMapper &OpdMapper) const override;
90
91 const InstructionMapping &
92 getInstrMapping(const MachineInstr &MI) const override;
93};
94
95} // namespace llvm
96#endif
unsigned const MachineRegisterInfo * MRI
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
IRTranslator LLVM IR MI
unsigned const TargetRegisterInfo * TRI
Helper class to build MachineInstr.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Helper class that represents how the value of an instruction may be mapped and what is the related co...
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
Holds all the information related to register banks.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:587
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1210
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static PartialMappingIdx getPartialMappingIdx(const MachineInstr &MI, const LLT &Ty, bool isFP)
static RegisterBankInfo::PartialMapping PartMappings[]
static RegisterBankInfo::ValueMapping ValMappings[]
static const RegisterBankInfo::ValueMapping * getValueMapping(PartialMappingIdx Idx, unsigned NumOperands)
This class provides the information for the target register banks.
InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const override
Get the alternative mappings for MI.
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
void applyMappingImpl(MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const override
See RegisterBankInfo::applyMapping.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Helper struct that represents how a value is partially mapped into a register.
Helper struct that represents how a value is mapped through different register banks.