LLVM  15.0.0git
llvm::LanaiInstrInfo Member List

This is the complete list of members for llvm::LanaiInstrInfo, including all inherited members.

analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TrueBlock, MachineBasicBlock *&FalseBlock, SmallVectorImpl< MachineOperand > &Condition, bool AllowModify) const overridellvm::LanaiInstrInfo
analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const overridellvm::LanaiInstrInfo
analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const overridellvm::LanaiInstrInfo
areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const overridellvm::LanaiInstrInfo
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, const DebugLoc &DL, MCRegister DestinationRegister, MCRegister SourceRegister, bool KillSource) const overridellvm::LanaiInstrInfo
decomposeMachineOperandsTargetFlags(unsigned TF) const overridellvm::LanaiInstrInfo
expandPostRAPseudo(MachineInstr &MI) const overridellvm::LanaiInstrInfo
getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const overridellvm::LanaiInstrInfo
getMemOperandWithOffsetWidth(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, unsigned &Width, const TargetRegisterInfo *TRI) constllvm::LanaiInstrInfo
getRegisterInfo() constllvm::LanaiInstrInfoinlinevirtual
getSerializableDirectMachineOperandTargetFlags() const overridellvm::LanaiInstrInfo
insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock, MachineBasicBlock *FalseBlock, ArrayRef< MachineOperand > Condition, const DebugLoc &DL, int *BytesAdded=nullptr) const overridellvm::LanaiInstrInfo
isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::LanaiInstrInfo
isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const overridellvm::LanaiInstrInfo
isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const overridellvm::LanaiInstrInfo
LanaiInstrInfo()llvm::LanaiInstrInfo
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, Register DestinationRegister, int FrameIndex, const TargetRegisterClass *RegisterClass, const TargetRegisterInfo *RegisterInfo) const overridellvm::LanaiInstrInfo
optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const overridellvm::LanaiInstrInfo
optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool PreferFalse) const overridellvm::LanaiInstrInfo
removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const overridellvm::LanaiInstrInfo
reverseBranchCondition(SmallVectorImpl< MachineOperand > &Condition) const overridellvm::LanaiInstrInfo
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, Register SourceRegister, bool IsKill, int FrameIndex, const TargetRegisterClass *RegisterClass, const TargetRegisterInfo *RegisterInfo) const overridellvm::LanaiInstrInfo