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X86FrameLowering.cpp
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00001 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the X86 implementation of TargetFrameLowering class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "X86FrameLowering.h"
00015 #include "X86InstrBuilder.h"
00016 #include "X86InstrInfo.h"
00017 #include "X86MachineFunctionInfo.h"
00018 #include "X86Subtarget.h"
00019 #include "X86TargetMachine.h"
00020 #include "llvm/ADT/SmallSet.h"
00021 #include "llvm/CodeGen/MachineFrameInfo.h"
00022 #include "llvm/CodeGen/MachineFunction.h"
00023 #include "llvm/CodeGen/MachineInstrBuilder.h"
00024 #include "llvm/CodeGen/MachineModuleInfo.h"
00025 #include "llvm/CodeGen/MachineRegisterInfo.h"
00026 #include "llvm/IR/DataLayout.h"
00027 #include "llvm/IR/Function.h"
00028 #include "llvm/MC/MCAsmInfo.h"
00029 #include "llvm/MC/MCSymbol.h"
00030 #include "llvm/Support/CommandLine.h"
00031 #include "llvm/Target/TargetOptions.h"
00032 
00033 using namespace llvm;
00034 
00035 // FIXME: completely move here.
00036 extern cl::opt<bool> ForceStackAlign;
00037 
00038 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
00039   return !MF.getFrameInfo()->hasVarSizedObjects();
00040 }
00041 
00042 /// hasFP - Return true if the specified function should have a dedicated frame
00043 /// pointer register.  This is true if the function has variable sized allocas
00044 /// or if frame pointer elimination is disabled.
00045 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
00046   const MachineFrameInfo *MFI = MF.getFrameInfo();
00047   const MachineModuleInfo &MMI = MF.getMMI();
00048   const TargetRegisterInfo *RegInfo = TM.getRegisterInfo();
00049 
00050   return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
00051           RegInfo->needsStackRealignment(MF) ||
00052           MFI->hasVarSizedObjects() ||
00053           MFI->isFrameAddressTaken() || MFI->hasInlineAsmWithSPAdjust() ||
00054           MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
00055           MMI.callsUnwindInit() || MMI.callsEHReturn());
00056 }
00057 
00058 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
00059   if (IsLP64) {
00060     if (isInt<8>(Imm))
00061       return X86::SUB64ri8;
00062     return X86::SUB64ri32;
00063   } else {
00064     if (isInt<8>(Imm))
00065       return X86::SUB32ri8;
00066     return X86::SUB32ri;
00067   }
00068 }
00069 
00070 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
00071   if (IsLP64) {
00072     if (isInt<8>(Imm))
00073       return X86::ADD64ri8;
00074     return X86::ADD64ri32;
00075   } else {
00076     if (isInt<8>(Imm))
00077       return X86::ADD32ri8;
00078     return X86::ADD32ri;
00079   }
00080 }
00081 
00082 static unsigned getLEArOpcode(unsigned IsLP64) {
00083   return IsLP64 ? X86::LEA64r : X86::LEA32r;
00084 }
00085 
00086 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
00087 /// when it reaches the "return" instruction. We can then pop a stack object
00088 /// to this register without worry about clobbering it.
00089 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
00090                                        MachineBasicBlock::iterator &MBBI,
00091                                        const TargetRegisterInfo &TRI,
00092                                        bool Is64Bit) {
00093   const MachineFunction *MF = MBB.getParent();
00094   const Function *F = MF->getFunction();
00095   if (!F || MF->getMMI().callsEHReturn())
00096     return 0;
00097 
00098   static const uint16_t CallerSavedRegs32Bit[] = {
00099     X86::EAX, X86::EDX, X86::ECX, 0
00100   };
00101 
00102   static const uint16_t CallerSavedRegs64Bit[] = {
00103     X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
00104     X86::R8,  X86::R9,  X86::R10, X86::R11, 0
00105   };
00106 
00107   unsigned Opc = MBBI->getOpcode();
00108   switch (Opc) {
00109   default: return 0;
00110   case X86::RETL:
00111   case X86::RETQ:
00112   case X86::RETIL:
00113   case X86::RETIQ:
00114   case X86::TCRETURNdi:
00115   case X86::TCRETURNri:
00116   case X86::TCRETURNmi:
00117   case X86::TCRETURNdi64:
00118   case X86::TCRETURNri64:
00119   case X86::TCRETURNmi64:
00120   case X86::EH_RETURN:
00121   case X86::EH_RETURN64: {
00122     SmallSet<uint16_t, 8> Uses;
00123     for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
00124       MachineOperand &MO = MBBI->getOperand(i);
00125       if (!MO.isReg() || MO.isDef())
00126         continue;
00127       unsigned Reg = MO.getReg();
00128       if (!Reg)
00129         continue;
00130       for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
00131         Uses.insert(*AI);
00132     }
00133 
00134     const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
00135     for (; *CS; ++CS)
00136       if (!Uses.count(*CS))
00137         return *CS;
00138   }
00139   }
00140 
00141   return 0;
00142 }
00143 
00144 
00145 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
00146 /// stack pointer by a constant value.
00147 static
00148 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
00149                   unsigned StackPtr, int64_t NumBytes,
00150                   bool Is64Bit, bool IsLP64, bool UseLEA,
00151                   const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
00152   bool isSub = NumBytes < 0;
00153   uint64_t Offset = isSub ? -NumBytes : NumBytes;
00154   unsigned Opc;
00155   if (UseLEA)
00156     Opc = getLEArOpcode(IsLP64);
00157   else
00158     Opc = isSub
00159       ? getSUBriOpcode(IsLP64, Offset)
00160       : getADDriOpcode(IsLP64, Offset);
00161 
00162   uint64_t Chunk = (1LL << 31) - 1;
00163   DebugLoc DL = MBB.findDebugLoc(MBBI);
00164 
00165   while (Offset) {
00166     uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
00167     if (ThisVal == (Is64Bit ? 8 : 4)) {
00168       // Use push / pop instead.
00169       unsigned Reg = isSub
00170         ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
00171         : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
00172       if (Reg) {
00173         Opc = isSub
00174           ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
00175           : (Is64Bit ? X86::POP64r  : X86::POP32r);
00176         MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
00177           .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
00178         if (isSub)
00179           MI->setFlag(MachineInstr::FrameSetup);
00180         Offset -= ThisVal;
00181         continue;
00182       }
00183     }
00184 
00185     MachineInstr *MI = NULL;
00186 
00187     if (UseLEA) {
00188       MI =  addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
00189                           StackPtr, false, isSub ? -ThisVal : ThisVal);
00190     } else {
00191       MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
00192             .addReg(StackPtr)
00193             .addImm(ThisVal);
00194       MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
00195     }
00196 
00197     if (isSub)
00198       MI->setFlag(MachineInstr::FrameSetup);
00199 
00200     Offset -= ThisVal;
00201   }
00202 }
00203 
00204 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
00205 static
00206 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
00207                       unsigned StackPtr, uint64_t *NumBytes = NULL) {
00208   if (MBBI == MBB.begin()) return;
00209 
00210   MachineBasicBlock::iterator PI = std::prev(MBBI);
00211   unsigned Opc = PI->getOpcode();
00212   if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
00213        Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
00214        Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
00215       PI->getOperand(0).getReg() == StackPtr) {
00216     if (NumBytes)
00217       *NumBytes += PI->getOperand(2).getImm();
00218     MBB.erase(PI);
00219   } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
00220               Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
00221              PI->getOperand(0).getReg() == StackPtr) {
00222     if (NumBytes)
00223       *NumBytes -= PI->getOperand(2).getImm();
00224     MBB.erase(PI);
00225   }
00226 }
00227 
00228 /// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower iterator.
00229 static
00230 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
00231                         MachineBasicBlock::iterator &MBBI,
00232                         unsigned StackPtr, uint64_t *NumBytes = NULL) {
00233   // FIXME:  THIS ISN'T RUN!!!
00234   return;
00235 
00236   if (MBBI == MBB.end()) return;
00237 
00238   MachineBasicBlock::iterator NI = std::next(MBBI);
00239   if (NI == MBB.end()) return;
00240 
00241   unsigned Opc = NI->getOpcode();
00242   if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
00243        Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
00244       NI->getOperand(0).getReg() == StackPtr) {
00245     if (NumBytes)
00246       *NumBytes -= NI->getOperand(2).getImm();
00247     MBB.erase(NI);
00248     MBBI = NI;
00249   } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
00250               Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
00251              NI->getOperand(0).getReg() == StackPtr) {
00252     if (NumBytes)
00253       *NumBytes += NI->getOperand(2).getImm();
00254     MBB.erase(NI);
00255     MBBI = NI;
00256   }
00257 }
00258 
00259 /// mergeSPUpdates - Checks the instruction before/after the passed
00260 /// instruction. If it is an ADD/SUB/LEA instruction it is deleted argument and the
00261 /// stack adjustment is returned as a positive value for ADD/LEA and a negative for
00262 /// SUB.
00263 static int mergeSPUpdates(MachineBasicBlock &MBB,
00264                            MachineBasicBlock::iterator &MBBI,
00265                            unsigned StackPtr,
00266                            bool doMergeWithPrevious) {
00267   if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
00268       (!doMergeWithPrevious && MBBI == MBB.end()))
00269     return 0;
00270 
00271   MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
00272   MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : std::next(MBBI);
00273   unsigned Opc = PI->getOpcode();
00274   int Offset = 0;
00275 
00276   if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
00277        Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
00278        Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
00279       PI->getOperand(0).getReg() == StackPtr){
00280     Offset += PI->getOperand(2).getImm();
00281     MBB.erase(PI);
00282     if (!doMergeWithPrevious) MBBI = NI;
00283   } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
00284               Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
00285              PI->getOperand(0).getReg() == StackPtr) {
00286     Offset -= PI->getOperand(2).getImm();
00287     MBB.erase(PI);
00288     if (!doMergeWithPrevious) MBBI = NI;
00289   }
00290 
00291   return Offset;
00292 }
00293 
00294 static bool isEAXLiveIn(MachineFunction &MF) {
00295   for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
00296        EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
00297     unsigned Reg = II->first;
00298 
00299     if (Reg == X86::EAX || Reg == X86::AX ||
00300         Reg == X86::AH || Reg == X86::AL)
00301       return true;
00302   }
00303 
00304   return false;
00305 }
00306 
00307 void X86FrameLowering::emitCalleeSavedFrameMoves(
00308     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL,
00309     unsigned FramePtr) const {
00310   MachineFunction &MF = *MBB.getParent();
00311   MachineFrameInfo *MFI = MF.getFrameInfo();
00312   MachineModuleInfo &MMI = MF.getMMI();
00313   const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
00314   const X86InstrInfo &TII = *TM.getInstrInfo();
00315 
00316   // Add callee saved registers to move list.
00317   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
00318   if (CSI.empty()) return;
00319 
00320   const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
00321   bool HasFP = hasFP(MF);
00322 
00323   // Calculate amount of bytes used for return address storing.
00324   int stackGrowth = -RegInfo->getSlotSize();
00325 
00326   // FIXME: This is dirty hack. The code itself is pretty mess right now.
00327   // It should be rewritten from scratch and generalized sometimes.
00328 
00329   // Determine maximum offset (minimum due to stack growth).
00330   int64_t MaxOffset = 0;
00331   for (std::vector<CalleeSavedInfo>::const_iterator
00332          I = CSI.begin(), E = CSI.end(); I != E; ++I)
00333     MaxOffset = std::min(MaxOffset,
00334                          MFI->getObjectOffset(I->getFrameIdx()));
00335 
00336   // Calculate offsets.
00337   int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
00338   for (std::vector<CalleeSavedInfo>::const_iterator
00339          I = CSI.begin(), E = CSI.end(); I != E; ++I) {
00340     int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
00341     unsigned Reg = I->getReg();
00342     Offset = MaxOffset - Offset + saveAreaOffset;
00343 
00344     // Don't output a new machine move if we're re-saving the frame
00345     // pointer. This happens when the PrologEpilogInserter has inserted an extra
00346     // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
00347     // generates one when frame pointers are used. If we generate a "machine
00348     // move" for this extra "PUSH", the linker will lose track of the fact that
00349     // the frame pointer should have the value of the first "PUSH" when it's
00350     // trying to unwind.
00351     //
00352     // FIXME: This looks inelegant. It's possibly correct, but it's covering up
00353     //        another bug. I.e., one where we generate a prolog like this:
00354     //
00355     //          pushl  %ebp
00356     //          movl   %esp, %ebp
00357     //          pushl  %ebp
00358     //          pushl  %esi
00359     //           ...
00360     //
00361     //        The immediate re-push of EBP is unnecessary. At the least, it's an
00362     //        optimization bug. EBP can be used as a scratch register in certain
00363     //        cases, but probably not when we have a frame pointer.
00364     if (HasFP && FramePtr == Reg)
00365       continue;
00366 
00367     unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
00368     unsigned CFIIndex =
00369         MMI.addFrameInst(MCCFIInstruction::createOffset(0, DwarfReg, Offset));
00370     BuildMI(MBB, MBBI, DL, TII.get(X86::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);
00371   }
00372 }
00373 
00374 /// usesTheStack - This function checks if any of the users of EFLAGS
00375 /// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has
00376 /// to use the stack, and if we don't adjust the stack we clobber the first
00377 /// frame index.
00378 /// See X86InstrInfo::copyPhysReg.
00379 static bool usesTheStack(const MachineFunction &MF) {
00380   const MachineRegisterInfo &MRI = MF.getRegInfo();
00381 
00382   for (MachineRegisterInfo::reg_instr_iterator
00383        ri = MRI.reg_instr_begin(X86::EFLAGS), re = MRI.reg_instr_end();
00384        ri != re; ++ri)
00385     if (ri->isCopy())
00386       return true;
00387 
00388   return false;
00389 }
00390 
00391 /// emitPrologue - Push callee-saved registers onto the stack, which
00392 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
00393 /// space for local variables. Also emit labels used by the exception handler to
00394 /// generate the exception handling frames.
00395 void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
00396   MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
00397   MachineBasicBlock::iterator MBBI = MBB.begin();
00398   MachineFrameInfo *MFI = MF.getFrameInfo();
00399   const Function *Fn = MF.getFunction();
00400   const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
00401   const X86InstrInfo &TII = *TM.getInstrInfo();
00402   MachineModuleInfo &MMI = MF.getMMI();
00403   X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
00404   bool needsFrameMoves = MMI.hasDebugInfo() ||
00405     Fn->needsUnwindTableEntry();
00406   uint64_t MaxAlign  = MFI->getMaxAlignment(); // Desired stack alignment.
00407   uint64_t StackSize = MFI->getStackSize();    // Number of bytes to allocate.
00408   bool HasFP = hasFP(MF);
00409   bool Is64Bit = STI.is64Bit();
00410   bool IsLP64 = STI.isTarget64BitLP64();
00411   bool IsWin64 = STI.isTargetWin64();
00412   bool UseLEA = STI.useLeaForSP();
00413   unsigned StackAlign = getStackAlignment();
00414   unsigned SlotSize = RegInfo->getSlotSize();
00415   unsigned FramePtr = RegInfo->getFrameRegister(MF);
00416   unsigned StackPtr = RegInfo->getStackRegister();
00417   unsigned BasePtr = RegInfo->getBaseRegister();
00418   DebugLoc DL;
00419 
00420   // If we're forcing a stack realignment we can't rely on just the frame
00421   // info, we need to know the ABI stack alignment as well in case we
00422   // have a call out.  Otherwise just make sure we have some alignment - we'll
00423   // go with the minimum SlotSize.
00424   if (ForceStackAlign) {
00425     if (MFI->hasCalls())
00426       MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
00427     else if (MaxAlign < SlotSize)
00428       MaxAlign = SlotSize;
00429   }
00430 
00431   // Add RETADDR move area to callee saved frame size.
00432   int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
00433   if (TailCallReturnAddrDelta < 0)
00434     X86FI->setCalleeSavedFrameSize(
00435       X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
00436 
00437   // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
00438   // function, and use up to 128 bytes of stack space, don't have a frame
00439   // pointer, calls, or dynamic alloca then we do not need to adjust the
00440   // stack pointer (we fit in the Red Zone). We also check that we don't
00441   // push and pop from the stack.
00442   if (Is64Bit && !Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
00443                                                    Attribute::NoRedZone) &&
00444       !RegInfo->needsStackRealignment(MF) &&
00445       !MFI->hasVarSizedObjects() &&                     // No dynamic alloca.
00446       !MFI->adjustsStack() &&                           // No calls.
00447       !IsWin64 &&                                       // Win64 has no Red Zone
00448       !usesTheStack(MF) &&                              // Don't push and pop.
00449       !MF.shouldSplitStack()) {                         // Regular stack
00450     uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
00451     if (HasFP) MinSize += SlotSize;
00452     StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
00453     MFI->setStackSize(StackSize);
00454   }
00455 
00456   // Insert stack pointer adjustment for later moving of return addr.  Only
00457   // applies to tail call optimized functions where the callee argument stack
00458   // size is bigger than the callers.
00459   if (TailCallReturnAddrDelta < 0) {
00460     MachineInstr *MI =
00461       BuildMI(MBB, MBBI, DL,
00462               TII.get(getSUBriOpcode(IsLP64, -TailCallReturnAddrDelta)),
00463               StackPtr)
00464         .addReg(StackPtr)
00465         .addImm(-TailCallReturnAddrDelta)
00466         .setMIFlag(MachineInstr::FrameSetup);
00467     MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
00468   }
00469 
00470   // Mapping for machine moves:
00471   //
00472   //   DST: VirtualFP AND
00473   //        SRC: VirtualFP              => DW_CFA_def_cfa_offset
00474   //        ELSE                        => DW_CFA_def_cfa
00475   //
00476   //   SRC: VirtualFP AND
00477   //        DST: Register               => DW_CFA_def_cfa_register
00478   //
00479   //   ELSE
00480   //        OFFSET < 0                  => DW_CFA_offset_extended_sf
00481   //        REG < 64                    => DW_CFA_offset + Reg
00482   //        ELSE                        => DW_CFA_offset_extended
00483 
00484   uint64_t NumBytes = 0;
00485   int stackGrowth = -SlotSize;
00486 
00487   if (HasFP) {
00488     // Calculate required stack adjustment.
00489     uint64_t FrameSize = StackSize - SlotSize;
00490     if (RegInfo->needsStackRealignment(MF)) {
00491       // Callee-saved registers are pushed on stack before the stack
00492       // is realigned.
00493       FrameSize -= X86FI->getCalleeSavedFrameSize();
00494       NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
00495     } else {
00496       NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
00497     }
00498 
00499     // Get the offset of the stack slot for the EBP register, which is
00500     // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
00501     // Update the frame offset adjustment.
00502     MFI->setOffsetAdjustment(-NumBytes);
00503 
00504     // Save EBP/RBP into the appropriate stack slot.
00505     BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
00506       .addReg(FramePtr, RegState::Kill)
00507       .setMIFlag(MachineInstr::FrameSetup);
00508 
00509     if (needsFrameMoves) {
00510       // Mark the place where EBP/RBP was saved.
00511       // Define the current CFA rule to use the provided offset.
00512       assert(StackSize);
00513       unsigned CFIIndex = MMI.addFrameInst(
00514           MCCFIInstruction::createDefCfaOffset(0, 2 * stackGrowth));
00515       BuildMI(MBB, MBBI, DL, TII.get(X86::CFI_INSTRUCTION))
00516           .addCFIIndex(CFIIndex);
00517 
00518       // Change the rule for the FramePtr to be an "offset" rule.
00519       unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(FramePtr, true);
00520       CFIIndex = MMI.addFrameInst(
00521           MCCFIInstruction::createOffset(0, DwarfFramePtr, 2 * stackGrowth));
00522       BuildMI(MBB, MBBI, DL, TII.get(X86::CFI_INSTRUCTION))
00523           .addCFIIndex(CFIIndex);
00524     }
00525 
00526     // Update EBP with the new base value.
00527     BuildMI(MBB, MBBI, DL,
00528             TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
00529         .addReg(StackPtr)
00530         .setMIFlag(MachineInstr::FrameSetup);
00531 
00532     if (needsFrameMoves) {
00533       // Mark effective beginning of when frame pointer becomes valid.
00534       // Define the current CFA to use the EBP/RBP register.
00535       unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(FramePtr, true);
00536       unsigned CFIIndex = MMI.addFrameInst(
00537           MCCFIInstruction::createDefCfaRegister(0, DwarfFramePtr));
00538       BuildMI(MBB, MBBI, DL, TII.get(X86::CFI_INSTRUCTION))
00539           .addCFIIndex(CFIIndex);
00540     }
00541 
00542     // Mark the FramePtr as live-in in every block except the entry.
00543     for (MachineFunction::iterator I = std::next(MF.begin()), E = MF.end();
00544          I != E; ++I)
00545       I->addLiveIn(FramePtr);
00546   } else {
00547     NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
00548   }
00549 
00550   // Skip the callee-saved push instructions.
00551   bool PushedRegs = false;
00552   int StackOffset = 2 * stackGrowth;
00553 
00554   while (MBBI != MBB.end() &&
00555          (MBBI->getOpcode() == X86::PUSH32r ||
00556           MBBI->getOpcode() == X86::PUSH64r)) {
00557     PushedRegs = true;
00558     MBBI->setFlag(MachineInstr::FrameSetup);
00559     ++MBBI;
00560 
00561     if (!HasFP && needsFrameMoves) {
00562       // Mark callee-saved push instruction.
00563       // Define the current CFA rule to use the provided offset.
00564       assert(StackSize);
00565       unsigned CFIIndex = MMI.addFrameInst(
00566           MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
00567       BuildMI(MBB, MBBI, DL, TII.get(X86::CFI_INSTRUCTION))
00568           .addCFIIndex(CFIIndex);
00569       StackOffset += stackGrowth;
00570     }
00571   }
00572 
00573   // Realign stack after we pushed callee-saved registers (so that we'll be
00574   // able to calculate their offsets from the frame pointer).
00575 
00576   // NOTE: We push the registers before realigning the stack, so
00577   // vector callee-saved (xmm) registers may be saved w/o proper
00578   // alignment in this way. However, currently these regs are saved in
00579   // stack slots (see X86FrameLowering::spillCalleeSavedRegisters()), so
00580   // this shouldn't be a problem.
00581   if (RegInfo->needsStackRealignment(MF)) {
00582     assert(HasFP && "There should be a frame pointer if stack is realigned.");
00583     MachineInstr *MI =
00584       BuildMI(MBB, MBBI, DL,
00585               TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr)
00586       .addReg(StackPtr)
00587       .addImm(-MaxAlign)
00588       .setMIFlag(MachineInstr::FrameSetup);
00589 
00590     // The EFLAGS implicit def is dead.
00591     MI->getOperand(3).setIsDead();
00592   }
00593 
00594   // If there is an SUB32ri of ESP immediately before this instruction, merge
00595   // the two. This can be the case when tail call elimination is enabled and
00596   // the callee has more arguments then the caller.
00597   NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
00598 
00599   // If there is an ADD32ri or SUB32ri of ESP immediately after this
00600   // instruction, merge the two instructions.
00601   mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
00602 
00603   // Adjust stack pointer: ESP -= numbytes.
00604 
00605   // Windows and cygwin/mingw require a prologue helper routine when allocating
00606   // more than 4K bytes on the stack.  Windows uses __chkstk and cygwin/mingw
00607   // uses __alloca.  __alloca and the 32-bit version of __chkstk will probe the
00608   // stack and adjust the stack pointer in one go.  The 64-bit version of
00609   // __chkstk is only responsible for probing the stack.  The 64-bit prologue is
00610   // responsible for adjusting the stack pointer.  Touching the stack at 4K
00611   // increments is necessary to ensure that the guard pages used by the OS
00612   // virtual memory manager are allocated in correct sequence.
00613   if (NumBytes >= 4096 && STI.isOSWindows() && !STI.isTargetMacho()) {
00614     const char *StackProbeSymbol;
00615 
00616     if (Is64Bit) {
00617       if (STI.isTargetCygMing()) {
00618         StackProbeSymbol = "___chkstk_ms";
00619       } else {
00620         StackProbeSymbol = "__chkstk";
00621       }
00622     } else if (STI.isTargetCygMing())
00623       StackProbeSymbol = "_alloca";
00624     else
00625       StackProbeSymbol = "_chkstk";
00626 
00627     // Check whether EAX is livein for this function.
00628     bool isEAXAlive = isEAXLiveIn(MF);
00629 
00630     if (isEAXAlive) {
00631       // Sanity check that EAX is not livein for this function.
00632       // It should not be, so throw an assert.
00633       assert(!Is64Bit && "EAX is livein in x64 case!");
00634 
00635       // Save EAX
00636       BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
00637         .addReg(X86::EAX, RegState::Kill)
00638         .setMIFlag(MachineInstr::FrameSetup);
00639     }
00640 
00641     if (Is64Bit) {
00642       // Handle the 64-bit Windows ABI case where we need to call __chkstk.
00643       // Function prologue is responsible for adjusting the stack pointer.
00644       BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
00645         .addImm(NumBytes)
00646         .setMIFlag(MachineInstr::FrameSetup);
00647     } else {
00648       // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
00649       // We'll also use 4 already allocated bytes for EAX.
00650       BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
00651         .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
00652         .setMIFlag(MachineInstr::FrameSetup);
00653     }
00654 
00655     BuildMI(MBB, MBBI, DL,
00656             TII.get(Is64Bit ? X86::W64ALLOCA : X86::CALLpcrel32))
00657       .addExternalSymbol(StackProbeSymbol)
00658       .addReg(StackPtr,    RegState::Define | RegState::Implicit)
00659       .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit)
00660       .setMIFlag(MachineInstr::FrameSetup);
00661 
00662     if (Is64Bit) {
00663       // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
00664       // themself. It also does not clobber %rax so we can reuse it when
00665       // adjusting %rsp.
00666       BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64rr), StackPtr)
00667         .addReg(StackPtr)
00668         .addReg(X86::RAX)
00669         .setMIFlag(MachineInstr::FrameSetup);
00670     }
00671     if (isEAXAlive) {
00672         // Restore EAX
00673         MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
00674                                                 X86::EAX),
00675                                         StackPtr, false, NumBytes - 4);
00676         MI->setFlag(MachineInstr::FrameSetup);
00677         MBB.insert(MBBI, MI);
00678     }
00679   } else if (NumBytes)
00680     emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, IsLP64,
00681                  UseLEA, TII, *RegInfo);
00682 
00683   // If we need a base pointer, set it up here. It's whatever the value
00684   // of the stack pointer is at this point. Any variable size objects
00685   // will be allocated after this, so we can still use the base pointer
00686   // to reference locals.
00687   if (RegInfo->hasBasePointer(MF)) {
00688     // Update the frame pointer with the current stack pointer.
00689     unsigned Opc = Is64Bit ? X86::MOV64rr : X86::MOV32rr;
00690     BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
00691       .addReg(StackPtr)
00692       .setMIFlag(MachineInstr::FrameSetup);
00693   }
00694 
00695   if (( (!HasFP && NumBytes) || PushedRegs) && needsFrameMoves) {
00696     // Mark end of stack pointer adjustment.
00697     if (!HasFP && NumBytes) {
00698       // Define the current CFA rule to use the provided offset.
00699       assert(StackSize);
00700       unsigned CFIIndex = MMI.addFrameInst(
00701           MCCFIInstruction::createDefCfaOffset(0, -StackSize + stackGrowth));
00702 
00703       BuildMI(MBB, MBBI, DL, TII.get(X86::CFI_INSTRUCTION))
00704           .addCFIIndex(CFIIndex);
00705     }
00706 
00707     // Emit DWARF info specifying the offsets of the callee-saved registers.
00708     if (PushedRegs)
00709       emitCalleeSavedFrameMoves(MBB, MBBI, DL, HasFP ? FramePtr : StackPtr);
00710   }
00711 }
00712 
00713 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
00714                                     MachineBasicBlock &MBB) const {
00715   const MachineFrameInfo *MFI = MF.getFrameInfo();
00716   X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
00717   const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
00718   const X86InstrInfo &TII = *TM.getInstrInfo();
00719   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
00720   assert(MBBI != MBB.end() && "Returning block has no instructions");
00721   unsigned RetOpcode = MBBI->getOpcode();
00722   DebugLoc DL = MBBI->getDebugLoc();
00723   bool Is64Bit = STI.is64Bit();
00724   bool IsLP64 = STI.isTarget64BitLP64();
00725   bool UseLEA = STI.useLeaForSP();
00726   unsigned StackAlign = getStackAlignment();
00727   unsigned SlotSize = RegInfo->getSlotSize();
00728   unsigned FramePtr = RegInfo->getFrameRegister(MF);
00729   unsigned StackPtr = RegInfo->getStackRegister();
00730 
00731   switch (RetOpcode) {
00732   default:
00733     llvm_unreachable("Can only insert epilog into returning blocks");
00734   case X86::RETQ:
00735   case X86::RETL:
00736   case X86::RETIL:
00737   case X86::RETIQ:
00738   case X86::TCRETURNdi:
00739   case X86::TCRETURNri:
00740   case X86::TCRETURNmi:
00741   case X86::TCRETURNdi64:
00742   case X86::TCRETURNri64:
00743   case X86::TCRETURNmi64:
00744   case X86::EH_RETURN:
00745   case X86::EH_RETURN64:
00746     break;  // These are ok
00747   }
00748 
00749   // Get the number of bytes to allocate from the FrameInfo.
00750   uint64_t StackSize = MFI->getStackSize();
00751   uint64_t MaxAlign  = MFI->getMaxAlignment();
00752   unsigned CSSize = X86FI->getCalleeSavedFrameSize();
00753   uint64_t NumBytes = 0;
00754 
00755   // If we're forcing a stack realignment we can't rely on just the frame
00756   // info, we need to know the ABI stack alignment as well in case we
00757   // have a call out.  Otherwise just make sure we have some alignment - we'll
00758   // go with the minimum.
00759   if (ForceStackAlign) {
00760     if (MFI->hasCalls())
00761       MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
00762     else
00763       MaxAlign = MaxAlign ? MaxAlign : 4;
00764   }
00765 
00766   if (hasFP(MF)) {
00767     // Calculate required stack adjustment.
00768     uint64_t FrameSize = StackSize - SlotSize;
00769     if (RegInfo->needsStackRealignment(MF)) {
00770       // Callee-saved registers were pushed on stack before the stack
00771       // was realigned.
00772       FrameSize -= CSSize;
00773       NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
00774     } else {
00775       NumBytes = FrameSize - CSSize;
00776     }
00777 
00778     // Pop EBP.
00779     BuildMI(MBB, MBBI, DL,
00780             TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
00781   } else {
00782     NumBytes = StackSize - CSSize;
00783   }
00784 
00785   // Skip the callee-saved pop instructions.
00786   while (MBBI != MBB.begin()) {
00787     MachineBasicBlock::iterator PI = std::prev(MBBI);
00788     unsigned Opc = PI->getOpcode();
00789 
00790     if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
00791         !PI->isTerminator())
00792       break;
00793 
00794     --MBBI;
00795   }
00796   MachineBasicBlock::iterator FirstCSPop = MBBI;
00797 
00798   DL = MBBI->getDebugLoc();
00799 
00800   // If there is an ADD32ri or SUB32ri of ESP immediately before this
00801   // instruction, merge the two instructions.
00802   if (NumBytes || MFI->hasVarSizedObjects())
00803     mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
00804 
00805   // If dynamic alloca is used, then reset esp to point to the last callee-saved
00806   // slot before popping them off! Same applies for the case, when stack was
00807   // realigned.
00808   if (RegInfo->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
00809     if (RegInfo->needsStackRealignment(MF))
00810       MBBI = FirstCSPop;
00811     if (CSSize != 0) {
00812       unsigned Opc = getLEArOpcode(IsLP64);
00813       addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
00814                    FramePtr, false, -CSSize);
00815     } else {
00816       unsigned Opc = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
00817       BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
00818         .addReg(FramePtr);
00819     }
00820   } else if (NumBytes) {
00821     // Adjust stack pointer back: ESP += numbytes.
00822     emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, IsLP64, UseLEA,
00823                  TII, *RegInfo);
00824   }
00825 
00826   // We're returning from function via eh_return.
00827   if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
00828     MBBI = MBB.getLastNonDebugInstr();
00829     MachineOperand &DestAddr  = MBBI->getOperand(0);
00830     assert(DestAddr.isReg() && "Offset should be in register!");
00831     BuildMI(MBB, MBBI, DL,
00832             TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
00833             StackPtr).addReg(DestAddr.getReg());
00834   } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
00835              RetOpcode == X86::TCRETURNmi ||
00836              RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
00837              RetOpcode == X86::TCRETURNmi64) {
00838     bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
00839     // Tail call return: adjust the stack pointer and jump to callee.
00840     MBBI = MBB.getLastNonDebugInstr();
00841     MachineOperand &JumpTarget = MBBI->getOperand(0);
00842     MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
00843     assert(StackAdjust.isImm() && "Expecting immediate value.");
00844 
00845     // Adjust stack pointer.
00846     int StackAdj = StackAdjust.getImm();
00847     int MaxTCDelta = X86FI->getTCReturnAddrDelta();
00848     int Offset = 0;
00849     assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
00850 
00851     // Incoporate the retaddr area.
00852     Offset = StackAdj-MaxTCDelta;
00853     assert(Offset >= 0 && "Offset should never be negative");
00854 
00855     if (Offset) {
00856       // Check for possible merge with preceding ADD instruction.
00857       Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
00858       emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, IsLP64,
00859                    UseLEA, TII, *RegInfo);
00860     }
00861 
00862     // Jump to label or value in register.
00863     if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
00864       MachineInstrBuilder MIB =
00865         BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
00866                                        ? X86::TAILJMPd : X86::TAILJMPd64));
00867       if (JumpTarget.isGlobal())
00868         MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
00869                              JumpTarget.getTargetFlags());
00870       else {
00871         assert(JumpTarget.isSymbol());
00872         MIB.addExternalSymbol(JumpTarget.getSymbolName(),
00873                               JumpTarget.getTargetFlags());
00874       }
00875     } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
00876       MachineInstrBuilder MIB =
00877         BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
00878                                        ? X86::TAILJMPm : X86::TAILJMPm64));
00879       for (unsigned i = 0; i != 5; ++i)
00880         MIB.addOperand(MBBI->getOperand(i));
00881     } else if (RetOpcode == X86::TCRETURNri64) {
00882       BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
00883         addReg(JumpTarget.getReg(), RegState::Kill);
00884     } else {
00885       BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
00886         addReg(JumpTarget.getReg(), RegState::Kill);
00887     }
00888 
00889     MachineInstr *NewMI = std::prev(MBBI);
00890     NewMI->copyImplicitOps(MF, MBBI);
00891 
00892     // Delete the pseudo instruction TCRETURN.
00893     MBB.erase(MBBI);
00894   } else if ((RetOpcode == X86::RETQ || RetOpcode == X86::RETL ||
00895               RetOpcode == X86::RETIQ || RetOpcode == X86::RETIL) &&
00896              (X86FI->getTCReturnAddrDelta() < 0)) {
00897     // Add the return addr area delta back since we are not tail calling.
00898     int delta = -1*X86FI->getTCReturnAddrDelta();
00899     MBBI = MBB.getLastNonDebugInstr();
00900 
00901     // Check for possible merge with preceding ADD instruction.
00902     delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
00903     emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, IsLP64, UseLEA, TII,
00904                  *RegInfo);
00905   }
00906 }
00907 
00908 int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
00909   const X86RegisterInfo *RegInfo =
00910     static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
00911   const MachineFrameInfo *MFI = MF.getFrameInfo();
00912   int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
00913   uint64_t StackSize = MFI->getStackSize();
00914 
00915   if (RegInfo->hasBasePointer(MF)) {
00916     assert (hasFP(MF) && "VLAs and dynamic stack realign, but no FP?!");
00917     if (FI < 0) {
00918       // Skip the saved EBP.
00919       return Offset + RegInfo->getSlotSize();
00920     } else {
00921       assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
00922       return Offset + StackSize;
00923     }
00924   } else if (RegInfo->needsStackRealignment(MF)) {
00925     if (FI < 0) {
00926       // Skip the saved EBP.
00927       return Offset + RegInfo->getSlotSize();
00928     } else {
00929       assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
00930       return Offset + StackSize;
00931     }
00932     // FIXME: Support tail calls
00933   } else {
00934     if (!hasFP(MF))
00935       return Offset + StackSize;
00936 
00937     // Skip the saved EBP.
00938     Offset += RegInfo->getSlotSize();
00939 
00940     // Skip the RETADDR move area
00941     const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
00942     int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
00943     if (TailCallReturnAddrDelta < 0)
00944       Offset -= TailCallReturnAddrDelta;
00945   }
00946 
00947   return Offset;
00948 }
00949 
00950 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
00951                                              unsigned &FrameReg) const {
00952   const X86RegisterInfo *RegInfo =
00953       static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
00954   // We can't calculate offset from frame pointer if the stack is realigned,
00955   // so enforce usage of stack/base pointer.  The base pointer is used when we
00956   // have dynamic allocas in addition to dynamic realignment.
00957   if (RegInfo->hasBasePointer(MF))
00958     FrameReg = RegInfo->getBaseRegister();
00959   else if (RegInfo->needsStackRealignment(MF))
00960     FrameReg = RegInfo->getStackRegister();
00961   else
00962     FrameReg = RegInfo->getFrameRegister(MF);
00963   return getFrameIndexOffset(MF, FI);
00964 }
00965 
00966 bool X86FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
00967                                              MachineBasicBlock::iterator MI,
00968                                         const std::vector<CalleeSavedInfo> &CSI,
00969                                           const TargetRegisterInfo *TRI) const {
00970   if (CSI.empty())
00971     return false;
00972 
00973   DebugLoc DL = MBB.findDebugLoc(MI);
00974 
00975   MachineFunction &MF = *MBB.getParent();
00976 
00977   unsigned SlotSize = STI.is64Bit() ? 8 : 4;
00978   unsigned FPReg = TRI->getFrameRegister(MF);
00979   unsigned CalleeFrameSize = 0;
00980 
00981   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
00982   X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
00983 
00984   // Push GPRs. It increases frame size.
00985   unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
00986   for (unsigned i = CSI.size(); i != 0; --i) {
00987     unsigned Reg = CSI[i-1].getReg();
00988     if (!X86::GR64RegClass.contains(Reg) &&
00989         !X86::GR32RegClass.contains(Reg))
00990       continue;
00991     // Add the callee-saved register as live-in. It's killed at the spill.
00992     MBB.addLiveIn(Reg);
00993     if (Reg == FPReg)
00994       // X86RegisterInfo::emitPrologue will handle spilling of frame register.
00995       continue;
00996     CalleeFrameSize += SlotSize;
00997     BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
00998       .setMIFlag(MachineInstr::FrameSetup);
00999   }
01000 
01001   X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
01002 
01003   // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
01004   // It can be done by spilling XMMs to stack frame.
01005   // Note that only Win64 ABI might spill XMMs.
01006   for (unsigned i = CSI.size(); i != 0; --i) {
01007     unsigned Reg = CSI[i-1].getReg();
01008     if (X86::GR64RegClass.contains(Reg) ||
01009         X86::GR32RegClass.contains(Reg))
01010       continue;
01011     // Add the callee-saved register as live-in. It's killed at the spill.
01012     MBB.addLiveIn(Reg);
01013     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
01014     TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(),
01015                             RC, TRI);
01016   }
01017 
01018   return true;
01019 }
01020 
01021 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
01022                                                MachineBasicBlock::iterator MI,
01023                                         const std::vector<CalleeSavedInfo> &CSI,
01024                                           const TargetRegisterInfo *TRI) const {
01025   if (CSI.empty())
01026     return false;
01027 
01028   DebugLoc DL = MBB.findDebugLoc(MI);
01029 
01030   MachineFunction &MF = *MBB.getParent();
01031   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
01032 
01033   // Reload XMMs from stack frame.
01034   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
01035     unsigned Reg = CSI[i].getReg();
01036     if (X86::GR64RegClass.contains(Reg) ||
01037         X86::GR32RegClass.contains(Reg))
01038       continue;
01039     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
01040     TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
01041                              RC, TRI);
01042   }
01043 
01044   // POP GPRs.
01045   unsigned FPReg = TRI->getFrameRegister(MF);
01046   unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
01047   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
01048     unsigned Reg = CSI[i].getReg();
01049     if (!X86::GR64RegClass.contains(Reg) &&
01050         !X86::GR32RegClass.contains(Reg))
01051       continue;
01052     if (Reg == FPReg)
01053       // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
01054       continue;
01055     BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
01056   }
01057   return true;
01058 }
01059 
01060 void
01061 X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
01062                                                    RegScavenger *RS) const {
01063   MachineFrameInfo *MFI = MF.getFrameInfo();
01064   const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
01065   unsigned SlotSize = RegInfo->getSlotSize();
01066 
01067   X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
01068   int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
01069 
01070   if (TailCallReturnAddrDelta < 0) {
01071     // create RETURNADDR area
01072     //   arg
01073     //   arg
01074     //   RETADDR
01075     //   { ...
01076     //     RETADDR area
01077     //     ...
01078     //   }
01079     //   [EBP]
01080     MFI->CreateFixedObject(-TailCallReturnAddrDelta,
01081                            TailCallReturnAddrDelta - SlotSize, true);
01082   }
01083 
01084   if (hasFP(MF)) {
01085     assert((TailCallReturnAddrDelta <= 0) &&
01086            "The Delta should always be zero or negative");
01087     const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
01088 
01089     // Create a frame entry for the EBP register that must be saved.
01090     int FrameIdx = MFI->CreateFixedObject(SlotSize,
01091                                           -(int)SlotSize +
01092                                           TFI.getOffsetOfLocalArea() +
01093                                           TailCallReturnAddrDelta,
01094                                           true);
01095     assert(FrameIdx == MFI->getObjectIndexBegin() &&
01096            "Slot for EBP register must be last in order to be found!");
01097     (void)FrameIdx;
01098   }
01099 
01100   // Spill the BasePtr if it's used.
01101   if (RegInfo->hasBasePointer(MF))
01102     MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());
01103 }
01104 
01105 static bool
01106 HasNestArgument(const MachineFunction *MF) {
01107   const Function *F = MF->getFunction();
01108   for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
01109        I != E; I++) {
01110     if (I->hasNestAttr())
01111       return true;
01112   }
01113   return false;
01114 }
01115 
01116 /// GetScratchRegister - Get a temp register for performing work in the
01117 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
01118 /// and the properties of the function either one or two registers will be
01119 /// needed. Set primary to true for the first register, false for the second.
01120 static unsigned
01121 GetScratchRegister(bool Is64Bit, const MachineFunction &MF, bool Primary) {
01122   CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
01123 
01124   // Erlang stuff.
01125   if (CallingConvention == CallingConv::HiPE) {
01126     if (Is64Bit)
01127       return Primary ? X86::R14 : X86::R13;
01128     else
01129       return Primary ? X86::EBX : X86::EDI;
01130   }
01131 
01132   if (Is64Bit)
01133     return Primary ? X86::R11 : X86::R12;
01134 
01135   bool IsNested = HasNestArgument(&MF);
01136 
01137   if (CallingConvention == CallingConv::X86_FastCall ||
01138       CallingConvention == CallingConv::Fast) {
01139     if (IsNested)
01140       report_fatal_error("Segmented stacks does not support fastcall with "
01141                          "nested function.");
01142     return Primary ? X86::EAX : X86::ECX;
01143   }
01144   if (IsNested)
01145     return Primary ? X86::EDX : X86::EAX;
01146   return Primary ? X86::ECX : X86::EAX;
01147 }
01148 
01149 // The stack limit in the TCB is set to this many bytes above the actual stack
01150 // limit.
01151 static const uint64_t kSplitStackAvailable = 256;
01152 
01153 void
01154 X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
01155   MachineBasicBlock &prologueMBB = MF.front();
01156   MachineFrameInfo *MFI = MF.getFrameInfo();
01157   const X86InstrInfo &TII = *TM.getInstrInfo();
01158   uint64_t StackSize;
01159   bool Is64Bit = STI.is64Bit();
01160   unsigned TlsReg, TlsOffset;
01161   DebugLoc DL;
01162 
01163   unsigned ScratchReg = GetScratchRegister(Is64Bit, MF, true);
01164   assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
01165          "Scratch register is live-in");
01166 
01167   if (MF.getFunction()->isVarArg())
01168     report_fatal_error("Segmented stacks do not support vararg functions.");
01169   if (!STI.isTargetLinux() && !STI.isTargetDarwin() &&
01170       !STI.isTargetWin32() && !STI.isTargetWin64() && !STI.isTargetFreeBSD())
01171     report_fatal_error("Segmented stacks not supported on this platform.");
01172 
01173   MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
01174   MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
01175   X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
01176   bool IsNested = false;
01177 
01178   // We need to know if the function has a nest argument only in 64 bit mode.
01179   if (Is64Bit)
01180     IsNested = HasNestArgument(&MF);
01181 
01182   // The MOV R10, RAX needs to be in a different block, since the RET we emit in
01183   // allocMBB needs to be last (terminating) instruction.
01184 
01185   for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
01186          e = prologueMBB.livein_end(); i != e; i++) {
01187     allocMBB->addLiveIn(*i);
01188     checkMBB->addLiveIn(*i);
01189   }
01190 
01191   if (IsNested)
01192     allocMBB->addLiveIn(X86::R10);
01193 
01194   MF.push_front(allocMBB);
01195   MF.push_front(checkMBB);
01196 
01197   // Eventually StackSize will be calculated by a link-time pass; which will
01198   // also decide whether checking code needs to be injected into this particular
01199   // prologue.
01200   StackSize = MFI->getStackSize();
01201 
01202   // When the frame size is less than 256 we just compare the stack
01203   // boundary directly to the value of the stack pointer, per gcc.
01204   bool CompareStackPointer = StackSize < kSplitStackAvailable;
01205 
01206   // Read the limit off the current stacklet off the stack_guard location.
01207   if (Is64Bit) {
01208     if (STI.isTargetLinux()) {
01209       TlsReg = X86::FS;
01210       TlsOffset = 0x70;
01211     } else if (STI.isTargetDarwin()) {
01212       TlsReg = X86::GS;
01213       TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
01214     } else if (STI.isTargetWin64()) {
01215       TlsReg = X86::GS;
01216       TlsOffset = 0x28; // pvArbitrary, reserved for application use
01217     } else if (STI.isTargetFreeBSD()) {
01218       TlsReg = X86::FS;
01219       TlsOffset = 0x18;
01220     } else {
01221       report_fatal_error("Segmented stacks not supported on this platform.");
01222     }
01223 
01224     if (CompareStackPointer)
01225       ScratchReg = X86::RSP;
01226     else
01227       BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP)
01228         .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
01229 
01230     BuildMI(checkMBB, DL, TII.get(X86::CMP64rm)).addReg(ScratchReg)
01231       .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
01232   } else {
01233     if (STI.isTargetLinux()) {
01234       TlsReg = X86::GS;
01235       TlsOffset = 0x30;
01236     } else if (STI.isTargetDarwin()) {
01237       TlsReg = X86::GS;
01238       TlsOffset = 0x48 + 90*4;
01239     } else if (STI.isTargetWin32()) {
01240       TlsReg = X86::FS;
01241       TlsOffset = 0x14; // pvArbitrary, reserved for application use
01242     } else if (STI.isTargetFreeBSD()) {
01243       report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
01244     } else {
01245       report_fatal_error("Segmented stacks not supported on this platform.");
01246     }
01247 
01248     if (CompareStackPointer)
01249       ScratchReg = X86::ESP;
01250     else
01251       BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
01252         .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
01253 
01254     if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64()) {
01255       BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
01256         .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
01257     } else if (STI.isTargetDarwin()) {
01258 
01259       // TlsOffset doesn't fit into a mod r/m byte so we need an extra register
01260       unsigned ScratchReg2;
01261       bool SaveScratch2;
01262       if (CompareStackPointer) {
01263         // The primary scratch register is available for holding the TLS offset
01264         ScratchReg2 = GetScratchRegister(Is64Bit, MF, true);
01265         SaveScratch2 = false;
01266       } else {
01267         // Need to use a second register to hold the TLS offset
01268         ScratchReg2 = GetScratchRegister(Is64Bit, MF, false);
01269 
01270         // Unfortunately, with fastcc the second scratch register may hold an arg
01271         SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
01272       }
01273 
01274       // If Scratch2 is live-in then it needs to be saved
01275       assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
01276              "Scratch register is live-in and not saved");
01277 
01278       if (SaveScratch2)
01279         BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
01280           .addReg(ScratchReg2, RegState::Kill);
01281 
01282       BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
01283         .addImm(TlsOffset);
01284       BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
01285         .addReg(ScratchReg)
01286         .addReg(ScratchReg2).addImm(1).addReg(0)
01287         .addImm(0)
01288         .addReg(TlsReg);
01289 
01290       if (SaveScratch2)
01291         BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
01292     }
01293   }
01294 
01295   // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
01296   // It jumps to normal execution of the function body.
01297   BuildMI(checkMBB, DL, TII.get(X86::JA_4)).addMBB(&prologueMBB);
01298 
01299   // On 32 bit we first push the arguments size and then the frame size. On 64
01300   // bit, we pass the stack frame size in r10 and the argument size in r11.
01301   if (Is64Bit) {
01302     // Functions with nested arguments use R10, so it needs to be saved across
01303     // the call to _morestack
01304 
01305     if (IsNested)
01306       BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10);
01307 
01308     BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10)
01309       .addImm(StackSize);
01310     BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11)
01311       .addImm(X86FI->getArgumentStackSize());
01312     MF.getRegInfo().setPhysRegUsed(X86::R10);
01313     MF.getRegInfo().setPhysRegUsed(X86::R11);
01314   } else {
01315     BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
01316       .addImm(X86FI->getArgumentStackSize());
01317     BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
01318       .addImm(StackSize);
01319   }
01320 
01321   // __morestack is in libgcc
01322   if (Is64Bit)
01323     BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
01324       .addExternalSymbol("__morestack");
01325   else
01326     BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
01327       .addExternalSymbol("__morestack");
01328 
01329   if (IsNested)
01330     BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
01331   else
01332     BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
01333 
01334   allocMBB->addSuccessor(&prologueMBB);
01335 
01336   checkMBB->addSuccessor(allocMBB);
01337   checkMBB->addSuccessor(&prologueMBB);
01338 
01339 #ifdef XDEBUG
01340   MF.verify();
01341 #endif
01342 }
01343 
01344 /// Erlang programs may need a special prologue to handle the stack size they
01345 /// might need at runtime. That is because Erlang/OTP does not implement a C
01346 /// stack but uses a custom implementation of hybrid stack/heap architecture.
01347 /// (for more information see Eric Stenman's Ph.D. thesis:
01348 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
01349 ///
01350 /// CheckStack:
01351 ///   temp0 = sp - MaxStack
01352 ///   if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
01353 /// OldStart:
01354 ///   ...
01355 /// IncStack:
01356 ///   call inc_stack   # doubles the stack space
01357 ///   temp0 = sp - MaxStack
01358 ///   if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
01359 void X86FrameLowering::adjustForHiPEPrologue(MachineFunction &MF) const {
01360   const X86InstrInfo &TII = *TM.getInstrInfo();
01361   MachineFrameInfo *MFI = MF.getFrameInfo();
01362   const unsigned SlotSize = TM.getRegisterInfo()->getSlotSize();
01363   const bool Is64Bit = STI.is64Bit();
01364   DebugLoc DL;
01365   // HiPE-specific values
01366   const unsigned HipeLeafWords = 24;
01367   const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
01368   const unsigned Guaranteed = HipeLeafWords * SlotSize;
01369   unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ?
01370                             MF.getFunction()->arg_size() - CCRegisteredArgs : 0;
01371   unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize;
01372 
01373   assert(STI.isTargetLinux() &&
01374          "HiPE prologue is only supported on Linux operating systems.");
01375 
01376   // Compute the largest caller's frame that is needed to fit the callees'
01377   // frames. This 'MaxStack' is computed from:
01378   //
01379   // a) the fixed frame size, which is the space needed for all spilled temps,
01380   // b) outgoing on-stack parameter areas, and
01381   // c) the minimum stack space this function needs to make available for the
01382   //    functions it calls (a tunable ABI property).
01383   if (MFI->hasCalls()) {
01384     unsigned MoreStackForCalls = 0;
01385 
01386     for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end();
01387          MBBI != MBBE; ++MBBI)
01388       for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end();
01389            MI != ME; ++MI) {
01390         if (!MI->isCall())
01391           continue;
01392 
01393         // Get callee operand.
01394         const MachineOperand &MO = MI->getOperand(0);
01395 
01396         // Only take account of global function calls (no closures etc.).
01397         if (!MO.isGlobal())
01398           continue;
01399 
01400         const Function *F = dyn_cast<Function>(MO.getGlobal());
01401         if (!F)
01402           continue;
01403 
01404         // Do not update 'MaxStack' for primitive and built-in functions
01405         // (encoded with names either starting with "erlang."/"bif_" or not
01406         // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
01407         // "_", such as the BIF "suspend_0") as they are executed on another
01408         // stack.
01409         if (F->getName().find("erlang.") != StringRef::npos ||
01410             F->getName().find("bif_") != StringRef::npos ||
01411             F->getName().find_first_of("._") == StringRef::npos)
01412           continue;
01413 
01414         unsigned CalleeStkArity =
01415           F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
01416         if (HipeLeafWords - 1 > CalleeStkArity)
01417           MoreStackForCalls = std::max(MoreStackForCalls,
01418                                (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
01419       }
01420     MaxStack += MoreStackForCalls;
01421   }
01422 
01423   // If the stack frame needed is larger than the guaranteed then runtime checks
01424   // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
01425   if (MaxStack > Guaranteed) {
01426     MachineBasicBlock &prologueMBB = MF.front();
01427     MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
01428     MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
01429 
01430     for (MachineBasicBlock::livein_iterator I = prologueMBB.livein_begin(),
01431            E = prologueMBB.livein_end(); I != E; I++) {
01432       stackCheckMBB->addLiveIn(*I);
01433       incStackMBB->addLiveIn(*I);
01434     }
01435 
01436     MF.push_front(incStackMBB);
01437     MF.push_front(stackCheckMBB);
01438 
01439     unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
01440     unsigned LEAop, CMPop, CALLop;
01441     if (Is64Bit) {
01442       SPReg = X86::RSP;
01443       PReg  = X86::RBP;
01444       LEAop = X86::LEA64r;
01445       CMPop = X86::CMP64rm;
01446       CALLop = X86::CALL64pcrel32;
01447       SPLimitOffset = 0x90;
01448     } else {
01449       SPReg = X86::ESP;
01450       PReg  = X86::EBP;
01451       LEAop = X86::LEA32r;
01452       CMPop = X86::CMP32rm;
01453       CALLop = X86::CALLpcrel32;
01454       SPLimitOffset = 0x4c;
01455     }
01456 
01457     ScratchReg = GetScratchRegister(Is64Bit, MF, true);
01458     assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
01459            "HiPE prologue scratch register is live-in");
01460 
01461     // Create new MBB for StackCheck:
01462     addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
01463                  SPReg, false, -MaxStack);
01464     // SPLimitOffset is in a fixed heap location (pointed by BP).
01465     addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
01466                  .addReg(ScratchReg), PReg, false, SPLimitOffset);
01467     BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_4)).addMBB(&prologueMBB);
01468 
01469     // Create new MBB for IncStack:
01470     BuildMI(incStackMBB, DL, TII.get(CALLop)).
01471       addExternalSymbol("inc_stack_0");
01472     addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
01473                  SPReg, false, -MaxStack);
01474     addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
01475                  .addReg(ScratchReg), PReg, false, SPLimitOffset);
01476     BuildMI(incStackMBB, DL, TII.get(X86::JLE_4)).addMBB(incStackMBB);
01477 
01478     stackCheckMBB->addSuccessor(&prologueMBB, 99);
01479     stackCheckMBB->addSuccessor(incStackMBB, 1);
01480     incStackMBB->addSuccessor(&prologueMBB, 99);
01481     incStackMBB->addSuccessor(incStackMBB, 1);
01482   }
01483 #ifdef XDEBUG
01484   MF.verify();
01485 #endif
01486 }
01487 
01488 void X86FrameLowering::
01489 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
01490                               MachineBasicBlock::iterator I) const {
01491   const X86InstrInfo &TII = *TM.getInstrInfo();
01492   const X86RegisterInfo &RegInfo = *TM.getRegisterInfo();
01493   unsigned StackPtr = RegInfo.getStackRegister();
01494   bool reseveCallFrame = hasReservedCallFrame(MF);
01495   int Opcode = I->getOpcode();
01496   bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
01497   bool IsLP64 = STI.isTarget64BitLP64();
01498   DebugLoc DL = I->getDebugLoc();
01499   uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
01500   uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
01501   I = MBB.erase(I);
01502 
01503   if (!reseveCallFrame) {
01504     // If the stack pointer can be changed after prologue, turn the
01505     // adjcallstackup instruction into a 'sub ESP, <amt>' and the
01506     // adjcallstackdown instruction into 'add ESP, <amt>'
01507     // TODO: consider using push / pop instead of sub + store / add
01508     if (Amount == 0)
01509       return;
01510 
01511     // We need to keep the stack aligned properly.  To do this, we round the
01512     // amount of space needed for the outgoing arguments up to the next
01513     // alignment boundary.
01514     unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
01515     Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
01516 
01517     MachineInstr *New = 0;
01518     if (Opcode == TII.getCallFrameSetupOpcode()) {
01519       New = BuildMI(MF, DL, TII.get(getSUBriOpcode(IsLP64, Amount)),
01520                     StackPtr)
01521         .addReg(StackPtr)
01522         .addImm(Amount);
01523     } else {
01524       assert(Opcode == TII.getCallFrameDestroyOpcode());
01525 
01526       // Factor out the amount the callee already popped.
01527       Amount -= CalleeAmt;
01528 
01529       if (Amount) {
01530         unsigned Opc = getADDriOpcode(IsLP64, Amount);
01531         New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
01532           .addReg(StackPtr).addImm(Amount);
01533       }
01534     }
01535 
01536     if (New) {
01537       // The EFLAGS implicit def is dead.
01538       New->getOperand(3).setIsDead();
01539 
01540       // Replace the pseudo instruction with a new instruction.
01541       MBB.insert(I, New);
01542     }
01543 
01544     return;
01545   }
01546 
01547   if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
01548     // If we are performing frame pointer elimination and if the callee pops
01549     // something off the stack pointer, add it back.  We do this until we have
01550     // more advanced stack pointer tracking ability.
01551     unsigned Opc = getSUBriOpcode(IsLP64, CalleeAmt);
01552     MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
01553       .addReg(StackPtr).addImm(CalleeAmt);
01554 
01555     // The EFLAGS implicit def is dead.
01556     New->getOperand(3).setIsDead();
01557 
01558     // We are not tracking the stack pointer adjustment by the callee, so make
01559     // sure we restore the stack pointer immediately after the call, there may
01560     // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
01561     MachineBasicBlock::iterator B = MBB.begin();
01562     while (I != B && !std::prev(I)->isCall())
01563       --I;
01564     MBB.insert(I, New);
01565   }
01566 }
01567