#include <X86ISelLowering.h>
Detailed Description
Definition at line 475 of file X86ISelLowering.h.
Constructor & Destructor Documentation
| X86TargetLowering::X86TargetLowering | ( | X86TargetMachine & | TM | ) | [explicit] |
Definition at line 161 of file X86ISelLowering.cpp.
References llvm::TargetLoweringBase::getDataLayout(), llvm::X86TargetMachine::getRegisterInfo(), llvm::TargetMachine::getSubtarget(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), and resetOperationActions().
Member Function Documentation
allowsUnalignedMemoryAccesses - Returns true if the target allows unaligned memory accesses. of the specified type. Returns whether it is "fast" by reference in the second argument.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1470 of file X86ISelLowering.cpp.
References llvm::X86Subtarget::isUnalignedMemAccessFast().
| SDValue X86TargetLowering::BuildFILD | ( | SDValue | Op, |
| EVT | SrcVT, | ||
| SDValue | Chain, | ||
| SDValue | StackSlot, | ||
| SelectionDAG & | DAG | ||
| ) | const |
Definition at line 8010 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::lltok::APFloat, llvm::array_lengthof(), llvm::ISD::BITCAST, llvm::EVT::bitsGT(), llvm::EVT::bitsLT(), llvm::BitsToDouble(), llvm::ISD::BUILD_PAIR, llvm::MachineFrameInfo::CreateStackObject(), llvm::SelectionDAG::CreateStackTemporary(), llvm::dyn_cast(), llvm::N86::EAX, llvm::N86::EDX, llvm::ISD::EXTLOAD, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::f80, llvm::ISD::FADD, llvm::X86ISD::FHADD, llvm::X86ISD::FILD, llvm::X86ISD::FILD_FLAG, llvm::X86ISD::FLD, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::X86ISD::FP_TO_INT16_IN_MEM, llvm::X86ISD::FP_TO_INT32_IN_MEM, llvm::X86ISD::FP_TO_INT64_IN_MEM, llvm::X86ISD::FST, llvm::ISD::FSUB, llvm::ConstantInt::get(), llvm::ConstantFP::get(), llvm::ConstantVector::get(), llvm::ConstantDataVector::get(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getConstantFP(), llvm::MachinePointerInfo::getConstantPool(), llvm::SelectionDAG::getConstantPool(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyFromReg(), llvm::SDValue::getDebugLoc(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getExtLoad(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::FrameIndexSDNode::getIndex(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getSetCC(), getSetCCResultType(), getShuffleVectorZeroOrUndef(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getStore(), getTargetShuffleNode(), getUnpackl(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::MVT::Glue, llvm::X86Subtarget::hasSSE3(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::APFloat::IEEEdouble, llvm::X86Subtarget::is64Bit(), isIntegerTypeFTOL(), isScalarFPTypeInSSEReg(), llvm::EVT::isVector(), llvm_unreachable, llvm::SPII::Load, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, llvm::ISD::OR, llvm::APIntOps::Or(), llvm::MVT::Other, llvm::X86ISD::PSHUFD, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SELECT, llvm::ISD::SETLT, llvm::SelectionDAG::SignBitIsZero(), llvm::MVT::SimpleTy, llvm::ISD::SINT_TO_FP, llvm::SPII::Store, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v4i8, llvm::MVT::v8i16, llvm::MVT::v8i8, llvm::X86ISD::WIN_FTOL, llvm::ISD::ZERO_EXTEND, and llvm::APInt::zext().
Referenced by PerformSINT_TO_FPCombine().
| void X86TargetLowering::computeMaskedBitsForTargetNode | ( | const SDValue | Op, |
| APInt & | KnownZero, | ||
| APInt & | KnownOne, | ||
| const SelectionDAG & | DAG, | ||
| unsigned | Depth = 0 |
||
| ) | const [virtual] |
computeMaskedBitsForTargetNode - Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.
Reimplemented from llvm::TargetLowering.
Definition at line 14932 of file X86ISelLowering.cpp.
References llvm::X86ISD::ADC, llvm::X86ISD::ADD, llvm::X86ISD::AND, llvm::ISD::BUILTIN_OP_END, llvm::X86ISD::DEC, llvm::APInt::getBitWidth(), llvm::APInt::getHighBitsSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), llvm::X86ISD::INC, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm_unreachable, llvm::X86ISD::OR, llvm::X86ISD::SBB, llvm::X86ISD::SETCC, llvm::X86ISD::SMUL, llvm::X86ISD::SUB, llvm::X86ISD::UMUL, and llvm::X86ISD::XOR.
| unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode | ( | SDValue | Op, |
| unsigned | Depth | ||
| ) | const [virtual] |
ComputeNumSignBitsForTargetNode - This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner.
Reimplemented from llvm::TargetLowering.
Definition at line 14999 of file X86ISelLowering.cpp.
References llvm::SDValue::getOpcode(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), and llvm::X86ISD::SETCC_CARRY.
| FastISel * X86TargetLowering::createFastISel | ( | FunctionLoweringInfo & | funcInfo, |
| const TargetLibraryInfo * | libInfo | ||
| ) | const [virtual] |
createFastISel - This method returns a target specific FastISel object, or null if the target does not support "fast" ISel.
Reimplemented from llvm::TargetLowering.
Definition at line 3021 of file X86ISelLowering.cpp.
| MachineBasicBlock * X86TargetLowering::EmitInstrWithCustomInserter | ( | MachineInstr * | MI, |
| MachineBasicBlock * | MBB | ||
| ) | const [virtual] |
Reimplemented from llvm::TargetLowering.
Definition at line 14702 of file X86ISelLowering.cpp.
References llvm::addFrameReference(), llvm::addFullAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::X86AddressMode::Base, llvm::X86AddressMode::BaseType, llvm::BuildMI(), llvm::MachineFrameInfo::CreateStackObject(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::X86AddressMode::Disp, EmitMonitor(), EmitPCMPSTRI(), EmitPCMPSTRM(), EmitXBegin(), llvm::MachineInstr::eraseFromParent(), llvm::X86ISD::FNSTCW16m, llvm::X86AddressMode::FrameIndex, llvm::X86AddressMode::FrameIndexBase, llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineFunction::getFrameInfo(), llvm::MachineOperand::getGlobal(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::TargetMachine::getInstrInfo(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::TargetLoweringBase::getTargetMachine(), llvm::X86AddressMode::GV, llvm::X86Subtarget::hasSSE42(), llvm::X86AddressMode::IndexReg, llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm_unreachable, llvm::X86AddressMode::Reg, llvm::X86AddressMode::RegBase, llvm::X86AddressMode::Scale, llvm::X86ISD::VAARG_64, llvm::X86ISD::VASTART_SAVE_XMM_REGS, and llvm::X86ISD::WIN_ALLOCA.
ExpandInlineAsm - This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to. This is useful for turning simple inline asms into LLVM intrinsics, which gives the compiler more information about the behavior of the code.
Reimplemented from llvm::TargetLowering.
Definition at line 18016 of file X86ISelLowering.cpp.
References llvm::array_pod_sort(), llvm::SmallVectorTemplateCommon< T >::begin(), llvm::SmallVectorImpl< T >::clear(), llvm::dyn_cast(), llvm::SmallVectorTemplateCommon< T >::end(), llvm::InlineAsm::getAsmString(), llvm::IntegerType::getBitWidth(), llvm::CallInst::getCalledValue(), llvm::InlineAsm::getConstraintString(), llvm::Value::getType(), llvm::Type::isIntegerTy(), llvm::IntrinsicLowering::LowerToByteSwap(), llvm::InlineAsm::ParseConstraints(), llvm::SmallVectorTemplateCommon< T >::size(), and llvm::SplitString().
| std::pair< const TargetRegisterClass *, uint8_t > X86TargetLowering::findRepresentativeClass | ( | MVT | VT | ) | const [protected, virtual] |
findRepresentativeClass - Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1529 of file X86ISelLowering.cpp.
References llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::X86Subtarget::is64Bit(), llvm::MSP430ISD::RRC, llvm::MVT::SimpleTy, llvm::MVT::v16i8, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v32i8, llvm::MVT::v4f32, llvm::MVT::v4f64, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v8f32, llvm::MVT::v8i16, llvm::MVT::v8i32, and llvm::MVT::x86mmx.
getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the caller parameter area. For X86, aggregates that contains are placed at 16-byte boundaries while the rest are at 4-byte boundaries.
getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the caller parameter area. For X86, aggregates that contain SSE vectors are placed at 16-byte boundaries while the rest are at 4-byte boundaries.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1398 of file X86ISelLowering.cpp.
References Align(), llvm::DataLayout::getABITypeAlignment(), getMaxByValAlign(), llvm::X86Subtarget::hasSSE1(), and llvm::X86Subtarget::is64Bit().
| X86TargetLowering::ConstraintType X86TargetLowering::getConstraintType | ( | const std::string & | Constraint | ) | const [virtual] |
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Reimplemented from llvm::TargetLowering.
Definition at line 18103 of file X86ISelLowering.cpp.
References llvm::TargetLowering::C_Other, llvm::TargetLowering::C_Register, and llvm::TargetLowering::C_RegisterClass.
| unsigned X86TargetLowering::getJumpTableEncoding | ( | ) | const [virtual] |
getJumpTableEncoding - Return the entry encoding for a jump table in the current function. The returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
Reimplemented from llvm::TargetLowering.
Definition at line 1479 of file X86ISelLowering.cpp.
References llvm::MachineJumpTableInfo::EK_Custom32, llvm::TargetLoweringBase::getTargetMachine(), llvm::X86Subtarget::isPICStyleGOT(), and llvm::Reloc::PIC_.
| EVT X86TargetLowering::getOptimalMemOpType | ( | uint64_t | Size, |
| unsigned | DstAlign, | ||
| unsigned | SrcAlign, | ||
| bool | IsMemset, | ||
| bool | ZeroMemset, | ||
| bool | MemcpyStrSrc, | ||
| MachineFunction & | MF | ||
| ) | const [virtual] |
getOptimalMemOpType - Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering. If DstAlign is zero that means it's safe to destination alignment can satisfy any constraint. Similarly if SrcAlign is zero it means there isn't a need to check it against alignment requirement, probably because the source does not need to be loaded. If 'IsMemset' is true, that means it's expanding a memset. If 'ZeroMemset' is true, that means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it does not need to be loaded. It returns EVT::Other if the type should be determined using generic target-independent logic.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1425 of file X86ISelLowering.cpp.
References F(), llvm::MVT::f64, llvm::AttributeSet::FunctionIndex, llvm::Function::getAttributes(), llvm::MachineFunction::getFunction(), llvm::AttributeSet::hasAttribute(), llvm::X86Subtarget::hasFp256(), llvm::X86Subtarget::hasInt256(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::MVT::i32, llvm::MVT::i64, llvm::X86Subtarget::is64Bit(), llvm::X86Subtarget::isUnalignedMemAccessFast(), llvm::Attribute::NoImplicitFloat, llvm::MVT::v4f32, llvm::MVT::v4i32, llvm::MVT::v8f32, and llvm::MVT::v8i32.
| SDValue X86TargetLowering::getPICJumpTableRelocBase | ( | SDValue | Table, |
| SelectionDAG & | DAG | ||
| ) | const [virtual] |
getPICJumpTableRelocaBase - Returns relocation base for the given PIC jumptable.
Reimplemented from llvm::TargetLowering.
Definition at line 1504 of file X86ISelLowering.cpp.
References llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::X86ISD::GlobalBaseReg, and llvm::X86Subtarget::is64Bit().
| const MCExpr * X86TargetLowering::getPICJumpTableRelocBaseExpr | ( | const MachineFunction * | MF, |
| unsigned | JTI, | ||
| MCContext & | Ctx | ||
| ) | const [virtual] |
getPICJumpTableRelocBaseExpr - This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.
Reimplemented from llvm::TargetLowering.
Definition at line 1517 of file X86ISelLowering.cpp.
References llvm::MCSymbolRefExpr::Create(), llvm::MachineFunction::getPICBaseSymbol(), llvm::TargetLowering::getPICJumpTableRelocBaseExpr(), and llvm::X86Subtarget::isPICStyleRIPRel().
| std::pair< unsigned, const TargetRegisterClass * > X86TargetLowering::getRegForInlineAsmConstraint | ( | const std::string & | Constraint, |
| EVT | VT | ||
| ) | const [virtual] |
getRegForInlineAsmConstraint - Given a physical register constraint (e.g. {edx}), return the register number and the register class for the register. This should only be used for C_Register constraints. On error, this returns a register number of 0.
Reimplemented from llvm::TargetLowering.
Definition at line 18401 of file X86ISelLowering.cpp.
References llvm::A64CC::AL, llvm::XCoreISD::BL, llvm::N86::EAX, llvm::N86::EBP, llvm::N86::EBX, llvm::N86::ECX, llvm::N86::EDI, llvm::N86::EDX, llvm::StringRef::equals_lower(), llvm::N86::ESI, llvm::N86::ESP, llvm::MVT::f32, llvm::MVT::f64, llvm::EVT::getSimpleVT(), llvm::X86Subtarget::hasMMX(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::MVT::i1, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, if(), llvm::X86Subtarget::is64Bit(), isScalarFPTypeInSSEReg(), llvm::MVT::SimpleTy, llvm::MVT::v16i16, llvm::MVT::v16i8, llvm::MVT::v2f64, llvm::MVT::v2i64, llvm::MVT::v32i8, llvm::MVT::v4f32, llvm::MVT::v4f64, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v8f32, llvm::MVT::v8i16, and llvm::MVT::v8i32.
| SDValue X86TargetLowering::getReturnAddressFrameIndex | ( | SelectionDAG & | DAG | ) | const |
Definition at line 3120 of file X86ISelLowering.cpp.
References llvm::MachineFrameInfo::CreateFixedObject(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getPointerTy(), llvm::X86MachineFunctionInfo::getRAIndex(), llvm::X86RegisterInfo::getSlotSize(), and llvm::X86MachineFunctionInfo::setRAIndex().
Referenced by LowerINTRINSIC_W_CHAIN().
Reimplemented from llvm::TargetLoweringBase.
Definition at line 481 of file X86ISelLowering.h.
References llvm::MVT::i8.
| EVT X86TargetLowering::getSetCCResultType | ( | LLVMContext & | Context, |
| EVT | VT | ||
| ) | const [virtual] |
getSetCCResultType - Return the value type to use for ISD::SETCC.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1364 of file X86ISelLowering.cpp.
References llvm::EVT::changeVectorElementTypeToInteger(), llvm::MVT::i8, and llvm::EVT::isVector().
Referenced by BuildFILD().
| TargetLowering::ConstraintWeight X86TargetLowering::getSingleConstraintMatchWeight | ( | AsmOperandInfo & | info, |
| const char * | constraint | ||
| ) | const [virtual] |
Examine constraint string and operand type and determine a weight value. The operand object must already have been set up with the operand type.
Examine constraint type and operand type and determine a weight value. This object must already have been set up with the operand type and the current alternative constraint selected.
Reimplemented from llvm::TargetLowering.
Definition at line 18147 of file X86ISelLowering.cpp.
References llvm::TargetLowering::AsmOperandInfo::CallOperandVal, llvm::TargetLowering::CW_Constant, llvm::TargetLowering::CW_Default, llvm::TargetLowering::CW_Invalid, llvm::TargetLowering::CW_Register, llvm::TargetLowering::CW_SpecificReg, llvm::Type::getPrimitiveSizeInBits(), llvm::Value::getType(), llvm::X86Subtarget::hasFp256(), llvm::X86Subtarget::hasMMX(), llvm::X86Subtarget::hasSSE1(), llvm::Type::isFloatingPointTy(), llvm::Type::isIntegerTy(), and llvm::Type::isX86_MMXTy().
| bool X86TargetLowering::getStackCookieLocation | ( | unsigned & | AddressSpace, |
| unsigned & | Offset | ||
| ) | const [virtual] |
getStackCookieLocation - Return true if the target stores stack protector cookies at a fixed offset in some non-standard address space, and populates the address space and offset as appropriate.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1554 of file X86ISelLowering.cpp.
References llvm::TargetMachine::getCodeModel(), llvm::TargetLoweringBase::getTargetMachine(), llvm::X86Subtarget::is64Bit(), llvm::X86Subtarget::isTargetLinux(), and llvm::CodeModel::Kernel.
| const X86Subtarget* llvm::X86TargetLowering::getSubtarget | ( | ) | const [inline] |
Definition at line 689 of file X86ISelLowering.h.
Referenced by LowerVECTOR_SHUFFLEv16i8(), and PerformSINT_TO_FPCombine().
| const char * X86TargetLowering::getTargetNodeName | ( | unsigned | Opcode | ) | const [virtual] |
getTargetNodeName - This method returns the name of a target specific DAG node.
Reimplemented from llvm::TargetLowering.
Definition at line 12682 of file X86ISelLowering.cpp.
References llvm::X86ISD::ADC, llvm::X86ISD::ADD, llvm::X86ISD::AND, llvm::X86ISD::ANDNP, llvm::X86ISD::ATOMADD64_DAG, llvm::X86ISD::ATOMAND64_DAG, llvm::X86ISD::ATOMNAND64_DAG, llvm::X86ISD::ATOMOR64_DAG, llvm::X86ISD::ATOMSUB64_DAG, llvm::X86ISD::ATOMXOR64_DAG, llvm::X86ISD::BLENDI, llvm::X86ISD::BLENDV, llvm::X86ISD::BLSI, llvm::X86ISD::BLSMSK, llvm::X86ISD::BLSR, llvm::X86ISD::BRCOND, llvm::X86ISD::BSF, llvm::X86ISD::BSR, llvm::X86ISD::BT, llvm::X86ISD::CALL, llvm::X86ISD::CMOV, llvm::X86ISD::CMP, llvm::X86ISD::CMPP, llvm::X86ISD::COMI, llvm::X86ISD::DEC, llvm::X86ISD::EH_RETURN, llvm::X86ISD::EH_SJLJ_LONGJMP, llvm::X86ISD::EH_SJLJ_SETJMP, llvm::X86ISD::FAND, llvm::X86ISD::FHADD, llvm::X86ISD::FHSUB, llvm::X86ISD::FILD_FLAG, llvm::X86ISD::FLD, llvm::X86ISD::FMADD, llvm::X86ISD::FMADDSUB, llvm::X86ISD::FMAX, llvm::X86ISD::FMAXC, llvm::X86ISD::FMIN, llvm::X86ISD::FMINC, llvm::X86ISD::FMSUB, llvm::X86ISD::FMSUBADD, llvm::X86ISD::FNMADD, llvm::X86ISD::FNMSUB, llvm::X86ISD::FNSTCW16m, llvm::X86ISD::FNSTSW16r, llvm::X86ISD::FOR, llvm::X86ISD::FP_TO_INT16_IN_MEM, llvm::X86ISD::FP_TO_INT32_IN_MEM, llvm::X86ISD::FP_TO_INT64_IN_MEM, llvm::X86ISD::FRCP, llvm::X86ISD::FRSQRT, llvm::X86ISD::FSETCCsd, llvm::X86ISD::FSETCCss, llvm::X86ISD::FSRL, llvm::X86ISD::FST, llvm::X86ISD::FXOR, llvm::X86ISD::GlobalBaseReg, llvm::X86ISD::HADD, llvm::X86ISD::HSUB, llvm::X86ISD::INC, llvm::X86ISD::INSERTPS, llvm::X86ISD::LCMPXCHG8_DAG, llvm::X86ISD::LCMPXCHG_DAG, llvm::X86ISD::MEMBARRIER, llvm::X86ISD::MOVDDUP, llvm::X86ISD::MOVHLPS, llvm::X86ISD::MOVLHPD, llvm::X86ISD::MOVLHPS, llvm::X86ISD::MOVLPD, llvm::X86ISD::MOVLPS, llvm::X86ISD::MOVSD, llvm::X86ISD::MOVSHDUP, llvm::X86ISD::MOVSLDUP, llvm::X86ISD::MOVSS, llvm::X86ISD::MUL_IMM, llvm::X86ISD::OR, llvm::X86ISD::PALIGNR, llvm::X86ISD::PCMPEQ, llvm::X86ISD::PCMPESTRI, llvm::X86ISD::PCMPGT, llvm::X86ISD::PCMPISTRI, llvm::X86ISD::PEXTRB, llvm::X86ISD::PEXTRW, llvm::X86ISD::PINSRB, llvm::X86ISD::PINSRW, llvm::X86ISD::PMULUDQ, llvm::X86ISD::PSHUFB, llvm::X86ISD::PSHUFD, llvm::X86ISD::PSHUFHW, llvm::X86ISD::PSHUFLW, llvm::X86ISD::PSIGN, llvm::X86ISD::PTEST, llvm::X86ISD::RDRAND, llvm::X86ISD::RDSEED, llvm::X86ISD::RDTSC_DAG, llvm::X86ISD::REP_MOVS, llvm::X86ISD::REP_STOS, llvm::X86ISD::RET_FLAG, llvm::X86ISD::SAHF, llvm::X86ISD::SBB, llvm::X86ISD::SEG_ALLOCA, llvm::X86ISD::SETCC, llvm::X86ISD::SETCC_CARRY, llvm::X86ISD::SHLD, llvm::X86ISD::SHRD, llvm::X86ISD::SHUFP, llvm::X86ISD::SMAX, llvm::X86ISD::SMIN, llvm::X86ISD::SMUL, llvm::X86ISD::SUB, llvm::X86ISD::SUBUS, llvm::X86ISD::TC_RETURN, llvm::X86ISD::TESTP, llvm::X86ISD::TLSADDR, llvm::X86ISD::TLSBASEADDR, llvm::X86ISD::TLSCALL, llvm::X86ISD::UCOMI, llvm::X86ISD::UMAX, llvm::X86ISD::UMIN, llvm::X86ISD::UMUL, llvm::X86ISD::UNPCKH, llvm::X86ISD::UNPCKL, llvm::X86ISD::VAARG_64, llvm::X86ISD::VASTART_SAVE_XMM_REGS, llvm::X86ISD::VBROADCAST, llvm::X86ISD::VFPEXT, llvm::X86ISD::VFPROUND, llvm::X86ISD::VPERM2X128, llvm::X86ISD::VPERMI, llvm::X86ISD::VPERMILP, llvm::X86ISD::VPERMV, llvm::X86ISD::VSEXT, llvm::X86ISD::VSEXT_MOVL, llvm::X86ISD::VSHL, llvm::X86ISD::VSHLDQ, llvm::X86ISD::VSHLI, llvm::X86ISD::VSRA, llvm::X86ISD::VSRAI, llvm::X86ISD::VSRL, llvm::X86ISD::VSRLDQ, llvm::X86ISD::VSRLI, llvm::X86ISD::VZEXT, llvm::X86ISD::VZEXT_LOAD, llvm::X86ISD::VZEXT_MOVL, llvm::X86ISD::WIN_ALLOCA, llvm::X86ISD::WIN_FTOL, llvm::X86ISD::Wrapper, llvm::X86ISD::WrapperRIP, llvm::X86ISD::XOR, and llvm::X86ISD::XTEST.
isTypeDesirable - Return true if the target has native support for the specified value type and it is 'desirable' to use the type. e.g. On x86 i16 is legal, but undesirable since i16 instruction encodings are longer and some i16 instructions are slow.
IsDesirableToPromoteOp - This method query the target whether it is beneficial for dag combiner to promote the specified node. If true, it should return the desired promotion type by reference.
Reimplemented from llvm::TargetLowering.
Definition at line 17924 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::CopyToReg, llvm::LoadSDNode::getExtensionType(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::ISD::LOAD, MayFoldIntoStore(), MayFoldLoad(), llvm::ISD::MUL, llvm::ISD::NON_EXTLOAD, llvm::ISD::OR, llvm::TargetLoweringBase::Promote, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SRL, llvm::ISD::SUB, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than a pair of mul and add instructions. fmuladd intrinsics will be expanded to FMAs when this method returns true (and FMAs are legal), otherwise fmuladd is expanded to mul + add.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 653 of file X86ISelLowering.h.
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively. If false, the legalizer will materialize the FP immediate as a load from a constant pool.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 3301 of file X86ISelLowering.cpp.
References llvm::APFloat::bitwiseIsEqual().
| bool X86TargetLowering::isGAPlusOffset | ( | SDNode * | N, |
| const GlobalValue *& | GA, | ||
| int64_t & | Offset | ||
| ) | const [virtual] |
isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.
Reimplemented from llvm::TargetLowering.
Definition at line 15011 of file X86ISelLowering.cpp.
References llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), and llvm::ARMISD::Wrapper.
isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be used for fptoui to the given type.
Definition at line 708 of file X86ISelLowering.h.
References llvm::MVT::i64, and isTargetFTOL().
Referenced by BuildFILD(), and ReplaceNodeResults().
| bool X86TargetLowering::isLegalAddImmediate | ( | int64_t | Imm | ) | const [virtual] |
isLegalAddImmediate - Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 12905 of file X86ISelLowering.cpp.
References llvm::isInt< 32 >().
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 12841 of file X86ISelLowering.cpp.
References llvm::TargetLoweringBase::AddrMode::BaseGV, llvm::TargetLoweringBase::AddrMode::BaseOffs, llvm::X86Subtarget::ClassifyGlobalReference(), llvm::TargetMachine::getCodeModel(), llvm::TargetMachine::getRelocationModel(), llvm::TargetLoweringBase::getTargetMachine(), llvm::TargetLoweringBase::AddrMode::HasBaseReg, llvm::X86Subtarget::is64Bit(), llvm::isGlobalRelativeToPICBase(), llvm::isGlobalStubReference(), llvm::X86::isOffsetSuitableForCodeModel(), llvm::TargetLoweringBase::AddrMode::Scale, llvm::CodeModel::Small, and llvm::Reloc::Static.
| bool X86TargetLowering::isLegalICmpImmediate | ( | int64_t | Imm | ) | const [virtual] |
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 12901 of file X86ISelLowering.cpp.
References llvm::isInt< 32 >().
isNarrowingProfitable - Return true if it's profitable to narrow operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from i32 to i16.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 12952 of file X86ISelLowering.cpp.
References llvm::MVT::i32.
isSafeMemOpType - Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline. This is mostly true for all types except for some special cases. For example, on X86 targets without SSE2 f64 load / store are done with fldl / fstpl which also does type conversion. Note the specified type doesn't have to be legal as the hook is used before type legalization.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 1461 of file X86ISelLowering.cpp.
References llvm::MVT::f32, and llvm::MVT::f64.
isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is computed in an SSE register, not on the X87 floating point stack.
Definition at line 695 of file X86ISelLowering.h.
References llvm::MVT::f32, and llvm::MVT::f64.
Referenced by BuildFILD(), and getRegForInlineAsmConstraint().
| bool X86TargetLowering::isShuffleMaskLegal | ( | const SmallVectorImpl< int > & | M, |
| EVT | VT | ||
| ) | const [virtual] |
isShuffleMaskLegal - Targets can use this to indicate that they only support *some* VECTOR_SHUFFLE operations, those with specific masks. By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 12962 of file X86ISelLowering.cpp.
References llvm::EVT::getSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::X86Subtarget::hasFp256(), llvm::X86Subtarget::hasInt256(), isMOVLMask(), isPALIGNRMask(), isPSHUFDMask(), isPSHUFHWMask(), isPSHUFLWMask(), isSHUFPMask(), llvm::ShuffleVectorSDNode::isSplatMask(), isUNPCKH_v_undef_Mask(), isUNPCKHMask(), isUNPCKL_v_undef_Mask(), and isUNPCKLMask().
| bool llvm::X86TargetLowering::isTargetFTOL | ( | ) | const [inline] |
isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine for fptoui.
Definition at line 702 of file X86ISelLowering.h.
References llvm::X86Subtarget::is64Bit(), and llvm::X86Subtarget::isTargetWindows().
Referenced by isIntegerTypeFTOL(), and resetOperationActions().
isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16 by referencing its sub-register AX.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 12893 of file X86ISelLowering.cpp.
References llvm::Type::getPrimitiveSizeInBits(), and llvm::Type::isIntegerTy().
Reimplemented from llvm::TargetLoweringBase.
Definition at line 12910 of file X86ISelLowering.cpp.
References llvm::EVT::getSizeInBits(), and llvm::EVT::isInteger().
isTypeDesirableForOp - Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type. e.g. On x86 i16 is legal, but undesirable since i16 instruction encodings are longer and some i16 instructions are slow.
Reimplemented from llvm::TargetLowering.
Definition at line 17896 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::TargetLoweringBase::isTypeLegal(), llvm::ISD::LOAD, llvm::ISD::MUL, llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
| bool X86TargetLowering::isVectorClearMaskLegal | ( | const SmallVectorImpl< int > & | Mask, |
| EVT | VT | ||
| ) | const [virtual] |
isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is used by Targets can use this to indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a constant pool entry.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 12984 of file X86ISelLowering.cpp.
References llvm::EVT::getVectorNumElements(), llvm::X86Subtarget::hasFp256(), llvm::EVT::is128BitVector(), isCommutedMOVLMask(), isMOVLMask(), and isSHUFPMask().
isZExtFree - Return true if any actual instruction that defines a value of type Ty1 implicit zero-extends the value to Ty2 in the result register. This does not necessarily include registers defined in unknown ways, such as incoming arguments, or copies from unknown virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to truncate instructions. e.g. on x86-64, all instructions that define 32-bit values implicit zero-extend the result out to 64 bits.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 12918 of file X86ISelLowering.cpp.
References llvm::X86Subtarget::is64Bit(), and llvm::Type::isIntegerTy().
Referenced by isZExtFree().
Reimplemented from llvm::TargetLoweringBase.
Definition at line 12923 of file X86ISelLowering.cpp.
References llvm::MVT::i32, llvm::MVT::i64, and llvm::X86Subtarget::is64Bit().
isZExtFree - Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads).
Reimplemented from llvm::TargetLoweringBase.
Definition at line 12928 of file X86ISelLowering.cpp.
References llvm::SDValue::getOpcode(), llvm::EVT::getSimpleVT(), llvm::SDValue::getValueType(), llvm::MVT::i32, llvm::MVT::i8, llvm::EVT::isInteger(), llvm::EVT::isSimple(), isZExtFree(), llvm::ISD::LOAD, and llvm::MVT::SimpleTy.
| void X86TargetLowering::LowerAsmOperandForConstraint | ( | SDValue | Op, |
| std::string & | Constraint, | ||
| std::vector< SDValue > & | Ops, | ||
| SelectionDAG & | DAG | ||
| ) | const [virtual] |
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector. If it is invalid, don't add anything to Ops. If hasMemory is true it means one of the asm constraint of the inline asm instruction being processed is 'm'.
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector. If it is invalid, don't add anything to Ops.
Reimplemented from llvm::TargetLowering.
Definition at line 18267 of file X86ISelLowering.cpp.
References ADD, llvm::X86Subtarget::ClassifyGlobalReference(), llvm::SelectionDAG::getContext(), llvm::SDValue::getDebugLoc(), llvm::GlobalAddressSDNode::getGlobal(), llvm::Type::getInt32Ty(), llvm::SDValue::getNode(), llvm::GlobalAddressSDNode::getOffset(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::TargetLoweringBase::getTargetMachine(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::MVT::i64, llvm::isGlobalStubReference(), llvm::isInt< 8 >(), llvm::X86Subtarget::isPICStyleGOT(), llvm::X86Subtarget::isPICStyleStubPIC(), llvm::ConstantInt::isValueValidForType(), and SUB.
| const MCExpr * X86TargetLowering::LowerCustomJumpTableEntry | ( | const MachineJumpTableInfo * | MJTI, |
| const MachineBasicBlock * | MBB, | ||
| unsigned | uid, | ||
| MCContext & | Ctx | ||
| ) | const [virtual] |
Reimplemented from llvm::TargetLowering.
Definition at line 1491 of file X86ISelLowering.cpp.
References llvm::MCSymbolRefExpr::Create(), llvm::MachineBasicBlock::getSymbol(), llvm::TargetLoweringBase::getTargetMachine(), llvm::X86Subtarget::isPICStyleGOT(), llvm::Reloc::PIC_, and llvm::MCSymbolRefExpr::VK_GOTOFF.
| SDValue X86TargetLowering::LowerOperation | ( | SDValue | Op, |
| SelectionDAG & | DAG | ||
| ) | const [virtual] |
LowerOperation - Provide custom lowering hooks for some operations.
Reimplemented from llvm::TargetLowering.
Definition at line 12374 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::ISD::ADJUST_TRAMPOLINE, llvm::ISD::ANY_EXTEND, llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_FENCE, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_STORE, llvm::ISD::BITCAST, llvm::ISD::BlockAddress, llvm::ISD::BRCOND, llvm::ISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::ISD::ConstantPool, llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTTZ, llvm::ISD::DYNAMIC_STACKALLOC, llvm::ISD::EH_RETURN, llvm::ISD::EH_SJLJ_LONGJMP, llvm::ISD::EH_SJLJ_SETJMP, llvm::ISD::ExternalSymbol, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FABS, llvm::ISD::FCOPYSIGN, llvm::ISD::FGETSIGN, llvm::ISD::FLT_ROUNDS_, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FRAME_TO_ARGS_OFFSET, llvm::ISD::FRAMEADDR, llvm::ISD::FSINCOS, llvm::SDValue::getOpcode(), llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::ISD::INIT_TRAMPOLINE, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::JumpTable, llvm_unreachable, LowerADD(), LowerADDC_ADDE_SUBC_SUBE(), LowerADJUST_TRAMPOLINE(), LowerATOMIC_FENCE(), LowerATOMIC_STORE(), LowerCMP_SWAP(), LowerCONCAT_VECTORS(), LowerCTLZ(), LowerCTLZ_ZERO_UNDEF(), LowerCTTZ(), LowerEXTRACT_SUBVECTOR(), LowerFGETSIGN(), LowerFP_EXTEND(), LowerINSERT_SUBVECTOR(), LowerINTRINSIC_W_CHAIN(), LowerINTRINSIC_WO_CHAIN(), LowerLOAD_SUB(), LowerMUL(), LowerREADCYCLECOUNTER(), LowerSCALAR_TO_VECTOR(), LowerSUB(), LowerVACOPY(), LowerXALUO(), llvm::ISD::MUL, llvm::ISD::READCYCLECOUNTER, llvm::ISD::RETURNADDR, llvm::ISD::SADDO, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SDIV, llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SHL_PARTS, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SINT_TO_FP, llvm::ISD::SMULO, llvm::ISD::SRA, llvm::ISD::SRA_PARTS, llvm::ISD::SRL, llvm::ISD::SRL_PARTS, llvm::ISD::SSUBO, llvm::ISD::SUB, llvm::ISD::SUBC, llvm::ISD::SUBE, llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UINT_TO_FP, llvm::ISD::UMULO, llvm::ISD::USUBO, llvm::ISD::VAARG, llvm::ISD::VACOPY, llvm::ISD::VASTART, llvm::ISD::VECTOR_SHUFFLE, and llvm::ISD::ZERO_EXTEND.
| const char * X86TargetLowering::LowerXConstraint | ( | EVT | ConstraintVT | ) | const [virtual] |
LowerXConstraint - try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand.
Reimplemented from llvm::TargetLowering.
Definition at line 18252 of file X86ISelLowering.cpp.
References llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), and llvm::EVT::isFloatingPoint().
| SDValue X86TargetLowering::PerformDAGCombine | ( | SDNode * | N, |
| DAGCombinerInfo & | DCI | ||
| ) | const [virtual] |
PerformDAGCombine - This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.
The semantics are as follows: Return Value: SDValue.Val == 0 - No change was made SDValue.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand.
In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.
Reimplemented from llvm::TargetLowering.
Definition at line 17831 of file X86ISelLowering.cpp.
References llvm::X86ISD::ADC, llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::X86ISD::BRCOND, llvm::X86ISD::BT, llvm::X86ISD::CMOV, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::X86ISD::FAND, llvm::ISD::FMA, llvm::X86ISD::FMAX, llvm::X86ISD::FMIN, llvm::X86ISD::FOR, llvm::ISD::FSUB, llvm::X86ISD::FXOR, llvm::SDNode::getOpcode(), llvm::ISD::LOAD, llvm::X86ISD::MOVHLPS, llvm::X86ISD::MOVLHPS, llvm::X86ISD::MOVSD, llvm::X86ISD::MOVSS, llvm::ISD::MUL, llvm::ISD::OR, llvm::X86ISD::PALIGNR, PerformADCCombine(), PerformAddCombine(), PerformAndCombine(), PerformBrCondCombine(), PerformBTCombine(), PerformCMOVCombine(), PerformEXTRACT_VECTOR_ELTCombine(), PerformFADDCombine(), PerformFANDCombine(), PerformFMACombine(), PerformFMinFMaxCombine(), PerformFORCombine(), PerformFSUBCombine(), PerformISDSETCCCombine(), PerformLOADCombine(), PerformMulCombine(), PerformOrCombine(), PerformSELECTCombine(), PerformSETCCCombine(), PerformSExtCombine(), PerformShiftCombine(), PerformShuffleCombine(), PerformSIGN_EXTEND_INREGCombine(), PerformSINT_TO_FPCombine(), PerformSTORECombine(), PerformSubCombine(), PerformTruncateCombine(), PerformVZEXT_MOVLCombine(), performVZEXTCombine(), PerformXorCombine(), PerformZExtCombine(), llvm::X86ISD::PSHUFD, llvm::X86ISD::PSHUFHW, llvm::X86ISD::PSHUFLW, llvm::ISD::SELECT, llvm::X86ISD::SETCC, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::X86ISD::SHUFP, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SINT_TO_FP, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::TRUNCATE, llvm::X86ISD::UNPCKH, llvm::X86ISD::UNPCKL, llvm::ISD::VECTOR_SHUFFLE, llvm::X86ISD::VPERM2X128, llvm::X86ISD::VPERMILP, llvm::ISD::VSELECT, llvm::X86ISD::VZEXT, llvm::X86ISD::VZEXT_MOVL, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
| void X86TargetLowering::ReplaceNodeResults | ( | SDNode * | N, |
| SmallVectorImpl< SDValue > & | Results, | ||
| SelectionDAG & | DAG | ||
| ) | const [virtual] |
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code.
ReplaceNodeResults - Replace a node with an illegal result type with a new node built out of custom code.
Reimplemented from llvm::TargetLowering.
Definition at line 12503 of file X86ISelLowering.cpp.
References llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::array_lengthof(), llvm::ARMISD::ATOMADD64_DAG, llvm::ARMISD::ATOMAND64_DAG, llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_MAX, llvm::ISD::ATOMIC_LOAD_MIN, llvm::ISD::ATOMIC_LOAD_NAND, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_UMAX, llvm::ISD::ATOMIC_LOAD_UMIN, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_SWAP, llvm::ARMISD::ATOMMAX64_DAG, llvm::ARMISD::ATOMMIN64_DAG, llvm::ARMISD::ATOMNAND64_DAG, llvm::ARMISD::ATOMOR64_DAG, llvm::ARMISD::ATOMSUB64_DAG, llvm::ARMISD::ATOMSWAP64_DAG, llvm::ARMISD::ATOMUMAX64_DAG, llvm::ARMISD::ATOMUMIN64_DAG, llvm::ARMISD::ATOMXOR64_DAG, llvm::ISD::BITCAST, llvm::BitsToDouble(), llvm::ISD::BUILD_PAIR, llvm::ISD::BUILD_VECTOR, llvm::N86::EAX, llvm::N86::EBX, llvm::N86::ECX, llvm::N86::EDX, llvm::ISD::EXTRACT_ELEMENT, llvm::MVT::f64, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FSUB, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::SDNode::getDebugLoc(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::TargetLoweringBase::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MVT::Glue, llvm::X86Subtarget::hasSSE2(), llvm::MVT::i128, llvm::MVT::i32, llvm::MVT::i64, isIntegerTypeFTOL(), llvm::TargetLoweringBase::isTypeLegal(), llvm::X86ISD::LCMPXCHG16_DAG, llvm::X86ISD::LCMPXCHG8_DAG, llvm_unreachable, llvm::ISD::OR, llvm::APIntOps::Or(), llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike >::push_back(), llvm::X86ISD::RDTSC_DAG, llvm::ISD::READCYCLECOUNTER, ReplaceATOMIC_BINARY_64(), ReplaceATOMIC_LOAD(), llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SUBC, llvm::ISD::SUBE, llvm::ISD::UINT_TO_FP, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4f32, llvm::X86ISD::VFPROUND, and llvm::ISD::ZERO_EXTEND.
| void X86TargetLowering::resetOperationActions | ( | ) | [virtual] |
Reset the operation actions based on target options.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 172 of file X86ISelLowering.cpp.
References llvm::ISD::ADD, llvm::TargetLoweringBase::addBypassSlowDiv(), llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::TargetLoweringBase::AddPromotedToType(), llvm::TargetLoweringBase::addRegisterClass(), llvm::ISD::ADJUST_TRAMPOLINE, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::lltok::APFloat, llvm::array_lengthof(), llvm::ISD::ATOMIC_CMP_SWAP, llvm::ISD::ATOMIC_FENCE, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_AND, llvm::ISD::ATOMIC_LOAD_MAX, llvm::ISD::ATOMIC_LOAD_MIN, llvm::ISD::ATOMIC_LOAD_NAND, llvm::ISD::ATOMIC_LOAD_OR, llvm::ISD::ATOMIC_LOAD_SUB, llvm::ISD::ATOMIC_LOAD_UMAX, llvm::ISD::ATOMIC_LOAD_UMIN, llvm::ISD::ATOMIC_LOAD_XOR, llvm::ISD::ATOMIC_STORE, llvm::ISD::ATOMIC_SWAP, llvm::ISD::BITCAST, llvm::ISD::BlockAddress, llvm::ISD::BR_CC, llvm::ISD::BR_JT, llvm::ISD::BRCOND, llvm::ISD::BSWAP, llvm::ISD::BUILD_VECTOR, llvm::APFloat::changeSign(), llvm::TargetLoweringBase::computeRegisterProperties(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::ConstantPool, llvm::APFloat::convert(), llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::TargetLoweringBase::Custom, llvm::ISD::DEBUGTRAP, llvm::Reloc::Default, llvm::ISD::DYNAMIC_STACKALLOC, llvm::N86::EAX, llvm::N86::EDX, llvm::ISD::EH_LABEL, llvm::ISD::EH_RETURN, llvm::ISD::EH_SJLJ_LONGJMP, llvm::ISD::EH_SJLJ_SETJMP, llvm::ISD::EHSELECTION, llvm::TargetOptions::EnableSegmentedStacks, llvm::ISD::EXCEPTIONADDR, llvm::TargetLoweringBase::Expand, llvm::ISD::ExternalSymbol, llvm::ISD::EXTLOAD, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f32, llvm::MVT::f64, llvm::MVT::f80, llvm::ISD::FABS, llvm::ISD::FADD, llvm::ISD::FCEIL, llvm::ISD::FCOPYSIGN, llvm::ISD::FCOS, llvm::ISD::FDIV, llvm::ISD::FEXP, llvm::ISD::FEXP2, llvm::ISD::FFLOOR, llvm::ISD::FGETSIGN, llvm::MVT::FIRST_VECTOR_VALUETYPE, llvm::ISD::FLOG, llvm::ISD::FLOG10, llvm::ISD::FLOG2, llvm::ISD::FLT_ROUNDS_, llvm::ISD::FMA, llvm::ISD::FMUL, llvm::ISD::FNEARBYINT, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_ROUND_INREG, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::ISD::FPOW, llvm::ISD::FPOWI, llvm::RTLIB::FPTOUINT_F32_I32, llvm::RTLIB::FPTOUINT_F32_I64, llvm::RTLIB::FPTOUINT_F64_I32, llvm::RTLIB::FPTOUINT_F64_I64, llvm::ISD::FRAME_TO_ARGS_OFFSET, llvm::ISD::FREM, llvm::ISD::FRINT, llvm::ISD::FSIN, llvm::ISD::FSINCOS, llvm::ISD::FSQRT, llvm::ISD::FSUB, llvm::ISD::FTRUNC, llvm::TargetMachine::getOptLevel(), llvm::X86RegisterInfo::getStackRegister(), llvm::TargetLoweringBase::getTargetMachine(), llvm::MVT::getVectorNumElements(), llvm::APFloat::getZero(), llvm::ISD::GlobalAddress, llvm::ISD::GlobalTLSAddress, llvm::X86Subtarget::hasBMI(), llvm::X86Subtarget::hasCmpxchg16b(), llvm::X86Subtarget::hasFMA(), llvm::X86Subtarget::hasFMA4(), llvm::X86Subtarget::hasFp256(), llvm::X86Subtarget::hasInt256(), llvm::X86Subtarget::hasLZCNT(), llvm::X86Subtarget::hasMMX(), llvm::X86Subtarget::hasPOPCNT(), llvm::X86Subtarget::hasSinCos(), llvm::X86Subtarget::hasSlowDivide(), llvm::X86Subtarget::hasSSE1(), llvm::X86Subtarget::hasSSE2(), llvm::X86Subtarget::hasSSE3(), llvm::X86Subtarget::hasSSE41(), llvm::MVT::i1, llvm::MVT::i128, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::Sched::ILP, llvm::ISD::INIT_TRAMPOLINE, llvm::TargetLoweringBase::initActions(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::MVT::is128BitVector(), llvm::MVT::is256BitVector(), llvm::X86Subtarget::is64Bit(), llvm::X86Subtarget::isAtom(), llvm::isPowerOf2_32(), llvm::X86Subtarget::isTargetCOFF(), llvm::X86Subtarget::isTargetCygMing(), llvm::X86Subtarget::isTargetDarwin(), llvm::X86Subtarget::isTargetELF(), llvm::X86Subtarget::isTargetEnvMacho(), isTargetFTOL(), llvm::X86Subtarget::isTargetMingw(), llvm::X86Subtarget::isTargetWindows(), llvm::ISD::JumpTable, llvm::MVT::LAST_VECTOR_VALUETYPE, llvm::TargetLoweringBase::Legal, llvm::ISD::LOAD, llvm::TargetLoweringBase::MaxStoresPerMemcpy, llvm::TargetLoweringBase::MaxStoresPerMemcpyOptSize, llvm::TargetLoweringBase::MaxStoresPerMemmove, llvm::TargetLoweringBase::MaxStoresPerMemmoveOptSize, llvm::TargetLoweringBase::MaxStoresPerMemset, llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize, llvm::ISD::MUL, llvm::RTLIB::MUL_I64, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::TargetMachine::Options, llvm::ISD::OR, llvm::MVT::Other, llvm::TargetLoweringBase::PredictableSelectIsExpensive, llvm::ISD::PREFETCH, llvm::TargetLoweringBase::Promote, llvm::ISD::READCYCLECOUNTER, llvm::Sched::RegPressure, llvm::APFloat::rmNearestTiesToEven, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SADDO, llvm::ISD::SCALAR_TO_VECTOR, llvm::ISD::SDIV, llvm::RTLIB::SDIV_I64, llvm::ISD::SDIVREM, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::TargetLoweringBase::setBooleanContents(), llvm::TargetLoweringBase::setBooleanVectorContents(), llvm::ISD::SETCC, llvm::TargetLoweringBase::setCondCodeAction(), llvm::TargetLoweringBase::setExceptionPointerRegister(), llvm::TargetLoweringBase::setExceptionSelectorRegister(), llvm::TargetLoweringBase::setLibcallCallingConv(), llvm::TargetLoweringBase::setLibcallName(), llvm::TargetLoweringBase::setLoadExtAction(), llvm::ISD::SETOEQ, llvm::TargetLoweringBase::setOperationAction(), llvm::TargetLoweringBase::setPrefFunctionAlignment(), llvm::TargetLoweringBase::setPrefLoopAlignment(), llvm::TargetLoweringBase::setSchedulingPreference(), llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore(), llvm::TargetLoweringBase::setTargetDAGCombine(), llvm::TargetLoweringBase::setTruncStoreAction(), llvm::ISD::SETUNE, llvm::TargetLoweringBase::setUseUnderscoreLongJmp(), llvm::TargetLoweringBase::setUseUnderscoreSetJmp(), llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::RTLIB::SHL_I128, llvm::ISD::SHL_PARTS, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::RTLIB::SINCOS_F32, llvm::RTLIB::SINCOS_F64, llvm::ISD::SINT_TO_FP, llvm::ISD::SMUL_LOHI, llvm::ISD::SMULO, llvm::ISD::SRA, llvm::RTLIB::SRA_I128, llvm::ISD::SRA_PARTS, llvm::ISD::SREM, llvm::RTLIB::SREM_I64, llvm::ISD::SRL, llvm::RTLIB::SRL_I128, llvm::ISD::SRL_PARTS, llvm::ISD::SSUBO, llvm::ISD::STACKRESTORE, llvm::ISD::STACKSAVE, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::SUBC, llvm::ISD::SUBE, llvm::ISD::TRAP, llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::ISD::UDIV, llvm::RTLIB::UDIV_I64, llvm::ISD::UDIVREM, llvm::ISD::UINT_TO_FP, llvm::ISD::UMUL_LOHI, llvm::ISD::UMULO, llvm::ISD::UNDEF, llvm::TargetOptions::UnsafeFPMath, llvm::ISD::UREM, llvm::RTLIB::UREM_I64, llvm::TargetOptions::UseSoftFloat, llvm::ISD::USUBO, llvm::MVT::v16i16, llvm::MVT::v16i8, llvm::MVT::v1i64, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v32i8, llvm::MVT::v4f32, llvm::MVT::v4f64, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v4i64, llvm::MVT::v4i8, llvm::MVT::v8f32, llvm::MVT::v8i16, llvm::MVT::v8i32, llvm::MVT::v8i8, llvm::ISD::VAARG, llvm::ISD::VACOPY, llvm::ISD::VAEND, llvm::ISD::VASTART, llvm::ISD::VECTOR_SHUFFLE, llvm::ISD::VSELECT, llvm::CallingConv::X86_StdCall, llvm::MVT::x86mmx, llvm::APFloat::x87DoubleExtended, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, llvm::TargetLoweringBase::ZeroOrOneBooleanContent, and llvm::ISD::ZEXTLOAD.
Referenced by X86TargetLowering().
ShouldShrinkFPConstant - If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime.
Reimplemented from llvm::TargetLoweringBase.
Definition at line 682 of file X86ISelLowering.h.
References llvm::MVT::f80.
The documentation for this class was generated from the following files:
1.7.5.1