LLVM  9.0.0svn
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AMDGPUISelDAGToDAG.cpp File Reference

Defines an instruction selector for the AMDGPU target. More...

#include "AMDGPU.h"
#include "AMDGPUArgumentUsageInfo.h"
#include "AMDGPUISelLowering.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPUPerfHintAnalysis.h"
#include "AMDGPURegisterInfo.h"
#include "AMDGPUSubtarget.h"
#include "AMDGPUTargetMachine.h"
#include "SIDefines.h"
#include "SIISelLowering.h"
#include "SIInstrInfo.h"
#include "SIMachineFunctionInfo.h"
#include "SIRegisterInfo.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/Analysis/LegacyDivergenceAnalysis.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Instruction.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/MathExtras.h"
#include <cassert>
#include <cstdint>
#include <new>
#include <vector>
#include "AMDGPUGenDAGISel.inc"
#include "R600GenDAGISel.inc"
Include dependency graph for AMDGPUISelDAGToDAG.cpp:

Go to the source code of this file.

Namespaces

 llvm
 This class represents lattice values for constants.
 

Macros

#define DEBUG_TYPE   "isel"
 

Functions

 INITIALIZE_PASS_BEGIN (AMDGPUDAGToDAGISel, "amdgpu-isel", "AMDGPU DAG->DAG Pattern Instruction Selection", false, false) INITIALIZE_PASS_END(AMDGPUDAGToDAGISel
 
static unsigned selectSGPRVectorRegClassID (unsigned NumVectorElts)
 
static bool getConstantValue (SDValue N, uint32_t &Out)
 
static bool isStackPtrRelative (const MachinePointerInfo &PtrInfo)
 

Variables

amdgpu isel
 
amdgpu AMDGPU DAG DAG Pattern Instruction Selection
 
amdgpu AMDGPU DAG DAG Pattern Instruction false
 

Detailed Description

Defines an instruction selector for the AMDGPU target.

Definition in file AMDGPUISelDAGToDAG.cpp.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "isel"

Definition at line 54 of file AMDGPUISelDAGToDAG.cpp.

Function Documentation

◆ getConstantValue()

static bool getConstantValue ( SDValue  N,
uint32_t Out 
)
static

Definition at line 558 of file AMDGPUISelDAGToDAG.cpp.

References llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::ISD::AND, llvm::AMDGPU::HSAMD::Kernel::Key::Args, assert(), llvm::AMDGPUISD::ATOMIC_CMP_SWAP, llvm::AMDGPUISD::ATOMIC_DEC, llvm::AMDGPUISD::ATOMIC_INC, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_LOAD_FADD, llvm::AMDGPUISD::ATOMIC_LOAD_FMAX, llvm::AMDGPUISD::ATOMIC_LOAD_FMIN, llvm::ISD::ATOMIC_STORE, llvm::AMDGPUISD::BFE_I32, llvm::AMDGPUISD::BFE_U32, llvm::EVT::bitsEq(), llvm::ISD::BRCOND, llvm::ISD::BUILD_PAIR, llvm::ISD::BUILD_VECTOR, C, llvm::ISD::Constant, llvm::ISD::ConstantFP, llvm::ISD::CopyToReg, llvm::AMDGPUISD::CVT_PK_I16_I32, llvm::AMDGPUISD::CVT_PK_U16_U32, llvm::AMDGPUISD::CVT_PKNORM_I16_F32, llvm::AMDGPUISD::CVT_PKNORM_U16_F32, llvm::AMDGPUISD::CVT_PKRTZ_F16_F32, llvm::AMDGPUISD::DIV_SCALE, llvm::AMDGPUISD::DWORDADDR, llvm::dyn_cast(), llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FMA, llvm::AMDGPUISD::FMA_W_CHAIN, llvm::ISD::FMAD, llvm::AMDGPUISD::FMUL_W_CHAIN, llvm::Instruction::getMetadata(), llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::ConstantSDNode::getSExtValue(), llvm::EVT::getSizeInBits(), llvm::AMDGPURegisterInfo::getSubRegFromChannel(), llvm::BasicBlock::getTerminator(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SDNode::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::Glue, llvm::MVT::i1, llvm::MVT::i128, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::ISD::INTRINSIC_W_CHAIN, llvm::SDNode::isDivergent(), llvm::SIInstrInfo::isLegalMUBUFImmOffset(), llvm::SDNode::isMachineOpcode(), llvm::isUInt< 16 >(), llvm::isUInt< 32 >(), llvm::isUInt< 8 >(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm_unreachable, llvm::ISD::LOAD, Lowering, llvm::AMDGPUISD::MAD_I64_I32, llvm::AMDGPUISD::MAD_U64_U32, N, llvm::ISD::OR, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::MCID::RegSequence, llvm::ISD::SCALAR_TO_VECTOR, llvm::AMDGPUSubtarget::SEA_ISLANDS, llvm::MCID::Select, selectSGPRVectorRegClassID(), llvm::SDNode::setNodeId(), llvm::ISD::SIGN_EXTEND_INREG, Signed, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::SUBC, llvm::ISD::SUBE, llvm::ISD::UADDO, llvm::ISD::USUBO, llvm::MVT::v2f16, llvm::MVT::v2i16, llvm::MVT::v2i32, llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS, and llvm::SITargetLowering::wrapAddr64Rsrc().

Referenced by llvm::ExecutionEngine::ExecutionEngine(), llvm::ExecutionEngine::getConstantValue(), and llvm::ExecutionEngine::InitializeMemory().

◆ INITIALIZE_PASS_BEGIN()

INITIALIZE_PASS_BEGIN ( AMDGPUDAGToDAGISel  ,
"amdgpu-isel ,
"AMDGPU DAG->DAG Pattern Instruction Selection ,
false  ,
false   
)

◆ isStackPtrRelative()

static bool isStackPtrRelative ( const MachinePointerInfo PtrInfo)
static

Definition at line 1297 of file AMDGPUISelDAGToDAG.cpp.

References llvm::SISrcMods::ABS, llvm::ISD::AND, assert(), B, llvm::ISD::BRCOND, llvm::ISD::BUILD_VECTOR, llvm::SITargetLowering::buildRSRC(), C, llvm::TargetInstrInfo::CommuteAnyOperandIndex, AMDGPUAS::CONSTANT_ADDRESS, AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::ISD::CopyToReg, llvm::countPopulation(), llvm::PointerUnion< PT1, PT2 >::dyn_cast(), llvm::dyn_cast(), E, llvm::MVT::f16, llvm::MVT::f32, llvm::ISD::FABS, llvm::SIInstrInfo::findCommutedOpIndices(), AMDGPUAS::FLAT_ADDRESS, llvm::ISD::FMA, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::SIMachineFunctionInfo::get32BitAddressHighBits(), llvm::MemSDNode::getAddressSpace(), llvm::APInt::getAllOnesValue(), llvm::MemSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SIInstrInfo::getDefaultRsrcDataFormat(), llvm::SDNode::getFlags(), llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::MachineFunction::getInfo(), llvm::SDNode::getMachineOpcode(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::MCInstrDesc::getNumDefs(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), llvm::SIMachineFunctionInfo::getScratchWaveOffsetReg(), llvm::ConstantSDNode::getSExtValue(), llvm::SDValue::getSimpleValueType(), llvm::SDNode::getSimpleValueType(), llvm::AMDGPU::getSMRDEncodedOffset(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SDNode::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::APInt::getZExtValue(), AMDGPUAS::GLOBAL_ADDRESS, llvm::SDNodeFlags::hasNoUnsignedWrap(), llvm::SDValue::hasOneUse(), llvm::SDNode::hasOneUse(), llvm::MipsISD::Hi, llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::tgtok::In, Info, llvm::MCInstrDesc::isCommutable(), llvm::SDNode::isDivergent(), llvm::SIInstrInfo::isLegalMUBUFImmOffset(), llvm::AMDGPU::isLegalSMRDImmOffset(), llvm::SDNode::isMachineOpcode(), llvm::isMask_32(), llvm::SIRegisterInfo::isSGPRClass(), llvm::PseudoSourceValue::isStack(), llvm::isUInt< 32 >(), llvm::SDValue::isUndef(), llvm::MipsISD::Lo, Lowering, llvm::BitmaskEnumDetail::Mask(), N, llvm::SISrcMods::NEG, llvm::SISrcMods::NEG_HI, llvm::SISrcMods::OP_SEL_0, llvm::SISrcMods::OP_SEL_1, llvm::MVT::Other, AMDGPUAS::REGION_ADDRESS, llvm::AMDGPUSubtarget::SEA_ISLANDS, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETNE, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, Signed, llvm::AMDGPUSubtarget::SOUTHERN_ISLANDS, llvm::ISD::SRA, llvm::ISD::SRL, SubReg, TII, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), llvm::MachinePointerInfo::V, and llvm::MVT::v4i32.

◆ selectSGPRVectorRegClassID()

static unsigned selectSGPRVectorRegClassID ( unsigned  NumVectorElts)
static

Definition at line 537 of file AMDGPUISelDAGToDAG.cpp.

References llvm_unreachable.

Referenced by getConstantValue().

Variable Documentation

◆ false

amdgpu AMDGPU DAG DAG Pattern Instruction false

Definition at line 294 of file AMDGPUISelDAGToDAG.cpp.

◆ isel

amdgpu isel

Definition at line 294 of file AMDGPUISelDAGToDAG.cpp.

◆ Selection

amdgpu AMDGPU DAG DAG Pattern Instruction Selection