28#define DEBUG_TYPE "hexagon-cext-opt"
34 cl::desc(
"Minimum number of extenders to trigger replacement"));
38 cl::desc(
"Maximum number of replacements"));
45static int32_t
adjustUp(int32_t V, uint8_t
A, uint8_t O) {
47 int32_t U = (V & -
A) + O;
48 return U >= V ? U : U+
A;
53 int32_t U = (V & -
A) + O;
54 return U <= V ? U : U-
A;
62 int32_t Min = INT_MIN,
Max = INT_MAX;
66 OffsetRange() =
default;
67 OffsetRange(int32_t L, int32_t
H, uint8_t
A, uint8_t O = 0)
74 if (Offset >=
A.Offset && (Offset -
A.Offset) %
A.Align == 0) {
84 std::tie(Min, Max,
Align) = std::make_tuple(0, -1, 1);
87 OffsetRange &shift(int32_t S) {
93 OffsetRange &extendBy(int32_t
D) {
97 Min = (INT_MIN-
D < Min) ? Min+
D : INT_MIN;
99 Max = (INT_MAX-
D >
Max) ? Max+
D : INT_MAX;
109 return Min ==
R.Min &&
Max ==
R.Max &&
Align ==
R.Align;
114 bool operator<(
const OffsetRange &R)
const {
121 static OffsetRange
zero() {
return {0, 0, 1}; }
130 const OffsetRange &
Range;
134 Node *Root =
nullptr;
136 void add(
const OffsetRange &R) {
148 nodesWith(Root,
P, CheckAlign, Nodes);
155 for (
Node *
N : Nodes)
162 void nodesWith(
Node *
N, int32_t
P,
bool CheckA,
169 unsigned height(
Node *
N) {
170 return N !=
nullptr ?
N->Height : 0;
174 N->Height = 1 + std::max(height(
N->Left), height(
N->Right));
176 N->MaxEnd = std::max(
N->MaxEnd,
N->Left->MaxEnd);
178 N->MaxEnd = std::max(
N->MaxEnd,
N->Right->MaxEnd);
183 int32_t Balance = height(
N->Right) - height(
N->Left);
185 return rotateRight(
N->Left,
N);
187 return rotateLeft(
N->Right,
N);
198 if (
B->end() == It) {
202 Pos = std::distance(
B->begin(), It);
207 return Block->getNumber() <
A.Block->getNumber();
210 return Pos != -1 && Pos <
A.Pos;
227 return "Hexagon constant-extender optimization";
240 Sub =
Op.getSubReg();
241 }
else if (
Op.isFI()) {
246 bool isVReg()
const {
247 return Reg != 0 && !
Reg.isStack() &&
Reg.isVirtual();
249 bool isSlot()
const {
return Reg != 0 &&
Reg.isStack(); }
265 return Reg <
R.Reg || (
Reg ==
R.Reg && Sub <
R.Sub);
298 ExtExpr(
Register RS,
bool NG,
unsigned SH) : Rs(RS), S(SH), Neg(NG) {}
300 bool trivial()
const {
304 return Rs == Ex.Rs && S == Ex.S && Neg == Ex.Neg;
309 bool operator<(
const ExtExpr &Ex)
const {
314 return !Neg && Ex.Neg;
320 unsigned OpNum = -1u;
353 return Kind == ER.Kind &&
V.ImmVal == ER.V.ImmVal;
361 struct ExtValue :
public ExtRoot {
365 ExtValue(
const ExtDesc &ED) : ExtValue(ED.getOp()) {}
366 ExtValue(
const ExtRoot &ER, int32_t Off) : ExtRoot(ER),
Offset(
Off) {}
367 bool operator<(
const ExtValue &EV)
const;
369 return ExtRoot(*
this) == ExtRoot(EV) &&
Offset == EV.Offset;
378 using ExtenderInit = std::pair<ExtValue, ExtExpr>;
379 using AssignmentMap = std::map<ExtenderInit, IndexList>;
380 using LocDefList = std::vector<std::pair<Loc, IndexList>>;
387 std::vector<ExtDesc> Extenders;
388 std::vector<unsigned> NewRegs;
390 bool isStoreImmediate(
unsigned Opc)
const;
391 bool isRegOffOpcode(
unsigned ExtOpc)
const ;
392 unsigned getRegOffOpcode(
unsigned ExtOpc)
const;
393 unsigned getDirectRegReplacement(
unsigned ExtOpc)
const;
395 OffsetRange getOffsetRange(
const ExtDesc &ED)
const;
396 OffsetRange getOffsetRange(
Register Rd)
const;
401 void assignInits(
const ExtRoot &ER,
unsigned Begin,
unsigned End,
402 AssignmentMap &IMap);
403 void calculatePlacement(
const ExtenderInit &ExtI,
const IndexList &Refs,
405 Register insertInitializer(Loc DefL,
const ExtenderInit &ExtI);
406 bool replaceInstrExact(
const ExtDesc &ED,
Register ExtR);
407 bool replaceInstrExpr(
const ExtDesc &ED,
const ExtenderInit &ExtI,
409 bool replaceInstr(
unsigned Idx,
Register ExtR,
const ExtenderInit &ExtI);
410 bool replaceExtenders(
const AssignmentMap &IMap);
418 friend struct PrintRegister;
419 friend struct PrintExpr;
420 friend struct PrintInit;
421 friend struct PrintIMap;
423 const struct PrintRegister &
P);
433 using HCE = HexagonConstExtenders;
444 struct PrintRegister {
463 const HCE::ExtExpr &Ex;
469 OS <<
"## " << (
P.Ex.Neg ?
"- " :
"+ ");
470 if (
P.Ex.Rs.Reg != 0)
474 OS <<
" << " <<
P.Ex.S;
480 : ExtI(EI), HRI(
I) {}
481 const HCE::ExtenderInit &ExtI;
487 OS <<
'[' <<
P.ExtI.first <<
", "
488 << PrintExpr(
P.ExtI.second,
P.HRI) <<
']';
503 OS <<
" = " << PrintExpr(ED.Expr, HRI);
513 OS <<
"imm:" << ER.V.ImmVal;
516 OS <<
"fpi:" << *ER.V.CFP;
519 OS <<
"sym:" << *ER.V.SymbolName;
522 OS <<
"gad:" << ER.V.GV->getName();
525 OS <<
"blk:" << *ER.V.BA;
528 OS <<
"tgi:" << ER.V.ImmVal;
531 OS <<
"cpi:" << ER.V.ImmVal;
534 OS <<
"jti:" << ER.V.ImmVal;
537 OS <<
"???:" << ER.V.ImmVal;
545 OS << HCE::ExtRoot(EV) <<
" off:" << EV.Offset;
552 const HCE::AssignmentMap &IMap;
559 for (
const std::pair<const HCE::ExtenderInit, HCE::IndexList> &Q :
P.IMap) {
560 OS <<
" " << PrintInit(Q.first,
P.HRI) <<
" -> {";
561 for (
unsigned I : Q.second)
571 "Hexagon constant-extender optimization",
false,
false)
582 dbgs() <<
"Root: " << Root <<
'\n';
588 dbgs() <<
"Node: " <<
N <<
'\n';
589 dbgs() <<
" Height: " <<
N->Height <<
'\n';
590 dbgs() <<
" Count: " <<
N->Count <<
'\n';
591 dbgs() <<
" MaxEnd: " <<
N->MaxEnd <<
'\n';
592 dbgs() <<
" Range: " <<
N->Range <<
'\n';
593 dbgs() <<
" Left: " <<
N->Left <<
'\n';
594 dbgs() <<
" Right: " <<
N->Right <<
"\n\n";
608 order(
N->Right, Seq);
611void RangeTree::nodesWith(
Node *
N, int32_t
P,
bool CheckA,
613 if (
N ==
nullptr ||
N->MaxEnd <
P)
615 nodesWith(
N->Left,
P, CheckA, Seq);
616 if (
N->Range.Min <=
P) {
617 if ((CheckA &&
N->Range.contains(
P)) || (!CheckA && P <= N->
Range.Max))
619 nodesWith(
N->Right,
P, CheckA, Seq);
623RangeTree::Node *RangeTree::add(
Node *
N,
const OffsetRange &R) {
633 N->Left =
add(
N->Left, R);
635 N->Right =
add(
N->Right, R);
636 return rebalance(update(
N));
639RangeTree::Node *RangeTree::remove(
Node *
N,
const Node *
D) {
643 assert(
N->Range !=
D->Range &&
"N and D should not be equal");
644 if (
D->Range <
N->Range)
648 return rebalance(update(
N));
653 if (
N->Left ==
nullptr ||
N->Right ==
nullptr)
654 return (
N->Left ==
nullptr) ?
N->Right :
N->Left;
663 return rebalance(update(M));
666RangeTree::Node *RangeTree::rotateLeft(
Node *
Lower,
Node *Higher) {
671 if (height(
Lower->Left) > height(
Lower->Right))
681RangeTree::Node *RangeTree::rotateRight(
Node *
Lower,
Node *Higher) {
686 if (height(
Lower->Left) < height(
Lower->Right))
702 else if (
Op.isFPImm())
703 V.CFP =
Op.getFPImm();
704 else if (
Op.isSymbol())
705 V.SymbolName =
Op.getSymbolName();
706 else if (
Op.isGlobal())
707 V.GV =
Op.getGlobal();
708 else if (
Op.isBlockAddress())
709 V.BA =
Op.getBlockAddress();
710 else if (
Op.isCPI() ||
Op.isTargetIndex() ||
Op.isJTI())
711 V.ImmVal =
Op.getIndex();
716 TF =
Op.getTargetFlags();
719bool HCE::ExtRoot::operator< (
const HCE::ExtRoot &ER)
const {
721 return Kind < ER.Kind;
727 return V.ImmVal < ER.V.ImmVal;
729 const APFloat &ThisF =
V.CFP->getValueAPF();
730 const APFloat &OtherF = ER.V.CFP->getValueAPF();
740 assert(!
V.GV->getName().empty() && !ER.V.GV->getName().empty());
741 return V.GV->getName() < ER.V.GV->getName();
744 const BasicBlock *OtherB = ER.V.BA->getBasicBlock();
751 return V.ImmVal < ER.V.ImmVal;
757 else if (
Op.isFPImm() ||
Op.isJTI())
759 else if (
Op.isSymbol() ||
Op.isGlobal() ||
Op.isBlockAddress() ||
760 Op.isCPI() ||
Op.isTargetIndex())
766bool HCE::ExtValue::operator< (
const HCE::ExtValue &EV)
const {
767 const ExtRoot &ER = *
this;
768 if (!(ER == ExtRoot(EV)))
770 return Offset < EV.Offset;
799bool HCE::isStoreImmediate(
unsigned Opc)
const {
801 case Hexagon::S4_storeirbt_io:
802 case Hexagon::S4_storeirbf_io:
803 case Hexagon::S4_storeirht_io:
804 case Hexagon::S4_storeirhf_io:
805 case Hexagon::S4_storeirit_io:
806 case Hexagon::S4_storeirif_io:
807 case Hexagon::S4_storeirb_io:
808 case Hexagon::S4_storeirh_io:
809 case Hexagon::S4_storeiri_io:
817bool HCE::isRegOffOpcode(
unsigned Opc)
const {
819 case Hexagon::L2_loadrub_io:
820 case Hexagon::L2_loadrb_io:
821 case Hexagon::L2_loadruh_io:
822 case Hexagon::L2_loadrh_io:
823 case Hexagon::L2_loadri_io:
824 case Hexagon::L2_loadrd_io:
825 case Hexagon::L2_loadbzw2_io:
826 case Hexagon::L2_loadbzw4_io:
827 case Hexagon::L2_loadbsw2_io:
828 case Hexagon::L2_loadbsw4_io:
829 case Hexagon::L2_loadalignh_io:
830 case Hexagon::L2_loadalignb_io:
831 case Hexagon::L2_ploadrubt_io:
832 case Hexagon::L2_ploadrubf_io:
833 case Hexagon::L2_ploadrbt_io:
834 case Hexagon::L2_ploadrbf_io:
835 case Hexagon::L2_ploadruht_io:
836 case Hexagon::L2_ploadruhf_io:
837 case Hexagon::L2_ploadrht_io:
838 case Hexagon::L2_ploadrhf_io:
839 case Hexagon::L2_ploadrit_io:
840 case Hexagon::L2_ploadrif_io:
841 case Hexagon::L2_ploadrdt_io:
842 case Hexagon::L2_ploadrdf_io:
843 case Hexagon::S2_storerb_io:
844 case Hexagon::S2_storerh_io:
845 case Hexagon::S2_storerf_io:
846 case Hexagon::S2_storeri_io:
847 case Hexagon::S2_storerd_io:
848 case Hexagon::S2_pstorerbt_io:
849 case Hexagon::S2_pstorerbf_io:
850 case Hexagon::S2_pstorerht_io:
851 case Hexagon::S2_pstorerhf_io:
852 case Hexagon::S2_pstorerft_io:
853 case Hexagon::S2_pstorerff_io:
854 case Hexagon::S2_pstorerit_io:
855 case Hexagon::S2_pstorerif_io:
856 case Hexagon::S2_pstorerdt_io:
857 case Hexagon::S2_pstorerdf_io:
858 case Hexagon::A2_addi:
866unsigned HCE::getRegOffOpcode(
unsigned ExtOpc)
const {
869 using namespace Hexagon;
871 case A2_tfrsi:
return A2_addi;
876 if (
D.mayLoad() ||
D.mayStore()) {
886 case L4_loadrub_ur:
return L2_loadrub_io;
889 case L4_loadrb_ur:
return L2_loadrb_io;
892 case L4_loadruh_ur:
return L2_loadruh_io;
895 case L4_loadrh_ur:
return L2_loadrh_io;
898 case L4_loadri_ur:
return L2_loadri_io;
901 case L4_loadrd_ur:
return L2_loadrd_io;
903 case L4_loadbzw2_ur:
return L2_loadbzw2_io;
905 case L4_loadbzw4_ur:
return L2_loadbzw4_io;
907 case L4_loadbsw2_ur:
return L2_loadbsw2_io;
909 case L4_loadbsw4_ur:
return L2_loadbsw4_io;
910 case L4_loadalignh_ap:
911 case L4_loadalignh_ur:
return L2_loadalignh_io;
912 case L4_loadalignb_ap:
913 case L4_loadalignb_ur:
return L2_loadalignb_io;
914 case L4_ploadrubt_abs:
return L2_ploadrubt_io;
915 case L4_ploadrubf_abs:
return L2_ploadrubf_io;
916 case L4_ploadrbt_abs:
return L2_ploadrbt_io;
917 case L4_ploadrbf_abs:
return L2_ploadrbf_io;
918 case L4_ploadruht_abs:
return L2_ploadruht_io;
919 case L4_ploadruhf_abs:
return L2_ploadruhf_io;
920 case L4_ploadrht_abs:
return L2_ploadrht_io;
921 case L4_ploadrhf_abs:
return L2_ploadrhf_io;
922 case L4_ploadrit_abs:
return L2_ploadrit_io;
923 case L4_ploadrif_abs:
return L2_ploadrif_io;
924 case L4_ploadrdt_abs:
return L2_ploadrdt_io;
925 case L4_ploadrdf_abs:
return L2_ploadrdf_io;
928 case S4_storerb_ur:
return S2_storerb_io;
931 case S4_storerh_ur:
return S2_storerh_io;
934 case S4_storerf_ur:
return S2_storerf_io;
937 case S4_storeri_ur:
return S2_storeri_io;
940 case S4_storerd_ur:
return S2_storerd_io;
941 case S4_pstorerbt_abs:
return S2_pstorerbt_io;
942 case S4_pstorerbf_abs:
return S2_pstorerbf_io;
943 case S4_pstorerht_abs:
return S2_pstorerht_io;
944 case S4_pstorerhf_abs:
return S2_pstorerhf_io;
945 case S4_pstorerft_abs:
return S2_pstorerft_io;
946 case S4_pstorerff_abs:
return S2_pstorerff_io;
947 case S4_pstorerit_abs:
return S2_pstorerit_io;
948 case S4_pstorerif_abs:
return S2_pstorerif_io;
949 case S4_pstorerdt_abs:
return S2_pstorerdt_io;
950 case S4_pstorerdf_abs:
return S2_pstorerdf_io;
956 if (!isStoreImmediate(ExtOpc))
966unsigned HCE::getDirectRegReplacement(
unsigned ExtOpc)
const {
968 case Hexagon::A2_addi:
return Hexagon::A2_add;
969 case Hexagon::A2_andir:
return Hexagon::A2_and;
970 case Hexagon::A2_combineii:
return Hexagon::A4_combineri;
971 case Hexagon::A2_orir:
return Hexagon::A2_or;
972 case Hexagon::A2_paddif:
return Hexagon::A2_paddf;
973 case Hexagon::A2_paddit:
return Hexagon::A2_paddt;
974 case Hexagon::A2_subri:
return Hexagon::A2_sub;
975 case Hexagon::A2_tfrsi:
return TargetOpcode::COPY;
976 case Hexagon::A4_cmpbeqi:
return Hexagon::A4_cmpbeq;
977 case Hexagon::A4_cmpbgti:
return Hexagon::A4_cmpbgt;
978 case Hexagon::A4_cmpbgtui:
return Hexagon::A4_cmpbgtu;
979 case Hexagon::A4_cmpheqi:
return Hexagon::A4_cmpheq;
980 case Hexagon::A4_cmphgti:
return Hexagon::A4_cmphgt;
981 case Hexagon::A4_cmphgtui:
return Hexagon::A4_cmphgtu;
982 case Hexagon::A4_combineii:
return Hexagon::A4_combineir;
983 case Hexagon::A4_combineir:
return TargetOpcode::REG_SEQUENCE;
984 case Hexagon::A4_combineri:
return TargetOpcode::REG_SEQUENCE;
985 case Hexagon::A4_rcmpeqi:
return Hexagon::A4_rcmpeq;
986 case Hexagon::A4_rcmpneqi:
return Hexagon::A4_rcmpneq;
987 case Hexagon::C2_cmoveif:
return Hexagon::A2_tfrpf;
988 case Hexagon::C2_cmoveit:
return Hexagon::A2_tfrpt;
989 case Hexagon::C2_cmpeqi:
return Hexagon::C2_cmpeq;
990 case Hexagon::C2_cmpgti:
return Hexagon::C2_cmpgt;
991 case Hexagon::C2_cmpgtui:
return Hexagon::C2_cmpgtu;
992 case Hexagon::C2_muxii:
return Hexagon::C2_muxir;
993 case Hexagon::C2_muxir:
return Hexagon::C2_mux;
994 case Hexagon::C2_muxri:
return Hexagon::C2_mux;
995 case Hexagon::C4_cmpltei:
return Hexagon::C4_cmplte;
996 case Hexagon::C4_cmplteui:
return Hexagon::C4_cmplteu;
997 case Hexagon::C4_cmpneqi:
return Hexagon::C4_cmpneq;
998 case Hexagon::M2_accii:
return Hexagon::M2_acci;
1000 case Hexagon::M2_macsip:
return Hexagon::M2_maci;
1001 case Hexagon::M2_mpysin:
return Hexagon::M2_mpyi;
1002 case Hexagon::M2_mpysip:
return Hexagon::M2_mpyi;
1003 case Hexagon::M2_mpysmi:
return Hexagon::M2_mpyi;
1004 case Hexagon::M2_naccii:
return Hexagon::M2_nacci;
1005 case Hexagon::M4_mpyri_addi:
return Hexagon::M4_mpyri_addr;
1006 case Hexagon::M4_mpyri_addr:
return Hexagon::M4_mpyrr_addr;
1007 case Hexagon::M4_mpyrr_addi:
return Hexagon::M4_mpyrr_addr;
1008 case Hexagon::S4_addaddi:
return Hexagon::M2_acci;
1009 case Hexagon::S4_addi_asl_ri:
return Hexagon::S2_asl_i_r_acc;
1010 case Hexagon::S4_addi_lsr_ri:
return Hexagon::S2_lsr_i_r_acc;
1011 case Hexagon::S4_andi_asl_ri:
return Hexagon::S2_asl_i_r_and;
1012 case Hexagon::S4_andi_lsr_ri:
return Hexagon::S2_lsr_i_r_and;
1013 case Hexagon::S4_ori_asl_ri:
return Hexagon::S2_asl_i_r_or;
1014 case Hexagon::S4_ori_lsr_ri:
return Hexagon::S2_lsr_i_r_or;
1015 case Hexagon::S4_subaddi:
return Hexagon::M2_subacc;
1016 case Hexagon::S4_subi_asl_ri:
return Hexagon::S2_asl_i_r_nac;
1017 case Hexagon::S4_subi_lsr_ri:
return Hexagon::S2_lsr_i_r_nac;
1020 case Hexagon::S4_storeirbf_io:
return Hexagon::S2_pstorerbf_io;
1021 case Hexagon::S4_storeirb_io:
return Hexagon::S2_storerb_io;
1022 case Hexagon::S4_storeirbt_io:
return Hexagon::S2_pstorerbt_io;
1023 case Hexagon::S4_storeirhf_io:
return Hexagon::S2_pstorerhf_io;
1024 case Hexagon::S4_storeirh_io:
return Hexagon::S2_storerh_io;
1025 case Hexagon::S4_storeirht_io:
return Hexagon::S2_pstorerht_io;
1026 case Hexagon::S4_storeirif_io:
return Hexagon::S2_pstorerif_io;
1027 case Hexagon::S4_storeiri_io:
return Hexagon::S2_storeri_io;
1028 case Hexagon::S4_storeirit_io:
return Hexagon::S2_pstorerit_io;
1050 unsigned Opc =
MI.getOpcode();
1053 if (!isRegOffOpcode(Opc) || HII->isConstExtended(
MI))
1054 return OffsetRange::zero();
1056 if (Opc == Hexagon::A2_addi) {
1058 if (Rb !=
Register(Op1) || !Op2.isImm())
1059 return OffsetRange::zero();
1060 OffsetRange
R = { -(1<<15)+1, (1<<15)-1, 1 };
1061 return R.shift(Op2.getImm());
1065 if (HII->isPostIncrement(
MI))
1066 return OffsetRange::zero();
1069 assert(
D.mayLoad() ||
D.mayStore());
1071 unsigned BaseP, OffP;
1072 if (!HII->getBaseAndOffsetPosition(
MI, BaseP, OffP) ||
1074 !
MI.getOperand(OffP).isImm())
1075 return OffsetRange::zero();
1086 int32_t
Off =
MI.getOperand(OffP).getImm();
1089 OffsetRange
R = { Min,
Max,
A };
1090 return R.shift(Off);
1100OffsetRange HCE::getOffsetRange(
const ExtDesc &ED)
const {
1104 unsigned IdxOpc = getRegOffOpcode(ED.UseMI->getOpcode());
1107 return OffsetRange::zero();
1108 case Hexagon::A2_addi:
1109 return { -32767, 32767, 1 };
1110 case Hexagon::A2_subri:
1111 return { -511, 511, 1 };
1114 if (!ED.UseMI->mayLoad() && !ED.UseMI->mayStore())
1115 return OffsetRange::zero();
1124 return { Min,
Max,
A };
1129OffsetRange HCE::getOffsetRange(
Register Rd)
const {
1136 return OffsetRange::zero();
1137 Range.intersect(getOffsetRange(Rd, *
Op.getParent()));
1143 unsigned Opc =
MI.getOpcode();
1147 bool IsLoad =
MI.mayLoad();
1148 bool IsStore =
MI.mayStore();
1154 if (
Op.isFI() &&
Op.getIndex() < 0)
1157 if (IsLoad || IsStore) {
1158 unsigned AM = HII->getAddrMode(
MI);
1164 ED.Rd =
MI.getOperand(OpNum-1);
1171 if (!isStoreImmediate(Opc))
1172 ED.Expr.Rs =
MI.getOperand(OpNum-1);
1175 ED.Expr.Rs =
MI.getOperand(OpNum-2);
1176 ED.Expr.S =
MI.getOperand(OpNum-1).getImm();
1183 case Hexagon::A2_tfrsi:
1184 ED.Rd =
MI.getOperand(0);
1187 case Hexagon::A2_combineii:
1188 case Hexagon::A4_combineir:
1189 ED.Rd = {
MI.getOperand(0).getReg(), Hexagon::isub_hi };
1192 case Hexagon::A4_combineri:
1193 ED.Rd = {
MI.getOperand(0).getReg(), Hexagon::isub_lo };
1196 case Hexagon::A2_addi:
1197 ED.Rd =
MI.getOperand(0);
1198 ED.Expr.Rs =
MI.getOperand(OpNum-1);
1200 case Hexagon::M2_accii:
1201 case Hexagon::M2_naccii:
1202 case Hexagon::S4_addaddi:
1203 ED.Expr.Rs =
MI.getOperand(OpNum-1);
1205 case Hexagon::A2_subri:
1206 ED.Rd =
MI.getOperand(0);
1207 ED.Expr.Rs =
MI.getOperand(OpNum+1);
1210 case Hexagon::S4_subaddi:
1211 ED.Expr.Rs =
MI.getOperand(OpNum+1);
1222 ExtRoot ER(ED.getOp());
1224 if (ER.V.GV->getName().empty())
1228 if (ER.V.BA->getFunction() != &(
MI.getMF()->getFunction()))
1230 Extenders.push_back(ED);
1234 if (!HII->isConstExtended(
MI))
1238 unsigned Opc =
MI.getOpcode();
1240 case Hexagon::M2_macsin:
1241 case Hexagon::C4_addipc:
1242 case Hexagon::S4_or_andi:
1243 case Hexagon::S4_or_andix:
1244 case Hexagon::S4_or_ori:
1247 recordExtender(
MI, HII->getCExtOpNum(
MI));
1261void HCE::assignInits(
const ExtRoot &ER,
unsigned Begin,
unsigned End,
1262 AssignmentMap &IMap) {
1265 for (
unsigned I = Begin;
I !=
End; ++
I)
1266 assert(ER == ExtRoot(Extenders[
I].getOp()));
1272 std::vector<OffsetRange>
Ranges(
End-Begin);
1278 for (
unsigned I = Begin;
I !=
End; ++
I) {
1279 const ExtDesc &ED = Extenders[
I];
1285 Ranges[
I-Begin] = getOffsetRange(ED.Rd).shift(EV.Offset);
1290 if (ED.UseMI->getOpcode() == Hexagon::A2_tfrsi) {
1292 Ranges[
I-Begin].extendBy(-
D).extendBy(
D);
1298 for (
unsigned I = Begin;
I !=
End; ++
I) {
1299 const ExtDesc &ED = Extenders[
I];
1304 OffsetRange Dev = getOffsetRange(ED);
1305 Ranges[
I-Begin].intersect(Dev.shift(EV.Offset));
1311 std::map<OffsetRange, IndexList> RangeMap;
1312 for (
unsigned I = Begin;
I !=
End; ++
I)
1313 RangeMap[Ranges[
I-Begin]].insert(
I);
1316 dbgs() <<
"Ranges\n";
1317 for (
unsigned I = Begin;
I !=
End; ++
I)
1319 dbgs() <<
"RangeMap\n";
1320 for (
auto &
P : RangeMap) {
1321 dbgs() <<
" " <<
P.first <<
" ->";
1322 for (
unsigned I :
P.second)
1334 using CandData = std::pair<unsigned, SmallVector<RangeTree::Node*,8>>;
1335 std::map<int32_t, CandData> CandMap;
1338 for (
const OffsetRange &R : Ranges)
1345 for (RangeTree::Node *
N : Nodes) {
1360 std::set<int32_t> CandSet;
1361 for (RangeTree::Node *
N : Nodes) {
1362 const OffsetRange &
R =
N->Range;
1363 auto P0 = MaxAlign(Tree.nodesWith(
R.Min,
false),
R.Align,
R.Offset);
1364 CandSet.insert(
R.Min);
1365 if (
R.Align < P0.first)
1366 CandSet.insert(
adjustUp(
R.Min, P0.first, P0.second));
1367 auto P1 = MaxAlign(Tree.nodesWith(
R.Max,
false),
R.Align,
R.Offset);
1368 CandSet.insert(
R.Max);
1369 if (
R.Align < P1.first)
1370 CandSet.insert(
adjustDown(
R.Max, P1.first, P1.second));
1379 using CMap = std::map<int32_t,unsigned>;
1381 for (
auto It = CandSet.begin(), Et = CandSet.end(); It != Et; ) {
1382 auto &&
V = Tree.nodesWith(*It);
1383 unsigned N = std::accumulate(
V.begin(),
V.end(), 0u,
1384 [](
unsigned Acc,
const RangeTree::Node *
N) {
1385 return Acc + N->Count;
1388 Counts.insert({*It,
N});
1389 It = (
N != 0) ? std::next(It) : CandSet.erase(It);
1396 Counts, [](
const CMap::value_type &
A,
const CMap::value_type &
B) {
1397 return A.second <
B.second || (
A.second ==
B.second &&
A <
B);
1399 int32_t Best = BestIt->first;
1400 ExtValue BestV(ER, Best);
1401 for (RangeTree::Node *
N : Tree.nodesWith(Best)) {
1402 for (
unsigned I : RangeMap[
N->Range])
1403 IMap[{BestV,Extenders[
I].Expr}].insert(
I);
1408 LLVM_DEBUG(
dbgs() <<
"IMap (before fixup) = " << PrintIMap(IMap, *HRI));
1417 for (std::pair<const ExtenderInit,IndexList> &
P : IMap) {
1419 if (
P.first.second.trivial())
1423 const ExtValue &EV =
P.first.first;
1424 AssignmentMap::iterator
F = IMap.find({EV, ExtExpr()});
1425 if (
F == IMap.end())
1464 bool IsStack =
any_of(
F->second, [
this](
unsigned I) {
1465 return Extenders[I].Expr.Rs.isSlot();
1467 auto SameValue = [&EV,
this,IsStack](
unsigned I) {
1468 const ExtDesc &ED = Extenders[
I];
1469 return ED.Expr.Rs.isSlot() == IsStack &&
1470 ExtValue(ED).Offset == EV.Offset;
1472 if (
all_of(
P.second, SameValue)) {
1473 F->second.insert(
P.second.begin(),
P.second.end());
1478 LLVM_DEBUG(
dbgs() <<
"IMap (after fixup) = " << PrintIMap(IMap, *HRI));
1481void HCE::calculatePlacement(
const ExtenderInit &ExtI,
const IndexList &Refs,
1493 const ExtDesc &ED0 = Extenders[Refs[0]];
1495 RefMIs.
insert(ED0.UseMI);
1497 for (
unsigned i = 1, e = Refs.size(); i != e; ++i) {
1498 const ExtDesc &ED = Extenders[Refs[i]];
1501 DomB = MDT->findNearestCommonDominator(DomB,
MBB);
1509 const MachineInstr *DefI = Rs.isVReg() ?
MRI->getVRegDef(Rs.Reg) :
nullptr;
1517 if (
Blocks.count(DomB)) {
1520 for (It = DomB->
begin(); It !=
End; ++It)
1521 if (RefMIs.
count(&*It))
1523 assert(It !=
End &&
"Should have found a ref in DomB");
1528 Loc DefLoc(DomB, It);
1529 Defs.emplace_back(DefLoc, Refs);
1532HCE::Register HCE::insertInitializer(Loc DefL,
const ExtenderInit &ExtI) {
1536 DebugLoc dl = DefL.Block->findDebugLoc(DefL.At);
1537 const ExtValue &EV = ExtI.first;
1540 const ExtExpr &Ex = ExtI.second;
1543 if (Ex.Rs.isSlot()) {
1544 assert(Ex.S == 0 &&
"Cannot have a shift of a stack slot");
1545 assert(!Ex.Neg &&
"Cannot subtract a stack slot");
1547 InitI =
BuildMI(
MBB, At, dl, HII->get(Hexagon::PS_fi), DefR)
1551 assert((Ex.Rs.Reg == 0 || Ex.Rs.isVReg()) &&
"Expecting virtual register");
1554 InitI =
BuildMI(
MBB, At, dl, HII->get(Hexagon::A2_tfrsi), DefR)
1556 }
else if (Ex.S == 0) {
1559 InitI =
BuildMI(
MBB, At, dl, HII->get(Hexagon::A2_subri), DefR)
1564 InitI =
BuildMI(
MBB, At, dl, HII->get(Hexagon::A2_addi), DefR)
1569 if (HST->useCompound()) {
1570 unsigned NewOpc = Ex.Neg ? Hexagon::S4_subi_asl_ri
1571 : Hexagon::S4_addi_asl_ri;
1573 InitI =
BuildMI(
MBB, At, dl, HII->get(NewOpc), DefR)
1582 BuildMI(
MBB, At, dl, HII->get(Hexagon::S2_asl_i_r), TmpR)
1586 InitI =
BuildMI(
MBB, At, dl, HII->get(Hexagon::A2_subri), DefR)
1590 InitI =
BuildMI(
MBB, At, dl, HII->get(Hexagon::A2_addi), DefR)
1600 <<
" for initializer: " << PrintInit(ExtI, *HRI) <<
"\n "
1606bool HCE::replaceInstrExact(
const ExtDesc &ED,
Register ExtR) {
1611 unsigned ExtOpc =
MI.getOpcode();
1616 unsigned RegOpc = getDirectRegReplacement(ExtOpc);
1618 if (RegOpc == TargetOpcode::REG_SEQUENCE) {
1619 if (ExtOpc == Hexagon::A4_combineri)
1621 .
add(
MI.getOperand(0))
1622 .
add(
MI.getOperand(1))
1623 .
addImm(Hexagon::isub_hi)
1625 .
addImm(Hexagon::isub_lo);
1626 else if (ExtOpc == Hexagon::A4_combineir)
1628 .
add(
MI.getOperand(0))
1630 .
addImm(Hexagon::isub_hi)
1631 .
add(
MI.getOperand(2))
1632 .
addImm(Hexagon::isub_lo);
1638 if (ExtOpc == Hexagon::C2_cmpgei || ExtOpc == Hexagon::C2_cmpgeui) {
1639 unsigned NewOpc = ExtOpc == Hexagon::C2_cmpgei ? Hexagon::C2_cmplt
1640 : Hexagon::C2_cmpltu;
1642 .
add(
MI.getOperand(0))
1644 .
add(
MI.getOperand(1));
1651 unsigned RegN = ED.OpNum;
1653 for (
unsigned i = 0, e =
MI.getNumOperands(); i != e; ++i) {
1655 MIB.
add(
MI.getOperand(i));
1664 if (
MI.mayLoadOrStore() && !isStoreImmediate(ExtOpc)) {
1672 unsigned RegOpc, Shift;
1673 unsigned AM = HII->getAddrMode(
MI);
1675 RegOpc = HII->changeAddrMode_io_rr(ExtOpc);
1680 RegOpc = HII->changeAddrMode_ur_rr(ExtOpc);
1681 Shift =
MI.getOperand(
MI.mayLoad() ? 2 : 1).getImm();
1686 if (RegOpc == -1u) {
1687 dbgs() <<
"\nExtOpc: " << HII->getName(ExtOpc) <<
" has no rr version\n";
1692 unsigned BaseP, OffP;
1693 HII->getBaseAndOffsetPosition(
MI, BaseP, OffP);
1699 MIB.
add(getLoadResultOp(
MI));
1701 if (HII->isPredicated(
MI))
1702 MIB.
add(getPredicateOp(
MI));
1705 MIB.
add(
MI.getOperand(BaseP));
1709 MIB.
add(getStoredValueOp(
MI));
1723bool HCE::replaceInstrExpr(
const ExtDesc &ED,
const ExtenderInit &ExtI,
1729 unsigned ExtOpc =
MI.getOpcode();
1731 if (ExtOpc == Hexagon::A2_tfrsi) {
1740 unsigned IdxOpc = getRegOffOpcode(ExtOpc);
1741 assert(IdxOpc == Hexagon::A2_addi);
1744 int32_t
D = isInt<16>(Diff) ? Diff : (Diff > 0 ? 32767 : -32768);
1750 OffsetRange
R = getOffsetRange(
MI.getOperand(0));
1755 .
add(
MI.getOperand(0))
1763 OffsetRange
Uses = getOffsetRange(
MI.getOperand(0));
1764 if (!
Uses.contains(-Diff))
1765 dbgs() <<
"Diff: " << -Diff <<
" out of range " <<
Uses
1773 const ExtValue &EV = ExtI.first; (void)EV;
1774 const ExtExpr &Ex = ExtI.second; (void)Ex;
1776 if (ExtOpc == Hexagon::A2_addi || ExtOpc == Hexagon::A2_subri) {
1781 bool IsAddi = ExtOpc == Hexagon::A2_addi;
1784 assert(Ex.Rs == RegOp && EV == ImmOp && Ex.Neg != IsAddi &&
1785 "Initializer mismatch");
1787 BuildMI(
MBB, At, dl, HII->get(TargetOpcode::COPY))
1788 .
add(
MI.getOperand(0))
1794 if (ExtOpc == Hexagon::M2_accii || ExtOpc == Hexagon::M2_naccii ||
1795 ExtOpc == Hexagon::S4_addaddi || ExtOpc == Hexagon::S4_subaddi) {
1804 bool IsSub = ExtOpc == Hexagon::S4_subaddi;
1806 ExtValue
V =
MI.getOperand(IsSub ? 2 : 3);
1807 assert(EV == V && Rs == Ex.Rs && IsSub == Ex.Neg &&
"Initializer mismatch");
1809 unsigned NewOpc = ExtOpc == Hexagon::M2_naccii ? Hexagon::A2_sub
1812 .
add(
MI.getOperand(0))
1813 .
add(
MI.getOperand(1))
1819 if (
MI.mayLoadOrStore()) {
1820 unsigned IdxOpc = getRegOffOpcode(ExtOpc);
1821 assert(IdxOpc &&
"Expecting indexed opcode");
1826 MIB.
add(getLoadResultOp(
MI));
1828 if (HII->isPredicated(
MI))
1829 MIB.
add(getPredicateOp(
MI));
1835 MIB.
add(getStoredValueOp(
MI));
1842 dbgs() <<
'\n' << PrintInit(ExtI, *HRI) <<
" " <<
MI;
1848bool HCE::replaceInstr(
unsigned Idx,
Register ExtR,
const ExtenderInit &ExtI) {
1854 const ExtDesc &ED = Extenders[
Idx];
1855 assert((!ED.IsDef || ED.Rd.Reg != 0) &&
"Missing Rd for def");
1856 const ExtValue &DefV = ExtI.first;
1857 assert(ExtRoot(ExtValue(ED)) == ExtRoot(DefV) &&
"Extender root mismatch");
1858 const ExtExpr &DefEx = ExtI.second;
1861 int32_t Diff = EV.Offset - DefV.Offset;
1864 << PrintRegister(ExtR, *HRI) <<
" Diff:" << Diff <<
'\n');
1868 bool IsAbs =
false, IsAbsSet =
false;
1869 if (
MI.mayLoadOrStore()) {
1870 unsigned AM = HII->getAddrMode(
MI);
1879 std::vector<std::pair<MachineInstr*,unsigned>> RegOps;
1880 if (ED.IsDef && Diff != 0) {
1883 RegOps.push_back({&UI, getOperandIndex(UI,
Op)});
1888 bool Replaced =
false;
1889 if (Diff == 0 && DefEx.trivial() && !IsAbs && !IsAbsSet)
1890 Replaced = replaceInstrExact(ED, ExtR);
1892 Replaced = replaceInstrExpr(ED, ExtI, ExtR, Diff);
1894 if (Diff != 0 && Replaced && ED.IsDef) {
1896 for (std::pair<MachineInstr*,unsigned>
P : RegOps) {
1897 unsigned J =
P.second;
1898 assert(
P.first->getNumOperands() > J+1 &&
1899 P.first->getOperand(J+1).isImm());
1908 assert(ED.Rd.Sub == 0 && ExtR.Sub == 0);
1909 MRI->replaceRegWith(ED.Rd.Reg, ExtR.Reg);
1916bool HCE::replaceExtenders(
const AssignmentMap &IMap) {
1918 bool Changed =
false;
1920 for (
const std::pair<const ExtenderInit, IndexList> &
P : IMap) {
1921 const IndexList &Idxs =
P.second;
1926 calculatePlacement(
P.first, Idxs, Defs);
1927 for (
const std::pair<Loc,IndexList> &Q : Defs) {
1928 Register DefR = insertInitializer(Q.first,
P.first);
1929 NewRegs.push_back(DefR.Reg);
1930 for (
unsigned I : Q.second)
1931 Changed |= replaceInstr(
I, DefR,
P.first);
1939 for (
unsigned i = 0, n =
MI.getNumOperands(); i != n; ++i)
1940 if (&
MI.getOperand(i) == &
Op)
1948 if (!
Op.isReg() || !
Op.isUse() ||
1949 MRI->getRegClass(
Op.getReg()) != &Hexagon::PredRegsRegClass)
1951 assert(
Op.getSubReg() == 0 &&
"Predicate register with a subregister");
1959 return MI.getOperand(0);
1964 return MI.getOperand(
MI.getNumExplicitOperands()-1);
1972 <<
" due to exception handling\n");
1979 HRI = HST->getRegisterInfo();
1980 MDT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
1985 llvm::sort(Extenders, [
this](
const ExtDesc &
A,
const ExtDesc &
B) {
1986 ExtValue VA(
A),
VB(
B);
1993 return A.OpNum <
B.OpNum;
2001 return MDT->dominates(MA, MB);
2004 bool Changed =
false;
2005 LLVM_DEBUG(
dbgs() <<
"Collected " << Extenders.size() <<
" extenders\n");
2006 for (
unsigned I = 0, E = Extenders.size();
I != E; ) {
2008 const ExtRoot &
T = Extenders[
B].getOp();
2009 while (
I != E && ExtRoot(Extenders[
I].getOp()) ==
T)
2013 assignInits(
T,
B,
I, IMap);
2014 Changed |= replaceExtenders(IMap);
2019 MF.
print(
dbgs() <<
"After " << getPassName() <<
'\n',
nullptr);
2021 dbgs() <<
"No changes\n";
2027 return new HexagonConstExtenders();
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
#define LLVM_ATTRIBUTE_UNUSED
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
DenseMap< Block *, BlockRelaxAux > Blocks
Rewrite Partial Register Uses
static cl::opt< unsigned > CountThreshold("hexagon-cext-threshold", cl::init(3), cl::Hidden, cl::desc("Minimum number of extenders to trigger replacement"))
hexagon cext Hexagon constant extender static false unsigned ReplaceCounter
static int32_t adjustUp(int32_t V, uint8_t A, uint8_t O)
hexagon cext Hexagon constant extender optimization
static cl::opt< unsigned > ReplaceLimit("hexagon-cext-limit", cl::init(0), cl::Hidden, cl::desc("Maximum number of replacements"))
static int32_t adjustDown(int32_t V, uint8_t A, uint8_t O)
static ValueLatticeElement intersect(const ValueLatticeElement &A, const ValueLatticeElement &B)
Combine two sets of facts about the same value into a single set of facts.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file implements a set that has insertion order iteration characteristics.
This file defines the SmallVector class.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
APInt bitcastToAPInt() const
bool ult(const APInt &RHS) const
Unsigned less than comparison.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
LLVM Basic Block Representation.
const Function * getParent() const
Return the enclosing method, or null if none.
The address of a basic block.
ConstantFP - Floating Point Values [float, double].
This class represents an Operation in the Expression.
Implements a dense probed hash-table based set.
FunctionPass class - This class is used to implement most global optimizations.
bool hasPersonalityFn() const
Check whether this function has a personality function.
const HexagonInstrInfo * getInstrInfo() const override
Describe properties that are true of each instruction in the target description file.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Analysis pass which computes a MachineDominatorTree.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Representation of each machine instruction.
const MachineBasicBlock * getParent() const
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateES(const char *SymName, unsigned TargetFlags=0)
static MachineOperand CreateFPImm(const ConstantFP *CFP)
void setImm(int64_t immVal)
static MachineOperand CreateImm(int64_t Val)
static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags=0)
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned TargetFlags=0)
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_GlobalAddress
Address of a global value.
@ MO_BlockAddress
Address of a basic block.
@ MO_ExternalSymbol
Name of external global symbol.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
@ MO_TargetIndex
Target-dependent index+offset operand.
@ MO_FPImmediate
Floating-point immediate operand.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateFI(int Idx)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
static int stackSlot2Index(Register Reg)
Compute the frame index from a register value representing a stack slot.
static Register index2StackSlot(int FI)
Convert a non-negative frame index to a stack slot register value.
A vector that has set insertion semantics.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
std::pair< iterator, bool > insert(const ValueT &V)
size_type count(const_arg_type_t< ValueT > V) const
Return 1 if the specified key is in the set, 0 otherwise.
self_iterator getIterator()
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char SymbolName[]
Key for Kernel::Metadata::mSymbolName.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
static LLVM_ATTRIBUTE_UNUSED unsigned getMemAccessSizeInBytes(MemAccessSize S)
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
std::error_code remove(const Twine &path, bool IgnoreNonExisting=true)
Remove path.
This is an optimization pass for GlobalISel generic memory operations.
void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)
bool operator<(int64_t V1, const APSInt &V2)
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool operator!=(uint64_t V1, const APInt &V2)
constexpr T alignDown(U Value, V Align, W Skew=0)
Returns the largest unsigned integer less than or equal to Value and is Skew mod Align.
FunctionPass * createHexagonConstExtenders()
bool operator==(const AddressRangeValuePair &LHS, const AddressRangeValuePair &RHS)
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
void erase(Container &C, ValueType V)
Wrapper function to remove a value from a container:
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
void sort(IteratorTy Start, IteratorTy End)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
DWARFExpression::Operation Op
auto max_element(R &&Range)
Provide wrappers to std::max_element which take ranges instead of having to pass begin/end explicitly...
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
void initializeHexagonConstExtendersPass(PassRegistry &)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
This struct is a compact representation of a valid (non-zero power of two) alignment.