33#define DEBUG_TYPE "arm-mve-vpt"
48 MachineFunctionProperties::Property::NoVRegs);
52 return "MVE VPT block insertion pass";
59char MVEVPTBlock::ID = 0;
67 unsigned &NewOpcode) {
72 while (CmpMI !=
MI->getParent()->begin()) {
74 if (CmpMI->modifiesRegister(ARM::VPR,
TRI))
76 if (CmpMI->readsRegister(ARM::VPR,
TRI))
103 unsigned &NumInstrsSteppedOver) {
106 NumInstrsSteppedOver = 0;
108 while (Iter != EndIter) {
109 if (Iter->isDebugInstr()) {
117 "VPT block pass does not expect Else preds");
122 ++NumInstrsSteppedOver;
125 return NumInstrsSteppedOver != 0 &&
133 for (; Iter !=
End; ++Iter)
134 if (Iter->definesRegister(ARM::VPR) || Iter->killsRegister(ARM::VPR))
143 return ARM::PredBlockMask::T;
145 return ARM::PredBlockMask::TT;
147 return ARM::PredBlockMask::TTT;
149 return ARM::PredBlockMask::TTTT;
168 "Expected a Predicated Instruction");
177 AddedInstIter != Iter; ++AddedInstIter) {
178 if (AddedInstIter->isDebugInstr())
180 dbgs() <<
" adding: ";
181 AddedInstIter->dump();
190 while (
BlockSize < 4 && Iter != EndIter &&
191 Iter->getOpcode() == ARM::MVE_VPNOT) {
195 unsigned ElseInstCnt = 0;
220 for (; Iter != VPNOTBlockEndIter; ++Iter) {
221 if (Iter->isDebugInstr())
229 Iter->getOperand(OpIdx).setImm(CurrentPredicate);
248 while (MBIter != EndIter) {
275 LLVM_DEBUG(
dbgs() <<
" final block mask: " << (
unsigned)BlockMask <<
"\n");
280 MIBuilder.
add(
VCMP->getOperand(1));
281 MIBuilder.
add(
VCMP->getOperand(2));
282 MIBuilder.
add(
VCMP->getOperand(3));
288 MII.clearRegisterKills(
VCMP->getOperand(1).getReg(),
TRI);
289 MII.clearRegisterKills(
VCMP->getOperand(2).getReg(),
TRI);
292 VCMP->eraseFromParent();
302 DeadInstructions.clear();
316 if (!STI.
isThumb2() || !STI.hasMVEIntegerOps())
323 <<
"********** Function: " << Fn.
getName() <<
'\n');
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
const HexagonInstrInfo * TII
static ARM::PredBlockMask GetInitialBlockMask(unsigned BlockSize)
static ARM::PredBlockMask CreateVPTBlock(MachineBasicBlock::instr_iterator &Iter, MachineBasicBlock::instr_iterator EndIter, SmallVectorImpl< MachineInstr * > &DeadInstructions)
static bool StepOverPredicatedInstrs(MachineBasicBlock::instr_iterator &Iter, MachineBasicBlock::instr_iterator EndIter, unsigned MaxSteps, unsigned &NumInstrsSteppedOver)
static bool IsVPRDefinedOrKilledByBlock(MachineBasicBlock::iterator Iter, MachineBasicBlock::iterator End)
static MachineInstr * findVCMPToFoldIntoVPST(MachineBasicBlock::iterator MI, const TargetRegisterInfo *TRI, unsigned &NewOpcode)
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
static const int BlockSize
const ARMBaseInstrInfo * getInstrInfo() const override
const ARMBaseRegisterInfo * getRegisterInfo() const override
FunctionPass class - This class is used to implement most global optimizations.
Instructions::iterator instr_iterator
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Representation of each machine instruction.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
PredBlockMask
Mask values for IT and VPT Blocks, to be used by MCOperands.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
This is an optimization pass for GlobalISel generic memory operations.
void finalizeBundle(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
finalizeBundle - Finalize a machine instruction bundle which includes a sequence of instructions star...
int findFirstVPTPredOperandIdx(const MachineInstr &MI)
ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI, Register &PredReg)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
bool registerDefinedBetween(unsigned Reg, MachineBasicBlock::iterator From, MachineBasicBlock::iterator To, const TargetRegisterInfo *TRI)
Return true if Reg is defd between From and To.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
ARM::PredBlockMask expandPredBlockMask(ARM::PredBlockMask BlockMask, ARMVCC::VPTCodes Kind)
static unsigned VCMPOpcodeToVPT(unsigned Opcode)
FunctionPass * createMVEVPTBlockPass()
createMVEVPTBlock - Returns an instance of the MVE VPT block insertion pass.