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44 enum Lowering { TouchAndSub, Sub, Probe };
53 Lowering getLowering(int64_t CurrentOffset, int64_t AllocaAmount);
63 unsigned SlotSize = 0;
64 int64_t StackProbeSize = 0;
65 bool NoStackArgProbe =
false;
67 StringRef getPassName()
const override {
return "X86 DynAlloca Expander"; }
76 return new X86DynAllocaExpander();
81 assert(
MI->getOpcode() == X86::DYN_ALLOCA_32 ||
82 MI->getOpcode() == X86::DYN_ALLOCA_64);
85 Register AmountReg =
MI->getOperand(0).getReg();
89 (
Def->getOpcode() != X86::MOV32ri &&
Def->getOpcode() != X86::MOV64ri) ||
90 !
Def->getOperand(1).isImm())
93 return Def->getOperand(1).getImm();
96 X86DynAllocaExpander::Lowering
97 X86DynAllocaExpander::getLowering(int64_t CurrentOffset,
98 int64_t AllocaAmount) {
100 if (AllocaAmount < 0 || AllocaAmount > StackProbeSize)
104 if (CurrentOffset + AllocaAmount <= StackProbeSize)
112 switch (
MI.getOpcode()) {
132 LoweringMap &Lowerings) {
140 OutOffset[&
MBB] = INT32_MAX;
153 if (Offset == -1)
Offset = INT32_MAX;
156 if (
MI.getOpcode() == X86::DYN_ALLOCA_32 ||
157 MI.getOpcode() == X86::DYN_ALLOCA_64) {
160 Lowering L = getLowering(Offset, Amount);
176 }
else if (
MI.getOpcode() == X86::ADJCALLSTACKUP32 ||
177 MI.getOpcode() == X86::ADJCALLSTACKUP64) {
178 Offset -=
MI.getOperand(0).getImm();
179 }
else if (
MI.getOpcode() == X86::ADJCALLSTACKDOWN32 ||
180 MI.getOpcode() == X86::ADJCALLSTACKDOWN64) {
181 Offset +=
MI.getOperand(0).getImm();
182 }
else if (
MI.modifiesRegister(StackPtr,
TRI)) {
194 return isInt<8>(Amount) ? X86::SUB64ri8 : X86::SUB64ri32;
195 return isInt<8>(Amount) ? X86::SUB32ri8 : X86::SUB32ri;
205 MI->eraseFromParent();
211 bool Is64Bit = STI->is64Bit();
212 bool Is64BitAlloca =
MI->getOpcode() == X86::DYN_ALLOCA_64;
213 assert(SlotSize == 4 || SlotSize == 8);
216 if (
unsigned Num =
MI->peekDebugInstrNum()) {
223 assert(Amount >= SlotSize);
226 unsigned RegA = Is64Bit ? X86::RAX :
X86::EAX;
238 if (Amount == SlotSize) {
240 unsigned RegA = Is64Bit ? X86::RAX :
X86::EAX;
252 if (!NoStackArgProbe) {
254 unsigned RegA = Is64BitAlloca ? X86::RAX :
X86::EAX;
256 .
addReg(
MI->getOperand(0).getReg());
264 TII->get(Is64BitAlloca ? X86::SUB64rr : X86::SUB32rr), StackPtr)
266 .
addReg(
MI->getOperand(0).getReg());
271 Register AmountReg =
MI->getOperand(0).getReg();
272 MI->eraseFromParent();
277 AmountDef->eraseFromParent();
286 TII = STI->getInstrInfo();
287 TRI = STI->getRegisterInfo();
289 SlotSize =
TRI->getSlotSize();
291 StackProbeSize = 4096;
302 LoweringMap Lowerings;
303 computeLowerings(MF, Lowerings);
304 for (
auto &
P : Lowerings)
305 lower(
P.first,
P.second);
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
FunctionPass * createX86DynAllocaExpander()
Return a pass that expands DynAlloca pseudo-instructions.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
rpo function Deduce function attributes in RPO
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
This class implements a map that also provides access to all stored values in a deterministic order.
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
bool hasDynAlloca() const
unsigned const TargetRegisterInfo * TRI
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
TargetInstrInfo - Interface to description of machine instruction set.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
static unsigned getSubOpcode(bool Is64Bit, int64_t Amount)
const HexagonInstrInfo * TII
static int64_t getDynAllocaAmount(MachineInstr *MI, MachineRegisterInfo *MRI)
Return the allocation amount for a DynAlloca instruction, or -1 if unknown.
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
StringRef getValueAsString() const
Return the attribute's value as a string.
std::enable_if_t< std::numeric_limits< T >::is_signed, bool > getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
bool use_empty(Register RegNo) const
use_empty - Return true if there are no instructions using the specified register.
static bool isPushPop(const MachineInstr &MI)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
constexpr bool isInt< 8 >(int64_t x)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Representation of each machine instruction.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
iterator_range< pred_iterator > predecessors()
StringRef - Represent a constant reference to a string, i.e.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
Function & getFunction()
Return the LLVM function that this machine code represents.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
FunctionPass class - This class is used to implement most global optimizations.
@ Undef
Value of the register doesn't matter.